Memory device security and row hammer mitigation

Abstract

Systems, methods, and devices are described for memory device security and row hammer mitigation. Control mechanisms can be implemented in a front-end and / or back-end of a memory subsystem to flush rows of the memory. A row activate command can be received at control circuitry of a memory subsystem with a row address and increment a first count of a row counter stored in a content addressable memory (CAM) of the memory subsystem corresponding to the row address. The control circuitry can determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count can be incremented each time the CAM has been full. When it is determined that the first count is greater than the RHT minus the second count, a flush command can be issued to the row address.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to memory device security and line hammer mitigation. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. Memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at memory devices and retrieve data from memory devices. Summary of the Invention

[0003] This disclosure provides a method for memory device security and row hammer mitigation, wherein the method includes: receiving a row activation command having a row address at a control circuitry of a memory subsystem; incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory subsystem; determining at the control circuitry whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrement counter (CDC), wherein the second count is incremented whenever the CAM is full; and issuing a refresh command to the row address in response to determining that the first count is greater than the RHT minus the second count.

[0004] Another aspect of this disclosure provides an apparatus for memory device security and row hammer mitigation, wherein the apparatus includes: a content-addressable memory (CAM); a memory device; and a control circuitry system coupled to the memory device and configured to: receive a row activation command having a row address of the memory device; increment a first count of the row counter in response to determining that a row counter corresponding to the row address is stored in the CAM; determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrement counter (CDC), wherein the CDC stores the number of times different row addresses have been deassociated from the CAM once the CAM is full; and issue a refresh command to the row address in response to determining that the first count is greater than the RHT minus the second count.

[0005] Another aspect of this disclosure provides an apparatus for memory device security and row hammer mitigation, wherein the apparatus includes: a content-addressable memory (CAM); a memory device; and a control circuitry system coupled to the memory device and configured to: receive a row activation command pointing to a row address of the memory device; determine whether a row counter corresponding to the row address is stored in the CAM; in response to determining that the row counter corresponding to the row address is stored in the CAM, determine whether a first count of the row counter is greater than the difference between a row hammer threshold (RHT) and a second count of a CAM decrement counter (CDC), wherein the CDC stores the number of times different row addresses have been deassociated from the CAM once the CAM is full; and in response to determining that the first count is greater than the difference between the RHT and the second count, issue a refresh command to the row address. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments thereof.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This is a block diagram corresponding to a refresh circuit system according to some embodiments of the present disclosure.

[0009] Figure 3 This is a flowchart corresponding to a refresh circuit system according to some embodiments of the present disclosure.

[0010] Figure 4 This is a flowchart corresponding to a method for refreshing rows according to some embodiments of this disclosure.

[0011] Figure 5 This is a block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0012] This disclosure relates to memory device security and line hammer mitigation, and more particularly to a memory subsystem including a refresh circuitry system. The memory subsystem may be a storage system, a storage device, a memory module, or a combination thereof. An example of a memory subsystem is a storage system, such as a solid-state drive (SSD). The following description... Figure 1 Examples describing storage devices and memory modules are provided. Generally, a host system may utilize a memory subsystem comprising one or more components, such as a memory device for storing data. The host system can provide data stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0013] The front end (e.g., front end interface) and / or back end of the memory subsystem may include line hammer mitigation mechanisms to mitigate line hammer attacks. In various memory subsystems, the front end may be connected to a media controller, which in turn can access various media types, including DRAM, 3DXP, and / or NAND (e.g., emerging memories). The media controller may be referred to as the back end of the memory subsystem.

[0014] As used herein, a row hammer attack accesses memory cells in a row of a memory array to leak charge stored in that row of memory cells into neighboring rows. For example, memory cells corresponding to a specific row may be affected by a row hammer attack. A row hammer refers to an undesirable change in the capacitor voltage of a memory cell corresponding to a row adjacent to a frequently accessed row. Row hammer attacks can be used to intentionally alter data stored in memory by rapidly and repeatedly accessing a specific row. The target of a row hammer attack can be to corrupt data in inaccessible neighboring rows.

[0015] For example, the first row, which is adjacent to the second row, can be repeatedly accessed within a short period of time. Repeated access to the first row can leak voltage from memory cells coupled to the second row to memory cells coupled to the first row. This voltage leakage can corrupt data stored in memory cells coupled to the second row. A row hammer attack corrupts data stored in memory cells coupled to the second row by activating memory cells coupled to the first row, where the first row is adjacent to the second row. In some instances, the first and second rows may not be adjacent, but may be within several rows of each other.

[0016] As used herein, memory cells and / or rows may be adjacent to each other if they are physically adjacent to each other in the memory array, or if physical proximity is sufficient to allow charge leakage from memory cells coupled to a row to different memory cells coupled to different rows. Rows of memory cells may be adjacent to different rows if the addresses of the rows are contiguous and / or if there are no other rows between adjacent rows. Memory cells may be adjacent to each other if they are coupled to rows that are adjacent to each other.

[0017] Due to the various physical effects of shrinking manufacturing process geometry, the row hammer threshold (RHT) of a memory subsystem has been reduced to a level at which an application running on the host of a computer system might unintentionally corrupt its own data or the data of different applications sharing the same system memory. As used herein, RHT is the threshold amount of a row of memory cells that leak charge after which the memory cells in that row are accessed.

[0018] Various row hammer detector algorithms (e.g., address sampling, priority content-addressable memory) are probabilistic and therefore may not guarantee perfect (e.g., complete, accurate, and / or precise) prevention of data corruption. If an attacker knows enough details about these existing row hammer detection methods and their implementation mechanisms, they can exploit their weaknesses to bypass or destroy them and corrupt data. The storage and operational power required to implement various row hammer detector algorithms are too high for practical use.

[0019] Row hammer detection can involve determining which addresses in the memory subsystem are accessed most frequently and refreshing the identified addresses. Determining which addresses are accessed most frequently can involve storing each accessed address and counting the most frequently accessed addresses. However, storing every accessed address may be impractical due to memory limitations. Maintaining a count for every received address may also be impractical due to memory limitations, especially when each received address is distinct. Mesa-Grise can be used to identify the most frequent items in a finite data stream. For example, Mesa-Grise can be used to identify elements that appear for more than a predefined amount of time. For example, Mesa-Grise can be used to identify elements (e.g., addresses) that appear more than five times in the address stream received from the host.

[0020] Mesa-Gris stores addresses in a dictionary. If the dictionary contains addresses, we can count the given addresses. If the dictionary does not contain addresses but there is space for them, we can add the addresses to the dictionary and set a corresponding count of 1. If the dictionary does not contain addresses and there is no space for them, the count corresponding to an address in the dictionary can be decremented by 1, and addresses associated with a count of 0 can be removed from the dictionary. Mesa-Gris identifies the most frequent elements in a stream, but it can also identify less frequent elements. Mesa-Gris may not guarantee that the identified elements are greater than a threshold that might lead to false positives. False positives may contain elements that do not meet the criteria but are still identified. Similar to a Bloom filter, Mesa-Gris identifies false positives but not false negatives. False negatives are elements that meet the criteria but are not identified.

[0021] The aspects of this disclosure address the above and other shortcomings by implementing control mechanisms in the front and / or back ends of the memory subsystem to refresh memory rows. These aspects can utilize smaller memory (e.g., SRAM) sizes and smaller maximum false positive rates, and will not pose a "denial of service" risk compared to various prior methods used to detect row hammer attacks. Although the examples provided herein are in the context of row hammer attacks, these examples can also be applied to data loss attributable to memory cell leaks caused by accessing memory cells or adjacent memory cells at rates greater than RHT.

[0022] In various instances, RHT and memory down-counters can be used to determine when to refresh rows of memory cells. As used herein, a memory down-counter can be implemented in Content Addressable Memory (CAM), which may be referred to as associative memory. The CAM compares input retrieval data with a stored data table. The CAM returns the address of the matching data. However, other types of memory can be used to store the memory down-counter. The memory down-counter can also be referred to as a CAM down-counter (CDC). The CDC can be used to track the number of times the counter corresponding to a row in the memory subsystem has been reduced. The CDC can be used to set a threshold for refreshing rows of memory cells under it; for example, it can be used to remove row counters from memory (e.g., CAM). Removing row counters from memory limits the amount of memory used to track access commands. Limiting the amount of memory used to track access commands saves power and memory resources. The lower bound of the error affirmation generated in the various instances described herein can be used to determine the size of the memory used to track access commands and their associated addresses. Given that the amount of false affirmations generated using the examples described herein can be less than the amount of false affirmations generated using the Mesa-Griss system, it may be beneficial to control the amount of false affirmations using the examples described herein compared to accepting false affirmations generated using the Mesa-Griss system.

[0023] Interfaces such as Peripheral Component Interconnect High Speed ​​(PCIe), Compute High Speed ​​Link (CXL), and Accelerator Cache Coherent Interconnect (CCIX) allow various memory devices to be connected to a host system. The combination of interface and memory technology improvements allows for the deployment of “remote memory,” which can consist of system memory (e.g., memory devices) implemented behind a memory subsystem such as PCIe, CXL, CCIX, GenZ, etc. As used herein, the front end of a memory subsystem may also be referred to as the interface of the memory subsystem or the front end of the controller of the memory subsystem. As used herein, the front end of a memory subsystem may include hardware and / or firmware configured to receive data (e.g., requests and / or data) and provide data to the back end of the memory subsystem. The back end of a memory subsystem may include hardware and / or firmware for receiving data (e.g., requests and / or data) from the front end of the memory subsystem and may include the ability to execute requests provided from the host to the memory devices of the memory subsystem.

[0024] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0025] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0026] The computing system 100 may be, for example, a desktop computer, a laptop computer, a server, a web server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car or other means of transport), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer contained in a vehicle, industrial equipment or a networked commercial device), or a computing device that includes memory and processing devices.

[0027] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediary component), whether wired or wireless, including connections such as electrical, optical, magnetic and the like.

[0028] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and to read data from memory subsystem 110.

[0029] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include (but are not limited to) Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Double Data Rate (DDR) memory bus, Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM slot interfaces supporting Double Data Rate (DDR)), Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize NVM High Speed ​​(NVMe) interface access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data and other signals between the memory subsystem 110 and the host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple individual communication connections, and / or combinations of communication connections.

[0030] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0031] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-situ write memory, such as a three-dimensional crosspoint (“3D crosspoint”) memory device, which is a crosspoint array of non-volatile memory cells. The crosspoint array of non-volatile memory can perform bit storage based on volume resistance variations combined with a stackable crossgate format data access array. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-situ write operations, where non-volatile memory cells can be programmed without previously erasing non-volatile memory cells. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0032] Each of the memory devices 130 and 140 may include one or more arrays of memory cells. One type of memory cell, for example, includes a single-level cell (SLC) where each cell can store one bit. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), can store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include SLC portions and MLC portions, TLC portions, QLC portions, or PLC portions of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0033] Although a non-volatile memory assembly and NAND-type memory (e.g., 2D NAND, 3D NAND) such as a three-dimensional cross-point array of non-volatile memory cells are described, memory device 130 may be based on any other type of non-volatile memory or storage device, such as (e.g.) read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0034] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-coded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0035] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0036] In some embodiments, local memory 119 may include memory registers storing memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although already Figure 1 The instance memory subsystem 110 is described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0037] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to memory devices 130 and / or 140. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling operations, discard item collection operations, error detection and error correction code (ECC) operations, encryption operations, caching operations, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses, physical media locations, etc.) associated with memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access memory devices 130 and / or 140, and translate responses associated with memory devices 130 and / or 140 into information for the host system 120.

[0038] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access memory devices 130 and / or 140.

[0039] In some embodiments, memory device 130 includes a local media controller 135, which operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a native memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0040] Memory subsystem 110 may include refresh circuitry system 113. Although Figure 1 While not shown in the diagrams to avoid confusion, refresh circuitry system 113 may include various circuitry systems for facilitating the determination of when to refresh rows of memory devices 130, 140. In some embodiments, refresh circuitry system 113 may include dedicated circuitry systems in the form of ASICs, FPGAs, state machines, and / or other logic circuitry systems, which may allow refresh circuitry system 113 to orchestrate and / or perform operations to selectively refresh rows of memory devices 130, 140 based on RHT and / or CDC.

[0041] In some embodiments, the memory subsystem controller 115 includes at least a portion of the refresh circuitry system 113. For example, the memory subsystem controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the refresh circuitry system 113 is part of the host system 110, an application program, or an operating system.

[0042] In a non-limiting example, the device (e.g., computing system 110) may include a memory subsystem refresh circuitry system 113. The refresh circuitry system 113 may reside on the memory subsystem 110. As used herein, the term "resides on" means something physically located on a particular component. For example, a refresh circuitry system 113 "resides" on memory subsystem 110 means that the hardware circuitry system including the refresh circuitry system 113 is physically located on memory subsystem 110. In this document, the term "resides on" may be used interchangeably with other terms such as "deployed on" or "located on".

[0043] The refresh circuitry 113 may subtract the CDC from the RHT to generate a threshold that can be used to determine whether to refresh rows of memory devices 130, 140. For example, the refresh circuitry 113 may track multiple counts corresponding to rows of memory subsystems 130, 140. As used herein, counts describe the sum of multiple events. For example, the count corresponding to a row may be the sum of the number of activation commands received by the memory subsystem controller 115 for a particular row. The refresh circuitry 113 may track the number of rows. For example, the refresh circuitry 113 may track the number of received activation commands for multiple rows.

[0044] Each row count can be compared to the difference between RHT and CDC (e.g., RHT-CDC). For example, if an activation is received for a specific row and the row count for that row is greater than the difference between RHT and CDC, then refresh circuitry 113 may avoid refreshing that row. If an activation is received for a specific row and the row count for that row is less than the difference between RHT and CDC, then refresh circuitry 113 may refresh the specific row and reset the row count corresponding to that row.

[0045] The refresh circuitry system 113 can also track the number of times the memory storing row counts is full. For example, whenever an activation command is received for a row in memory devices 130, 140 that does not have a corresponding row count stored in memory (e.g., CAM), the refresh circuitry system 113 can decrement each of the row counts stored in memory and increment CDC. Row counts equal to 0 can be deleted from memory (e.g., CAM) to track activation commands for untracked rows (e.g., specific rows). The row counts and / or other data can include a structure that may be called a counter. The counter can be stored in the CAM (e.g., memory). The counter can be an entry in the CAM. While the CAM may include hardware structures, the counter may include logical structures containing counts of rows corresponding to different memories.

[0046] Figure 2 This is a block diagram corresponding to refresh circuitry system 213 according to some embodiments of the present disclosure. Refresh circuitry system 213 includes a row counter 201, an RHT 202, and a CDC 203. In various instances, the row counter 201 and / or the RHT 202 and CDC 203 may be stored in memory. The memory may, for example, be... Figure 1 The local memory 119 and / or memory devices 130, 140. For example, the memory storing line counter 201 and CDC 203 may be a CAM. The memory storing RHT 202 may be a register in other possible types of memory that can be used to store line counter 201, CDC 203 and / or RHT 202.

[0047] Considering that RHT 202 may remain unchanged, RHT 202 may be static, or it may be dynamic, allowing RHT 202 to change over the lifetime of the memory device in the memory subsystem. Row counter 201 may be dynamic. Row counter 201 may be updated each time an activation command is received. For example, in response to receiving an activation command for a specific row, the count of the row counter stored in the CAM may be updated from a first count to a second count. Activation commands may include read commands and / or write commands, as well as other possible activation commands.

[0048] Figure 3 This is a flowchart corresponding to a refresh circuit system according to some embodiments of the present disclosure. In various examples, Figure 1 The refresh circuitry system 113 can perform operations corresponding to the flowchart. At operation 321, the CAM can be initialized and the CDC can be set to 0. Initializing the CAM may include setting the size of the CAM. The size of the CAM can be set based on a frequency target and maximum row activation during a time period. The frequency target can be a target number of activation commands that can be received and processed for a row during the time period. The frequency target can be less than or can represent the RHT of a time period and a specific row. Maximum row activation can describe the maximum number of times a specific row of the memory device can be activated within a time period. The size of the CAM can be expressed as maximum row activation (n) divided by the frequency target (F). In various examples, the size of the CAM can be selected in real time or pre-selected. For example, the CAM size can be selected before deploying the memory subsystem. For example, the CAM size can also be selected each time the computing system is initialized.

[0049] In various examples, the size of the CAM can also be set based on the desired false positive rate. For instance, the size of the CAM can increase as the false positive rate decreases. The size of the CAM can also decrease as the false positive rate increases. In various examples, a desired false positive rate can be selected, and the CAM size can be set based on the selected false positive rate.

[0050] At operation 322, a row activation command can be received. The row activation command can be received from the host. At operation 323, it can be determined whether the row counter corresponding to the row targeted by the row activation command is stored in the CAM. Each activation command can be associated with a row of the memory device. For example, an activation command (e.g., a read command or a write command, etc.) can be used to access a row of the memory device. The activation command can be received along with the address of the row targeted by the activation command. In various examples, the row address can be used as an identifier for the row, but different identifiers for the row can be used. The address of the row can be used to determine whether the row counter corresponding to a specific row is stored in the CAM. The address of a specific row can be used to query the CAM. If the row counter corresponding to a specific row is stored in the CAM, then the CAM can return the row counter and / or row count corresponding to the specific row. The row count can be represented as an incrementing or decrementing value. The CAM can return the value corresponding to the row count. If a value is received from the CAM, then the flowchart can proceed to operation 326. For example, if it is determined that the row counter and / or row count corresponding to the row associated with the activation command is stored in the CAM, then the flowchart may proceed to operation 326. If no value is received from the CAM (e.g., the CAM does not store the row counter and / or row count corresponding to the row), then the flowchart may proceed to operation 324. For example, if it is determined that the row counter corresponding to the row associated with the activation command is not stored in the CAM (e.g., it does not exist), then the flowchart may proceed to operation 324.

[0051] At operation 326, the row count can be incremented by 1. The incremented row count can correspond to the row targeted by the activation command (e.g., a row activation command). The flowchart can continue to operation 329. At operation 329, it can be determined whether the value of the row count corresponding to the row targeted by the activation command is greater than RHT minus CDC (row count > RHT - CDC).

[0052] If the row count is not greater than RHT minus CDC, the flowchart can continue to operation 332. If the row count is greater than RHT minus CDC, the flowchart can continue to operation 331.

[0053] At operation 331, the row targeted by the activation command can be refreshed, and the row counter can be deleted from the CAM. The row counter can be deleted from the CAM by deleting the value corresponding to the row count. In various examples, Figure 1 The refresh circuitry system 113 can refresh the corresponding row from the memory device. For example, Figure 1The refresh circuitry 113 can provide signals to the processing apparatus of the control circuitry of the memory subsystem to cause rows of the memory device to be refreshed. Deleting the row counter from the CAM reduces the size of the CAM compared to not deleting it each time a row is refreshed. Since setting the row count to 0 does not reduce the size of the CAM, deleting the row counter from the CAM can be different from setting the row count to 0. At operation 332, the refresh circuitry can wait to receive an additional activation command (e.g., a row activation command).

[0054] At operation 324, it can be determined whether the CAM has space. For example, it can be determined whether the CAM can store an additional row counter corresponding to the row targeted by the activation command. If the CAM has space to store the additional row counter, the flowchart can continue to operation 327. If the CAM does not have space to store the additional row counter, the flowchart can continue to operation 325.

[0055] At operation 327, a row counter can be inserted into the CAM, and the row counting of the row counter can be started with a specific value, such as 1. The row counter can be inserted into the CAM using, for example, the address of the row and the identifier of the row count (e.g., a specific value). The flowchart can continue to operation 332.

[0056] At operation 325, the row count in the CAM can be decremented (e.g., reduced) by 1. The row count decremented by 1 can include the row count corresponding to the row targeted by the activation command and other row counts stored in the CAM. At operation 325, it can also be determined whether any row count has a value equal to 0. If a row count has a value equal to 0, then the corresponding row counter can be deleted from the CAM. The flowchart can continue to operation 328.

[0057] At operation 328, increment CDC by 1. Incrementing CDC reflects that the row count of CAM has been decremented by 1. CDC reflects the number of times the row count of CAM has been decremented by 1 in a given time period. The flowchart can continue to operation 332.

[0058] Figure 4 This is a flowchart corresponding to method 441 for refreshing rows according to some embodiments of the present disclosure. Method 441 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 441 is performed by... Figure 1The refresh circuitry system 113 performs the operation. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0059] At operation 442, a row activation command with a row address can be received at the control circuitry of the memory subsystem. The refresh circuitry of the control circuitry can receive the activation command. For example, the refresh circuitry of the control circuitry can intercept the activation command (e.g., several activation commands). The row activation command can be received from the host. At operation 443, a first count of the row counter corresponding to the row address can be incremented. The first counter can be stored in the content-addressable memory (CAM) of the memory subsystem. The first count can be incremented by a predetermined amount. For example, the first count of the row counter can be incremented by 1 or by a value greater than 1.

[0060] At operation 444, it can be determined whether a first count is greater than a second count (e.g., RHT minus CDC). This determination can be made at the control circuitry of the memory subsystem. The second count of CDC can be incremented whenever the CAM is full. For example, the second count can be incremented whenever the CAM is adjusted to make room for the row counter corresponding to the row address. At operation 445, in response to determining that the first count is greater than RHT minus the second count, a refresh command can be issued to the row address. The first count being less than RHT minus the second count can indicate that processing the access command will not have a negative impact. For example, RHT minus the second count can create a new threshold, which can be used to determine whether accessing a memory cell with a row address is safe. If the first count is greater than the new threshold (RHT minus the second count), then the refresh circuitry can determine that accessing the memory cell with the address without refreshing the memory cell with the address before processing the access command is unsafe. In various examples, the access command can be ignored instead of issuing a refresh command in response to the first counter being greater than the new threshold (RHT minus the second count).

[0061] In response to determining that the first count is greater than RHT minus the second count (RHT - second count), a row counter can be deleted from the CAM. Deleting a row counter from the CAM may include making memory cells of the CAM available to store row counters corresponding to different addresses. For example, deleting a row counter corresponding to a row address from the CAM may include deassociating the row counter with the row address. Deleting a row counter may also include associating the row counter with a different row address. Deleting a row counter may also include resetting the first count of the row counter. The first count may be represented as a value stored in the CAM. Thus, resetting the first count may include including a default value in the portion of the row counter stored in the CAM associated with the row address. Incrementing or decrementing the first count may include adding or subtracting from the value stored in the portion of the CAM associated with the row counter.

[0062] In various examples, multiple counts in the CDC containing the second count can be initialized to 0 before receiving row activation commands. For example, the second count can be initialized to 0 before incrementing or decrementing the count stored in the CAM. The size of the CAM can be set based on a target frequency of row activation commands less than the RHT. The size of the CAM can also be set based on the maximum number of row activations within a time period. The frequency target is defined as the number of row activation commands expected to be received for a row address within a time period. The size of the CAM can be set to n / F, where n is the maximum row activation within the time period. The maximum row activation describes the maximum number of row activation commands that can be received for a row address within the time period. Setting the size of the CAM to n / F reduces the size of the CAM compared to all row addresses of the tracking memory device. In various instances, the frequency target can be less than the RHT, such that the size of the CAM can be proportional to a value less than the RHT.

[0063] In various examples, a row activation command with a row address of the memory device can be received at the control circuitry of the memory subsystem. In response to determining that a row counter corresponding to the row address is stored in the CAM, a first count of the row counter corresponding to the row address stored in the CAM can be incremented. For example, the first count can be incremented by 1 whenever an access command with a row address is received by the memory subsystem.

[0064] It can be determined whether the first count is greater than the second count of RHT minus CDC, where CDC stores the number of times different row addresses have been unassociated from the CAM once it is full. Before incrementing the row counter, it can be determined whether the row counter is stored in the CAM. For example, it can be determined whether the row address corresponding to the access command is associated with a portion of the CAM. If the row address is associated with a portion of the CAM (e.g., the row counter), then it can be determined that the row counter is stored in the CAM. If the row counter is stored in the CAM, then the first count of the row counter can be incremented.

[0065] If it is determined that a row address is not associated with any part of the CAM, then it can be determined that the row counter corresponding to the row address is not stored in the CAM. In response to determining that the row counter is not stored in the CAM, it can be determined whether the CAM has space to store the row counter. If at least a portion of the CAM is not associated with any row address, then the CAM may have space to store the row counter. In response to determining that the CAM has space to store the row counter (e.g., at least a portion of the CAM is not associated with any row address), the row counter associated with the row address of the access command may be stored in the CAM. In response to storing the row counter in the CAM, a first count of the row counter may be set to 1. In response to setting the first count to 1, the refresh circuitry of the memory subsystem may wait for the next row access command. In response to determining that the first counter is greater than RHT minus CDC, a refresh command may be issued to the row address, after which the refresh circuitry may wait for the next row access command.

[0066] In response to determining that the CAM does not have space to store a counter, multiple counts in the CAM containing the first count can be decremented. In response to determining that the CAM does not have space to store a row counter, multiple counts with zero values ​​and any of the corresponding row counters are deleted to deassociate the specific row corresponding to the deleted count from the CAM. In response to determining that the CAM does not have space to store a row counter, a second count in the CDC can be incremented.

[0067] In various examples, a row activation command pointing to a row address of a memory device can be received. The row address may correspond to a row in the memory device. It can be determined whether a row counter corresponding to the row address is stored in the CAM. In response to determining that the row counter corresponding to the row address is stored in the CAM, it can be determined whether a first count of the row counter is greater than the difference between a second count of the RHT and the CDC, where the CDC stores the number of times different row addresses have been deassociated from the CAM once it is full. In response to determining that the first count is greater than the difference between the RHT and the second count, a refresh command can be issued to the row address.

[0068] In response to determining that the first count is greater than the difference between the RHT and the second count, the row counter corresponding to the row address can be deleted from the CAM. In various examples, the first count of the row counter can be reset instead of deleting the row counter from the CAM. The row counter can be deleted from the CAM by deassociating the row address corresponding to the row counter with a portion of the CAM or by deassociating the row address corresponding to the row counter with each of the portions of the CAM.

[0069] After determining that the row counter corresponding to the row address is not stored in the CAM, it can be determined whether the CAM has space to store the row counter. In response to determining that the CAM does not have space to store the row counter, multiple counts of the multiple row counters stored in the CAM can be decremented. For example, each of the multiple counts stored in the CAM can be decremented by 1. In response to decrementing the multiple counts, it can be determined whether any of the multiple counts is equal to 0. In response to determining that at least one of the multiple counts is equal to 0, the corresponding row counter can be deleted from the CAM. The corresponding row counter can be deleted from the CAM by deassociating the corresponding row address with any part of the CAM. In response to deleting the corresponding row counter from the CAM, the CDC can be incremented. The CDC can be incremented by adding a second value. For example, the second value of the CDC can be incremented by 1 or by a different setting value.

[0070] Figure 5 This is a block diagram of an example computer system 500 in which embodiments of this disclosure may operate. For example, Figure 5 An example machine illustrating computer system 500 is described, within which a set of instructions is executable to cause the machine to perform any or more of the methodologies discussed herein. In some embodiments, computer system 500 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1 (Operation of the refresh circuitry system 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer-to-peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0071] A machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network device, a server, a network router, a switch, or a bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by said machine. Furthermore, while describing a single machine, the term "machine" should also be considered as any collection of machines that individually or jointly execute a set (or more) of instructions to perform any or more of the methodologies discussed herein.

[0072] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), static memory 506 (e.g., flash memory, static random access memory (SRAM)), and a data storage system 518, which communicate with each other via a bus 530.

[0073] Processing device 502 represents one or more general-purpose processing devices, such as microprocessors, central processing units, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or multiple processors implementing combinations of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 may further include a network interface device 508 for communication via network 520.

[0074] Data storage system 518 may include machine-readable storage medium 524 (also referred to as computer-readable medium) storing one or more sets of instructions 526 or software embodying any or more of the methodologies or functions described herein. Instructions 526 may also reside wholly or at least partially within main memory 504 and / or processing device 502 during execution by computer system 500, which also constitute machine-readable storage medium. Machine-readable storage medium 524, data storage system 518, and / or main memory 504 may correspond to... Figure 1 The memory subsystem 110.

[0075] In one embodiment, instruction 526 includes implementing a refresh circuitry system (e.g., Figure 1 The refresh circuitry system 113) contains functional instructions. Although the machine-readable storage medium 524 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any or more of the methodologies of this disclosure. The term "machine-readable storage medium" should accordingly include (but is not limited to) solid-state memory, optical media, and magnetic media.

[0076] Some parts of the foregoing detailed description have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. The algorithms described herein are generally conceived as self-consistent sequences of operations that lead to desired results. An operation is an operation that requires the physical manipulation of physical quantities. Typically, although not always necessary, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that, primarily for common use, it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, or similar terms.

[0077] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels for application to those quantities. This disclosure may relate to the operation and processes of a computer system or similar electronic computing device that manipulate and transform data representing physical (electronic) quantities in the registers and memories of the computer system into other data similarly represented in the memory or registers of the computer system or other such information storage systems.

[0078] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0079] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used in conjunction with programs taught herein, or it may be proven convenient to construct more specialized devices to implement the methods. The architectures of many such systems will appear as described below. Furthermore, this disclosure is not described with reference to any particular programming language. It should be understood that various programming languages ​​can be used to implement the teachings of this disclosure as described herein.

[0080] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable to program a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any means for storing information in a form readable by a machine (e.g., a computer). In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0081] In the foregoing description, embodiments thereof have been described with reference to specific examples of this disclosure. It will be understood that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be regarded in an illustrative rather than restrictive sense.

Claims

1. A method comprising: The control circuitry of the memory subsystem receives a row activation command with a row address. Increment the first count of the row counter corresponding to the row address in the content-addressable memory CAM of the memory subsystem; At the control circuit system, it is determined whether the first count is greater than the second count of the row hammer threshold RHT minus the CAM decrement counter CDC, wherein the second count is incremented each time the CAM is full; and In response to determining that the first count is greater than the RHT minus the second count, a refresh command is issued to the row address.

2. The method of claim 1, further comprising deleting the row counter corresponding to the row address from the CAM in response to determining that the first count is greater than the RHT minus the second count.

3. The method of claim 1, further comprising initializing a plurality of CDCs containing the CDCs up to 0 before receiving the row activation command.

4. The method of claim 1, wherein incrementing the first count of the row counter includes incrementing the first count of the row counter in response to determining that the row counter is stored in the CAM.

5. The method of claim 1, further comprising setting the size of the CAM based on a frequency target for the row activation command.

6. The method of claim 1, further comprising setting the size of the CAM based on a frequency target smaller than the RHT for the row activation command.

7. The method of claim 1, further comprising setting the size of the CAM based on the maximum number of row activations within a specific period.

8. An apparatus comprising: Content-Addressable Memory (CAM); Memory devices; and A control circuit system, coupled to the memory device and configured to: Receive a row activation command having the row address of the memory device; In response to determining that a row counter corresponding to the row address is stored in the CAM, the first count of the row counter is incremented; Determine whether the first count is greater than the row hammer threshold RHT minus the second count of the CAM decrement counter CDC, wherein the CDC stores the number of times different row addresses have been unassociated with the CAM once the CAM is full; and In response to determining that the first count is greater than the RHT minus the second count, a refresh command is issued to the row address.

9. The device of claim 8, wherein the control circuitry is further configured to determine whether the CAM has space to store the row counter in response to determining that the row counter is not stored in the CAM.

10. The device of claim 9, wherein the control circuitry is further configured to store the row counter in the CAM in response to determining that the CAM has space for storing the row counter.

11. The device of claim 9, wherein the control circuitry is further configured to decrement a plurality of counts of the CAM containing the first count in response to determining that the CAM does not have space to store the row counter.

12. The device of claim 11, wherein the control circuitry is further configured to, in response to determining that the CAM does not have space to store the row counters, delete any of the plurality of counts having a zero value to deassociate the specific row corresponding to the deleted count from the CAM.

13. The device of claim 11, wherein the control circuitry is further configured to increment the second count of the CDC in response to determining that the CAM does not have space to store the counter.

14. An apparatus comprising: Content-Addressable Memory (CAM); Memory devices; A control circuit system, coupled to the memory device and configured to: Receive a row activation command pointing to the row address of the memory device; Determine whether the row counter corresponding to the row address is stored in the CAM; In response to determining that the row counter corresponding to the row address is stored in the CAM, it is determined whether a first count of the row counter is greater than the difference between the row hammer threshold RHT and the second count of the CAM decrement counter CDC, wherein the CDC stores the number of times different row addresses have been de-associated with the CAM once the CAM is full; and In response to determining that the first count is greater than the difference between the RHT and the second count, a refresh command is issued to the row address.

15. The device of claim 14, wherein the control circuitry is further configured to delete the row counter corresponding to the row address from the CAM in response to determining that the first count is greater than the difference between the RHT and the second count.

16. The device of claim 14, wherein the control circuitry is further configured to determine whether the CAM has space to store the row counter after determining that the row counter corresponding to the row address is not stored in the CAM.

17. The device of claim 16, wherein the control circuitry is further configured to decrement a plurality of counts of a plurality of row counters stored in the CAM in response to determining that the CAM does not have space for storing the row counters.

18. The device of claim 17, wherein the control circuitry is further configured to determine, in response to decrementing the plurality of counts, whether any one of the plurality of counts is equal to 0.

19. The device of claim 18, wherein the control circuitry is further configured to delete a corresponding row counter from the CAM in response to determining that at least one of the plurality of counts is equal to 0.

20. The device of claim 17, wherein the control circuitry is further configured to increment the second count of the CDC in response to decrementing the plurality of counts.

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