Execution of write commands for data protection and recovery schemes

Abstract

This disclosure relates to write command execution for data protection and recovery schemes. One or more data blocks of a write command can be written to a memory device independently of other data blocks grouped together for error correction operations on said data blocks. Furthermore, data blocks of different write commands can be executed together and simultaneously, rather than individually at different times, which can reduce the latency associated with executing said write commands.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor memories and methods, and more specifically to apparatus, systems and methods relating to the execution of write commands for data protection and recovery schemes. Background Technology

[0002] Memory devices are typically provided as internal semiconductor integrated circuit systems in computers or other electronic systems. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory requires power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM), etc. Non-volatile memory provides persistent data by retaining the stored data when no power is applied and includes NAND flash memory, NOR flash memory, ferroelectric random access memory (FeRAM), and resistive variable memory (e.g., phase-change random access memory (PCRAM)), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), etc.

[0003] A memory device may be coupled to a host computer (e.g., a host computing device) to store data, commands, and / or instructions for use by the host computer or electronic system while it is operating. For example, during the operation of a computing or other electronic system, data, commands, and / or instructions may be transferred between the host computer and the memory device. A controller may be used to manage the transfer of data, commands, and / or instructions between the host computer and the memory device. Summary of the Invention

[0004] On one hand, this disclosure provides a method for executing a write command, comprising: receiving a write command for writing a first user data block corresponding to a first channel coupled to one of a plurality of memory devices, wherein the first user data block is one of a group of data blocks as a unit of read access, and the data blocks are grouped together for error correction operations; and in response to the write command: retrieving a parity data block corresponding to a second channel and grouped together with the first user data block; updating the parity data block at least in part based on the first user data block; and writing the first user data block and the updated parity data block, independently of other user data blocks grouped together with the parity data block or the first data block, to memory devices respectively coupled to the first and second channels.

[0005] On the other hand, this disclosure further provides an apparatus for executing a write command, comprising: a plurality of memory devices coupled to a plurality of channels, the plurality of memory devices configured to store array data blocks, each array data block comprising a corresponding user data block grouped together for error correction operations and one or more parity blocks; and a controller coupled to the plurality of memory devices and configured to: receive a write command for writing a first user data block corresponding to a first group of user data blocks to a first location in the plurality of memory devices; in response to receiving the write command, retrieve a corresponding data block corresponding to the first group from the plurality of memory devices; update the retrieved one or more parity blocks at least in part based on the first user data block; and, independently of other data blocks in the first group, write the first user data block and the updated one or more parity blocks to the corresponding memory devices in the plurality of memory devices.

[0006] On the other hand, this disclosure further provides a method for executing write commands, comprising: receiving a plurality of write commands for writing corresponding user data blocks to memory devices respectively coupled to a plurality of channels, wherein each user data block in the corresponding user data block corresponds to a group of corresponding data blocks as a unit of read access, and the data blocks are grouped together for error correction operations; selecting, among the plurality of write commands, a write command having user data blocks for different memory devices; and, in order to execute the selected write command simultaneously, writing the user data blocks of the selected write command simultaneously to the different memory devices.

[0007] On the other hand, this disclosure further provides an apparatus for executing write commands, comprising: a plurality of memory devices coupled to a plurality of channels; and a controller coupled to the plurality of memory devices; the controller being configured to: receive a plurality of write commands; and in response to receiving the plurality of write commands: update parity data blocks corresponding to user data blocks of the plurality of write commands respectively; among the plurality of write commands, select a write command having user data blocks and corresponding parity data blocks for different memory devices among the plurality of memory devices; and simultaneously write the user data blocks and corresponding parity data blocks of the selected write command to the different memory devices. Attached Figure Description

[0008] Figure 1 This is a functional block diagram of a computing system including a memory controller according to several embodiments of the present disclosure.

[0009] Figure 2 This is a functional block diagram of a memory controller having a first configuration according to several embodiments of the present disclosure.

[0010] Figure 3 This is a timing diagram of several embodiments of the present disclosure associated with executing host write commands in a non-cached architecture.

[0011] Figure 4 This is a timing diagram associated with executing host write commands in a cache architecture according to several embodiments of the present disclosure.

[0012] Figure 5 This is a block diagram associated with executing a write command according to several embodiments of the present disclosure.

[0013] Figure 6 This is a block diagram associated with executing a write command selected according to several embodiments of this disclosure.

[0014] Figure 7 This is a flowchart of a method for independently executing write commands according to several embodiments of the present disclosure.

[0015] Figure 8 This is a flowchart of a method for independently executing write commands according to several embodiments of the present disclosure. Detailed Implementation

[0016] This describes systems, devices, and methods related to the execution of write commands for data protection and recovery schemes. Data protection and recovery schemes are typically an important aspect of the RAS (Reliability, Availability, and Serviceability) associated with memory systems. Such schemes provide "chip kill," where the memory system can continue to function correctly even if the constituent chips (e.g., memory dies) are damaged; thereby avoiding a single point of failure (SPOF) situation where one of the chips is the memory system. Chip kill capabilities are typically provided through various error correction code (ECC) schemes, including Redundant Array of Independent Disks (RAID) schemes, Low-Power Chip Kill (LPCK) schemes, etc., which allow data recovery from damaged chips by reading all constituent chips of the memory system.

[0017] Chip hunting can involve ECC data (e.g., RAID parity or LPCK parity) specifically designed for data recovery from damaged chips. ECC data and user data sharing the same ECC data can be referred to as being grouped together (e.g., spanning multiple memory devices or channels in the form of codewords and / or stripes). Alternatively, codewords and / or stripes can contain user data and ECC data shared by the user data.

[0018] Typically, a block of data containing at least one codeword and / or stripe and distributed across different chips can be used as the unit of read and write access, such that subsets of the block are always read or written together. For example, writing new data to replace one of the subsets can be accomplished by reading the block, updating the block's ECC data to conform to the new data, and writing the block with the replacement subset back to the chip. However, this ECC scheme can sometimes be inefficient because other subsets (other than the replaced subset) that do not contain any changes to the constituent bits are also read / written back. Furthermore, ECC data is often stored in a dedicated channel, making it difficult / impossible to combine subsets of different blocks to be written to the memory device simultaneously, since ECC data of different subsets cannot be written to the same dedicated channel at the same time.

[0019] In contrast, the embodiments described herein are data protection schemes involving the independent execution of write commands (e.g., host write commands). In several embodiments, for example, each subset of a block containing one or more codewords may be the unit of write access (rather than the block itself being the unit of write access), which allows a subset containing new data to be written to the chip without writing other subsets back to the chip along with said subsets. Therefore, the various embodiments described herein can save memory system resources by avoiding unnecessary write accesses. Furthermore, parity rotation can be implemented on the memory system of the embodiments described herein, such that ECC data for different blocks can be transmitted via different channels (e.g., stored in memory devices coupled to different channels), which allows resources freed up from avoiding blocks becoming the unit of write access to also be used for other host write commands. In some embodiments, for example, other host write commands can be executed while the first host write command is being executed.

[0020] As used herein, the singular forms “a / an” and “the” include both singular and plural indicators unless the content expressly indicates otherwise. Furthermore, the word “may” is used throughout this application in a permissive sense (i.e., possible, able) rather than a mandatory sense (i.e., required). The term “comprising” and its derivatives mean “including (but not limited to)”. The term “coupled” means a direct or indirect connection. It should be understood that data can be transmitted, received, or exchanged via electronic signals (e.g., current, voltage, etc.), and the phrase “signal indicating [data]” refers to the data itself being transmitted, received, or exchanged in a physical medium.

[0021] The diagrams in this document follow a numbering convention, where the first one or a few digits correspond to the diagram number, and the remaining digits identify the elements or components within the diagram. Similar elements or components between different diagrams can be identified using similar digits. For example, 110 could refer to... Figure 1 Component "10" in the text, and similar components in Figure 2The symbol 210 can be used as a reference. Similar elements within the diagram can be referenced using hyphens followed by additional numbers or letters. For example, see [reference 210]. Figure 1 Elements 102-1, 102-2, and 102-M are used in the figures. Such similar elements may generally be referred to without hyphens and additional numbers or letters. For example, elements 102-1, 102-2, and 102-M may be collectively referred to as element 102. As used herein, particularly with respect to reference numerals in the figures, the indicators “M” and “N” indicate that several specific features may be included. It will be understood that elements shown in the various embodiments herein may be added, interchanged, and / or eliminated to provide several additional embodiments of this disclosure. Furthermore, it should be understood that the scale and relative dimensions of the elements provided in the figures are intended to illustrate certain embodiments of the invention and should not be construed as limiting.

[0022] Figure 1 This is a functional block diagram of a computing system 101 including a memory controller 100 according to several embodiments of the present disclosure. The memory controller 100 may include a front-end portion 104, a central controller portion 110, and a back-end portion 119. The computing system 101 may include a host 103 and memory devices 126-1, ..., 126-N coupled to the memory controller 100.

[0023] The front-end portion 104 includes an interface and interface management circuitry for coupling the memory controller 100 to the host 103 via input / output (I / O) paths 102-1, 102-2, ..., 102-M, and circuitry for managing the I / O paths 102. Any number of I / O paths 102 may exist, such as eight, sixteen, or another number of I / O paths 102. In some embodiments, the I / O path 102 may be configured as a single port.

[0024] In some embodiments, memory controller 100 may be a compute-fast link (CXL) compliant memory controller. The host interface (e.g., front-end portion 104) is managed using the CXL protocol and coupled to host 103 via an interface configured for the Peripheral Component Interconnect Fast (PCIe) protocol. CXL is a high-speed central processing unit (CPU)-to-device and CPU-to-memory interconnect designed to accelerate next-generation data center performance. CXL technology maintains memory coherence between the CPU memory space and the memory on the attached device, allowing resource sharing for higher performance, reduced software stack complexity, and lower overall system cost. CXL is designed as an industry-open standard interface for high-speed communication, as accelerators are increasingly used to complement CPUs to support emerging applications such as artificial intelligence and machine learning. CXL technology is built on PCIe infrastructure, thereby leveraging PCIe physical and electrical interfaces to provide advanced protocols in areas such as input / output (I / O) protocols, memory protocols (e.g., initially allowing hosts and accelerators to share memory), and coherence interfaces.

[0025] The central controller section 110 may include and / or be referred to as a data management circuitry. The central controller section 110 may control the execution of memory operations in response to a request received from the host 103. Examples of memory operations include read operations for reading data from the memory device 126 or write operations for writing data to the memory device 126.

[0026] The central controller section 110 can generate error detection information and / or error correction information based on data received from the host 103. The central controller section 110 can perform error detection operations and / or error correction operations on data received from the host 103 or from the memory device 126. An example of an error detection operation is a Cyclic Redundancy Check (CRC) operation. CRC can be referred to as algebraic error detection. CRC may contain a check value derived from an algebraic calculation using the data to be protected. CRC can detect unexpected changes to data by comparing a check value stored in association with the data with a check value calculated based on the data. An example of an error correction operation is a chip kill operation, such as the LPCK operation, and the error correction information may include LPCK parity checks, etc.

[0027] Back-end portion 119 may include a media controller and a physical (PHY) layer that couples memory controller 100 to memory device 126. As used herein, the term "PHY layer" generally refers to the physical layer in the Open Systems Interconnection (OSI) model of a computing system. The PHY layer may be the first (e.g., lowest) layer of the OSI model and may be used to transmit data via a physical data transmission medium. In some embodiments, the physical data transmission medium may include channels 125-1, ..., 125-N. Channels 125 may include various types of data buses, such as a sixteen-pin data bus and a two-pin data mask inversion (DMI) bus, as well as other possible buses.

[0028] An example of memory device 126 is a dynamic random access memory (DRAM) operating according to a protocol such as Low Power Double Data Rate (LPDDRx), which may be referred to herein as an LPDDRx DRAM device, LPDDRx memory, etc. The "x" in LPDDRx refers to any of several generations of protocols (e.g., LPDDR5). In at least one embodiment, at least one of memory devices 126-1 is operated to enable low-power features of the LPDDRx DRAM device, and at least one of memory devices 126-N is operated to disable at least one low-power feature of the LPDDRx DRAM device. In some embodiments, although memory device 126 is an LPDDRx memory device, memory device 126 does not include circuitry configured to provide low-power functionality for memory device 126, such as a Dynamic Voltage Frequency Scaling Core (DVFSC), Subthreshold Current Reduction Circuit (SCRC), or other low-power functionality providing such circuitry. Providing an LPDDRx memory device 126 without such circuitry can advantageously reduce the cost, size, and / or complexity of the LPDDRx memory device 126. As an example, the LPDDRx memory device 126, which provides reduced low-power functionality for the circuitry system, can be used for applications other than mobile applications (e.g., if the memory is not intended for mobile applications, some or all of the low-power functionality can be sacrificed to reduce the cost of producing the memory).

[0029] Data may be transmitted between the back-end section 119 and the memory device 126 in the form of memory transfer blocks and / or data blocks. The term "data block" refers to a group of data bits transmitted (e.g., read and / or written) over a single channel 125 at its operating (e.g., predefined) burst length (e.g., 32-bit burst length "BL").

[0030] A burst (having a burst length) is a series of data transfers within multiple cycles (e.g., ticks). For example, a 32-bit burst length may consist of 32 ticks of data transfers. In an exemplary embodiment, each channel 125 may consist of 8 DQs, such that 8 bits are transferred within each tick of the burst length, resulting in 16 bits being transferred to and / or from the memory device 126 at a time (e.g., each tick of each burst length).

[0031] The term "memory transfer block" refers to a group of data blocks that are transmitted (e.g., read and / or written) over the burst length (e.g., 32-bit BL) of the memory controller 100 via channel 125. The data block may be a user data block containing host data (e.g., data received from host 103, and alternatively referred to as user data) or a parity data block containing error correction information configured for chip-hunting operations on user data blocks grouped together with the parity data block. Furthermore, as used herein, a group of data blocks may refer to data blocks grouped together (e.g., user / parity data blocks). As used herein, user data blocks sharing the same parity data block may be referred to as being grouped together (along with the parity data block) for error correction operations, such as chip-hunting operations (e.g., LPCK operations). Therefore, user data blocks and parity data blocks grouped together can be read together for chip-hunting operations such as LPCK operations.

[0032] The host data or error correction information of a single user data block may correspond to multiple codewords transmitted over a predefined burst length. As an example, data transmitted to and / or from each memory device 126 in each clock cycle of a 32-bit BL may correspond to 4 codewords. This results in a single data block (e.g., a user data block and / or a parity data block) containing data corresponding to 128 codewords (e.g., 32BL * 4 codewords / clock cycle = 128 codewords) being transmitted to and / or from each memory device 126 via a 32-bit BL. In some embodiments, the error correction information may be parity data configured for a chip-hunting operation, such as LPCK operation.

[0033] Memory device 126 can be configured in various ways for (alternatively referred to as "configured to store") parity data blocks. In one example, one of the memory devices 126 may be configured for parity data blocks. In another example, parity data blocks may be distributed (e.g., uniformly) across memory devices 126. As an example, each memory device 126 may be configured for a single parity data block, such that no more than a single parity data block is stored in each memory device 126.

[0034] In some embodiments, grouped data blocks may be read as a unit of access. For example, all grouped data blocks may be read to memory controller 100 even when a host read command (e.g., a read command received from host 103) is received to read only one of the data blocks. As further described herein, the data blocks read together may be used for chip-hunting operations at memory controller 100, and only the data blocks requested by a host write command may be further sent to host 103. In some embodiments, each of the grouped data blocks may be written as a unit of access. Alternatively, each data block may be written individually to memory device 126 without being written together with other grouped data blocks.

[0035] In some embodiments, the memory controller 100 may include a management unit 105 for initializing, configuring, and / or monitoring the characteristics of the memory controller 100. The management unit 105 may include an I / O bus for managing out-of-band data and / or commands, a management unit controller for executing instructions associated with initializing, configuring, and / or monitoring the characteristics of the memory controller, and a management unit memory for storing the characteristics associated with initializing, configuring, and / or monitoring the characteristics of the memory controller 100. As used herein, the term "out-of-band" generally refers to a transmission medium different from the primary transmission medium of the network. For example, out-of-band data and / or commands may be data and / or commands transmitted to the network using a different transmission medium than that used to transmit data within the network.

[0036] Figure 2 This is a functional block diagram of a memory controller 200 having a first configuration according to several embodiments of the present disclosure. As shown in Figure 2 As shown, the front-end portion 204 may include an interface 206, which includes multiple I / O paths 202-1, 202-2, ..., 202-M, and an interface management circuitry 208 for managing the interface 206. An example of the interface 206 is a Peripheral Component Interconnect Fast (PCIe) 5.0 interface. In some embodiments, the memory controller 200 may receive access requests relating to at least one of the high-speed memory 212 and memory devices 226-1, 226-2, ..., 226-(N-1), 226-N via the interface 206 according to the CXL protocol. The interface 206 can access data from the host (e.g., ...) via I / O path 202. Figure 1 The host 103 shown receives data. The interface management circuitry 208 can use the CXL protocol to manage the interface 206 and can be referred to as the CXL interface management circuitry 208. The CXL interface management circuitry 208 can be coupled to the host via the PCIe interface 206.

[0037] Data management circuitry 210 may be coupled to interface management circuitry 208. Data management circuitry 210 may be configured to enable memory operations. Data management circuitry 210 may include at least one of error detection circuitry 211 (e.g., a "CRC circuitry") and error correction circuitry 216. Error detection circuitry 211 may be configured to perform error detection operations on data. For example, error detection circuitry 211 may be configured to generate a checksum derived from an algebraic calculation of data received from interface management circuitry 208, and transmit the checksum to at least one of cache memory 212, buffer 213, and media control circuitry 220. The checksum may be referred to as CRC data or error detection data.

[0038] In some methods for LPDDRx memory, the checksum is stored in blocks along with the data (user data) in the same DRAM row as the user data in memory device 226. This reduces the overall capacity of memory device 226 to store user data. For LPDDRx memory, this method results in read amplification, where for a host read, the requested data is read from memory device 226, and the corresponding checksum is also read from memory device 226. Data can be accessed in 32-byte granularity, and CRC data can be accessed as 16 bytes, resulting in a read amplification factor of 1.5. However, according to at least one embodiment of this disclosure, the LPDDRx memory is modified such that the DRAM row is expanded to account for CRC data, so that a host reading in 32-byte granularity generates the requested read data and the corresponding CRC data without additional reads, thereby producing a read amplification factor of 1 (e.g., zero amplification).

[0039] In at least one embodiment, the error detection circuitry is configured to perform error detection on data received from the interface management circuitry, which is then cached and / or processed by the error correction circuitry 216. Another example of the error detection operation is generating a checksum derived from an algebraic calculation of data received from the media control circuitry, and comparing this checksum with a checksum received from the media control circuitry 220 to determine whether the data contains an error (e.g., if the two checksums are not equal).

[0040] Data management circuitry system 210 may include cache memory 212 for storing data, error detection information, error correction information, and / or metadata associated with the execution of memory operations. An example of cache memory 212 is a 32 (32)-way set-associative cache containing multiple cache lines. The cache line size may be equal to or greater than the access granularity of memory controller 200 (e.g., 64 bytes for the CXL protocol). For example, each cache line may contain 256 bytes of data. In another example, each cache line may contain 512 bytes of data. Read and write requests in the CXL memory system may be 64 bytes in size. Therefore, data entries in cache memory 212 may have 64 bytes of data. Each cache line may include 256 bytes. Therefore, multiple 64-byte requests can be stored in each cache line. In response to a request from the host, memory controller 200 may write 256 bytes of data to memory device 226. In some embodiments, 256 bytes of data may be written into user data blocks, which may be 64-byte blocks. Using cache memory 212 to store data associated with read or write operations improves the speed and / or efficiency of data access because cache memory 212 can prefetch data in the event of a cache miss and store the data in multiple 64-byte blocks. In the event of a cache miss, data can be read from cache memory 212 instead of searching a separate memory device. Accessing prefetched data requires less time and energy compared to a memory system that must first search for and then access the data.

[0041] The data management circuitry 210 may include a buffer 213 to store data, error detection information, error correction information, and / or metadata that are operated on by another component of the data management circuitry 210 (e.g., error detection circuitry 211, error correction circuitry 216, and low-power chip killer circuitry 214). The buffer 213 may allow temporary storage of information, for example, when another component of the data management circuitry 210 is busy. In some embodiments, the cache memory 212 may be used to temporarily store data, and the buffer 213 may be used to temporarily store other information associated with the data, such as error detection information, error correction information, and / or metadata.

[0042] The data management circuitry may include a low-power chip kill (LPCK) circuitry 214 coupled between the error detection circuitry 211 and the error correction circuitry 216. The LPCK circuitry 214 may be configured to perform operations associated with parity data, such as providing chip kill protection and / or updating parity data based on new host data. In some embodiments, chip kill protection provided to memory device 226 may be LPCK. LPCK protection against any single memory device 226 (chip) failure and / or multi-bit errors from any portion of a single memory chip may be provided across subsets of memory devices 226 (e.g., LPCK may be provided for a first subset of memory devices 226-1, 226-2 and separately for a second subset of memory devices 266-(N-1), 226-N) or may be implemented jointly across all memory devices 226.

[0043] An example chip-hunting implementation of a memory controller 200 comprising an eleven-channel 225 bus with a width of 176 bits coupled to eleven memory devices 226 may include writing data to eight of the eleven memory devices 226 and writing parity data to three of the eleven memory devices 226. Four codewords may be written, each consisting of eleven four-bit symbols, each symbol belonging to a different memory device 226. The first codeword may include the first four-bit symbol of each memory device 226, the second codeword may include the second four-bit symbol of each memory device 226, the third codeword may include the third four-bit symbol of each memory device 226, and the fourth codeword may include the fourth four-bit symbol of each memory device 226. These four codewords, each from a memory device 226, may be (at least partially) transmitted over a single tick of a predefined burst length (e.g., 32-bit BL), resulting in a total of 128 codewords transmitted over the 32-bit BL.

[0044] Three parity symbols allow the LPCK circuitry 214 to correct up to one symbol error and detect up to two symbol errors in each codeword. If only two parity symbols are added instead of three, the LPCK circuitry 214 can correct up to one symbol error but detect only one. In some embodiments, data symbols and parity symbols can be written to or read from memory device 226 concurrently. If every bit symbol in the die fails, only the bit symbols from that memory device 226 in the codeword will fail. This allows for the reconstruction of memory contents in the event of a complete failure of memory device 226. LPCK is considered "on-the-fly correction" because it corrects data without impacting performance by performing a repair operation. In contrast, regarding... Figures 4 to 5The more detailed description of a redundant array of independent disks (RAID) is considered "verification and recovery correction" because it initiates a repair process to recover data that has been corrupted. The LPCK circuit system 214 may contain combinational logic that uses a feedforward process.

[0045] The LPCK circuitry 214 can further update the parity symbol in association with the execution of a host write command. For example, the LPCK circuitry 214 can receive data symbols received from the host and which are part of a hot write command (e.g., containing data symbols from the host). Figure 1 The host 103 described herein receives user data and / or host data, retrieves the corresponding parity symbol (e.g., one or more parity symbols), and updates the parity symbol based on the data symbol.

[0046] The updated parity symbol can be written back to memory device 226 along with the data symbol received as part of a host write command. Data symbols and / or parity symbols can be communicated between memory controller 200 and memory device 226 in the form of data blocks. As used herein, the term "parity data block" refers to a data block containing one or more parity symbols, and the term "user data block" (alternately referred to as "host data block") refers to a data block containing one or more data symbols.

[0047] As in Figure 2 As shown, the data management circuitry 210 may include error correction circuitry systems 216-1 and 216-2, configured to perform error correction operations on the data (e.g., ECC encoding and / or ECC decoding of the data). For embodiments that do not include cache 212, buffer 213, or LPCK circuitry system 214 (not specifically described), error correction circuitry system 216 may be coupled to error detection circuitry system 211. Otherwise, error correction circuitry system 216 may be coupled to any of cache 212, buffer 213, or LPCK circuitry system 214 (as shown in...). Figure 2 (As illustrated in the description). Although two error correction circuits 216 are described, the embodiments are not so limited. Embodiments may include only one error correction circuit system 216 or more than two error correction circuits 216 in the data management circuit system 210. In at least one embodiment, the memory controller 200 may include an equal number of error correction circuits 216-1, 216-2 as the media controllers 221-1, 221-2. In at least one embodiment, data may be protected by the error detection circuit system 211, the LPCK circuit system 214, and the error correction circuit system 216 before being written to the memory device 226.

[0048] As in Figure 2As shown, the memory controller 200 may include a back-end section 219, which includes a media control circuitry 220 coupled to the data management circuitry 210. The media control circuitry 220 may include media controllers 221-1, 221-2. The back-end section 219 may include a physical (PHY) layer 222 having PHY memory interfaces 224-1, 224-2, ..., 224-(N-1), 224-N. Each physical interface 224 is configured to couple to a corresponding memory device 226. The PHY layer 222 may be an LPDDRx memory interface.

[0049] The back-end portion 219 can couple the PHY layer 222 to the memory banks 230-1, 230-2, ..., 230-(N-1), 230-N of the memory devices 226-1, 226-2, ..., 226-(N-1), 226-N. Each memory device 226 includes at least one array of memory cells. In some embodiments, the memory devices 226 may be different types of memory. The media control circuitry system 220 may be configured to control at least two different types of memory. For example, memory devices 226-1, 226-2 may be LPDDRx memory operating according to a first protocol, and memory devices 226-(N-1), 226-N may be LPDDRx memory operating according to a second protocol different from the first protocol. In this example, the first media controller 221-1 may be configured to control a first subset of memory devices 226-1 and 226-2 according to a first protocol, and the second media controller 221-2 may be configured to control a second subset of memory devices 226-(N-1) and 226-N according to a second protocol. In a particular example, the memory devices 226-1 and 226-2 may have an onboard error correction circuitry system.

[0050] In some embodiments that include different subsets of memory devices 226 operating according to different protocols, the data management circuitry 210 may selectively enable the error correction circuitry 216 based on the type of memory device 226 being operated. For example, the data management circuitry may disable error correction circuitry 216-1 for a first subset of memory devices 226-1, 226-2 that have their own error correction circuitry, and enable error correction circuitry 216-2 for a second subset of memory devices 266-(N-1), 226-N that do not have onboard error correction circuitry. This embodiment advantageously allows the memory controller 200 to be designed and manufactured generally for a wider range of memory devices 226 to be controlled, and allows the memory controller 200 to simultaneously control different types of memory operating according to different protocols.

[0051] In some embodiments that include different subsets of memory devices 226 operating according to different protocols, the memory controller 200 may be configured to disable at least one low-power feature of a first subset of memory devices 226-1, 226-2, and enable at least one low-power feature of a second subset of memory devices 226-(N-1), 226-N. Examples of such low-power features include DVFSC and SCRC of memory device 226. SCRC reduces subthreshold current, which is particularly useful for memory used in mobile applications. DVFSC, when enabled (e.g., via a mode register), allows low-power DRAM to operate its internal circuitry from high or low voltage rails depending on the operating frequency. Memory device 226 may internally switch some internal circuitry from one rail to another. However, when DVFSC is enabled, some memory operations may take longer to complete. In some embodiments, only those low-power features not supported by the CXL protocol are disabled.

[0052] Although not specifically stated, for some embodiments including LPCK circuitry 214, media controller circuitry 220 may include a single media controller 221. During chip hunting, channels 225-1, 225-2, ..., 225-(N-1), 225-N may be driven simultaneously to write data to memory device 226. However, in some embodiments, multiple media controllers 221-1, 221-2 may be used instead of a single media controller 221 to drive channels 225 in the LPCK architecture. When multiple media controllers 221 are used to drive channels 225 simultaneously, the media controllers 221 are utilized substantially simultaneously. In at least one embodiment, each of the media controllers 221 may receive the same command and address and drive channels 225 substantially simultaneously. By using the same command and address, each of the media controllers 221 may perform the same memory operation on the same memory cell using channel 225.

[0053] As used herein, the term "substantially" means that the characteristics do not need to be absolute, but are close enough to achieve the advantages of the characteristics. For example, "substantially simultaneous" is not limited to operations that are performed absolutely simultaneously, and can include timing that is expected to be simultaneous but may not be precisely synchronized due to manufacturing limitations. For example, due to the read / write latency that various interfaces (e.g., LPDDR5 and PCIe) may exhibit, the media controllers utilized for "substantially simultaneous" operations may not start or end at exactly the same time. For example, memory controllers can be used such that they write data to memory devices at the same time, regardless of whether one of the media controllers starts or terminates before the other.

[0054] The memory controller 200 may include a management unit 205 configured to initialize, configure, and / or monitor the characteristics of the memory controller 200. In some embodiments, the management unit 205 includes a system management (SM) bus 207. The SM bus 207 may manage out-of-band data and / or commands. The SM bus 207 may be a serial presence detection portion. In some embodiments, the SM bus 207 may be a single-ended simple two-wire bus for lightweight communication. The management unit 205 may include a CPU subsystem 215, which may be used as a controller for the management unit to execute instructions associated with initializing, configuring, and / or monitoring the characteristics of the memory controller 200. The management unit 205 may include miscellaneous circuitry 217, such as local memory for storing code and / or data associated with managing and / or monitoring the characteristics of the memory controller 200. The endpoints of the management unit 205 may be exposed to a host system (e.g., Figure 1 The host 103 shown in the figure manages data. In some embodiments, the characteristics monitored by the management unit 205 may include the voltage supplied to the memory controller 200 and / or the temperature measured by an external sensor. The management unit 205 may include interconnects 218, such as an Advanced High Performance Bus (AHB), to couple different components of the management unit 205.

[0055] Management unit 205 may include circuitry for managing in-band data (e.g., data transmitted via a primary transmission medium within a network such as a local area network (LAN)). In some embodiments, CPU subsystem 215 may be compliant with Joint Test Action Group (JTAG) standards and inter-integrated circuit system (IICS) protocols. 2 C or I 3 C) Protocol-operated controllers and auxiliary I / O circuitry. JTAG typically refers to an industry standard used for post-manufacturing design verification and testing of printed circuit boards. 2 C typically refers to a serial protocol used for connecting low-speed devices (such as microcontrollers, I / O interfaces, and other similar peripherals in embedded systems) via a two-wire interface. In some embodiments, an auxiliary I / O circuitry system may couple the management unit 205 to the memory controller 200. Furthermore, firmware for operating the management unit may be stored in miscellaneous circuitry system 217. In some embodiments, miscellaneous circuitry system 217 may be flash memory, such as flash NOR memory or other persistent flash memory devices.

[0056] In the unrestricted instance, the instance device (e.g., Figure 1 The computing system 101 described herein may include several channels (e.g., configured to store several sets of data blocks) respectively coupled to several channels. Figure 1 and 2 The plurality of memory devices (e.g., in channels 125 and / or 225) described herein) Figures 1 to 2 The memory devices 126 and / or 226 described herein, each of the plurality of data blocks comprising a corresponding user data block grouped together for error correction operations (e.g., chip kill operations (e.g., LPCK operations)) and one or more parity blocks. Each group of data blocks may be a unit of read access. The instance device may further include a controller coupled to the plurality of memory devices (e.g., ...). Figure 1 The memory controller 100 described herein. The controller can be configured to receive write commands (e.g., from...). Figure 1 The host 103 described herein sends a host write command to write a first user data block corresponding to a first group of user data blocks to a first location in a plurality of memory devices. The controller may be further configured to retrieve a corresponding data block corresponding to the first group from the plurality of memory devices in response to receiving the write command. The controller may be further configured to update one or more parity blocks retrieved, at least in part, based on the first user data block. The controller may be further configured to write the first user data block and the updated one or more parity blocks to the corresponding memory devices in the plurality of memory devices independently of other data blocks in the first group.

[0057] In some embodiments, the first write command may be one of a plurality of write commands for writing a corresponding user data block to a plurality of memory devices. In this example, the controller may be configured to select a write command from a plurality of write commands having user data blocks and corresponding parity data blocks for different memory devices in the plurality of memory devices. Furthermore, the controller may be configured to simultaneously write the user data block and corresponding parity data block of the selected write command to the corresponding memory devices in the plurality of memory devices.

[0058] In some embodiments, the controller may include a cache (e.g., cache 212). In this example, a write command is used to write a first user data block from the cache to a corresponding memory device in one of several memory devices, so that the cache is synchronized with the corresponding memory device in the several memory devices.

[0059] In some embodiments, each of the plurality of memory devices may be configured for a single parity data block, such that the parity data blocks of the group are distributed across different memory devices in the memory devices. In some embodiments, each of the plurality of memory devices may be configured for a single user data block in each group of an array of user data blocks, such that each group of user data blocks is distributed across different memory devices in the plurality of memory devices. The controller may be configured to access one of the plurality of memory devices independently of and simultaneously with the other memory devices in the plurality of memory devices.

[0060] In another non-limiting instance, the instance device (e.g., Figure 1 The computing system 101 described herein may include components respectively coupled to several channels (e.g., respectively in...). Figures 1 to 2 The plurality of memory devices (e.g., in channels 125 and / or 225) described herein) Figures 1 to 2 The memory devices 126 and / or 226 described herein may further include a controller coupled to several memory devices (e.g., Figure 1 The memory controller 100 described herein may be configured to receive a plurality of write commands. The controller may be further configured to, in response to receiving the plurality of write commands, update parity data blocks corresponding to user data blocks of the plurality of write commands respectively. The controller may be further configured to select, among the plurality of write commands, a write command having user data blocks and corresponding parity data blocks for different memory devices among the plurality of memory devices. The controller may be further configured to simultaneously write the user data blocks and corresponding parity data blocks of the selected write command to the different memory devices.

[0061] In some embodiments, the controller may be configured to prevent the selection of at least two write commands targeting the same memory device among several write commands. In some embodiments, the user data block and corresponding parity data block of the selected write command may be written to different memory devices as part of a cache write-back operation.

[0062] In some embodiments, an array of data blocks is configured across several memory devices. Each group may contain data blocks grouped together for error correction operations (e.g., chip kill operations, such as LPCK operations) and accessible as read units. In this example, the user data blocks selected for write commands correspond to data blocks in different groups. Furthermore, in this example, parity data blocks within the array of data blocks may be distributed across different memory devices in the array.

[0063] Figure 3 This is timing diagram 331, which is associated with executing host write commands in a non-cached architecture according to several embodiments of this disclosure. While the embodiments are not so limited, Figure 3 The example described includes five media controllers (e.g., Figure 2 The media controller 221 described herein can be coupled to five memory devices, for example, in... Figure 1 and 2 The memory devices 126 and / or 226 described herein.

[0064] Media controllers 321-X (e.g., four media controllers, such as "DMC 0 to 3" including DMC 0, DMC 1, DMC 2, and DMC 3) may represent one or more media controllers (e.g., ...) coupled to one or more memory devices configured for user data blocks. Figure 2 (Media controller 221 as described in the document). Furthermore, media controller 321-Y (e.g., media controller, such as "DMC 4") may represent a media controller coupled to a memory device configured to group parity data blocks with user data blocks configured with media controller 321-X.

[0065] At point 332, a host write command is sent from host 303 to front-end 304. Figure 3 The "Wr UDB0" described herein is used to write new user data block 0 (e.g., user data block 0 containing new host data) to a memory device (e.g., in the memory device). Figure 1 and 2 The specific location of the memory device 126 and / or 226 described herein. At 334, a host write command is further sent from front end 304 to LPCK circuit system 314. In response to the host write command, LPCK circuit system 314 generates a memory read command ( Figure 3 The “Rd UDB[0…3]” and “Rd PDB” shown in the diagram are used to read grouped together (e.g., user data blocks 0 to 3 and parity block PDB) from the memory device (e.g., user data block 10, which will be replaced by new user data block 0). Within cycle 336, a memory read command is sent from LPCK circuitry 314 to the corresponding media controller 321. For example, the memory read command “Rd UDB[0..3]” is sent to media controller 321-X to read the user data block, and the memory read instruction “Rd PDB” is sent to media controller 321-Y to read the parity data block.

[0066] Within cycle 338, the constituent data blocks are retrieved to the LPCK circuit system 314. The LPCK circuit system 314 updates the retrieved parity data block based on the retrieved user data blocks 0 to 3 and the new user data block 0. After updating the parity data block, the LPCK circuit system 314 generates a memory write command to write the new user data block 0 (instead of the user data block 0 retrieved from the memory device) and the updated parity data block back to the corresponding memory device.

[0067] These generated commands can be sent to the corresponding media controller within 339 cycles. For example, a memory write command to write a new user data block 0 can be sent to one of the media controllers 321-X (e.g., DMC 0 configured for user data block 0), and a memory write command to write an updated parity block can be sent to the media controller 321-Y (e.g., DMC 4).

[0068] Figure 4 This is a timing diagram 440 associated with executing a host write command in a cache architecture according to several embodiments of the present disclosure. At 441, a host write command can be sent from host 403 to front-end 404. Figure 4 The “WrUDB0” shown in the diagram is used to write a new user data block 0 (e.g., user data block 0 containing new host data). At 443, a host write command can be further sent from front end 404 to cache 412. In response to receiving the host write command, cache 412 can generate a memory read command to read the user data block (e.g., the old user data block 0 containing the location where the new user data block 0 will be written). At 445, the generated read command can be sent from cache 412 to LPCK circuitry 414. In response to receiving the read command from cache 412, LPCK circuitry 414 can further generate a memory read command to read the parity data block grouped with the user data block (e.g., user data block 0). The memory read commands generated at cache 412 and LPCK circuitry 414 can be sent to the corresponding media controller (e.g., ...) within cycle 447. Figure 2 The media controller 221 described herein.

[0069] Within cycle 449, the user data block grouped with user data block 0 and the parity data block can be retrieved to the LPCK circuitry 414. The LPCK circuitry 414 can correct any errors on the user data block (e.g., the old user data block 0) (and the parity data block) by performing a chip kill operation (e.g., an LPCK operation) using the parity data block. User data blocks 0 through 3 with any corrected errors can be further sent to cache 412 at 451 (so that subsequent accesses to any of user data blocks 0 through 3 can be performed at the cache level with a cache hit). At 452, the user data block read from memory (e.g., UBD0) is replaced with the updated user data block (e.g., new UDB0) in cache 412.

[0070] As in Figure 4 As explained in the document, additional host write commands are subsequently received at positions 453, 454, and 455 respectively. Figure 4(Wr UDBi, Wr UDBj, and Wr UDBk are shown in the diagram). At a certain time, cache 412 can generate a memory write command and send it to LPCK circuit system 414 to perform a cache write-back, which, in association with a host write command whose corresponding user data block has not yet been written to the memory device, synchronizes cache 412 with the memory device.

[0071] At 457, a memory write command for writing user data blocks 0 through 3 (e.g., containing dirty user data blocks, such as new user data blocks already stored in cache 412 but not yet written to the memory device) can be sent to LPCK circuitry 414. In response to the memory write command from cache 412, LPCK circuitry 414 updates the parity data block based on user data blocks 0 through 3. LPCK circuitry 414 further generates memory write commands for writing user data block 0 (e.g., dirty user data block) and the updated parity data block, which can be sent at 459 to the corresponding media controllers 421-X and 421-Y. Media controller 421-X (e.g., four media controllers, such as “DMC 0 through 3” including DMC 0, DMC 1, DMC 2, and DMC 3) can represent one or more media controllers (e.g., ...) coupled to one or more memory devices configured for user data blocks. Figure 2 (Media controller 221 as described in the document). Furthermore, media controller 421-Y (e.g., media controller, such as "DMC 4") may represent a media controller coupled to a memory device configured for parity data blocks.

[0072] In some embodiments, cache write-back can be performed using dirty data blocks from multiple host write commands. For example, at least one of the user data blocks received at 453, 454, and 455 can be written back to the memory device along with dirty user data block 0, instead of writing only dirty user data block 0 (and its corresponding parity data block) at 452. As further described herein, data blocks can be selected from the user data blocks (and their corresponding parity data blocks) received at 453, 454, and 455 based on the respective memory device to which the data block is to be written. For example, if dirty user data block 0 is for a memory device coupled to DMC 0, and the parity data block is for a memory device coupled to DMC 4, then the data blocks selected to be written along with dirty user data block 0 could be those data blocks for DMC 1, 2, and / or 3.

[0073] Figure 5This is a block diagram 560 associated with executing a write command according to several embodiments of the present disclosure. As used herein, a memory transfer block may be a group of data blocks that can be transferred at once via channel 525 to one or more memory devices 526. Memory device 526 may include multiple dies (e.g., Figure 5 The bare films described in the document (527-1, ..., 527-10), for example... Figure 5 The two bare wafers described herein. In some embodiments, Figure 5 The data block 566 described herein can be written to memory device 526 as part of the cache write-back operation.

[0074] The data bus can operate in burst length (e.g., a 32-bit burst length "BL"). A burst is a series of data transfers performed over multiple cycles (e.g., clock cycles). For example, a 32-bit burst length can consist of 32 clock cycles of data transfers. In an example embodiment, each channel 525 can consist of 8 DQs, such that 8 bits are transferred for each clock cycle of the burst length, resulting in 16 bits being transferred to and / or from the memory device 526 at a time (e.g., per clock cycle of each burst length).

[0075] Memory transfer blocks (e.g., Figure 5 The memory transfer block 562 described herein may include multiple slots, which may or may not be filled with data blocks (e.g., user data blocks and / or parity data blocks). For example, the memory transfer block 562 may include five slots (e.g., slots 564-1, ..., 564-5), each of which may or may not be filled with a corresponding data block. In several embodiments, this may be based on the memory controller (e.g., respectively in...). Figure 1 and 2 The channels (e.g., in the memory controllers 100 and / or 200 described herein) are coupled to the memory device 526 via channels (e.g., in the memory controllers 100 and / or 200 described herein). Figure 1 and 2 The number of channels 125 and / or 225 described herein determines (e.g., predetermined) the number of slots in the memory transfer block. For example, if there are 5 channels coupled between the memory controller and the memory device 526, then the memory transfer block may have 5 slots.

[0076] As in Figure 5 As described, the memory transfer block fills two data blocks at slots 564-2 and 564-5 respectively. The data blocks at slots 564-2 and 564-5 are associated with a single host write command. For example, data block 566-1 may contain a host write command (e.g., ...). Figure 1The user data block 566-2, which is a portion of the new host data received by the host 103 described herein, may be a parity data block, which is updated at least partially based on the host data of data block 566-1. Other slots may remain empty (not filled with additional data blocks). Therefore, a write operation associated with memory transfer block 562 can be performed by using two of the five channels to carry both user data block 566-1 and parity data block 566-2.

[0077] Figure 6 This is block diagram 668 associated with executing a write command selected according to several embodiments of this disclosure. In some embodiments, Figure 5 The data block 666 described herein can be written to memory device 626 as part of the cache write-back process.

[0078] Figure 6 The memory transfer block 662 described herein can be similar to Figure 5 The memory transfer block 562 described herein differs only in that its slots are filled with data blocks for different host write commands. For example, slots 664-2 and 664-5 can be filled with user data block 666-1 associated with the first host write command, respectively. Figure 6 The “UDB” shown in the image and the updated parity data block 666-2 ( Figure 6 The “PDB” shown in the image, and slots 664-1 and 664-3 can be filled with user data blocks 666-3 associated with the second host write command, respectively. Figure 6 The “UDB” shown in the image and the updated parity data block 666-4 ( Figure 6 (As shown in the diagram, "PDB"). Host write commands to be executed together (e.g., within the same memory transfer block) can be selected based on the channel used to carry the corresponding data blocks. For example, two host write commands whose constituent data blocks are carried via the same channel may not be selected for execution within the same memory transfer block. Therefore, data blocks of a memory transfer block can be executed simultaneously, even though the data blocks belong to different host write commands.

[0079] As in Figure 6 As explained, each host write command involves at least two distinct data blocks: one is a user data block, and the other is a parity data block. Therefore, slot 664-4 can remain empty (e.g., not filled with additional data blocks) because one slot is insufficient for additional data blocks from additional host write commands.

[0080] Figure 7This is a flowchart 770 of a method for independently executing write commands according to several embodiments of the present disclosure. Method 770 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 770 can be executed by... Figure 1 and 2 The memory controllers 100 and / or 200 described herein shall perform the operations. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0081] At 772, a device for writing to corresponding memory devices coupled to several memory devices (e.g., respectively) can be received. Figure 1 , 2 The first user data block of the first channel of one of the memory devices 126, 226 and / or 526 described in 5 (e.g., respectively in Figures 5 to 6 The write commands (e.g., from user data blocks 566-1, 666-1 and / or 666-3) described herein are used to write user data blocks 566-1, 666-1 and / or 666-3. Figure 1 The host write command of host 103 described herein). The first user data block may be one of a group of data blocks grouped together, and is the unit of read access. At 774, in response to the write command, the parity data block corresponding to the second channel and grouped together with the first user data block (e.g., respectively in) can be retrieved from the second location of a plurality of memory devices. Figures 5 to 6 (Parity data blocks 566-2, 666-2, and / or 666-4 as described in the diagram). At 776, the parity data block can be updated at least partially based on the first user data block. In some embodiments, other user data blocks grouped together with the parity data block or the first data block can also be retrieved from several memory devices, and the parity data block can be updated at least partially based on the first user data block and the other user data blocks.

[0082] At 778, the first user data block and the updated parity data block can be written to first and second locations of several memory devices independently of other user data blocks grouped together with the parity data block or the first data block. For example, the first user data block and the updated parity data block can be written to several memory devices without writing other user data blocks back to several memory devices.

[0083] In some embodiments, the write command may be a first write command. In this instance, a second write command may be received (e.g., from...). Figure 1 The host 103 described herein has a host write command, and the second write command can select a write command that targets a user data block and a corresponding parity data block at a location different from the first or second location. The first user data block and the updated parity data block of the first write command, as well as the user data block and the corresponding parity data block of the selected write command, can be simultaneously written to different locations of several memory devices.

[0084] In some embodiments, the first user data block may be stored in a cache (e.g., in...). Figure 2 and 4 Data blocks that are in cache 212 and / or 412 as described in the document and have not yet been written to the first location (e.g., respectively in cache 212 and / or 412) Figure 5 and 6 (Data blocks 564 and / or 664 as described in the document). In this example, a first user data block already stored in the cache can be written to a first location to synchronize the cache with several memory devices.

[0085] Figure 8 This is a flowchart 880 of a method for independently executing write commands according to several embodiments of the present disclosure. Method 880 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 880 may be executed by... Figure 1 and 2 The memory controllers 100 and / or 200 described herein shall perform the operations. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0086] At 882, it is possible to receive the corresponding user data blocks (e.g., respectively in...) Figures 5 to 6 User data blocks 566-1, 666-1 and / or 666-3 described herein are written to a memory device (e.g., respectively in...). Figure 1 , 2 And several write commands (e.g. from memory devices 126, 226 and / or 526) as described in 5) Figure 1(The host write command of host 103 described herein). Each user data block in the corresponding user data block may correspond to a group of corresponding data blocks grouped together, and is a unit of read access. At 884, among several write commands, a write command having user data blocks for different memory devices can be selected. At 886, in order to execute the selected write commands simultaneously, the user data blocks of the selected write commands can be written to different memory devices simultaneously.

[0087] In some embodiments, parity data blocks corresponding to array data blocks can be retrieved in response to several write commands (e.g., respectively in...). Figures 5 to 6 The parity data blocks 566-2, 666-2, and / or 666-4 are described in the document. The parity data blocks can be updated at least partially based on the corresponding user data blocks of several write commands. In this example, write commands with user data blocks and corresponding parity data blocks for different memory devices can be selected. Furthermore, in this example, user data blocks and corresponding parity data blocks can be written to different memory devices simultaneously.

[0088] Although specific embodiments have been described and illustrated herein, those skilled in the art will understand that arrangements calculated to achieve the same results may be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of this disclosure. It should be understood that the foregoing description has been carried out in an illustrative rather than restrictive manner. Those skilled in the art will understand, upon reviewing the foregoing description, combinations of the foregoing embodiments and other embodiments not explicitly described herein. The scope of one or more embodiments of this disclosure includes other applications using the above-described structures and processes. Therefore, the scope of one or more embodiments of this disclosure should be determined with reference to the appended claims and the full scope of their equivalents.

[0089] In the foregoing detailed embodiments, for the purpose of simplifying this disclosure, some features are grouped in a single embodiment. This approach of the disclosure should not be construed as reflecting an intention that the disclosed embodiments of the disclosure must use more features than expressly recited in each claim. Rather, as reflected in the appended claims, the subject matter of the invention exists in fewer than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed embodiments, wherein each claim is an independent, separate embodiment.

Claims

1. A method comprising: Receive a first write command for writing a first user data block corresponding to a first channel coupled to one of a plurality of memory devices, wherein the first user data block is one of a first group of data blocks as a unit of read access, and the data blocks are grouped together for error correction operations. Receive a second write command for writing a second user data block corresponding to a second channel coupled to one of the plurality of memory devices, wherein the second user data block is one of a second group of data blocks as a unit of read access, and the data blocks are grouped together for error correction operations. as well as In response to the first and second write commands: Retrieve the first parity data block that corresponds to the third channel and is grouped together with the first user data block; The first parity data block is updated at least in part based on the first user data block; as well as Independent of other user data blocks grouped together with the first parity data block or the first user data block, the first user data block, the second user data block, and the updated first parity data block are simultaneously written to memory devices respectively coupled to the first channel, the second channel, and the third channel.

2. The method of claim 1, further comprising, in response to the first write command: Retrieve the other user data blocks grouped together with the first user data block from the plurality of memory devices; and The first parity data block is updated based at least in part on the first user data block and the other user data blocks.

3. The method of claim 1, further comprising writing the first user data block and the updated first parity data block to the plurality of memory devices without writing the other user data blocks back to the plurality of memory devices.

4. The method of claim 1, further comprising, in response to the second write command: Retrieve the second parity data block that corresponds to the fourth channel and is grouped together with the second user data block; The second parity data block is updated at least in part based on the second user data block; as well as The second parity data block, the first user data block, the first parity data block, and the second user data block are simultaneously written to one of the plurality of memory devices coupled to the fourth channel.

5. The method of claim 1, wherein the first user data block is one that has been stored in a cache and has not yet been written to one of the plurality of memory devices coupled to the first channel; and wherein, The method further includes writing a first user data block already stored in a cache to one of the plurality of memory devices coupled to the first channel, so that the cache is synchronized with the plurality of memory devices.

6. An apparatus comprising: A plurality of memory devices, each coupled to a plurality of channels, are configured to store array data blocks, each array data block comprising a corresponding user data block grouped together for error correction operations and one or more parity blocks; and A controller, coupled to the plurality of memory devices and configured to: Receive multiple write commands for writing corresponding user data blocks to the plurality of memory devices; In response to receiving the plurality of write commands, parity data blocks corresponding to the user data blocks are retrieved respectively; The retrieved parity data blocks are updated based on the user data blocks respectively; as well as In the user data block and the updated parity data block, at least two user data blocks and one or more parity data blocks are written to and written to different memory devices among the plurality of memory devices.

7. The device according to claim 6, wherein: The controller includes a cache; and At least one of a plurality of write commands is used to write the corresponding user data block from the cache to the corresponding memory device among the plurality of memory devices, so that the cache is synchronized with the corresponding memory device among the plurality of memory devices.

8. The device of claim 6, wherein each of the plurality of memory devices is configured for a single parity data block, such that the parity data blocks in the array of data blocks are distributed across different memory devices in the plurality of memory devices.

9. The device of claim 6, wherein each of the plurality of memory devices is configured for a single user data block in each group of the array data blocks, such that the user data blocks in each group are distributed across different memory devices in the plurality of memory devices.

10. The device of claim 6, wherein the controller is configured to access one of the plurality of memory devices independently of the other memory devices among the plurality of memory devices, and to access the one of the plurality of memory devices simultaneously with the other memory devices among the plurality of memory devices.

11. A method comprising: Receive several write commands for writing corresponding user data blocks to memory devices respectively coupled to several channels, wherein each user data block in the corresponding user data block corresponds to a group of corresponding data blocks as a unit of read access, and the data blocks are grouped together for error correction operations. In response to the plurality of write commands, parity data blocks are retrieved, wherein each of the parity data blocks corresponds to the set of corresponding data blocks; The parity data block is updated at least in part based on the corresponding user data blocks of the several write commands; Among the several write commands, select the write command that targets user data blocks for different memory devices; as well as To execute the selected write command simultaneously, the user data block of the selected write command is written to the different memory devices simultaneously.

12. The method of claim 11, wherein selecting the write command having the user data block for a different memory device further comprises selecting the write command having the user data block for a different memory device and a corresponding parity data block.

13. The method of claim 12, wherein simultaneously writing the user data block of the selected write command to the different memory devices further comprises simultaneously writing the user data block and the corresponding parity data block to the different memory devices.

14. An apparatus comprising: Several memory devices, each coupled to several channels; and A controller, coupled to the plurality of memory devices; the controller is configured to: Receive several write commands; and In response to receiving the aforementioned write commands: Update the parity data blocks corresponding to the user data blocks of the several write commands respectively; Among the plurality of write commands, a write command is selected that has user data blocks and corresponding parity data blocks for different memory devices among the plurality of memory devices; The user data block and the corresponding parity data block of the selected write command are simultaneously written to the different memory devices.

15. The device of claim 14, wherein the controller is configured to prevent the selection of at least two write commands for the same memory device among the plurality of write commands.

16. The apparatus of claim 14, wherein the plurality of memory devices are configured for array data blocks, wherein each group is a unit of read access and comprises data blocks grouped together for error correction operations.

17. The device of claim 16, wherein the user data block of the selected write command corresponds to a different group of data blocks.

18. The device of claim 16, wherein the parity data block in the array data block is distributed across different memory devices in the plurality of memory devices.

19. The device of claim 14, wherein the user data block and the corresponding parity data block of the selected write command are written to the different memory devices as part of performing a cache write-back.

Images