Display panel and method for manufacturing display panel

Abstract

The present application provides a display panel and a method for manufacturing the display panel that can suppress insulation breakdown in a manufacturing process. The display panel has a protective element and a display portion containing a plurality of pixels, the display panel has an insulating substrate, a lower metal layer, a first interlayer insulating film arranged above the lower metal layer, a semiconductor layer arranged above the first interlayer insulating film, a gate insulating film arranged above the semiconductor layer, a gate metal layer arranged above the gate insulating film, a second interlayer insulating film arranged above the gate metal layer, and a source-drain metal layer arranged above the second interlayer insulating film, each of the plurality of pixels has a thin film transistor including a portion of each of the semiconductor layer, the gate metal layer, and the source-drain metal layer, and the protective element has a thin film transistor-type diode including another portion of each of the lower metal layer, the semiconductor layer, and the gate metal layer.

Description

Technical Field

[0001] The present application relates to a display panel and a method for manufacturing the display panel. Background Art

[0002] An organic EL (Electro Luminescence) display panel in which a plurality of pixels are arranged in a matrix is ​​a known display panel for a display device. For example, an organic EL display panel having a top emission structure has a circuit substrate and an EL device layer provided on the circuit substrate, and the circuit substrate has a thin film transistor (TFT: Thin Film Transistor) and the like. The thin film transistor is formed by laminating a plurality of insulating films and a plurality of wiring layers on a substrate.

[0003] In recent years, as display devices have become larger, the amount of charge on display panels has also increased, which has led to a problem of reduced yields due to insulation breakdown during the manufacturing process of display panels.

[0004] In order to suppress such insulation breakdown, it is known that a display panel has a protective element such as a thin film transistor diode, which is used to release the charge carried on the display panel (for example, Patent Document 1, etc.). The protective element described in Patent Document 1 is formed by connecting the drain and gate of a thin film transistor, and the thin film transistor has the same structure as the thin film transistor included in a plurality of pixels.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: JP2010-186185 Summary of the invention

[0008] Technical Problems to be Solved by the Invention

[0009] However, as display devices become larger, the length of wiring included in the display panel also becomes longer. Accordingly, the amount of charge accumulated between each wiring and the insulating film in the manufacturing process before the protective element of the display panel is formed also becomes larger. Therefore, for example, when the back side of the substrate is pushed up with a metal lifting pin or the like to move the substrate on which the thin film transistor is formed, the charge is concentrated in the substrate area located above the lifting pin, which may cause insulation breakdown.

[0010] The present application aims to solve the above-mentioned problems and provide a display panel, etc. that can suppress insulation breakdown during the manufacturing process.

[0011] Technical solutions for solving technical problems

[0012] In order to solve the above-mentioned problem, the present application provides a display panel having a protection element and a display portion having multiple pixels, wherein the display panel has an insulating substrate, a lower metal layer arranged above the substrate, a first interlayer insulating film arranged above the lower metal layer, a semiconductor layer arranged above the first interlayer insulating film, a gate insulating film arranged above the semiconductor layer, a gate metal layer arranged above the gate insulating film, a second interlayer insulating film arranged above the gate metal layer, and a source-drain metal layer arranged above the second interlayer insulating film, each of the multiple pixels has a thin film transistor including parts of the semiconductor layer, the gate metal layer, and the source-drain metal layer, and the protection element has a thin film transistor-type diode including another part of each of the lower metal layer, the semiconductor layer, and the gate metal layer.

[0013] In order to solve the above-mentioned problems, the present application provides a method for manufacturing a display panel having a protection element and a display portion having multiple pixels, the method for manufacturing the display panel comprising a preparation step of preparing an insulating substrate, a step of forming a lower metal layer above the substrate, a step of forming a first interlayer insulating film above the lower metal layer, a step of forming a semiconductor layer above the first interlayer insulating film, a step of forming a gate insulating film above the semiconductor layer, a step of forming a gate metal layer above the gate insulating film, a step of forming a second interlayer insulating film above the gate metal layer, and a step of forming a source-drain metal layer above the second interlayer insulating film, each of the multiple pixels having a thin film transistor including parts of the semiconductor layer, the gate metal layer and the source-drain metal layer, and the protection element having a thin film transistor-type diode including the lower metal layer, the semiconductor layer and another part of the gate metal layer.

[0014] According to the present application, a display panel capable of suppressing insulation breakdown during the manufacturing process can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic top view showing the structure of a display panel related to the embodiment.

[0016] Figure 2 It is a circuit diagram showing an equivalent circuit of a protection element according to an embodiment.

[0017] Figure 3 A schematic cross-sectional view showing a specific structure of a thin film transistor included in a pixel of a display panel according to an embodiment.

[0018] Figure 4 It is a schematic diagram showing a specific structure of a protection element of a display panel related to an embodiment.

[0019] Figure 5 It is a schematic cross-sectional view showing a first step of a method for manufacturing a thin film transistor according to an embodiment.

[0020] Figure 6 It is a schematic diagram showing a first step of the method for manufacturing a protection element according to the embodiment.

[0021] Figure 7 It is a schematic cross-sectional view showing a second step of the method for manufacturing a thin film transistor according to the embodiment.

[0022] Figure 8 It is a schematic diagram showing the second step of the method for manufacturing the protection element according to the embodiment.

[0023] Fig. 9 It is a schematic cross-sectional view showing a third step of the method for manufacturing the thin film transistor according to the embodiment.

[0024] Fig.10 It is a schematic diagram showing the third step of the method for manufacturing the protection element according to the embodiment.

[0025] Fig.11 It is a schematic cross-sectional view showing a fourth step of the method for manufacturing the thin film transistor according to the embodiment.

[0026] Fig.12 It is a schematic diagram showing a fourth step of the method for manufacturing the protection element according to the embodiment.

[0027] Fig.13 It is a schematic diagram showing the fifth step of the method for manufacturing the protection element according to the embodiment.

[0028] Fig.14 It is a schematic cross-sectional view showing a fifth step of the method for manufacturing the thin film transistor according to the embodiment.

[0029] Fig.15 It is a schematic diagram showing the sixth step of the method for manufacturing the protection element according to the embodiment.

[0030] Fig.16 It is a schematic cross-sectional view showing a sixth step of the method for manufacturing a thin film transistor according to the embodiment.

[0031] Fig.17 It is a schematic diagram showing the seventh step of the method for manufacturing the protection element according to the embodiment.

[0032] Fig.18 It is a schematic cross-sectional view showing a seventh step of the method for manufacturing the thin film transistor according to the embodiment.

[0033] Description of Reference Numerals

[0034] 10: Display Panel

[0035] 11: Display unit

[0036] 12: Pixel

[0037] 13: Peripheral area

[0038] 14: Lead-out wiring

[0039] 15: Protection element

[0040] 16: Common electrode

[0041] 17: Signal wiring

[0042] 18: Power wiring

[0043] 19: Thin Film Transistor

[0044] 20: Substrate

[0045] 30: Lower metal layer

[0046] 31: First lower electrode

[0047] 32: Second lower electrode

[0048] 35: Lower electrode

[0049] 40: First interlayer insulating film

[0050] 50: Semiconductor layer

[0051] 51a, 52a, 53a, 55a: High resistance area

[0052] 51b, 52b, 53b, 55b: Low resistance area

[0053] 60: Gate insulation film

[0054] 60h: Contact hole

[0055] 70: Gate metal layer

[0056] 71: First gate electrode

[0057] 71a: First gate region

[0058] 72: Second gate electrode

[0059] 72a: Second gate region

[0060] 73: Third gate electrode

[0061] 73a: Third gate region

[0062] 75: Gate electrode

[0063] 80: Second interlayer insulating film

[0064] 90: Source and drain metal layer

[0065] 95a, 95b: source and drain electrodes DETAILED DESCRIPTION

[0066] The embodiments of the present application are described below using the accompanying drawings. The embodiments described below are all specific examples in the content of the present application. Therefore, the numerical values, shapes, materials, structural elements, configuration positions and connection methods of structural elements, processes and process sequences, etc. shown in the following embodiments are all exemplary and are not used to limit the content of the present application. Therefore, among the structural elements of the following embodiments, the structural elements not recorded in the independent claims represent the highest-level concepts of the present application and are interpreted as arbitrary structural elements.

[0067] Furthermore, each of the drawings is a schematic diagram and is not a strict illustration. Therefore, the proportions and the like in each of the drawings are not consistent. In addition, in each of the drawings, substantially the same structure is marked with the same reference numeral, and repeated descriptions are omitted or simplified.

[0068] In this specification, the terms "above" and "below" do not refer to upward (vertically upward) and downward (vertically downward) in absolute spatial cognition, but are used as terms defined based on the relative positional relationship of the stacking order in the stacking structure. In addition, the terms "above" and "below" are applicable not only to the case where two structural elements are arranged with a gap between them and there is another structural element between the two structural elements, but also to the case where two structural elements are arranged in a state of contact with each other.

[0069] (Implementation Method)

[0070] Hereinafter, a display panel and a method for manufacturing the same according to an embodiment will be described.

[0071] [1. Structure of display panel]

[0072] use Figure 1 The structure of the display panel according to this embodiment will be described. Figure 1 It is a schematic plan view showing the structure of the display panel 10 according to the present embodiment.

[0073] Figure 1 The display panel 10 shown has a protection element 15 and a display portion 11 having a plurality of pixels 12. In this embodiment, the display panel 10 further has a peripheral region 13, lead wiring 14, a common electrode 16, a signal wiring 17, and a power wiring 18.

[0074] The display unit 11 is a portion that displays an image in the display panel 10. A plurality of pixels 12 are arranged in a matrix in the display unit 11.

[0075] The peripheral region 13 is a region located at the periphery of the display unit 11 , and is provided with lead wirings 14 , common electrodes 16 , protection elements 15 , and the like.

[0076] The plurality of pixels 12 are used to display an image on the display unit 11. Each of the plurality of pixels 12 has one or more thin film transistors. A pixel circuit is formed by one or more thin film transistors. The structure of the thin film transistor will be described later.

[0077] The signal wiring 17 is a wiring for transmitting a signal to each of the plurality of pixels 12. In the present embodiment, the plurality of signal wirings 17 are arranged in the row direction of the plurality of pixels 12 in the display unit 11 (ie, Figure 1 The plurality of signal wirings 17 each send a signal to the pixels 12 arranged in each row. It should be noted that, although not shown in the figure to avoid complicating the drawing, the plurality of signal wirings 17 may also be arranged in the column direction (i.e., Figure 1 longitudinal) extension.

[0078] The power wiring 18 is a wiring for supplying voltage to each of the plurality of pixels 12. In the present embodiment, the plurality of power wirings 18 extend in the column direction of the plurality of pixels 12 in the display unit 11. The plurality of power wirings 18 each supply voltage to the pixels 12 arranged in each column. It should be noted that, although not shown in the figure to avoid complicating the drawing, the plurality of power wirings 18 may also extend in the row direction of the plurality of pixels 12 in the display unit 11.

[0079] The lead wiring 14 is arranged in the peripheral region 13 and connected to each of the signal wirings 17 and the power wiring 18. The plurality of lead wirings 14 are connected to the plurality of signal wirings 17, respectively. The plurality of lead wirings 14 are connected to the plurality of power wirings 18, respectively.

[0080] The common electrode 16 is an electrode disposed in the peripheral region 13 and used to discharge static electricity. In the present embodiment, the common electrode 16 has a rectangular ring shape surrounding the display unit 11 .

[0081] The protection element 15 is an element for suppressing insulation breakdown in the display panel 10. The protection element 15 is arranged in the peripheral region 13 and connected between the common electrode 16 and the signal wiring 17 or the power wiring 18. In this embodiment, the protection element 15 is connected to the signal wiring 17 or the power wiring 18 via the lead wiring 14. Figure 2 Provide explanation. Figure 21 is a circuit diagram showing an equivalent circuit of the protection element 15 related to the present embodiment. Figure 2 As shown, the protection element 15 has more than one diode. In this embodiment, the protection element 15 has a thin film transistor type diode. That is, the protection element 15 is a diode formed by connecting the gate and drain of a thin film transistor. In addition, in this embodiment, the protection element 15 has a plurality of bidirectional diodes connected in series. Accordingly, when the signal wiring 17 or the power wiring 18 is at a high potential or a low potential relative to the common electrode 16, static electricity can be released through the protection element 15.

[0082] Next, use Figure 3 and Figure 4 The specific structures of the thin film transistor of the pixel 12 and the protection element 15 are described. Figure 3 1 is a schematic cross-sectional view showing a specific structure of a thin film transistor 19 of a pixel 12 of a display panel 10 according to the present embodiment. Figure 4 Schematic diagram showing the specific structure of the protection element 15 of the display panel 10 according to the present embodiment. The top view (a) and the cross-sectional view (b) of the protection element 15 are shown in FIG. Figure 4 Shown. Figure 4 The cross section along line IV-IV of the top view (a) is Figure 4 The profiles of the lower metal layer 30, the semiconductor layer 50 and the gate metal layer 70 are shown in FIG. Figure 4 (a) shows a top view of the device.

[0083] like Figure 3 and Figure 4 As shown, the display panel 10 has a substrate 20 , a lower metal layer 30 , a first interlayer insulating film 40 , a semiconductor layer 50 , a gate insulating film 60 , a gate metal layer 70 , a second interlayer insulating film 80 and a source-drain metal layer 90 .

[0084] The substrate 20 is an insulating plate-like component, which serves as the base of the circuit substrate of the display panel 10. For example, the substrate 20 is a glass substrate made of a glass material such as quartz glass, alkali-free glass or high heat-resistant glass. In addition, the substrate 20 may not be a rigid substrate, but a flexible substrate in sheet or film form such as a flexible glass substrate or a flexible resin substrate. As a flexible resin substrate, for example, a substrate composed of a single layer or a stack of thin film materials such as polyimide, polyethylene terephthalate, and polyethylene naphthalate can be used. It should be noted that a bottom covering layer composed of an insulating material can be formed on the surface of the substrate 20. For example, the bottom covering film can be a SiN layer stacked in sequence starting from a position close to the substrate 20. x Thus, substances (such as sodium ions) contained in the substrate 20 can be prevented from migrating to above the substrate 20.

[0085] The lower metal layer 30 is a conductive layer disposed above the substrate 20. Any metal film can be used as the lower metal layer 30. In the present embodiment, a laminated film composed of a Ti film, a Cu film, and a CuMn film is used as the lower metal layer 30. A laminated film composed of a metal such as molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), manganese (Mn), chromium (Cr), tantalum (Ta), niobium (Nb), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), indium (In), nickel (Ni), neodymium (Nd), or a metal selected from these metals, or an alloy of a metal selected from these metals can be used as the lower metal layer 30. As Figure 3 As shown, the lower metal layer 30 has a lower electrode 35. Figure 4 As shown, the lower metal layer 30 includes a first lower electrode 31 and a second lower electrode 32. The second lower electrode 32 is disposed adjacent to the first lower electrode 31 via a first interlayer insulating film 40.

[0086] The first interlayer insulating film 40 is an insulating film disposed above the lower metal layer 30. The first interlayer insulating film 40 covers the lower metal layer 30. In this embodiment, a SiN x A laminated film composed of a SiO2 film and a SiN film is used as the first interlayer insulating film 40. For example, SiN x As the first interlayer insulating film 40, a SiO2 film, a SiON film, or a laminated film selected from these insulating films.

[0087] The semiconductor layer 50 is a semiconductor layer disposed above the first interlayer insulating film 40. In the present embodiment, the semiconductor layer 50 includes an oxide semiconductor. The semiconductor layer 50 is composed of an oxide semiconductor including, for example, an oxide of at least one element selected from In, Ga, Zn, Sn, Ti, and Nb as a main component. For example, ITZO (indium tin zinc oxide), IGZO (InGaZnO), ZnO, IZO (indium zinc oxide), IGO (indium gallium oxide), ITO (indium tin oxide), InO, etc. can be used as the semiconductor layer 50.

[0088] like Figure 3 As shown, the semiconductor layer 50 has a high resistance region 55a and a low resistance region 55b. Figure 4 As shown, the semiconductor layer 50 has high resistance regions 51a, 52a and 53a and low resistance regions 51b, 52b and 53b. For example, when the gate insulating film 60 disposed on the semiconductor layer 50 is removed by dry etching, each low resistance region is a region formed by plasma loss and substantially functions as a conductor.

[0089] The gate insulating film 60 is an insulating film disposed above the semiconductor layer 50. For example, a SiO2 film can be used as the gate insulating film 60. In the present embodiment, the gate insulating film 60 is patterned in the same shape as the gate metal layer 70. In other words, the outline of the gate insulating film 60 in the top view is the same as the outline of the gate metal layer 70 in the top view. It should be noted that the state referred to by the "same shape" or "same outline" recorded here is not limited to a state in which the shapes or outlines are completely consistent, but also includes a state in which they are substantially consistent. The state referred to by the record of the same shape or the same outline includes, for example, a state in which the size of either the outline of the gate insulating film 60 or the outline of the gate metal layer 70 is less than 20% of the size of the gate metal layer 70.

[0090] The gate metal layer 70 is a conductive layer disposed above the gate insulating film 60. For example, any metal film can be used as the gate metal layer 70. A metal film having the same structure as the lower metal layer 30 can also be used as the gate metal layer 70. In the present embodiment, a laminated film composed of a Ti film, a Cu film, and a CuMn film is used as the gate metal layer 70. A laminated film composed of metals such as molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), manganese (Mn), chromium (Cr), tantalum (Ta), niobium (Nb), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), indium (In), nickel (Ni), neodymium (Nd), or a metal selected from these metals can also be used as the gate metal layer 70, or an alloy of a metal selected from these metals can be used. As Figure 3 As shown, the gate metal layer 70 has a gate electrode 75. Figure 4 As shown, the gate metal layer 70 includes a first gate electrode 71, a second gate electrode 72, and a third gate electrode 73. The second gate electrode 72 is disposed adjacent to the first gate electrode 71 and the third gate electrode 73 via a second interlayer insulating film 80.

[0091] The first gate electrode 71 has a first gate region 71a disposed at a position facing the first lower electrode 31. The second gate electrode 72 has a second gate region 72a disposed at a position facing the first lower electrode 31. The third gate electrode 73 has a third gate region 73a disposed at a position facing the second lower electrode 32.

[0092] The first lower electrode 31 of the lower metal layer 30 is connected to the first gate electrode 71 and the second gate electrode 72 via the contact hole 60h. The second lower electrode 32 of the lower metal layer 30 is connected to the third gate electrode 73 via the contact hole 60h.

[0093] The first gate electrode 71 is connected to the first lower electrode 31 and the semiconductor layer 50 in the first gate region 71a. The second gate electrode 72 is connected to the first lower electrode 31 and the semiconductor layer 50 in the second gate region 72a. The third gate electrode 73 is connected to the second lower electrode 32 and the semiconductor layer 50 in the third gate region 73a.

[0094] The second interlayer insulating film 80 is an insulating film disposed above the gate metal layer 70. In this embodiment, a SiO2 film is used as the second interlayer insulating film 80. For example, SiN x The second interlayer insulating film 80 may be an inorganic insulating film such as a SiON film or an Al 2 O 3 film, an organic insulating film such as a photosensitive polyimide or an acrylic resin, or a laminated film thereof.

[0095] The source-drain metal layer 90 is a conductive layer disposed above the second interlayer insulating film 80. For example, any metal film can be used as the source-drain metal layer 90. A metal film having the same structure as the gate metal layer 70 can also be used as the source-drain metal layer 90. In this embodiment, a stacked film composed of a Ti film, a Cu film, and a CuMn film is used as the source-drain metal layer 90. A stacked film composed of metals such as molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), manganese (Mn), chromium (Cr), tantalum (Ta), niobium (Nb), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), indium (In), nickel (Ni), neodymium (Nd), or a metal selected from these metals can also be used as the source-drain metal layer 90, or an alloy of a metal selected from these metals can be used. As Figure 3 As shown, the source-drain metal layer 90 has source-drain electrodes 95a and 95b. The source-drain electrodes 95a and 95b are connected to the low resistance region 55b of the semiconductor layer 50 via the release hole.

[0096] like Figure 3 As shown, the thin film transistor 19 includes a portion of each of the semiconductor layer 50, the gate metal layer 70, and the source-drain metal layer 90. More specifically, the thin film transistor 19 includes a high resistance region 55a and a low resistance region 55b of the semiconductor layer 50, a gate electrode 75 of the gate metal layer 70, and source-drain electrodes 95a and 95b of the source-drain metal layer 90. The thin film transistor 19 may further include a lower electrode 35 as a shielding electrode.

[0097] like Figure 4As shown, the protection element 15 includes another part of each of the lower metal layer 30, the semiconductor layer 50 and the gate metal layer 70. More specifically, the protection element 15 includes the first lower electrode 31 and the second lower electrode 32 of the lower metal layer 30, the high resistance regions 51a, 52a and 53a and the low resistance regions 51b, 52b and 53b of the semiconductor layer 50, and the first gate electrode 71, the second gate electrode 72 and the third gate electrode 73 of the gate metal layer 70. As such, the protection element 15 does not include the source-drain metal layer 90.

[0098] Figure 4 The protection element 15 shown in the cross-sectional view (b) of FIG. 1 functions as a thin film transistor, wherein the gate is the second gate electrode 72, the drain is the first gate electrode 71, and the source is the third gate electrode 73. The second gate electrode 72 as the gate is connected to the first gate electrode 71 as the drain through the first lower electrode 31. Accordingly, the protection element 15 functions as a thin film transistor diode.

[0099] It should be noted that the protection element 15 functions as a transistor by reducing the resistance of the high resistance regions 51a and 52a of the semiconductor layer 50. The reduction in resistance of the high resistance regions 51a and 52a will be described later.

[0100] [2. Method for manufacturing display panel]

[0101] A method for manufacturing the display panel 10 according to the present embodiment will be described. Figures 3 to 18 A method for manufacturing the thin film transistor 19 and the protective element 15 of the display panel 10 will be described. Figure 5 , Figure 7 , Fig. 9 , Fig.11 , Fig.14 , Fig.16 and Fig.18 Schematic diagrams showing the steps of the method for manufacturing the protection element 15 according to the present embodiment. The top view (a) and the cross-sectional view (b) of the protection element 15 are shown in FIG. Figure 6 , Figure 8 , Fig.10 , Fig.12 , Fig.13 , Fig.15 and Fig.17 Shown. Figure 6 The VI-VI line of the top view (a) Figure 8 The VIII-VIII line of the top view (a), Fig.10 The top view (a) of the XX line, Fig.12 The top view (a) of the XII-XII line, Fig.13 The XIII-XIII line of the top view (a), Fig.15The top view (a) of the XV-XV line and Fig.17 The cross sections along the line XVII-XVII of the top view (a) are respectively Figure 6 , Figure 8 , Fig.10 , Fig.12 , Fig.13 , Fig.15 and Fig.17 The cross-sectional view (b) is shown.

[0102] First, if Figure 5 and Figure 6 As shown, an insulating substrate 20 is prepared. Next, a lower metal layer 30 is formed above the substrate 20. In the present embodiment, a Ti film with a thickness of 30 nm, a Cu film with a thickness of 800 nm, and a CuMn film with a thickness of 50 nm are sequentially formed on the substrate 20 using a sputtering method. The lower metal layer 30 can be patterned into a specified shape by photolithography, wet etching, and dry etching. Specifically, first, a resist is formed on the lower metal layer 30, and the resist is treated to leave the resist in an area of ​​a specified shape. Then, the Cu film and CuMn film constituting the lower metal layer 30 in the area where the resist is not formed are removed by wet etching. It should be noted that a strong acid containing hydrogen peroxide (H2O2) can also be used as a wet etchant. Next, the Ti film constituting the lower metal layer 30 in the area where the resist is not formed is removed by dry etching. It should be noted that a chlorine-containing gas can also be used in dry etching. Thus, the lower metal layer 30 is processed into a predetermined shape to form the lower electrode 35, the first lower electrode 31, and the second lower electrode 32. It should be noted that the lower metal layer 30 can also be used as a wiring for connecting the protection element 15, the common electrode 16, or the lead wiring 14.

[0103] Then, if Figure 7 and 8 As shown in FIG. 1 , a first interlayer insulating film 40 is formed on the lower metal layer 30. In this embodiment, a SiN film having a thickness of 100 nm is deposited by CVD (Chemical Vapor Deposition). x A 200 nm thick SiO2 film is sequentially formed on the substrate 20 and the lower metal layer 30. Specifically, for example, silane gas (SiH4), ammonia gas (NH3) and nitrogen gas (N2) are used as introduced gases to form SiN by a plasma CVD method. x Then, silane gas (SiH4) and nitrous oxide gas (N2O) are used as introduction gases to form a SiO2 film by a plasma CVD method.

[0104] Then, if Fig. 9 and 10As shown, a semiconductor layer 50 is formed above the first interlayer insulating film 40. In this embodiment, an oxide semiconductor film containing In, Ga and Zn with a film thickness of 30 nm is formed by sputtering. Specifically, an oxide semiconductor (In-Ga-Zn-O) containing In, Ga and Zn is used as a sputtering target, argon (Ar) flows into the vacuum chamber as an inert gas, and a gas containing oxygen (O2) flows into the vacuum chamber as a reactive gas, and an oxide semiconductor film is formed by applying a specified power density voltage to the target material and performing sputtering. Next, the oxide semiconductor film is patterned into a specified shape by photolithography and wet etching. At this time, for the purpose of adjusting the carrier concentration of the oxide semiconductor film, annealing treatment can be performed in an environment containing suitable oxygen, etc.

[0105] Then, if Fig.11 and Fig.12 As shown, a gate insulating film 60 is formed on the semiconductor layer 50. In this embodiment, a SiO2 film with a film thickness of 200 nm is formed on the first interlayer insulating film 40 and the semiconductor layer 50 by a CVD method.

[0106] Then, if Fig.13 As shown, in the area where the protection element 15 is formed, a contact hole 60h connected to the gate metal layer 70 is formed in the lower metal layer 30 and the semiconductor layer 50. In the present embodiment, a contact hole 60h that penetrates the gate insulating film 60, the semiconductor layer 50, and the first interlayer insulating film 40 is formed by photolithography and dry etching using CF-based gas. Here, a portion of the contact hole 60h has an area where only the gate insulating film 60 is removed. That is, a portion of the contact hole 60h is formed only in the range from the upper surface of the gate insulating film 60 to the upper surface of the semiconductor layer 50. Accordingly, a portion of the upper surface of the semiconductor layer 50 is exposed. In this way, when the gate insulating film 60 is dry-etched using CF-based gas, since a portion of the semiconductor layer 50 is exposed, the exposed area of ​​the semiconductor layer 50 is reduced in resistance by plasma damage. Accordingly, Fig.13 As shown, low resistance regions 51 b and 53 b are formed in the semiconductor layer 50 .

[0107] Then, if Fig.14 and Fig.15 As shown, a gate metal layer 70 is formed on the gate insulating film 60. In this embodiment, a Ti film with a thickness of 30 nm, a Cu film with a thickness of 400 nm, and a CuMn film with a thickness of 50 nm are sequentially formed on the gate insulating film 60 and inside the contact hole 60h by sputtering. Next, the gate metal layer 70 is patterned into a predetermined shape by photolithography, wet etching of the Cu film and the CuMn film constituting the gate metal layer 70, and dry etching of the Ti film constituting the gate metal layer 70. Thus, a gate metal layer 70 is formed. Fig.14The gate electrode 75 and Fig.15 The first gate electrode 71 , the second gate electrode 72 , and the third gate electrode 73 are shown. Here, the first gate electrode 71 is connected to the low resistance region 51 b of the semiconductor layer 50 , and the third gate electrode 73 is connected to the low resistance region 53 b of the semiconductor layer 50 .

[0108] Then, if Fig.16 and Fig.17 As shown, the gate insulating film 60 is patterned. In this embodiment, the gate insulating film 60 is patterned by dry etching using the gate metal layer 70 as a mask. For example, CF-based gas can be used in the dry etching. Thus, the gate insulating film 60 is patterned into the same shape as the gate metal layer 70.

[0109] In addition, by removing the gate insulating film 60 by dry etching and exposing the semiconductor layer 50, the semiconductor layer 50 in the exposed area can be damaged by plasma in the dry etching to reduce the resistance. Fig.16 The low resistance region 55b and Fig.17 It should be noted that the area of ​​the semiconductor layer 50 that is not damaged by plasma ( Fig.16 The high resistance region 55a and Fig.17 The high resistance regions 51a, 52a and 53a) shown are not made low-resistance.

[0110] Then, if Fig.18 and Figure 4 As shown in FIG. 1 , a second interlayer insulating film 80 is formed on the gate metal layer 70. In this embodiment, a SiO2 film with a thickness of 500 nm is formed on the gate metal layer 70, the semiconductor layer 50, and the first interlayer insulating film 40 by CVD. Thus, the source-drain metal layer 90 can be formed before the step of forming the source-drain metal layer 90. Figure 4 The protection element 15 is shown.

[0111] Then, if Figure 3 As shown, a source-drain metal layer 90 is formed on the second interlayer insulating film 80. In this embodiment, after a contact hole reaching the low resistance region 55b of the semiconductor layer 50 is formed in the second interlayer insulating film 80, a Ti film with a film thickness of 30nm, a Cu film with a film thickness of 800nm, and a CuMn film with a film thickness of 50nm are sequentially formed on the second interlayer insulating film 80 and inside the contact hole by sputtering. Next, the source-drain metal layer 90 is patterned into a predetermined shape by photolithography, wet etching of the Cu film and the CuMn film constituting the source-drain metal layer 90, and dry etching of the Ti film constituting the source-drain metal layer 90. In this way, a structure having Figure 3The source-drain metal layer 90 of the source-drain electrodes 95a and 95b is shown. It should be noted that the source-drain metal layer 90 can also be used as a wiring for connecting the protection element 15, the common electrode 16 or the lead wiring 14.

[0112] In the above-described manner, the present application can manufacture the display panel 10 having the thin film transistor 19 and the protection element 15 .

[0113] [3. Effect]

[0114] Effects of the display panel 10 and the method for manufacturing the same according to the present embodiment will be described.

[0115] As described above, the display panel 10 according to the present embodiment includes the protection element 15. Figure 4 As shown in FIG. 1 , the semiconductor layer 50 included in the protection element 15 has a high resistance region 51a located between the first gate region 71a of the first gate electrode 71 and the first lower electrode 31, and a low resistance region 51b having a lower resistance than the high resistance region 51a. The low resistance region 51b is connected to the first gate electrode 71, and the high resistance region 51a is connected to the low resistance region 51b and is located below the gate insulating film 60.

[0116] Furthermore, the semiconductor layer 50 included in the protection element 15 has a high resistance region 53a located between the third gate region 73a of the third gate electrode 73 and the second lower electrode 32, and a low resistance region 53b having a lower resistance than the high resistance region 53a. The low resistance region 53b is connected to the third gate electrode 73, and the high resistance region 53a is connected to the low resistance region 53b and is located below the gate insulating film 60.

[0117] Thus, the high resistance region 51a is arranged between the low resistance region 51b and the low resistance region 52b connected to the first gate electrode 71 (see FIG. Figure 4). In addition, the high resistance region 53a is arranged between the low resistance region 53b and the low resistance region 52b connected to the third gate electrode 73. Therefore, in this regard, the protection element 15 does not function as a transistor. However, in the protection element 15 related to the present embodiment, for example, when a high voltage is applied to the second lower electrode 32, an inversion layer is formed in the high resistance region 53a of the semiconductor layer 50 by the electric field generated by the second lower electrode 32. Therefore, the high resistance region 53a is low-resistance. An inversion layer is similarly formed in the high resistance region 51a of the semiconductor layer 50. Accordingly, the protection element 15 can function as a thin film transistor in which the first gate electrode 71 is a drain, the second gate electrode 72 is a gate, and the third gate electrode 73 is a source. In addition, since the first gate electrode 71 and the second gate electrode 72 are connected by the first lower electrode 31, the protection element 15 can function as a thin film transistor diode. Accordingly, the charge carried by the display panel 10 can be released to the common electrode 16 via the protection element 15. Therefore, insulation breakdown in the manufacturing process of the display panel 10 can be suppressed.

[0118] In addition, as described above, in the method for manufacturing the display panel 10 according to the present embodiment, the protection element 15 is formed before the step of forming the source-drain metal layer 90. Therefore, even before the step of forming the source-drain metal layer 90, the protection element 15 can be used to suppress insulation breakdown in the display panel 10 during manufacturing.

[0119] For example, when the gate metal layer 70 and the gate insulating film 60 are processed by dry etching, charges can be accumulated in the electrically floating (in a floating state) gate metal layer 70. In addition, when the second interlayer insulating film 80 is formed, charges can also be accumulated on the surface of the second interlayer insulating film 80 and the gate metal layer 70. In these cases, since the protection element 15 related to the present embodiment has been completely formed, the charges can be released from the gate metal layer 70 to the common electrode 16. In this way, according to the protection element 15 related to the present embodiment, even before the process of forming the source-drain metal layer 90, insulation breakdown can be suppressed.

[0120] Furthermore, in the present embodiment, in the protection element 15, a thin film transistor type diode is formed by using the lower metal layer 30 instead of the source-drain metal layer 90. That is, in the display panel, the metal layer used as the shielding electrode is also used as the electrode of the protection element 15. Therefore, the protection element 15 can be formed without adding a metal layer dedicated to the protection element 15.

[0121] (Other embodiments)

[0122] The display panel 10 and the like related to the present application are described above based on the embodiments, but the display panel 10 and the like related to the present application are not limited to the above-mentioned embodiments. For the embodiments, within the scope of the present disclosure, various modifications that can be thought of by a person skilled in the art are also included in the present disclosure.

[0123] The present application is particularly useful for display devices having large display panels, etc.

Claims

1. A display panel having a display unit including a plurality of pixels and a protection element, characterized in that: The display panel comprises: Insulating substrate; a lower metal layer disposed above the substrate; A first interlayer insulating film disposed above the lower metal layer; a semiconductor layer disposed above the first interlayer insulating film; a gate insulating film disposed above the semiconductor layer; A gate metal layer, which is disposed above the gate insulating film; A second interlayer insulating film, which is disposed above the gate metal layer; a source-drain metal layer, which is arranged above the second interlayer insulating film, Each of the plurality of pixels has a thin film transistor including a portion of each of the semiconductor layer, the gate metal layer, and the source-drain metal layer. The protection element has a thin film transistor type diode including the lower metal layer, the semiconductor layer and another portion of each of the gate metal layer, The lower metal layer has: a first lower electrode; a second lower electrode disposed adjacent to the first lower electrode via the first interlayer insulating film; The gate metal layer has a first gate electrode, a second gate electrode and a third gate electrode, The second gate electrode is arranged at a position adjacent to each of the first gate electrode and the third gate electrode via the second interlayer insulating film. The first lower electrode is connected to each of the first gate electrode and the second gate electrode, The second lower electrode is connected to the third gate electrode, The first gate electrode has a first gate region disposed at a position opposing the first lower electrode. The second gate electrode has a second gate region disposed at a position opposing the first lower electrode. The third gate electrode has a third gate region disposed at a position facing the second lower electrode. The first gate electrode is connected to the first lower electrode and the semiconductor layer in the first gate region, The second gate electrode is connected to the first lower electrode and the semiconductor layer in the second gate region, The third gate electrode is connected to the second lower electrode and the semiconductor layer in the third gate region, The semiconductor layer has a high resistance region between the first gate region of the first gate electrode and the first lower electrode, and a low resistance region having a lower resistance than the high resistance region, The low resistance region is connected to the first gate electrode, The high resistance region is connected to the low resistance region and is located below the gate insulating film.

2. The display panel according to claim 1, wherein: The semiconductor layer includes an oxide semiconductor.

3. The display panel according to claim 2, wherein: The gate insulating film is patterned in the same shape as the gate metal layer.

4. A method for manufacturing a display panel, comprising: The manufacturing method of the display panel includes: A step of preparing an insulating substrate; forming a lower metal layer above the substrate; forming a first interlayer insulating film on the lower metal layer; forming a semiconductor layer on the first interlayer insulating film; forming a gate insulating film on the semiconductor layer; forming a gate metal layer on the gate insulating film; forming a second interlayer insulating film on the gate metal layer; forming a source-drain metal layer on the second interlayer insulating film, Each of the plurality of pixels has a thin film transistor including a portion of each of the semiconductor layer, the gate metal layer, and the source-drain metal layer. The protection element has a thin film transistor type diode including the lower metal layer, the semiconductor layer and another part of each of the gate metal layer, and the protection element is formed before the process of forming the source and drain metal layers. The lower metal layer has: a first lower electrode; a second lower electrode disposed adjacent to the first lower electrode via the first interlayer insulating film; The gate metal layer has a first gate electrode, a second gate electrode and a third gate electrode, The second gate electrode is arranged at a position adjacent to each of the first gate electrode and the third gate electrode via the second interlayer insulating film. The first lower electrode is connected to each of the first gate electrode and the second gate electrode, The second lower electrode is connected to the third gate electrode, The first gate electrode has a first gate region disposed at a position opposing the first lower electrode. The second gate electrode has a second gate region disposed at a position opposing the first lower electrode. The third gate electrode has a third gate region disposed at a position facing the second lower electrode. The first gate electrode is connected to the first lower electrode and the semiconductor layer in the first gate region, The second gate electrode is connected to the first lower electrode and the semiconductor layer in the second gate region, The third gate electrode is connected to the second lower electrode and the semiconductor layer in the third gate region, The semiconductor layer has a high resistance region between the first gate region of the first gate electrode and the first lower electrode, and a low resistance region having a lower resistance than the high resistance region, The low resistance region is connected to the first gate electrode, The high resistance region is connected to the low resistance region and is located below the gate insulating film.

5. The method for manufacturing a display panel according to claim 4, wherein: The semiconductor layer includes an oxide semiconductor.

6. The method for manufacturing a display panel according to claim 5, wherein: The gate insulating film is patterned by dry etching using the gate metal layer as a mask.

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