Test control device and test system thereof

Abstract

The application provides a test control device and a test system thereof. The test control device is connected between an emulator and a plurality of JTAG devices in series. The test control device comprises a signal transceiver module, a multiplexing switch and a gating controller. A first JTAG pin group of the signal transceiver module is used to connect the emulator so that the test control device and the emulator interact with each other, and a TDI pin and a TDO pin of a second JTAG pin group are connected to an input end and an output end of the multiplexing switch, respectively. A first gating end and an i-th gating end of the multiplexing switch are connected to a TDI pin of a first JTAG device and a TDO pin of a last JTAG device, respectively, and other gating ends are connected to connecting lines between two adjacent JTAG devices in turn. The gating controller controls the input end and the output end to correspond to two gating ends so that the plurality of JTAG devices are in corresponding test modes, and the testable JTAG devices are different in different test modes.

Description

Technical Field

[0001] This invention belongs to the field of testing technology, and particularly relates to a test control device for controlling boundary scan testing of multiple JTAG devices connected in series, and a test system including the test control device. Background Technology

[0002] During PCB manufacturing, in-circuit testing of chips is typically performed to eliminate potential open circuits, short circuits, and other faults. Currently, most chips use the interface defined by the Joint Test Action Group (JTAG) (i.e., the JTAG interface).

[0003] In related technologies, PCBs are increasingly packed with large-scale integrated chips, and reserving a separate JTAG interface for each chip would waste a significant amount of board space. To address this issue, boundary scan testing is becoming increasingly common. Its advantage is that, based on the JTAG interface definition, the TDI pins (test data input pins) and TDO pins (test data output pins) of all chips are connected in series, thus requiring only one external JTAG interface and saving board space. However, this chain-like design reduces the flexibility of the test system. Testing any chip requires the test signal to traverse the entire test chain, increasing the uncertainty of the test results and adding complexity to the test design. Summary of the Invention

[0004] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention provides a test control device and a test system thereof. The test control device is used to control the boundary scan test of multiple JTAG devices connected in series, enabling any or some of the JTAG devices to be tested to be in the corresponding test mode, thereby avoiding the need for the test signal to pass through all JTAG devices, improving test flexibility and the reliability of test results.

[0005] To achieve the above objectives, in one aspect, the present invention provides a test control device for controlling boundary scan testing of multiple JTAG devices connected in series, each JTAG device including a TDI pin and a TDO pin, and the TDO pin of each JTAG device being connected via a connecting line to the TDI pin of the next JTAG device located in the series direction, the test control device comprising:

[0006] The signal transceiver module includes a first JTAG pin group and a second JTAG pin group. Both the first JTAG pin group and the second JTAG pin group include a TDI pin and a TDO pin. The first JTAG pin group is used to connect to an emulator to receive test signals from the emulator for boundary scan testing of at least one of the JTAG devices, and to output feedback signals after testing of at least one of the JTAG devices to the emulator.

[0007] A multiplexer switch includes an input terminal, an output terminal, and multiple gating terminals. The input terminal is connected to the TDI pin of the second JTAG pin group, and the output terminal is connected to the TDO pin of the second JTAG pin group. The multiple gating terminals include gating terminals 1 to N. The first gating terminal is connected to the TDI pin of the first JTAG device in the series direction, and the i-th gating terminal is connected to the TDO pin of the last JTAG device in the series direction. The other gating terminals between the first gating terminal and the i-th gating terminal are sequentially connected to the connection lines between two adjacent JTAG devices in the series direction, where N≥i and N is a natural number greater than or equal to 3.

[0008] A gating controller is connected to the multiplexer switch. The gating controller is used to control the two gating terminals connected to the input terminal and the output terminal respectively, so that the multiple JTAG devices are in the corresponding test modes. In different test modes, at least one of the two gating terminals connected to the input terminal and the output terminal is different, so that the JTAG devices being tested are different.

[0009] In one embodiment, the gating controller includes at least one signal receiving pin. The gating controller acquires a mode selection signal through the at least one signal receiving pin and determines the current test mode according to the mode selection signal, so as to control the input terminal and the output terminal to connect to the corresponding two gating terminals.

[0010] In one embodiment, the number of signal receiving pins is one, and the gating controller selects a signal based on the different attribute modes received by the one signal receiving pin to determine the corresponding test mode;

[0011] Alternatively, the number of signal receiving pins may be multiple, and the gating controller may select signals based on different combinations of modes received by the multiple signal receiving pins to determine the corresponding test mode;

[0012] The mode selection signal includes one or more of the following: a level signal, a floating signal, and a pulse signal.

[0013] In one embodiment, the test control device further includes a power pin for connecting to an input power supply, the power pin receiving a voltage provided by the input power supply to power the test control device.

[0014] The power supply pins are multiple, and each power supply pin is used to receive multiple voltages with different voltage values ​​provided by the input power supply; or, the power supply pin is one, and the power supply pin is used to receive a first voltage provided by the input power supply. The test control device also includes a voltage conversion module connected to the power supply pin. The voltage conversion module is used to acquire the first voltage and convert the first voltage into a second voltage, wherein the voltage values ​​of the first voltage and the second voltage are different.

[0015] In one embodiment, each of the JTAG devices and the second JTAG pin group includes a TCK pin, a TMS pin, and a TRST pin. The TCK pin of the second JTAG pin group is connected to the TCK pin of all JTAG devices, the TMS pin of the second JTAG pin group is connected to the TMS pin of all JTAG devices, and the TRST pin of the second JTAG pin group is connected to the TRST pin of all JTAG devices.

[0016] In one embodiment, the strobe pin is a GPIO pin.

[0017] In one embodiment, the signal transceiver module further includes a level converter disposed between the first JTAG pin group and the second JTAG pin group, the level converter being used to perform level tuning on the test signal received by the signal transceiver module through the first JTAG pin group;

[0018] And / or, the signal transceiver module further includes an equalizer disposed between the first JTAG pin group and the second JTAG pin group, the equalizer being used to perform signal compensation on the test signal received by the signal transceiver module through the first JTAG pin group.

[0019] On the other hand, the present invention also provides a test system for testing multiple JTAG devices connected in series. The test system includes an emulator and a test control device as described above, wherein the test control device is connected between the emulator and the multiple JTAG devices.

[0020] In one embodiment, the test system further includes a test host, and the emulator is connected to the test host via a communication interface. The test host is used to convert test scripts into test signals and transmit them to the emulator. The test host is also used to receive feedback signals transmitted by the emulator after testing at least one of the JTAG devices, so as to determine the test results of at least one of the JTAG devices based on the feedback signals.

[0021] In one embodiment, the gating controller includes a signal receiving pin for connecting to the test host, and the test host is further configured to provide a mode selection signal. The gating controller obtains the mode selection signal through the signal receiving pin to determine the current test mode.

[0022] Compared with the prior art, the present invention has the following advantages: by controlling the multiplexer and the multiple JTAG devices in different connection modes through the gating controller, the multiple JTAG devices can be in different test modes, so that different JTAG devices in different test modes can complete boundary scan tests. In particular, according to actual needs, any or some of the JTAG devices to be tested can be in the corresponding test mode, so that the test signal does not need to pass through all the JTAG devices, which can improve test flexibility and test result reliability.

[0023] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0025] Figure 1 This is a framework diagram of the test system provided in this embodiment of the invention for testing multiple JTAG devices connected in series.

[0026] Figure 2 yes Figure 1 The diagram shows the connection between the test system and multiple JTAG devices.

[0027] Figure 3 yes Figure 2 The diagram shows the structure of the test control device.

[0028] Figure 4 yes Figure 3The diagram shows the connection between the multiplexer of the test control device and multiple JTAG devices in one embodiment.

[0029] Figure 5 yes Figure 3 The diagram shows the connection between the multiplexer of the test control device and multiple JTAG devices in another embodiment.

[0030] Figure 6 yes Figure 3 The diagram shows the connection between the multiplexer of the test control device and multiple JTAG devices in another embodiment.

[0031] Explanation of key component symbols:

[0032] Test System 1

[0033] JTAG device 2

[0034] Emulator 20

[0035] Test control device 40

[0036] Test host 60

[0037] Signal transceiver module 41

[0038] First JTAG pin group 411

[0039] Second JTAG pin group 412

[0040] Level converter 413

[0041] Equalizer 414

[0042] Multiplexer switch 43

[0043] Input terminal 431

[0044] Output 432

[0045] strobe terminal 433

[0046] strobe controller 45

[0047] Signal receiving pin 451

[0048] Power pin 47

[0049] Voltage conversion module 49

[0050] The following detailed description, in conjunction with the accompanying drawings, further illustrates the present invention. Detailed Implementation

[0051] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0052] Please refer to the following: Figure 1 and Figure 2 This invention provides a test system 1 for performing boundary scan tests on multiple JTAG devices 2 connected in series. The JTAG devices 2 refer to devices that support the JTAG test protocol, including but not limited to digital signal processors, central processing units, or IC chips. Figure 2 In the illustrated embodiment, the JTAG devices 2 are all IC chips, and their number can be... Figure 2 The three shown (referred to as IC1, IC2, and IC3 respectively) can also be two, four, or more than four, and there is no limitation in this regard. In other embodiments, the plurality of JTAG devices 2 can also be one type of JTAG device other than IC chips, or a combination of multiple JTAG devices, and there is no limitation in this regard either.

[0053] like Figure 2 As shown, in one embodiment of the present invention, each JTAG device 2 includes a TDI pin, a TDO pin, a TCK pin, a TMS pin, and a TRST pin. The TDO pin of each JTAG device 2 is connected via a connecting line to the TDI pin of the next JTAG device 2 in the series direction. That is, the TDI and TDO pins of the plurality of JTAG devices 2 are connected sequentially, thereby realizing the series connection between the plurality of JTAG devices 2. Those skilled in the art will understand that the TDI pin, TCK pin, TMS pin, and TRST pin are respectively used to receive TDI signals, TCK signals, TMS signals, and TRST signals to enable the JTAG device 2 to complete the boundary scan test. After completing the boundary scan test, the JTAG device 2 can output a TDO signal through the TDO pin as a feedback signal. It is also understood that each JTAG device 2 further includes other components, such as a test access port controller, for controlling the connection between the internal circuitry of the JTAG device 2 and the TDI pin, TDO pin, TCK pin, TMS pin, and TRST pin. The specific structure of the JTAG device 2 and the principle of completing the boundary scan test are the same as those of the existing JTAG device, and will not be described in detail here.

[0054] Please combine Figure 1 and Figure 2In one embodiment of the present invention, the test system 1 includes a simulator 20, a test control device 40, and a test host 60. The test control device 40 is connected between the simulator 20 and the plurality of JTAG devices 2 connected in series. The simulator 20 is connected to the test host 60 through a communication interface. The communication interface can be, but is not limited to, any communication interface such as a USB interface, a CAN network interface, an Ethernet interface, or a serial port interface, as long as it enables communication between the simulator 20 and the test host 60; there is no limitation on this.

[0055] It should be noted that, in the embodiments of the present invention, the test host 60 is used to convert the test script into a test signal and transmit it to the emulator 20. The emulator 20 is used to acquire the test signal and transmit it to at least one of the JTAG devices 2 through the test control device 40 for testing. The emulator 20 is also used to receive the feedback signal (i.e., the aforementioned TDO signal) output by the test control device 40 after the at least one JTAG device 2 has been tested and transmit it to the test host 60. The test host 60 can analyze the test results of at least one JTAG device 2 based on the feedback signal, thereby determining whether any of the tested JTAG devices 2 has an internal fault.

[0056] The test script can be pre-stored in the test host 60 or written by the tester using the test host 60. The test signals generated by the test script include the aforementioned TDI signal, TCK signal, TMS signal, and TRST signal. After the JTAG device 2 acquires the test signals, it can complete the boundary scan test and output the aforementioned TDO signal as the feedback signal, which is then fed back to the test host 60 through the simulator 20, so that the test host 60 can analyze the test results based on the feedback signal. In embodiments of the present invention, the test host 60 can be, but is not limited to, a PC.

[0057] It is important to note that, in the embodiments of the present invention, the test control device 40 is used to control the boundary scan test of the plurality of JTAG devices 2 connected in series. Specifically, the test control device 40 can control any one of the plurality of JTAG devices 2 to be tested individually, or it can control two or more of the plurality of JTAG devices 2 connected in series to be tested simultaneously. In other words, the test control device 40 can control the number of JTAG devices 2 performing boundary scan tests according to user needs, which is equivalent to controlling the length of the test link formed by the plurality of JTAG devices 2 being tested.

[0058] Please refer to the following: Figure 2 and Figure 3 In embodiments of the present invention, the test control device 40 includes at least a signal transceiver module 41, a multiplexer switch 43, and a gating controller 45. It should be noted that the test control device 40 may be, but is not limited to, a control chip, a control circuit, or a programmable controller; no limitation is imposed in this regard.

[0059] Specifically, such as Figure 3 As shown, the signal transceiver module 41 includes a first JTAG pin group 411 and a second JTAG pin group 412. Both the first JTAG pin group 411 and the second JTAG pin group 412 include a TDI pin, a TDO pin, a TCK pin, a TMS pin, and a TRST pin. Please refer to... Figure 2 and Figure 3 The first JTAG pin group 411 is used to connect to the emulator 20 to receive the test signal for performing boundary scan test on at least one of the JTAG devices 2 from the emulator 20, and to output the feedback signal after testing at least one of the JTAG devices 2 to the emulator 20, and then feed the feedback signal back to the test host 60 through the emulator 20, so that the test host 60 can determine whether any of the tested JTAG devices 2 has an internal fault based on the feedback signal.

[0060] Specifically, such as Figure 2 As shown, in an embodiment of the present invention, the emulator 20 has a JTAG interface for connecting to the first JTAG pin group 411. The TDI, TDO, TCK, TMS, and TRST pins in the JTAG interface are respectively connected to the TDI, TDO, TCK, TMS, and TRST pins of the first JTAG pin group 411, enabling the emulator 20 to interact with the test control device 40 (specifically, the signal transceiver module 41) to exchange the test signals (i.e., TDI, TCK, TMS, and TRST signals) and the feedback signal (i.e., TDO signal). The emulator 20 also includes a pin for connecting to the drive voltage VCC and a pin for grounding. The emulator 20 can use an existing 10-pin emulator, including but not limited to J-Link emulators, CMSIS DAP emulators, or OpenJtag emulators; there is no limitation on this.

[0061] Please combine again Figure 2 and Figure 3In an embodiment of the present invention, the TCK pin of the second JTAG pin group 412 is connected to the TCK pin of all JTAG devices 2, the TMS pin of the second JTAG pin group 412 is connected to the TMS pin of all JTAG devices 2, and the TRST pin of the second JTAG pin group 412 is connected to the TRST pin of all JTAG devices 2, thereby enabling the signal transceiver module 41 to transmit the TCK signal, TMS signal and TRST signal in the test signal obtained by the first JTAG pin group 411 to each JTAG device 2. The TDI and TDO pins of the second JTAG pin group 412 are respectively connected to the multiplexer 43, so that the TDI signal in the test signal is transmitted to at least one of the JTAG devices 2 to be tested through the multiplexer 43, and the TDO signal (feedback signal) output by at least one of the JTAG devices 2 after testing is received through the multiplexer 43. After the signal transceiver module 41 obtains the feedback signal through the second JTAG pin group 412, it further transmits it to the emulator 20 through the TDO pin of the first JTAG pin group 411, and then the emulator 20 feeds the feedback signal back to the test host 60, thereby completing the test.

[0062] Specifically, such as Figure 3 As shown, the multiplexer 43 includes an input terminal 431, an output terminal 432, and multiple selection terminals 433. The input terminal 431 and the output terminal 432 are respectively connected to the TDI pin and TDO pin of the second JTAG pin group 412. Please refer to... Figure 2 and Figure 3 The plurality of selectors 433 includes 1 to N selectors 433. The 1st selector 433 is connected to the TDI pin of the first JTAG device 2 in the serial direction, and the i-th selector 433 is connected to the TDO pin of the last JTAG device 2 in the serial direction. The other selectors 433 between the 1st selector 433 and the i-th selector 433 are sequentially connected to the connection lines between two adjacent JTAG devices 2 in the serial direction, where N ≥ i, and N is a natural number greater than or equal to 3. In an embodiment of the present invention, the number of selectors 433 of the multiplexer 43 is at least one more than the number of JTAG devices 2, which means that the number of JTAG devices 2 that the test control device 40 can control is at least one less than the number of selectors 433.

[0063] In embodiments of the present invention, the selection terminal 433 of the multiplexer 43 preferably uses a low-power, low-cost, and simple-wiring GPIO (General Purpose Input Output) pin. Each GPIO pin is connected to a GPIO line, and then connected to the corresponding TDI pin, or TDO pin, or the connecting line through the GPIO line. Specifically, as shown... Figure 3 As shown, the first gating terminal 433 is connected to the first GPIO line, the second gating terminal 433 is connected to the second GPIO line, and so on, with the Nth gating terminal 433 connected to the Nth GPIO line. Figure 2 and Figure 3 In the illustrated embodiment, there are five select terminals 433, and five GPIO lines, sequentially named GPIO1, GPIO2, GPIO3, GPIO4, and GPIO5. Specifically, the first select terminal 433, through its connected first GPIO line GPIO1, connects to the TDI pin of IC1 (i.e., the first JTAG device 2 in the serial direction). The second select terminal 433, through its connected second GPIO line GPIO2, connects to the connection line between IC1 and IC2. The third select terminal 433, through its connected third GPIO line GPIO3, connects to the connection line between IC2 and IC3. The fourth select terminal 433, through its connected fourth GPIO line GPIO4, connects to the TDO pin of IC3. The fifth select terminal 433, through its connected fifth GPIO line GPIO5, is left unused. It can be understood that in... Figure 2 and Figure 3 In the illustrated embodiment, the unused fifth strobe terminal 433 and its connected fifth GPIO line GPIO5 can serve as a backup connection. This not only allows for replacement when any of the other strobe terminals 433 and their connected GPIO lines fail, making the connection schemes between the test control device 40 and the multiple JTAG devices 2 more diverse and reliable, but also enables connection to the TDO pin of IC4 when an additional JTAG device 2 (such as IC4) is added. Correspondingly, the fourth strobe terminal 433 and its connected fourth GPIO line GPIO4 are connected to the connection line between IC3 and IC4, allowing the test control device 40 to control boundary scan tests of more JTAG devices 2, thus improving the applicability of the test system 1. Of course, in other embodiments, the test control device 40 may not have an unused strobe terminal 433 and its connected GPIO line.

[0064] Furthermore, please refer again. Figure 3In an embodiment of the present invention, the gating controller 45 is connected to the multiplexer 43 and is used to control the two gating terminals 433 connected to the input terminal 431 and the output terminal 432 respectively, so that the plurality of JTAG devices 2 are in the corresponding test modes. In different test modes, at least one of the two gating terminals 433 connected to the input terminal 431 and the output terminal 432 is different, so that the JTAG devices being tested are different. It should be noted that both the input terminal 431 and the output terminal 432 can be connected to either of the gating terminals 433 under the control of the gating controller 45, but the input terminal 431 and the output terminal 432 will not be connected to the same gating terminal 433. Thus, when the input terminal 431 and the output terminal 432 are respectively connected to the corresponding two gating terminals 433, the two gating terminals 433 can be connected to the TDI pin and TDO pin of at least one JTAG device 2 through the corresponding two GPIO lines, thereby enabling at least one JTAG device 2 to communicate with the test control device 40. In this way, the JTAG device 2 can receive the test signal to complete the boundary scan test, and output the feedback signal to the test control device 40 after completing the test.

[0065] It is understood that, in the embodiments of the present invention, when either of the two gate terminals 433 connected to the input terminal 431 and the output terminal 432 changes, the JTAG device 2 connected to the test control device 40 changes, and the JTAG device 2 capable of performing boundary scan testing also changes.

[0066] Specifically, please refer to Figures 4 to 6 The following describes the various test modes corresponding to the multiple JTAG devices 2 when the two gates 433 connected to the input terminal 431 and the output terminal 432 are in different states.

[0067] like Figure 4As shown, in one embodiment of the present invention, the input terminal 431 is connected to the first gating terminal 433, and then the first GPIO line GPIO1 connected through the first gating terminal 433 is connected to the TDI pin of IC1 (i.e., the first JTAG device 2). The output terminal 432 is connected to the fourth gating terminal 433, and then the fourth GPIO line GPIO4 connected through the fourth gating terminal 433 is connected to the TDO pin of IC3 (i.e., the last JTAG device 2). At this time, IC1, IC2 and IC3 connected in series are all connected to the test control device 40, so that IC1, IC2 and IC3 can be sequentially subjected to boundary scan test. In this embodiment, the gating controller 45 controls the input terminal 431 and the output terminal 432 to be connected to the TDI and TDO pins at the beginning and end of the series-connected JTAG devices 2, respectively, so that all JTAG devices 2 can be subjected to boundary scan testing. At this time, the test link formed by the multiple JTAG devices 2 being tested is the longest, and the test signal transmitted by the test control device 40 needs to pass through all JTAG devices 2. Figure 4 In the embodiment shown, the test mode corresponding to the plurality of JTAG devices 2 can be referred to as the full-scale test mode.

[0068] like Figure 5 As shown, in another embodiment of the present invention, the input terminal 431 is connected to the second gating terminal 433, and the second GPIO line GPIO2 connected through the second gating terminal 433 is correspondingly connected to the connection line between IC1 and IC2 connected in series. The output terminal 432 is connected to the fourth gating terminal 433, and the fourth GPIO line GPIO4 connected through the fourth gating terminal 433 is correspondingly connected to the TDO pin of IC3. At this time, both IC2 and IC3 connected in series are connected to the test control device 40, so that IC2 and IC3 can be sequentially subjected to boundary scan tests. It can be understood that in Figure 5In the illustrated embodiment, the output terminal 432 can also be connected to the third gating terminal 433, and then the third GPIO line GPIO3 connected through the third gating terminal 433 can be connected to the connection line between the series-connected IC2 and IC3, so that both the series-connected IC1 and IC2 are connected to the test control device 40 to complete the boundary scan test. In this embodiment, only some of the series-connected JTAG devices 2 can be tested for boundary scan. At this time, the test link formed by the multiple JTAG devices 2 being tested is shorter. The test signal transmitted by the test control device 40 only needs to pass through some of the JTAG devices 2, and does not need to pass through all of the JTAG devices 2. This can reduce the single test time and the uncertainties affecting the test results, which is conducive to quickly obtaining the single test results, thereby improving the efficiency of the single test and the reliability of the test results. Moreover, different parts of the JTAG devices 2 can be tested as needed, which also improves the test flexibility. Figure 5 In the embodiment shown, the test mode corresponding to the plurality of JTAG devices 2 can be referred to as the multi-person test mode.

[0069] like Figure 6 As shown, in another embodiment of the present invention, the input terminal 431 is connected to the first strobe terminal 433, and then the first GPIO line GPIO1 connected to the first strobe terminal 433 is connected to the TDI pin of IC1. The output terminal 432 is connected to the second strobe terminal 433, and then the second GPIO line GPIO2 connected to the second strobe terminal 433 is connected to the connection line between IC1 and IC2 connected in series. At this time, only IC1 is connected to the test control device 40, so only IC1 can perform boundary scan testing. It is not difficult to understand that in Figure 6 In the illustrated embodiment, the input terminal 431 and the output terminal 432 can also be connected to the second and third gating terminals 433, or to the third and fourth gating terminals 433, respectively, so that only IC2 or IC3 is connected to the test control device 40 to complete the boundary scan test individually. In this embodiment, only one of the plurality of JTAG devices 2 can be tested independently, and the test link formed by the plurality of JTAG devices 2 being tested is the shortest. The test signal transmitted by the test control device 40 only needs to pass through one of the JTAG devices 2, and does not need to pass through all of the JTAG devices 2, which can also improve the efficiency of a single test and the reliability of the test results, and increase the test flexibility. Figure 6 In the embodiment shown, the test mode corresponding to the plurality of JTAG devices 2 can be referred to as the single-person test mode.

[0070] It is understood that, in the embodiments of the present invention, all of the plurality of JTAG devices 2 can undergo boundary scan testing only when they are in the full-scale testing mode. When they are in the multi-scale testing mode or the single-scale testing mode, only some of the JTAG devices 2 or a single JTAG device 2 can undergo boundary scan testing. Therefore, when the plurality of JTAG devices 2 are in the multi-scale testing mode or the single-scale testing mode, multiple tests are required to complete the boundary scan testing of all the JTAG devices 2. It is also understood that when the plurality of JTAG devices 2 complete the boundary scan testing of all the JTAG devices 2 through multiple tests, some of the JTAG devices 2 can be tested using the multi-scale testing mode, while another part or at least one of the JTAG devices 2 can be tested using the single-scale testing mode. Further details are omitted here.

[0071] In summary, in the test system 1 provided by the present invention, the test control device 40 includes the signal transceiver module 41, the multiplexer switch 43, and the gating controller 45. The signal transceiver module 41 is connected between the multiplexer switch 43 and the simulator 20 of the test system 1. The multiplexer switch 43 connects multiple JTAG devices 2 connected in series. The gating controller 45 is connected to the multiplexer switch 43 and controls the multiple multiplexer switch 43 and the multiple JTAG devices 2 to be in different connection modes, thereby enabling the multiple JTAG devices 2 to be in different test modes, so that different JTAG devices 2 in different test modes can complete boundary scan tests. According to the actual test needs, any or some of the JTAG devices 2 that need to be tested can be in the corresponding test mode, so that the test signal does not need to pass through all the JTAG devices 2, improving the test flexibility and the reliability of the test results.

[0072] In an embodiment of the present invention, the gating controller 45 is used to control two gating terminals 433 correspondingly connected to the input terminal 431 and the output terminal 432, so that the plurality of JTAG devices 2 are in the corresponding test modes. Specifically, please refer to... Figure 3 According to Table 1, in an embodiment of the present invention, the gating controller 45 includes at least one signal receiving pin 451, and the gating controller 45 obtains a mode selection signal (e.g., ...) through the at least one signal receiving pin 451. Figure 3The signals M1-M3 shown are used to determine the current test mode based on the mode selection signal, so as to control the connection of the input terminal 431 and the output terminal 432 to the corresponding two selection terminals 433. The mode selection signal includes one or more of the following: a level signal, a floating signal, and a pulse signal; there is no limitation on this.

[0073] like Figure 3 As shown, in one embodiment of the present invention, the number of signal receiving pins 451 is three, defined as a first pin, a second pin, and a third pin, respectively. The first pin, the second pin, and the third pin are used to receive a first mode selection signal M1, a second mode selection signal M2, and a third mode selection signal M3, respectively. The gating controller 45 determines the test mode corresponding to the plurality of JTAG devices based on the different combinations of mode selection signals (M1-M3) received by the plurality of signal receiving pins 451. Table 1 below lists the one-to-one correspondence between the mode selection signals acquired by the gating controller 45 and the test modes of the plurality of JTAG devices 2.

[0074] Table 1

[0075] M1 M2 M3 Test mode IC1 IC2 IC3 L L L Test Mode 1 √ √ √ H L L Test Mode 2 √ √ × L H L Test Mode 3 × √ √ L L H Test Mode 4 √ × × H H L Test Mode 5 × √ × H L H Test Mode 6 × × √ L H H Reserved - - - H H H Reserved - - -

[0076] In Table 1, L and H represent low-level signals and high-level signals, respectively. "√" indicates connection, and "×" indicates disconnection. As shown in Table 1, each signal receiving pin 451 can receive a high-level signal or a low-level signal. The mode selection signals received by the multiple signal receiving pins 451 can form different combinations, and each combination corresponds to a test mode. For example, when the first pin, the second pin, and the third pin all receive a low-level signal, the gating controller 45 controls the input terminal 431 and the output terminal 432 to connect to the corresponding two gating terminals 433. All JTAG devices 2 (IC1-IC3) are then connected to the test control device 40, and the multiple JTAG devices 2 are in test mode 1 (i.e., the aforementioned all-personnel test mode). As another example, when the first pin receives a high-level signal and the second and third pins receive a low-level signal, the gating controller 45 controls the input terminal 431 and the output terminal 432 to connect to the corresponding two gating terminals 433. The series-connected JTAG devices 2 (IC1 and IC2) are then connected to the test control device 40, while the other JTAG devices 2 (IC3) are not connected to the test control device 40. The multiple JTAG devices 2 are in test mode 2 (i.e., one implementation of the aforementioned multi-personnel test mode). For example, when the first and second pins receive a low-level signal and the third pin receives a high-level signal, the gating controller 45 controls the input terminal 431 and the output terminal 432 to connect to the corresponding two gating terminals 433. Then, a single JTAG device 2 (IC1) is connected to the test control device 40, while the other JTAG devices 2 (IC2 and IC3) are not connected to the test control device 40. The multiple JTAG devices 2 are in test mode 4 (i.e., one implementation of the aforementioned single-user test mode). As mentioned earlier, the multi-user test mode also has other implementations (test mode 3 as shown in Table 1), and the single-user test mode also has other implementations (test modes 5-6 as shown in Table 1). When the multiple JTAG devices 2 are in test modes 3, 5, or 6, the signals received by the first pin, the second pin, and the third pin are shown in Table 1, and will not be elaborated further.

[0077] exist Figure 3In the embodiments shown in Table 1, the plurality of signal receiving pins 451 can receive eight combinations of mode selection signals, while the test modes corresponding to the three JTAG devices 2 have only six implementations, thus leaving two combinations of mode selection signals unused. Optionally, each unused combination of mode selection signals can be configured to correspond to any one of the test modes 1-6 shown in Table 1, that is, one or two of the test modes 1-6 can be determined by the gating controller 45 based on different two combinations of mode selection signals. Of course, each unused combination of mode selection signals can also be used to control the test control of the JTAG device 2 when the JTAG device 2 is added. For example, when the JTAG device 2 also includes IC4, the test modes corresponding to the four JTAG devices 2 have eight implementations, and the eight combinations of mode selection signals received by the plurality of signal receiving pins 451 can correspond one-to-one with the eight implementations of the test modes, which will not be elaborated further.

[0078] It is understood that in other embodiments, when the number of JTAG devices 2 is 4 or more, there are more than 8 implementations of the corresponding test modes. Therefore, the number of signal receiving pins 451 needs to be increased accordingly, and each signal receiving pin 451 can receive both high and low level signals, so that the multiple signal receiving pins 451 can receive more than 8 combinations of mode selection signals, thereby ensuring that the multiple combinations of mode selection signals can correspond one-to-one with the multiple implementations of the test modes corresponding to the multiple JTAG devices 2. Of course, in other embodiments, when the number of JTAG devices 2 is 4 or more, the number of signal receiving pins 451 can still be set to 3, but each signal receiving pin 451 can receive high-level signals or low-level signals with different signal values ​​or signal durations. Alternatively, the number of signal receiving pins 451 can be set to 3, but each signal receiving pin 451 can receive high-level signals, low-level signals, floating signals, or pulse signals. That is, each signal receiving pin 451 can receive more than 2 types of mode selection signals. Similarly, the multiple signal receiving pins 451 can receive more than 8 combinations of mode selection signals, ensuring that multiple combinations of mode selection signals can correspond one-to-one with the various implementation methods of the test modes corresponding to the multiple JTAG devices 2. This is not limited.

[0079] In other embodiments, the number of signal receiving pins 451 may also be one, and the gating controller 45 determines the test mode corresponding to the JTAG device 2 based on the different attribute mode selection signals received by the one signal receiving pin 451. The attributes of the mode selection signals include signal type, signal value, and signal duration, etc.

[0080] It should be noted that, in the embodiments of the present invention, the multiple mode selection signals can be provided by the test host 60, or by a dedicated signal source (not limited to a high-level signal source, a low-level signal source, and ground, etc.). Specifically, in one possible implementation, each signal receiving pin 451 can be correspondingly provided with a switching element, and the switching element can realize the connection or disconnection with the high-level signal source, the low-level signal source, and ground. Similarly, each signal receiving pin 451 can be connected to different mode selection signals, which will not be elaborated further. Figure 2 and Figure 3 In the illustrated embodiment, the gating controller 45 is connected to the test host 60 via the signal receiving pin 451, and the test host 60 is also used to provide the mode selection signal.

[0081] Please refer to it again. Figure 2 and Figure 3 Preferably, in one embodiment of the present invention, the signal transceiver module 41 further includes a level converter 413 and an equalizer 414 disposed between the first JTAG pin group 411 and the second JTAG pin group 412. The level converter 413 is connected to the equalizer 414. The level converter 413 is used to perform level tuning on the test signal received by the signal transceiver module 41 through the first JTAG pin group 411, and the equalizer 414 is used to perform signal compensation on the test signal. In this embodiment, by performing level tuning on the test signal through the level converter 413, the level standard of the test signal can be made to meet the level standard of the test access port of different JTAG devices 2. By performing signal compensation on the test signal through the equalizer 414, the problem of test signal attenuation when the test link is long can be solved. Thus, through the processing of the equalizer 414 and the level converter 413, the signal transceiver module 41 can output the test signal after signal compensation and level tuning, thereby improving the stability of the test system 1.

[0082] In other embodiments, the signal transceiver module 41 may also only include the level converter 413 or the equalizer 414, which can also improve the stability of the test system 1, and there is no limitation on this.

[0083] In the above embodiments, the level converter 413 and the equalizer 414 can be existing level converters and equalizers. The specific structure and working principle of the level converter 413 and the equalizer 414 will not be described in detail here.

[0084] Furthermore, such as Figure 3As shown, in one embodiment of the present invention, the test control device 40 further includes a power pin 47 for connecting to an input power supply (not shown). The power pin 47 receives the voltage provided by the input power supply to enable the test control device 40 to operate, for example, by transmitting it to the signal transceiver module 41 to enable it to operate normally.

[0085] Optionally, in one embodiment, the number of power supply pins 47 is plurality of pins, each of which is used to receive a plurality of voltages with different voltage values ​​provided by the input power supply. Figure 3 In the example, there are two power supply pins 47, one for receiving a first voltage (e.g., 1.8V, denoted as P1V8) and the other for receiving a second voltage (e.g., 3.3V, denoted as P3V3). Preferably, in Figure 3 In the illustrated embodiment, the test control device 40 may be equipped with a voltage conversion module 49 electrically connected to the plurality of power supply pins 47. The voltage conversion module 49 is used to convert the voltage received by any of the power supply pins 47 into a voltage with another voltage value. Thus, when one of the plurality of power supply pins 47 fails, the voltage conversion module 49 can correspondingly convert and output the voltage that the faulty power supply pin 47 should receive, thereby ensuring the normal operation of the test control device 40 and improving the operational safety and reliability of the test control device 40.

[0086] Of course, in another possible implementation, the number of power supply pins 47 can be set to only one. The power supply pin 47 is used to receive a first voltage (such as the aforementioned 1.8V) provided by the input power supply. The test control device 40 also includes a voltage conversion module 49 connected to the power supply pin 47. The voltage conversion module 49 is used to acquire the first voltage and convert it into a second voltage (such as the aforementioned 3.3V). The voltage values ​​of the first voltage and the second voltage are different. Through the voltage conversion function of the voltage conversion module 49, various voltages with different values ​​that meet the operational requirements of the test control device 40 can also be output.

[0087] It should be noted that, in the embodiments of the present invention, the voltage conversion module 49 includes multiple working units such as a voltage boosting unit and a voltage regulating unit. The specific structure and working principle of the voltage conversion module 49 are the same as those of existing voltage conversion modules, and will not be described in detail here. In the embodiments of the present invention, the input power supply can be the power generated after the operating voltage of the test host 60 is stepped down by components such as resistors inside the test host 60, or it can be a power supply outside the test system 1, such as mains power converted by a corresponding adapter; there is no limitation on this.

[0088] In the description of this invention, the terms "embodiment," "specific embodiment," "example," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0089] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A test control device for controlling boundary scan testing of multiple JTAG devices connected in series, each JTAG device including a TDI pin and a TDO pin, wherein the TDO pin of each JTAG device is connected via a connecting line to the TDI pin of the next JTAG device located in the series direction, characterized in that, The test control device includes: The signal transceiver module includes a first JTAG pin group and a second JTAG pin group. Both the first JTAG pin group and the second JTAG pin group include a TDI pin and a TDO pin. The first JTAG pin group is used to connect to an emulator to receive test signals from the emulator for boundary scan testing of at least one of the JTAG devices, and to output feedback signals after testing of at least one of the JTAG devices to the emulator. A multiplexer switch includes an input terminal, an output terminal, and multiple gating terminals. The input terminal is connected to the TDI pin of the second JTAG pin group, and the output terminal is connected to the TDO pin of the second JTAG pin group. The multiple gating terminals include gating terminals 1 to N. The first gating terminal is connected to the TDI pin of the first JTAG device in the series direction, and the i-th gating terminal is connected to the TDO pin of the last JTAG device in the series direction. The other gating terminals between the first gating terminal and the i-th gating terminal are sequentially connected to the connection lines between two adjacent JTAG devices in the series direction, where N≥i and N is a natural number greater than or equal to 3. A gating controller is connected to the multiplexer switch. The gating controller is used to control the two gating terminals connected to the input terminal and the output terminal respectively, so that the plurality of JTAG devices are in the corresponding test modes. In different test modes, at least one of the two gating terminals connected to the input terminal and the output terminal is different, so that the JTAG devices being tested are different. The testing modes for the multiple JTAG devices include a full-device testing mode, a multi-device testing mode, and a single-device testing mode. When the multiple JTAG devices are in the full-device testing mode, all of the JTAG devices are tested. When the multiple JTAG devices are in the multi-device testing mode, at least two of the JTAG devices are tested, and at least one of the JTAG devices is not tested. When the multiple JTAG devices are in the single-device testing mode, one of the multiple JTAG devices is tested.

2. The test control device as described in claim 1, characterized in that, The gating controller includes at least one signal receiving pin. The gating controller acquires a mode selection signal through the at least one signal receiving pin and determines the current test mode according to the mode selection signal, so as to control the input terminal and the output terminal to connect to the corresponding two gating terminals.

3. The test control device as described in claim 2, characterized in that, The number of signal receiving pins is one, and the gating controller selects a signal based on the different attribute modes received by the one signal receiving pin to determine the corresponding test mode; Alternatively, the number of signal receiving pins may be multiple, and the gating controller may select signals based on different combinations of modes received by the multiple signal receiving pins to determine the corresponding test mode; The mode selection signal includes one or more of the following: a level signal, a floating signal, and a pulse signal.

4. The test control device as described in claim 1, characterized in that, The test control device further includes a power pin for connecting to an input power supply, the power pin receiving a voltage provided by the input power supply to power the test control device. The power supply pins are multiple, and each power supply pin is used to receive multiple voltages with different voltage values ​​provided by the input power supply; or, the power supply pin is one, and the power supply pin is used to receive a first voltage provided by the input power supply. The test control device also includes a voltage conversion module connected to the power supply pin. The voltage conversion module is used to acquire the first voltage and convert the first voltage into a second voltage, wherein the voltage values ​​of the first voltage and the second voltage are different.

5. The test control device as described in claim 1, characterized in that, Each JTAG device and the second JTAG pin group include a TCK pin, a TMS pin, and a TRST pin. The TCK pin of the second JTAG pin group is connected to the TCK pin of all JTAG devices, the TMS pin of the second JTAG pin group is connected to the TMS pin of all JTAG devices, and the TRST pin of the second JTAG pin group is connected to the TRST pin of all JTAG devices.

6. The test control device as described in claim 1, characterized in that, The strobe pin is a GPIO pin.

7. The test control device according to any one of claims 1-6, characterized in that, The signal transceiver module further includes a level converter disposed between the first JTAG pin group and the second JTAG pin group. The level converter is used to perform level tuning on the test signal received by the signal transceiver module through the first JTAG pin group. And / or, the signal transceiver module further includes an equalizer disposed between the first JTAG pin group and the second JTAG pin group, the equalizer being used to perform signal compensation on the test signal received by the signal transceiver module through the first JTAG pin group.

8. A test system for testing multiple JTAG devices connected in series, characterized in that, The test system includes a simulator and a test control device as described in any one of claims 1-7, wherein the test control device is connected between the simulator and the plurality of JTAG devices.

9. The testing system as described in claim 8, characterized in that, The testing system further includes a testing host, and the simulator is connected to the testing host via a communication interface. The testing host is used to convert test scripts into test signals and transmit them to the simulator. The testing host is also used to receive feedback signals transmitted by the simulator after testing at least one of the JTAG devices, so as to determine the test results of at least one of the JTAG devices based on the feedback signals.

10. The testing system as described in claim 9, characterized in that, The gating controller includes a signal receiving pin for connecting to the test host. The test host is also used to provide a mode selection signal. The gating controller obtains the mode selection signal through the signal receiving pin to determine the current test mode.

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