A temperature independent reference source circuit

Abstract

The application belongs to the field of integrated circuit design, and particularly relates to a temperature-independent reference source circuit, which comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a first NPN transistor, a second NPN transistor, a third NPN transistor, a fourth NPN transistor, a fifth NPN transistor, a sixth NPN transistor, a seventh NPN transistor, an eighth NPN transistor, a ninth NPN transistor, a tenth NPN transistor, an eleventh NPN transistor, a twelfth NPN transistor, a capacitor, a power supply end, an input signal end and a ground end; the output voltage and the output current generated by the circuit have the characteristics of low temperature drift, simple structure, low design complexity, small chip area occupation and the like.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of integrated circuit design, and particularly relates to a temperature-independent reference source circuit. BACKGROUND

[0002] The temperature-independent reference source circuit is widely used in integrated circuits, especially in power management chips, to provide a stable reference voltage and reference current that is not affected by temperature, so as to improve the yield, accuracy and reliability of the overall circuit.

[0003] As Figure 1 A conventional temperature-independent reference source circuit includes two parts: a reference voltage generating unit and a current source generating unit, wherein the reference voltage generating unit includes a first operational amplifier A1, a first PMOS transistor M1 and a second PMOS transistor M2, a first NPN transistor Q1 and a second NPN transistor Q2, a first resistor R1, a second resistor R2 and a third resistor R3, and is used to generate a temperature-independent reference voltage V OUT ; M2 and M1 form a current mirror to copy the current in M1 to generate I PTAT ; the current source generating unit includes a second operational amplifier A2, a third PMOS transistor M3 and a fourth PMOS transistor M4, and a fourth resistor R4, and is used to generate a temperature-independent current source I OUT ; M4 and M3 form a current mirror to copy the current in M3 and output. According to the virtual short and virtual open principle, A2 adds V OUT to R4, and the current in R4 is output through the current mirror, wherein:

[0004] I OUT = V OUT / R4.

[0005] The resistor is a polysilicon resistor. Since the temperature coefficient of the polysilicon resistor in the semiconductor process is very small, the current I OUT is close to zero temperature coefficient. The conventional temperature-independent reference source generating circuit includes two operational amplifiers, which occupies a large chip area and increases the cost of the overall circuit. SUMMARY

[0006] To overcome the shortcomings of the above-mentioned reference source generating circuit, the present application provides a temperature-independent reference source circuit, which includes first to fourth resistors, first to seventh PMOS transistors, first to twelfth NPN transistors, a capacitor, a power supply end, an input signal end and a ground end, wherein:

[0007] The source of the first to sixth PMOS tubes is connected with the power supply end, the gate of the first PMOS tube is connected with the drain of the first PMOS tube, the collector of the first NPN transistor and the gates of the second to fourth PMOS tubes, the base of the first NPN transistor is connected with the base of the second NPN transistor, the drain of the second PMOS tube, the collector of the sixth NPN transistor and one end of the capacitor;

[0008] The emitter of the first NPN transistor is connected with the first resistor and one end of the second resistor, the other end of the first resistor is connected with the collector and base of the third NPN transistor and the bases of the fourth NPN transistor and the fifth NPN transistor;

[0009] The other end of the second resistor is connected with the collector of the fourth NPN transistor, the base of the sixth NPN transistor and the other end of the capacitor;

[0010] The emitter of the fourth NPN transistor is connected with one end of the third resistor, and the other end of the third resistor is connected with the ground end;

[0011] The collector of the second NPN transistor is connected with the power supply end, the emitter is connected with the collector of the fifth NPN transistor and serves as the voltage source output end of the circuit;

[0012] The gate of the fifth PMOS tube is connected with the drain of the fifth PMOS tube, the gate of the sixth PMOS tube and the collector of the eighth NPN transistor;

[0013] The gate of the seventh PMOS tube is connected with the input signal end, the source is connected with the drain of the third PMOS tube and the drain of the sixth PMOS tube, and the drain is connected with the collector and base of the ninth NPN transistor and the base of the tenth NPN transistor;

[0014] The base of the eighth NPN transistor is connected with the drain of the fourth PMOS tube and the collector of the seventh NPN transistor, the emitter is connected with the base of the seventh NPN transistor and one end of the fourth resistor, and the other end of the fourth resistor is connected with the ground end;

[0015] The emitter of the ninth NPN transistor is connected with the collector and base of the eleventh NPN transistor and the base of the twelfth NPN transistor;

[0016] The collector of the tenth NPN transistor serves as the current source output end independent of temperature, and the emitter is connected with the collector of the twelfth NPN transistor;

[0017] The emitters of the third NPN transistor, the fifth NPN transistor, the sixth NPN transistor, the seventh NPN transistor, the eleventh NPN transistor and the twelfth NPN transistor are connected with the ground end.

[0018] Further, the first to fourth resistors are polysilicon resistors.

[0019] Further, the voltage source output end of the circuit is a band-gap reference circuit output, the emitter area ratio of the third NPN transistor and the fourth NPN transistor is 1:n, and the output voltage is represented as:

[0020]

[0021] wherein V OUT is the voltage output by the voltage source output end of the circuit; V BE(Q3) is the BE junction voltage of the third NPN transistor; R1 is the resistance value of the first resistor; R3 is the resistance value of the third resistor; V T is the voltage equivalent of temperature, and V T = 26 mV at normal temperature.

[0022] Further,

[0023] The present application has the following beneficial effects:

[0024] (1) The present application has low temperature drift of the output reference voltage and reference current;

[0025] (2) The circuit structure of the present application is simple, has low design complexity, and small chip area;

[0026] (3) The present application has good stability of the output reference source. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 is a schematic diagram of a conventional temperature-independent reference source circuit structure;

[0028] Figure 2 is a schematic diagram of a temperature-independent reference source circuit structure of the present application;

[0029] Figure 3 is a curve of the output voltage V OUT of the voltage source circuit of the temperature-independent reference source circuit of the present application with respect to temperature T;

[0030] Figure 4 is a curve of the output current I OUT of the current source circuit of the temperature-independent reference source circuit of the present application with respect to temperature T;

[0031] Wherein, A1 is the first operational amplifier; A2 is the second operational amplifier; R1 is the first resistor; R2 is the second resistor; R3 is the third resistor; R4 is the fourth resistor; M1 is the first PMOS transistor; M2 is the second PMOS transistor; M3 is the third PMOS transistor; M4 is the fourth PMOS transistor; M5 is the fifth PMOS transistor; M6 is the sixth PMOS transistor; M7 is the seventh PMOS transistor; Q1 is the first NPN transistor; Q2 is the second NPN transistor; Q3 is the third NPN transistor; Q4 is the fourth NPN transistor; Q5 is the fifth NPN transistor; Q6 is the sixth NPN transistor; Q7 is the seventh NPN transistor; Q8 is the eighth NPN transistor; Q9 is the ninth NPN transistor; Q10 is the tenth NPN transistor; Q11 is the eleventh NPN transistor; Q12 is the twelfth NPN transistor; C1 is the capacitor; VIN0 is the power supply terminal; VIN1 is the input signal terminal; GND is the ground terminal; I OUT Current source output terminal; V OUT Voltage source output terminal; I PTAT Positive temperature current; VDD, power supply terminal; V BE1 The voltage between the first resistor and the first NPN transistor; V BE2 The voltage between the second resistor and the third resistor. Detailed Implementation

[0032] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] This invention proposes a temperature-independent reference source circuit, comprising a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M3, a fourth PMOS transistor M4, a fifth PMOS transistor M5, a sixth PMOS transistor M6, a seventh PMOS transistor M7, a first NPN transistor Q1, a second NPN transistor Q2, a third NPN transistor Q3, a fourth NPN transistor Q4, a fifth NPN transistor Q5, a sixth NPN transistor Q6, a seventh NPN transistor Q7, an eighth NPN transistor Q8, a ninth NPN transistor Q9, a tenth NPN transistor Q10, an eleventh NPN transistor Q11, a twelfth NPN transistor Q12, a capacitor C1, a power supply terminal VIN0, an input signal terminal VIN1, and a ground terminal GND, wherein:

[0034] The sources of the first to sixth PMOS transistors are connected to the power supply terminal. The gate of the first PMOS transistor and its drain, the collector of the first NPN transistor, and the gates of the second to fourth PMOS transistors are connected together. The base of the first NPN transistor, the base of the second NPN transistor, the drain of the second PMOS transistor, the collector of the sixth NPN transistor, and one end of the capacitor are connected together.

[0035] The emitter of the first NPN transistor is connected to one end of the first resistor and the second resistor, and the other end of the first resistor is connected to the collector and base of the third NPN transistor and the base of the fourth NPN transistor and the fifth NPN transistor.

[0036] The other end of the second resistor is connected to the collector of the fourth NPN transistor, the base of the sixth NPN transistor, and the other end of the capacitor.

[0037] The emitter of the fourth NPN transistor is connected to one end of the third resistor, and the other end of the third resistor is connected to the ground terminal;

[0038] The collector of the second NPN transistor is connected to the power supply terminal, and the emitter is connected to the collector of the fifth NPN transistor, serving as the voltage source output terminal of the circuit.

[0039] The gate of the fifth PMOS transistor is connected to its drain, the gate of the sixth PMOS transistor, and the collector of the eighth NPN transistor.

[0040] The gate of the seventh PMOS transistor is connected to the input signal terminal, the source is connected to the drain of the third PMOS transistor and the drain of the sixth PMOS transistor, and the drain is connected to the collector and base of the ninth NPN transistor and the base of the tenth NPN transistor.

[0041] The base of the eighth NPN transistor is connected to the drain of the fourth PMOS transistor and the collector of the seventh NPN transistor. The emitter is connected to the base of the seventh NPN transistor and one end of the fourth resistor. The other end of the fourth resistor is connected to the ground terminal.

[0042] The emitter of the ninth NPN transistor is connected to the collector and base of the eleventh NPN transistor and the base of the twelfth NPN transistor.

[0043] The collector of the tenth NPN transistor serves as a temperature-independent current source output, and its emitter is connected to the collector of the twelfth NPN transistor.

[0044] The emitters of the third, fifth, sixth, seventh, eleventh, and twelfth NPN transistors are connected to the ground terminal.

[0045] This invention consists of two parts: a temperature-independent reference voltage source and a temperature-independent reference current source. PMOS transistors M1 and M2, NPN transistors Q1-Q6, resistors R1-R3, and capacitor C1 together constitute the temperature-independent reference voltage source circuit. This reference voltage source circuit is a bandgap reference circuit. OUT For the reference circuit output, M2 and M1 form a current mirror to replicate the current in M1. Q3 and Q4 are the reference cores, and Q5 and Q6 provide clamping to ensure that the voltages at points A and B are the same, i.e., V. CA =V CB When R1 = R2, the currents flowing through branches Q3 and Q4 are equal; the emitter area ratio of Q3 and Q4 is 1:n, and the expression for the bandgap reference output voltage is:

[0046]

[0047] Among them, V OUT The voltage output from the voltage source of the circuit; V BE(Q3) R1 is the BE junction voltage of the third NPN transistor; R1 is the resistance of the first resistor; R3 is the resistance of the third resistor; ΔV BE(Q3、Q4) V is the difference between the BE junction voltage of the third NPN transistor and the BE junction voltage of the fourth NPN transistor; T V is the voltage equivalent of temperature at room temperature. T =26mV.

[0048] Due to the BE junction voltage V of the transistor BE It is a voltage that is negatively correlated with temperature, the difference ΔV between the BE junction voltages of the two transistors. BE It is positively correlated with temperature change. R3 is a polycrystalline silicon resistor, which has a very small temperature coefficient, so ΔV BE(Q3、Q4) A positive temperature-dependent current, PTAT current, will be generated in R3. The magnitude of the current in R3 is:

[0049]

[0050] Among them, I Q4 This is the current value flowing through R4.

[0051] Taking the R1 (polysilicon resistor) branch as an example, I Q3 A voltage positively correlated with temperature will be generated across R1, and the magnitude of the voltage across R1 is:

[0052]

[0053] Then the emitter of Q1 (i.e. Figure 2 The voltage at point C is the sum of a positive thermoelectric voltage and a negative thermoelectric voltage, and its magnitude is:

[0054]

[0055] By adjusting the values ​​of resistors R1 and R3, it can be made into a zero-temperature voltage independent of temperature. If Q1 and Q2 are exactly the same, then:

[0056]

[0057] Among them, V C for Figure 2 Voltage at point C; V D for Figure 2 Voltage at point D; V BE(Q1 / Q2) This is the BE junction voltage of Q1 or Q2.

[0058] This yields a temperature-independent voltage source V. OUT In addition, Q3, Q5, Q2, Q1 and Q4, Q6, Q2, Q1 can form a feedback loop, which together with the compensation capacitor C1 increases the circuit stability, thereby providing a stable low temperature drift voltage source.

[0059] Based on the bandgap reference circuit, PMOS transistors M3-M7, NPN transistors Q7-Q12, and resistor R4 together constitute a temperature-independent reference current source circuit. OUT This is the current source output. M3 and M4, together with M1, form current mirrors to replicate the current flowing through M1. Since the current flowing through M1 is a positive temperature current, the magnitude of the current flowing through M1 is:

[0060]

[0061] Among them, I Q3 I is the current flowing through the third NPN transistor; Q4 This represents the current flowing through the fourth NPN transistor.

[0062] Then M3 also receives a positive temperature current I after being mirrored. PTAT V BE(Q7) A negative temperature current is generated across R4 (polysilicon resistor), which is the current I flowing through M5. M5 Size:

[0063]

[0064] Among them, V BE(Q7) R1 is the BE junction voltage of the seventh NPN transistor; R4 is the resistance value of the fourth resistor.

[0065] M6 and M5 form a current mirror, I M5 After passing through the M6 ​​mirror and the positive temperature current I PTAT Adding them together yields a temperature-independent current I.M7 Then, after being mirrored twice by current mirrors Q9 and Q10, it becomes the output I. OUT Q8, Q11, and Q12 are used for clamping to improve stability, thereby obtaining a stable output current source that is independent of temperature.

[0066] Figure 3 The temperature-independent voltage source circuit of this invention outputs voltage V. OUT The curve showing the change in temperature T (power supply voltage VIN0 is 6V, input signal VIN1 is low). From Figure 3 It can be seen that within the temperature range of -55 to 125℃, the output voltage range of this invention is 1.207V to 1.214V, with a voltage temperature drift of only 7.351mV, exhibiting the characteristic of low temperature drift.

[0067] Figure 4 The temperature-independent current source circuit of this invention outputs current I. OUT The curve showing the change in temperature T (power supply voltage VIN0 is 6V, input signal VIN1 is low). From Figure 4 As can be seen, within the temperature range of -55 to 125°C, the output current range of this invention is 44.501μA to 48.585μA, with a current temperature drift of only 4.083μA, exhibiting the characteristic of low temperature drift.

[0068] The present invention provides a temperature-independent reference source circuit, which is particularly suitable for power supply chips to provide a stable reference voltage and reference current that are unaffected by temperature, thereby improving the overall circuit yield, accuracy and reliability.

[0069] The above-described embodiments further illustrate the purpose, technical solution, and advantages of the present invention. It should be understood that the above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made to the present invention within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A temperature-independent reference source circuit, characterized in that, This includes resistors 1-4, PMOS transistors 1-7, NPN transistors 1-12, capacitors, power supply terminals, input signal terminals, and ground terminals, wherein: The sources of the first to sixth PMOS transistors are connected to the power supply terminal. The gate of the first PMOS transistor and its drain, the collector of the first NPN transistor, and the gates of the second to fourth PMOS transistors are connected together. The base of the first NPN transistor, the base of the second NPN transistor, the drain of the second PMOS transistor, the collector of the sixth NPN transistor, and one end of the capacitor are connected together. The emitter of the first NPN transistor is connected to one end of the first resistor and the second resistor, and the other end of the first resistor is connected to the collector and base of the third NPN transistor and the base of the fourth NPN transistor and the fifth NPN transistor. The other end of the second resistor is connected to the collector of the fourth NPN transistor, the base of the sixth NPN transistor, and the other end of the capacitor. The emitter of the fourth NPN transistor is connected to one end of the third resistor, and the other end of the third resistor is connected to the ground terminal; The collector of the second NPN transistor is connected to the power supply terminal, and the emitter is connected to the collector of the fifth NPN transistor, serving as the voltage source output terminal of the circuit. The gate of the fifth PMOS transistor is connected to its drain, the gate of the sixth PMOS transistor, and the collector of the eighth NPN transistor. The gate of the seventh PMOS transistor is connected to the input signal terminal, the source is connected to the drain of the third PMOS transistor and the drain of the sixth PMOS transistor, and the drain is connected to the collector and base of the ninth NPN transistor and the base of the tenth NPN transistor. The base of the eighth NPN transistor is connected to the drain of the fourth PMOS transistor and the collector of the seventh NPN transistor. The emitter is connected to the base of the seventh NPN transistor and one end of the fourth resistor. The other end of the fourth resistor is connected to the ground terminal. The emitter of the ninth NPN transistor is connected to the collector and base of the eleventh NPN transistor and the base of the twelfth NPN transistor. The collector of the tenth NPN transistor serves as a temperature-independent current source output, and its emitter is connected to the collector of the twelfth NPN transistor. The emitters of the third, fifth, sixth, seventh, eleventh, and twelfth NPN transistors are connected to the ground terminal.

2. The temperature-independent reference source circuit according to claim 1, characterized in that, The first to fourth resistors are polycrystalline silicon resistors.

3. The temperature-independent reference source circuit according to claim 1, characterized in that, The voltage source output of the circuit is a bandgap reference circuit output. The emitter area ratio of the third NPN transistor and the fourth NPN transistor is 1:n. Therefore, the output voltage is expressed as: Among them, V OUT The voltage output from the voltage source of the circuit; V BE(Q3) R1 is the BE junction voltage of the third NPN transistor; R1 is the resistance of the first resistor; R3 is the resistance of the third resistor; V T This is the voltage equivalent of temperature.

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