Multi-granularity circuit reconfiguration and mapping method for large-scale brain-like computing
By employing a multi-granularity circuit reconstruction and mapping method, rapid iteration and diversified adaptation of neuromorphic computing hardware have been achieved, solving the problem that existing hardware cannot meet diverse needs and improving computational accuracy and system scalability.
Patent Information
- Application Number
- CN202311164459.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-11
- Publication Date
- 2025-12-09
- Estimated Expiration
- 2043-09-11
AI Technical Summary
Existing dedicated hardware for neuromorphic computing cannot meet the diverse needs of neuroscience researchers and developers of neuromorphic intelligent applications, and cannot quickly adapt to model changes, resulting in hardware systems that are insufficient to meet the simulation requirements of new models.
By employing a multi-granularity circuit reconstruction and mapping method, the configuration register values and storage formats are changed at the data flow level through a coarse-grained model, enabling the reconfigurability of neuron, synapse, and network connection models. Fine-grained hardware achieves reconfigurability of computational accuracy, performance indicators, and system scale through logic gate-level reconstruction, supporting various data precisions and network expansion.
It enables rapid iteration and diversified adaptation of neuromorphic computing hardware, meets the simulation requirements of different models, and improves computational accuracy and system scalability.
Smart Images
Figure CN117195981B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of brain-inspired computing, and in particular to a multi-granularity circuit reconstruction and mapping method for large-scale brain-inspired computing. BACKGROUND
[0002] Brain-inspired computing, also known as neuromorphic computing, is a general term for computing theories, architectures, chip designs, and application models and algorithms that draw on the information processing patterns and structures of biological neural systems. As a new computing paradigm, it aims to achieve higher energy efficiency and higher-level intelligent computing tasks by simulating brain structures and information processing mechanisms.
[0003] Currently, researching and designing special-purpose hardware for brain-inspired computing is the key to promoting the development of brain-inspired computing. Since the types of neurons, synapses, and network connection models that can be simulated by existing brain-inspired computing special-purpose hardware are limited, and the computing accuracy, performance indicators, and system expansion capabilities are relatively fixed, brain science researchers and brain-inspired intelligent application developers cannot meet the diversified needs of brain-inspired computing hardware, and thus cannot provide strong support for brain science and brain-inspired intelligent model research.
[0004] Therefore, there is an urgent need for a new technical solution to solve the above technical problems. SUMMARY
[0005] The present application aims to overcome the problems of the prior art and provides a multi-granularity circuit reconstruction and mapping method for large-scale brain-inspired computing to solve the technical problems that the prior art cannot meet the diversified needs of brain science researchers and brain-inspired intelligent application developers for brain-inspired computing hardware, and when the structure and operation mechanism of the brain-inspired computing model changes and the current hardware system is not sufficient for the new model, the brain-inspired computing model cannot be quickly adapted.
[0006] The above object is achieved by the following technical solution:
[0007] A multi-granularity circuit reconstruction and mapping method for large-scale brain-inspired computing, comprising:
[0008] The coarse-grained model is reconfigurable, and the configuration register value, sequence mapping table entry, and data storage format in the memory are changed at the data flow level through the model reconfigurable mapping method to realize reconfiguration of the neuron model, synapse model, and neural network connection model at the three levels of brain-inspired computing model without changing the logic circuit.
[0009] The fine-grained hardware is reconfigurable through the logic gate level hardware reconfiguration to realize reconfiguration of the computing accuracy, performance indicators, and system scalability of the brain-inspired hardware computing system.
[0010] Further, the reconfigurable design of the neuron model uses finite difference method to discretely approximate the differential, which is converted into algebraic equations for solving, including: dividing the parameters required for each time step algebraic equation calculation into shared constants, shared variables, private constants and private variables.
[0011] Further, the shared constant refers to a constant variable shared by all neurons and synaptic connections and not changing over time;
[0012] The shared variable refers to a variable shared by all neurons and synaptic connections but changing over time, the number of which is the same as the shared constant and will not increase with the expansion of the scale of neurons and synapses;
[0013] The private constant refers to a constant variable unique to each neuron and synaptic connection and not changing over time;
[0014] The private variable refers to a variable unique to each neuron and changing over time, and the private variable of a neuron will increase with the expansion of the scale of neurons.
[0015] Further, the shared constant and the shared variable are shared by all neurons, and only one copy needs to be stored; the private constant and the private variable are exclusively occupied by each neuron, and a storage space needs to be allocated for each neuron for separate storage.
[0016] Further, the neural synapse model is a reconfigurable neural synapse type with the number of neuron postsynaptic receptors as a hardware constraint condition, including a dual-transmitter four-receptor neural synapse type, a triple-transmitter three-receptor neural synapse type, a dual-transmitter dual-receptor neural synapse type, and a single-transmitter single-receptor neural synapse type.
[0017] Further, the reconfigurability of the neural network connection model is achieved by source indexing, which is not limited by the connection range and the number of connections, specifically:
[0018] The number of synaptic connections s between source neuron i and destination neuron j in chip c is recorded as fanout i,j , and the first address of continuous storage is recorded as staddr i,c , both of which together constitute the synaptic index Index i,c of the source neuron in chip c i,c =(staddr i,c ,fanout i,c ).
[0019] Further, the calculation accuracy reconfigurable adopts a hardware system with five data precisions of FP32, INT32, FP16, INT16 and INT8, and reconfigures the calculation accuracy of the calculation system at the circuit level through hardware reconfigurable method.
[0020] Further, the performance index reconfigurable parameters include: single-chip pulse memory depth at the hardware architecture level, the number of neuron processing units, the number of reconfigurable neurons in the neuron processing unit, the reconfigurable neuron storage size, the reconfigurable synapse connection storage size, and the storage size of a single synapse index;
[0021] The clock frequency and memory access bandwidth at the hardware implementation level;
[0022] The on-chip and off-chip storage size and memory access delay that cannot be changed after the hardware system is fixed.
[0023] Further, the system scale can be expanded by increasing the routing and inter-chip communication units in the brain-like computing system to realize the networking expansion of the chip, thereby increasing the scale of the chip accommodated by the computing system.
[0024] Further, the routing and inter-chip communication units in the brain-like computing system are specifically: a router and four-direction inter-chip communication modules are built in each chip node, and the chips are assembled into a 2D mesh chip array through the networking expansion of the chips; the router in each chip is responsible for collecting pulse data packets of the local and surrounding four chips, and sending them to the local and surrounding four chips according to the routing table.
[0025] Advantages
[0026] The multi-granularity circuit reconstruction and mapping method for large-scale brain-like computing provided by the application can be reconfigured through a coarse-grained model, can realize the reconfiguration of neuron models, synapse models and neural network connection models without changing the hardware, solves the problems of limited types of simulative neurons and synapse models and limited neuron connection range and connection number, can realize the rapid deployment of brain-like computing special hardware systems through fine-grained hardware reconfiguration, solves the problem of limited neuron and synapse computing precision, and meets the demand of rapid iteration of brain-like computing high-speed development and models. BRIEF DESCRIPTION OF DRAWINGS
[0027] Figure 1 The table for dividing different reconfigurable neuron types in the multi-granularity circuit reconstruction and mapping method for large-scale brain-like computing;
[0028] Figure 2 The table for dividing different reconfigurable synapse types in the multi-granularity circuit reconstruction and mapping method for large-scale brain-like computing;
[0029] Figure 3 The number base table of different neuron and synapse types under five data precisions in the multi-granularity circuit reconstruction and mapping method for large-scale brain-like computing;
[0030] Figure 4 The system scale can be expanded for the multi-granularity circuit reconstruction and mapping method for large-scale brain-like computing. DETAILED DESCRIPTION
[0031] The application will be described in further detail below with reference to the drawings and embodiments. The described embodiments are only some of the embodiments of the application, not all. Based on the embodiments in the application, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the scope of protection of the application.
[0032] Embodiment 1
[0033] The scheme provides a multi-granularity circuit reconstruction and mapping method for large-scale brain-like computing, comprising:
[0034] The coarse-grained model is reconfigurable. Without changing the logic circuit, the model reconfigurable mapping method changes the configuration register value, the sequence mapping table entry and the data storage format in the memory at the data flow level, to realize the reconfiguration of the neuron model, the neural synapse model and the neural network connection model at the three brain-like computing model levels.
[0035] The fine-grained hardware is reconfigurable. Through the hardware reconfiguration at the logic gate level, the computing accuracy, performance index reconfiguration and system scale expansion of the brain-like hardware computing system are realized.
[0036] Specifically, the coarse-grained reconfiguration in the embodiment refers to that, under the premise that the hardware system has been fixed, the configuration register value, the sequence mapping table entry and the data storage format in the memory are changed at the data flow level by the model reconfigurable mapping method to realize the reconfiguration of the neuron model, the neural synapse model and the network connection model at the three brain-like computing model levels. By analyzing the computing and connection characteristics of the brain-like computing model, the following is proposed:
[0037] Seven reconfigurable neuron types with the number of neuron model variables and constants as the hardware constraint condition;
[0038] Five reconfigurable synapse types with the number of neuron synapse receptors as the hardware constraint condition;
[0039] Network connection reconfiguration method with the number of network connections as the hardware constraint condition.
[0040] The fine-grained reconfigurable in the embodiment refers to a method of reconfiguring mapping of a new brain-like computing dedicated hardware system to a brain-like computing prototype system through hardware at different levels, thereby solving the problem that the brain-like computing dedicated hardware system is difficult to iterate quickly; and a fine-grained hardware reconfigurable architecture with FPGA as a design core is specifically proposed, and based on a coarse-grained model reconfigurable computing system, the calculation accuracy, performance index and system scale are reconfigurable, and the rapid iteration of the brain-like computing hardware is accelerated.
[0041] The scheme realizes a relatively general brain-like computing dedicated hardware through coarse-grained model reconfiguration, which can meet the simulation needs of most brain-like computing models; when the structure and operation mechanism of the brain-like computing model change and the current hardware system is insufficient for the new model, a new brain-like computing dedicated hardware system can be redesigned through fine-grained hardware reconfiguration, thereby realizing rapid adaptation of a new brain-like computing model.
[0042] Embodiment 2
[0043] As the optimization of the coarse-grained model reconfiguration in the scheme, it includes:
[0044] Neuron model reconfiguration: 7 types of neurons are supported, and Hodgkin-Huxley model, Izhikevich model, LIF and other neuron models can be simulated
[0045] Neurosynaptic model reconfiguration: 5 types of neurosynapses are supported, and neurosynaptic models of single neurotransmitter single receptor, two neurotransmitters two receptors, three neurotransmitters three receptors and double neurotransmitters four receptors can be simulated
[0046] Neural network connection model reconfiguration: the network connection model in which the connection range and the connection number of neurons are not limited but the total number of network connections is limited.
[0047] For different brain-like computing models, the neuron models, neurosynaptic models and neural network connection models used are different.
[0048] To realize simulation of any brain-like computing model, the coarse-grained reconfiguration design is completed in the embodiment, that is, under the premise that the logic circuit is unchanged, the neuron, neurosynaptic and network connection three-level brain-like computing model reconfiguration is realized through data remapping.
[0049] Specifically, as an explanation of the neuron model reconfiguration in the embodiment, the following is provided:
[0050] The mainstream neuron dynamics model is to approximate the physiological behavior of neurons through mathematical formulas, and the calculation formula is in the form of a differential equation.
[0051] The differential equations can be discretized by finite difference method to approximate the differential and transform them into algebraic equations for solving.
[0052] Firstly, the parameters required for each time step algebraic equation calculation are divided into four categories: shared constants, shared variables, private constants and private variables.
[0053] Among them, shared constants refer to constant variables shared by all neurons and synaptic connections and do not change over time. The storage space occupied is fixed and has a small capacity.
[0054] Shared variables refer to variables shared by all neurons and synaptic connections but change over time. The number of shared variables is the same as that of shared constants and will not increase with the expansion of neurons and synaptic scale. However, the calculation of shared variables may require the cooperation of multiple shared constants, so the storage space required should be smaller than that of shared constants.
[0055] Private constants refer to constant variables unique to each neuron and do not change over time.
[0056] Private variables refer to variables unique to each neuron and change over time. The private variables of neurons will increase with the expansion of neurons.
[0057] Shared constants and shared variables are shared by all neurons, and only one copy needs to be stored;
[0058] Private constants and private variables are exclusive to each neuron, and a block of storage space needs to be allocated for each neuron to store separately, usually in continuous storage.
[0059] For example, in the Hodgkin-Huxley neuron model, there are 5 variables (neuron membrane potential V m , empirical variables n, m, h describing ion conductance activation and inactivation, and external stimulus current Im) and 15 constants (membrane capacitance Cm, threshold potential Vth, reset potential Vrst, maximum ion conductance gNa, K, L of sodium, potassium and chloride, reversal potential VNa, K, L and parameters an, m, h, bn, m, h) ;
[0060] In the Izhikevich model, there are 3 variables (neuron membrane potential V, neuron membrane potential recovery variable u, and stimulus current I) and 8 constants (threshold potential Vth, constants 0.04, 5, 140, and parameters a, b, c, d) ;
[0061] In the LIF model, there are 2 variables (membrane potential Vm and stimulus current I) and 5 constants (threshold potential Vth, resting potential Vrest, reset potential Vrest, membrane resistance R, and time constant τ).
[0062] For example, Figure 1As shown, seven reconfigurable neuron types are presented, with hardware constraints based on the number of neuron model variables and constants. Although the number of unique variables and unique constants differs among the seven neuron types, they use the same hardware resources.
[0063] As an explanation of the reconfigurability of the neural synapse model described in this embodiment, the following is provided:
[0064] The integral accumulation effect in the synaptic model dynamics can be expressed by a step function Θ(tt) s To express it.
[0065] In general, the synaptic current I calculated from the synaptic model kinetic equations is... syn It is often used as the stimulation current I in the calculation formula of neuron model to participate in the calculation of neuron membrane potential update.
[0066] And due to the synaptic current I syn It is determined by the ionic conductivity g of the postsynaptic receptor. syn Therefore, the ionic conductivity g of the postsynaptic receptor is generally used. syn The total stimulus current I variable was calculated using a substitute neuron model.
[0067] Therefore, the number of postsynaptic receptors in neurons is also a unique variable in neuronal computational parameters.
[0068] like Figure 2 As shown, this embodiment establishes five types of reconfigurable neural synapses with the number of postsynaptic receptors of neurons as hardware constraints: dual neurotransmitter four-receptor, triple neurotransmitter three-receptor, dual neurotransmitter dual-receptor, and single neurotransmitter single-receptor neural synapse types.
[0069] The synaptic weight is the increase in the postsynaptic receptor variable corresponding to each presynaptic neuron after it is excited and releases neurotransmitters. Furthermore, the postsynaptic receptor variable is a unique variable among the neuron's computational parameters.
[0070] Furthermore, in the two-weighted, four-receptor synapse type, the weight type flag can be used to distinguish the weight type and thus determine its accumulation position.
[0071] As an explanation of the reconfigurability of the neural network connection model described in this embodiment, the following is provided:
[0072] All network models can be viewed as a directed graph, network = (N, S).
[0073] Where N is the set of all neurons (points in graph theory) in the neural network, and S is the set of all synaptic connections (edges in graph theory) in the neural network.
[0074] In order to maximize the reconfigurability of the network connection model, the connection range and the number of neurons are not limited by the source index, but the total number of network connections is limited, and the system is still applicable when the system scale is expanded.
[0075] The source neuron i in the neural network has a synaptic index Index in each chip i,c Corresponding to it, the synaptic connection s of the source neuron i and all the destination neurons j in the chip c i,j is stored continuously in the chip c.
[0076] In this scheme, the number of synaptic connections s of the source neuron i and the destination neuron j in the chip c i,j is recorded as fanout i,c , the first address of continuous storage is recorded as staddr i,c , and both of them together constitute the synaptic index Index of the source neuron in the chip c i,c =(staddr i,c , fanout i,c ).
[0077] Embodiment 3
[0078] As an optimization of fine-grained hardware reconfigurability in this scheme, based on the hardware programmable characteristics of FPGA, through hardware reconfiguration at the logic gate level, the computational accuracy, performance index reconfigurability and system scale expansion of the brain-like hardware computing system are realized, including:
[0079] Computational accuracy reconfigurable: support FP32, FP16 two floating point calculation accuracy, support INT32, INT16, INT8 three fixed point calculation accuracy, can realize the scalability of neuron / synaptic connection number;
[0080] Performance index reconfigurable: support neuron / synaptic connection scale, limit pulse firing rate and simulation speed ratio, etc. Performance index reconfigurable;
[0081] System scale reconfigurable: support network expansion of chips, can form a 2D Mesh chip array;
[0082] Specifically, as an illustration of the computational accuracy reconfigurable in this embodiment, as follows:
[0083] As Figure 3 shown, in order to meet the needs of various precision model simulation required by brain-like computing, this embodiment designs a hardware system using FP32, INT32, FP16, INT16 and INT8 five kinds of data precision, and the computational accuracy of the computing system can be reconfigured at the circuit level through hardware reconfiguration method.
[0084] In addition, by using data stream splitting and computation process optimization on the basis of the reconfigurable neuron and synapse types described above, the number of neurons and synapse connections that can be accommodated in the system can be increased without increasing the neuron and synapse storage resources when the model data precision of the brain-like computing system simulation is reduced.
[0085] As an illustration of the performance index reconfigurability described in this embodiment, the following is provided:
[0086] The performance index of the brain-like computing system model simulation capability: the number of neurons, the number of synapse connections, the pulse firing rate, and the simulation speedup ratio.
[0087] Among them, the pulse firing rate refers to the number of excitations per second of a neuron in a spiking neural network model;
[0088] The simulation speedup ratio refers to the ratio of the real simulation time of the hardware to the ideal time of the model.
[0089] That is, the hardware parameters that affect the simulation performance index are:
[0090] The single-chip pulse memory depth, the number of neuron processing units, the number of reconfigurable neurons in the neuron processing unit, the reconfigurable neuron storage size, the reconfigurable synapse connection storage size, and the storage size of a single synapse index at the hardware architecture level;
[0091] The clock frequency and memory access bandwidth at the hardware implementation level;
[0092] The on-chip and off-chip storage size and memory access delay that cannot be changed after the hardware system is fixed.
[0093] Among them, the number of neurons and synapse connections is related to the number of neuron processing units, the number of reconfigurable neurons in the neuron processing unit, the reconfigurable neuron storage size, and the reconfigurable synapse connection storage size;
[0094] The pulse firing rate is related to the number of neurons and synapse connections and the single-chip pulse memory depth;
[0095] The simulation speedup ratio is related to the clock frequency, the on-chip and off-chip storage size, and the memory access bandwidth.
[0096] Therefore, to realize the performance index reconfigurability of the brain-like computing dedicated hardware system, in addition to the two parameters of the on-chip and off-chip storage size and the memory access delay that cannot be changed after the hardware system is fixed, the other hardware parameters can be changed through the fine-grained hardware reconfigurability of the system
[0097] As an illustration of the system scale reconfigurability described in this embodiment, the following is provided:
[0098] In dedicated hardware systems for neuromorphic computing, the number of neurons and synaptic connections that a single chip can accommodate is always limited due to chip area constraints.
[0099] This embodiment achieves network expansion of the chip by adding routing and inter-chip communication units to the neuromorphic computing system through fine-grained hardware reconfiguration, thereby increasing the chip size that the computing system can accommodate.
[0100] like Figure 4 As shown, the neuromorphic computing system will have a router and four inter-chip communication modules built into each chip node, and the chips will be built into a 2Dmesh chip array through the network expansion of the chips.
[0101] Each chip's router is responsible for collecting pulse data packets from the local and four surrounding chips, and then forwarding them to the local and four surrounding chips according to the routing table.
[0102] Neuromorphic computing systems can be scalable by configuring routing tables within each chip to select the most suitable 2D mesh chip array for different neuromorphic computing models and combining the computing system into chip arrays of different sizes.
[0103] In addition, this solution can also adjust the maximum inter-chip communication load of the system by adjusting the number of routing entries in the routing table of the computing system.
[0104] The above description is merely illustrative of the embodiments of the present invention and is not intended to limit the present invention. For those skilled in the art, any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A multi-granularity circuit reconfiguration and mapping method for large-scale brain-like computing, characterized in that, The application relates to a class brain computing system and a method for realizing the class brain computing system. The reconfigurable design of the neuron model utilizes a finite difference method to discretely approximate differentiation and converts the differentiation into algebraic equations for solving, including: dividing parameters required for calculating an algebraic equation at each time step into shared constants, shared variables, unique constants and unique variables; the reconfigurable synapse model is a synapse type with the number of neuron postsynaptic receptors as a hardware constraint condition, including a dual-transmitter four-receptor synapse type, a triple-transmitter three-receptor synapse type, a dual-transmitter two-receptor synapse type and a single-transmitter single-receptor synapse type; the reconfigurable neuron network connection model realizes unlimited neuron connection range and connection number through a source index mode, specifically: the number of synapse connections si,j between a source neuron i and a destination neuron j in a chip c is recorded as fanouti,c, and a continuously stored first address is recorded as staddri,c, both of which together constitute a synapse index Indexi,c= (staddri,c,fanouti,c) of the source neuron in the chip c; The hardware reconfiguration at a logic gate level realizes reconfiguration of the calculation precision, performance index and system scale of the class brain hardware computing system; the calculation precision reconfiguration adopts a hardware system with five data precisions of FP32, INT32, FP16, INT16 and INT8, and reconfigures the calculation precision of the computing system at a circuit level; a routing and inter-chip communication unit is added in the class brain computing system, specifically: a router and four-direction inter-chip communication modules are built in each chip node, and the chips are assembled into a 2D mesh chip array through networked expansion of the chips; the router in each chip is responsible for collecting pulse data packets of the local and surrounding four chips, and sending the pulse data packets to the local and surrounding four chips according to a routing table. The shared constant refers to a constant variable shared by all neurons and synapse connections and not changing with time; 2. The method for multi-granularity circuit reconfiguration and mapping for large-scale brain-inspired computing according to claim 1, wherein, The shared variable refers to a variable shared by all neurons and synapse connections but changing with time, and the number of the shared variable is the same as that of the shared constant and does not increase with expansion of the neuron and synapse scale; The unique constant refers to a constant variable unique to each neuron and synapse connection and not changing with time; The unique variable refers to a variable unique to each neuron and changing with time, and the unique variable of the neuron increases with expansion of the neuron scale. The shared constant and the shared variable are shared by all neurons and only need to be stored once; the unique constant and the unique variable are exclusively occupied by each neuron and need to be allocated a storage space for each neuron for separate storage.
3. The method for multi-granularity circuit reconfiguration and mapping for large-scale brain-inspired computing according to claim 2, wherein, 4. The method for multi-granularity circuit reconfiguration and mapping for large-scale brain-inspired computing according to claim 1, wherein, The performance index reconfigurable parameters include: single-chip pulse memory depth at the hardware architecture level, the number of neuron processing units, the number of reconfigurable neurons in the neuron processing unit, the reconfigurable neuron storage size, the reconfigurable synapse connection storage size, and the storage size of a single synapse index; The clock frequency and the memory access bandwidth at the hardware implementation level; The on-chip and off-chip storage size and the memory access delay that cannot be changed after the hardware system is fixed.
5. The method for multi-granularity circuit reconfiguration and mapping for large-scale brain-inspired computing according to claim 1, wherein, The system scale is scalable, and the routing and inter-chip communication units are added in the brain-like computing system to realize the networked expansion of the chip, thereby increasing the chip scale accommodated by the computing system.