Gate drive circuit, driving method of gate drive circuit, device, and medium

Abstract

The application discloses a kind of gate drive circuit, the driving method of gate drive circuit, equipment and medium, general computer technology field, specifically related to image processing circuit field.The gate drive circuit includes first circuit module and second circuit module, the first circuit module is used to drive first display panel, the second circuit module is used to drive second display panel, the first display panel and the second display panel are adjacent up and down;The first circuit module is used to drive the display unit of the first display panel according to first scanning sequence row by row;The second circuit module is used to drive the display unit of the first display panel according to second scanning sequence row by row.It can let the active light-emitting display panel spliced as super large screen normal display image content, avoid the situation that frame number difference exists at screen splicing place and then leads to image tearing.

Description

Technical Field

[0001] This disclosure generally relates to the field of computer technology, specifically to the field of image processing circuits, and more particularly to a gate driving circuit, a driving method for the gate driving circuit, an apparatus, and a medium. Background Technology

[0002] With the continuous development of display panels, active-matrix display panels have become a popular type of display panel in the market due to their advantages such as being ultra-thin, energy-saving compared to non-active-matrix display panels, and not having excessive brightness and color changes due to different viewing angles.

[0003] When using self-emissive display panels (PEPs) as the display panel for ultra-large screens, several PEPs are typically spliced ​​together to create the ultra-large screen. In related technologies, each PEP panel independently performs the display process by scanning line by line from top to bottom.

[0004] However, since the super large screen is made up of several display panels, when each display panel is simultaneously scanning line by line, there will be a difference in the number of frames at the splicing point between the upper and lower screens, which will cause image tearing and make the spliced ​​super large screen unable to display properly. Summary of the Invention

[0005] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a gate driving circuit, a driving method, an apparatus and a medium for the gate driving circuit, which can enable the spliced ​​active light emission display panel to display image content normally as an ultra-large screen, avoiding the situation where there is a frame rate difference at the screen splicing point, which would lead to image tearing.

[0006] In a first aspect, a gate driving circuit is provided, which includes a first circuit module and a second circuit module. The first circuit module is used to drive a first display panel, and the second circuit module is used to drive a second display panel. The first display panel and the second display panel are vertically adjacent to each other.

[0007] The first circuit module is used to drive the display units of the first display panel line by line in a first scanning order;

[0008] The second circuit module is used to drive the display units of the first display panel line by line in a second scanning order;

[0009] Wherein, the scanning direction of the first scanning sequence is a first direction, the scanning direction of the second scanning sequence is a second direction, and the first direction is opposite to the second direction.

[0010] This application discloses a gate driving circuit, which includes a first circuit module and a second circuit module. The first circuit module drives a first display panel, and the second circuit module drives a second display panel that is vertically adjacent to the first display panel. The first circuit module drives the display units of the first display panel line by line according to a first scanning order, while the second circuit module drives the display units of the first display panel line by line according to a second scanning order (the scanning direction of the second scanning order is the second direction), which is opposite to the scanning direction of the first scanning order. Thus, because the scanning order of the display units in vertically adjacent display panels is opposite, the scanning timing of the display units at the junction of vertically adjacent display panels is the same, thereby preventing frame differences between the display units at the junction of different display panels, and thus preventing image tearing at the junction of different display panels.

[0011] In a second aspect, a driving method for a gate driving circuit is provided. The gate driving includes a first circuit module and a second circuit module. The first circuit module is used to drive a first display panel, and the second circuit module is used to drive a second display panel. The first display panel and the second display panel are vertically adjacent to each other. The method includes:

[0012] The first circuit module drives the display units of the first display panel line by line in the first scanning order;

[0013] The second circuit module drives the display units of the first display panel line by line according to the second scanning order;

[0014] The first scanning order is the reverse of the second scanning order.

[0015] Thirdly, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, it implements the method described in the second aspect above.

[0016] Fourthly, a computer-readable storage medium is provided having a computer program stored thereon, characterized in that the program, when executed by a processor, implements the method described in the second aspect above.

[0017] Fifthly, a computer program product is provided, which includes instructions that, when executed by a processor, implement the method described in the second aspect above.

[0018] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0019] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0020] Figure 1 This is a schematic diagram of the display panel structure according to an embodiment of this application;

[0021] Figure 2 This is a schematic diagram of the cascaded gate drive circuit according to an embodiment of this application;

[0022] Figure 3 One of the circuit unit structure diagrams of the gate driving circuit provided in the embodiments of this application;

[0023] Figure 4 This is one of the timing diagrams for the gate drive circuit provided in the embodiments of this application;

[0024] Figure 5 This is the second timing diagram of the gate drive circuit provided in the embodiments of this application;

[0025] Figure 6 A second schematic diagram of the circuit unit structure of the gate driving circuit provided in the embodiments of this application;

[0026] Figure 7 The third schematic diagram of the circuit unit structure of the gate driving circuit provided in the embodiments of this application;

[0027] Figure 8 A schematic flowchart of the driving method for the gate driving circuit provided in an embodiment of this application;

[0028] Figure 9 A schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0029] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0030] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0031] The following is an explanation of the terms appearing in the embodiments of this application:

[0032] 1. Gate Driven on Array (GOA) Circuit

[0033] GOA stands for Gate Driven on Array, which refers to gate drive integration on the array substrate. It is also sometimes referred to as ASG (Amorphous Silicon Gate) and enables progressive scan driving of liquid crystal panels. In traditional active-matrix liquid crystal displays (LCDs), the row scan signals are implemented by external integrated circuits (G-COF). However, with GOA driving, the row scan drive circuit is fabricated using the same process technology as thin-film transistors (TFTs), requiring only a few control signals from the external circuitry, to achieve progressive scan driving. Therefore, using GOA driving saves on the integrated circuits related to scan driving, reducing the manufacturing cost of LCDs.

[0034] As can be seen from the driving principle of LCD panels, the row scanning driving circuit is essentially equivalent to a shift register. Under the control signal of the external circuit, it generates a shift pulse signal. This shift pulse signal drives the pixels of the current row to turn on the TFT, and also serves as the start signal for the next row (the first row is triggered by the frame start signal STV) and the end signal for the previous row. The control signals of the external circuit mainly include the frame start signal (STV), the CLK and CLKB signal pairs with opposite phases, the DC voltage signal VSS (typically -8V) for TFT shutdown, and possibly the DC voltage signal VDD.

[0035] Compared to integrated circuit drivers, GOA (Glass Onboard Aspect) driver designs reduce the manufacturing cost of LCD panels, but they also consume more power and pose certain quality and reliability risks. This is mainly due to factors such as the threshold voltage offset characteristics and temperature characteristics of hydrogenated amorphous silicon semiconductors. Therefore, the driver unit structure usually needs to be optimized in the design.

[0036] 2. VGH signal

[0037] VGH is a high-voltage signal in the driving circuit of the display panel, used to control the orientation of liquid crystal molecules and rotate them to the desired angle.

[0038] 3. VGL signal

[0039] VGL is a low-voltage signal in the driving circuit of the display panel, used to control the transmittance of liquid crystal molecules, thereby controlling the brightness of the LCD screen.

[0040] This application proposes a gate drive circuit, apparatus, device, and medium that can solve the problem of excessive resource address space occupied in JWT, thereby greatly saving transmission resources between service nodes and improving the transmission efficiency between service nodes to a certain extent.

[0041] This application provides a gate driving circuit. The gate driving circuit includes a first circuit module and a second circuit module, wherein the first circuit module is used to drive a first display panel, and the second circuit module is used to drive a second display panel.

[0042] In this embodiment of the application, the first display panel and the second display panel are vertically adjacent.

[0043] Under normal circumstances, the circuit module of the display panel controls the vertical (column) signal scanning timing of the display panel through the data signal, and controls the horizontal signal scanning timing of the display panel through the gate signal. The data signal usually does not cause frame difference problems at the connection point between adjacent display panels on the left and right, while the gate signal will cause frame difference between adjacent display panels on the top and bottom, resulting in image tearing. Therefore, the first display panel and the second display panel used in this application embodiment are vertically adjacent display panels.

[0044] In this embodiment of the application, the first circuit module is used to drive the display units of the first display panel line by line in a first scanning order.

[0045] In this embodiment of the application, the second circuit module is used to drive the display units of the first display panel line by line in a second scanning order.

[0046] The first scanning order is the reverse of the second scanning order.

[0047] It should be noted that, in the embodiments of this application, both the first display panel and the second display panel are active-matrix light-emitting display panels. For example, OLED display panels and Micro-LED display panels.

[0048] It is understood that, in the embodiments of this application, as described above, the first scanning order of the first display panel and the second scanning order of the second display panel are opposite, and the first display panel and the second display panel are vertically adjacent display panels. Furthermore, assuming there is a third display panel vertically adjacent to the second display panel, the third scanning order of the third display panel is also opposite to the second scanning order of the second display panel; that is, the scanning orders of vertically adjacent display panels are all opposite scanning orders.

[0049] The gate driving circuit provided in this application includes a first circuit module and a second circuit module. The first circuit module drives a first display panel, and the second circuit module drives a second display panel that is vertically adjacent to the first display panel. The first circuit module drives the display units of the first display panel line by line according to a first scanning order, and the second circuit module drives the display units of the first display panel line by line according to a second scanning order (the scanning direction of the second scanning order is the second direction), which is opposite to the scanning direction of the first scanning order. Thus, since the scanning order of the display units in the vertically adjacent display panels is opposite, the scanning timing of the display units at the junction of the vertically adjacent display panels is the same, thereby preventing frame differences between the display units at the junction of different display panels, and preventing image tearing at the junction of different display panels.

[0050] In another embodiment of this application, a specific implementation of driving scanning in the first display panel and the second display panel is further provided. For example, in the above-described gate driving circuit, the first circuit module includes a plurality of first circuit units, and the second circuit module includes a plurality of second circuit units.

[0051] For example, the first circuit unit is used to drive a row of display units in the first display panel, and the second circuit unit is used to drive a row of display units in the second display panel.

[0052] As can be understood from the foregoing, the first display panel displays by scanning line by line using the first circuit module, driving the display units of the first display panel. Similarly, the second display panel displays by scanning line by line using the second circuit module, driving the display units of the second display panel. Therefore, each row of display units on the first display panel is controlled and driven by a circuit unit within the first circuit module, and similarly, each row of display units on the second display panel is controlled and driven by a circuit unit within the second circuit module. That is, if the first display module includes N rows of display units, it also includes N first circuit units; similarly, if the second display module includes N rows of display units, it also includes N second circuit units.

[0053] For example, the plurality of first circuit units are driven in a first driving sequence, and the plurality of second circuit units are driven in a second driving sequence.

[0054] For example, the first driving sequence of the plurality of first circuit units matches the first scanning sequence of the display units of the first display panel, and the second driving sequence of the plurality of second circuit units matches the second scanning sequence of the display units of the second display panel.

[0055] For example, the scanning direction of the first scanning sequence is a first direction, the scanning direction of the second scanning sequence is a second direction, and the first direction and the second direction are opposite.

[0056] It is understood that in this embodiment, the first display panel has multiple rows of display units arranged sequentially, each row of display units being controlled by a first circuit unit. The first panel includes multiple display units and correspondingly multiple first circuit units. The multiple first circuit units can be arranged sequentially or not in a sequential order, but the multiple first circuit units need to drive the multiple display units in the first display panel sequentially according to a first driving order. Similarly, the second display panel has multiple rows of display units arranged sequentially, each row of display units being controlled by a second circuit unit. The first panel includes multiple display units and correspondingly multiple second circuit units. The multiple second circuit units can be arranged sequentially or not in a sequential order, but the multiple second circuit units need to drive the multiple display units in the second display panel sequentially according to a second driving order.

[0057] Furthermore, as can be seen from the above, the display units in the first display panel and the display units in the second display panel are arranged row by row. In this embodiment, the scanning direction of the first scanning order is a first direction used to characterize: scanning row by row sequentially from top to bottom, or scanning row by row sequentially from bottom to top; correspondingly, the scanning direction of the second scanning order is a second direction used to characterize: scanning row by row sequentially from top to bottom, or scanning row by row sequentially from bottom to top.

[0058] Furthermore, since the first direction and the second direction are opposite, when the first direction is a scanning direction that scans line by line from top to bottom, the second direction is a scanning direction from bottom to top; correspondingly, when the first direction is a scanning direction that scans line by line from bottom to top, the second direction is a scanning direction from top to bottom.

[0059] like Figure 1 As shown, Figure 1 The diagram includes a first display panel and a second display panel. Figure 1 The dashed boxes 01 and 02 in the diagram are used to indicate two rows of several rows of display units in the first display panel. Each row of display units includes multiple display units. Figure 1The dashed boxes 03 and 04 in the diagram are used to indicate two rows of display units in the second display panel, each row containing multiple display units. In the first display panel, the scanning direction of the first scanning sequence is from dashed box 01 to dashed box 02, that is, scanning line by line from top to bottom. Correspondingly, since the first direction of the first scanning sequence is opposite to the second direction of the second scanning sequence, in the second display panel, the scanning direction of the second scanning sequence is from dashed box 04 to dashed box 03, that is, scanning line by line from bottom to top.

[0060] For example, matching the first driving order of the plurality of first circuit units with the first scanning order of the display units of the first display panel means driving the plurality of first circuit units line by line in a driving order consistent with the first scanning order of the display units of the first display panel. Correspondingly, matching the second driving order of the plurality of second circuit units with the second scanning order of the display units of the second display panel means driving the plurality of second circuit units line by line in a driving order consistent with the first scanning order of the display units of the second display panel.

[0061] In another embodiment of this application, a specific implementation method for implementing the above-mentioned different scanning sequences in a gate driving circuit is also provided. In the above-mentioned gate driving circuit, the first circuit unit is used to output a first signal to the next first circuit unit in response to a first driving signal; the second circuit unit is used to output a second signal to the previous first circuit unit in response to a second driving signal.

[0062] It is understandable that, since the first circuit unit and the second circuit unit belong to the first circuit module (for driving the first display panel) and the second circuit module (for driving the second display panel) respectively in the gate driving circuit, the driving directions of the first circuit unit and the second circuit unit are opposite.

[0063] For example, if the driving direction of the first circuit unit is downward, that is, driving the next first circuit unit, the driving direction of the second circuit unit is upward, that is, driving the next second circuit unit.

[0064] It should be noted that the above-mentioned upward driving and downward driving are limitations made to indicate that the driving directions of the first circuit unit and the second circuit unit are opposite. In the embodiments of this application, the first circuit unit also has the function of downward driving, and correspondingly, the second circuit unit also has the function of upward driving. For details, please refer to the following description, which will not be repeated here.

[0065] For example, the first driving signal is used to drive the next first circuit unit to start, that is, to start scanning, and to trigger the next first circuit unit to continue to output the first signal downward, so that the first circuit unit after the next first circuit unit repeats the operation of starting the next first circuit unit and outputting the first signal.

[0066] Accordingly, for example, the aforementioned second driving signal is used to drive the previous second circuit unit to start, that is, to start scanning, and to trigger the previous second circuit unit to continue to output the second signal upward, so that the second circuit unit after the previous second circuit unit repeats the above-mentioned operation of starting the previous second circuit unit and outputting the second signal.

[0067] For example, the first signal received by the first circuit unit is used to drive a row of display units in the first display panel corresponding to the first circuit unit.

[0068] For example, the second signal received by the second circuit unit is used to drive a row of display units in the second display panel that correspond to the second circuit unit.

[0069] It should be noted that the circuit unit type of the first circuit unit and the second circuit unit in the embodiments of this application belongs to the GOA circuit unit.

[0070] Further:

[0071] First, the circuit unit of the first display panel and the circuit unit of the second display panel are of the same type and have the same structure (see the following description for details).

[0072] Second, for the first and second circuit units, since they are both of the GOA circuit unit type, during driving, for the first display panel, only the first first circuit unit needs to be driven by an external signal, and the remaining first circuit units are driven by the preceding first circuit unit. Similarly, for the second display panel, only the first second circuit unit needs to be driven by an external signal, and the remaining second circuit units are driven by the preceding second circuit unit.

[0073] Third, as mentioned above, the scanning order of the first display panel and the second display panel are opposite. Correspondingly, the driving order of the multiple first circuit units corresponding to the multiple display units of the first display template and the multiple second circuit units corresponding to the multiple display units of the second display template are also opposite. Therefore, for the multiple first circuit units of the first display panel, assuming they are driven sequentially from top to bottom, the first circuit unit corresponding to the topmost display unit is the first first circuit unit of the first display panel. This first first circuit unit is driven by an external driving signal. Then, the first first circuit unit outputs a driving signal to drive the second first circuit unit corresponding to the next display unit after the topmost display unit. This second first circuit unit is driven by the driving signal output by the first first circuit unit. Subsequently, the second first circuit unit will also output a driving signal, and the third first circuit unit will be driven by the driving signal output by the second first circuit unit, and so on. Correspondingly, for the multiple second circuit units of the second display panel, assuming that the multiple second circuit units are driven sequentially from bottom to top, the second circuit unit corresponding to the bottommost display unit is the first second circuit unit of the second display panel. This first second circuit unit is driven by an external driving signal. Then, the first second circuit unit outputs a driving signal to drive the second second circuit unit corresponding to the display unit above the bottommost display unit. This second second circuit unit is driven by the driving signal output by the first second circuit unit. Subsequently, the second second circuit unit will also output a driving signal, and the third second circuit unit is driven by the driving signal output by the second second circuit unit, and so on.

[0074] In another embodiment of this application, the circuit structures used to control the scanning order in the first circuit unit and the second circuit unit are further explained.

[0075] Optionally, in the above gate drive circuit, the first circuit unit includes: a first control module and a first gate drive integrated module.

[0076] For example, the first control module is configured to turn on the first signal source in response to the first driving signal, and control the first gate driving integrated module to output the first signal under the action of the clock signal.

[0077] For example, the first control module and the first gate drive integrated module described above are used to control the first display panel.

[0078] For example, the first control module described above is used to control the scanning order of the first circuit unit, as detailed in the following description, and will not be repeated here.

[0079] For example, the first gate driving integrated module is used to drive the first display unit and output the first signal to the next first circuit unit.

[0080] It should be noted that during the line-by-line scanning process of the first display module, the start time of each line needs to be controlled by a clock signal, rather than starting immediately upon receiving the first drive signal, i.e., immediately turning on the first signal source. Only in this way can the first display module display according to certain timing requirements. For details, please refer to the following description, which will not be repeated here.

[0081] Optionally, the second circuit unit includes: a second control module and a second gate drive integrated module.

[0082] For example, the second control module is configured to turn on the second signal source in response to the second drive signal, and control the second gate drive integrated module to output the second signal under the action of the clock signal.

[0083] For example, the second control module and the second gate drive integrated module described above are used to control the second display panel.

[0084] For example, the second control module described above is used to control the scanning order of the second circuit unit, as detailed in the following description, and will not be repeated here.

[0085] For example, the second gate driving integrated module is used to drive the second display unit and output the second signal to the upper second circuit unit.

[0086] It should be noted that during the line-by-line scanning process of the second display module, the start time of each line needs to be controlled by a clock signal, rather than starting immediately upon receiving the second drive signal, i.e., immediately turning on the second signal source. Only in this way can the second display module display according to certain timing requirements. For details, please refer to the following description, which will not be repeated here.

[0087] For example, the first signal described above can be used to drive an adjacent first circuit unit and can be used together with a clock signal to cause the adjacent first circuit unit to start scanning. Similarly, the second signal described above can be used to drive an adjacent second circuit unit and can be used together with a clock signal to cause the adjacent second circuit unit to start scanning.

[0088] In one example, the first signal may include a positive control signal (first STV signal) for the first gate driver and a negative control signal (second STV signal) for the first gate driver.

[0089] Furthermore, the first STV signal can be either a positive pulse signal or a negative pulse signal; the second STV signal can also be either a positive pulse signal or a negative pulse signal.

[0090] In one example, the second signal may include a positive control signal (first STV signal) for the second gate driver and a negative control signal (second STV signal) for the second gate driver.

[0091] Furthermore, the first STV signal can be either a positive pulse signal or a negative pulse signal; the second STV signal can also be either a positive pulse signal or a negative pulse signal.

[0092] It should be noted that, generally, the circuit units of adjacent display panels (such as the first and second display panels mentioned above) can be respectively activated and scanned by inputting the first STV signal and the second STV signal, and the pulse directions of the first and second STV signals are the same. For example, if the first display unit inputs the first STV signal, and the first STV signal is a positive pulse signal, then the second display unit inputs the second STV signal, and the second STV signal is also a positive pulse signal; if the first display unit inputs the first STV signal, and the first STV signal is a negative pulse signal, then the second display unit inputs the second STV signal, and the second STV signal is also a negative pulse signal.

[0093] For example, both the first circuit unit and the second circuit unit are provided with clock signal gates. These clock signal gates can be triggered by a clock signal to turn on the input signal terminals of the first circuit unit and the second circuit unit, so that the input signal of the first circuit unit can be input to the first gate driver integrated module and the input signal of the second circuit unit can be input to the second gate driver integrated module.

[0094] In one example, the clock signal can be a low-level signal, and correspondingly, the clock signal gate can be a PMOS transistor, which can be turned on after receiving a low-level signal.

[0095] It should be noted that the above clock signal may include one clock signal or multiple clock signals.

[0096] In one example, when the aforementioned clock signal is multiple clock signals, these clock signals can be clock signal A, CLKA and clock signal B, CLKB. Clock signal A and clock signal B have the same clock interval but a certain phase difference. For example, when the clock signal is a duty cycle signal, clock signal A and clock signal B have the same duty cycle but a certain phase difference, which is less than the duty cycle.

[0097] Understandably, the reason for having multiple clock signals is that each row of circuit units requires a clock signal to drive it. In practical applications, the startup interval of circuit units is very short, meaning the display unit scanning speed and scanning interval are both small. A single clock signal, after controlling the first gate driver integrated module to output the first signal, may not be able to control the next first gate driver integrated module to output the next first signal within a short time interval. Similarly, a single clock signal, after controlling the second gate driver integrated module to output the second signal, may not be able to control the previous second gate driver integrated module to output the previous second signal within a short time interval. Therefore, adjacent clock signals A and B are used to control two adjacent first gate driver integrated modules or two adjacent second gate driver integrated modules respectively.

[0098] In another embodiment of this application, a specific implementation method is disclosed for the first control module to have the function of controlling the scanning direction and to realize downward scanning, and a specific implementation method for the second control module to have the function of controlling the scanning direction and to realize upward scanning.

[0099] Optionally, the first control module includes a first forward sub-control module and a first reverse sub-control module, wherein the first forward sub-control module is used to respond to a first forward sub-drive signal output by the previous first circuit unit, and the second reverse sub-control module is used to respond to the first reverse sub-drive signal output by the next first circuit unit.

[0100] For example, the first forward sub-control module is in the on state, the second reverse sub-control module is in the off state, the first forward sub-drive signal and the second reverse sub-drive signal have opposite driving directions, and the first signal includes the first forward sub-drive signal.

[0101] In one embodiment, the first forward sub-control module is used to control the reception of a first STV signal input from an external source and the reception of a first STV signal output by an adjacent first circuit unit of the first circuit unit; the first reverse sub-control module is used to control the reception of a second STV signal input from an external source and the reception of a second STV signal output by an adjacent first circuit unit of the first circuit unit.

[0102] It is understandable that the first control module itself has the function of controlling the first circuit unit to output signals in different directions. After determining the scanning direction of the first display panel (for example, scanning from top to bottom or scanning from bottom to top), the first control module will activate the state of the sub-control module (first forward sub-control module and first reverse sub-control module) corresponding to the scanning direction.

[0103] Furthermore, in one example, the first forward sub-control module is used to respond to the first forward sub-drive signal output by the previous first circuit unit and transmit the first forward sub-drive signal to the next first circuit unit. Therefore, when the downward transmission signal is transmitted in the forward direction, the control direction of the first control module should be forward. Based on this, when the first display template is scanned line by line in the forward direction, the first forward sub-control module in the first control module needs to be kept in the on state, while the first reverse sub-control module in the first control module needs to be kept in the off state.

[0104] It should be noted that the above description of "control direction is positive" is a definition made by the embodiments of this application for the purpose of conveniently and clearly describing the scanning direction. That is, "positive" is defined as scanning line by line from top to bottom. In actual application, "positive" can also be regarded as scanning line by line from bottom to top.

[0105] Optionally, the second control module includes: a second forward sub-control module and a second reverse sub-control module, wherein the second forward sub-control module is used to respond to the second forward sub-drive signal output by the next second circuit unit, and the second reverse sub-control module is used to respond to the second reverse sub-drive signal output by the previous second circuit unit.

[0106] For example, the second positive sub-control module is in the off state, the second negative sub-control module is in the on state, the driving directions of the second positive sub-drive signal and the second negative sub-drive signal are opposite, and the second signal includes the second negative sub-drive signal.

[0107] In one embodiment, the second forward sub-control module is used to control the reception of a first STV signal input from an external source and the reception of a first STV signal output by an adjacent second circuit unit of the second circuit unit; the second reverse sub-control module is used to control the reception of a second STV signal input from an external source and the reception of a second STV signal output by an adjacent second circuit unit of the second circuit unit.

[0108] It is understandable that the second control module itself has the function of controlling the second circuit unit to output signals in different directions. After determining the scanning direction of the second display panel (for example, scanning from top to bottom or scanning from bottom to top), the second control module will activate the state of the sub-control module (second forward sub-control module and second reverse sub-control module) corresponding to the scanning direction.

[0109] Furthermore, in one example, the second forward sub-control module is used to respond to the second reverse sub-drive signal output by the previous second circuit unit and transmit the second reverse sub-drive signal to the previous second circuit unit. Therefore, when the upward transmission signal is transmitted in reverse, the control direction of the second control module should be reversed. Based on this, when the second display template is scanned line by line in reverse, the second reverse sub-control module in the second control module needs to be kept in the on state, while the second forward sub-control module in the second control module needs to be kept in the off state.

[0110] It should be noted that the above description of "control direction is reverse" is a definition made by the embodiments of this application for the purpose of conveniently and clearly describing the scanning direction. That is, "reverse" is defined as scanning line by line from bottom to top. In actual application, "reverse" can also be regarded as scanning line by line from top to bottom.

[0111] The following is a description of specific embodiments of scanning different directions on adjacent display panels described above in this application.

[0112] like Figure 2 As shown, Figure 2 This is a structural diagram showing the relationship between multiple first circuit units in the first display panel or multiple second circuit units in the second display panel in an embodiment of this application. It should be noted that although the scanning order between the first and second display panels is reversed, both the first and second display panels have forward and reverse scanning functions. As described above, the first and second display panels control the scanning order of the display units in their respective circuit units through their control modules (the first control module corresponding to the first display panel and the second control module corresponding to the second display panel, respectively). Therefore, the circuit structures of the first and second circuit units are identical; however, their operating modes differ, resulting in different transmission directions for their signals (e.g., the first forward driving sub-signal and the second reverse driving word signal). Since the circuit structures of the first and second circuit units are identical, therefore... Figure 2 It can be used to describe the cascaded structure of the first circuit unit and the cascaded structure of the second circuit unit. In the following content, "circuit unit" is used to refer to both the first circuit unit and the second circuit unit.

[0113] exist Figure 2 In the middle, it shows the cascading method of different circuit units. Figure 2On the left are the signal lines for two clock signals, and on the right are three circuit units, each used to drive a row of display units to start scanning. The two clock signal lines are used to output clock signal A (CLKA) and clock signal B (CLKB). It can be seen that adjacent circuit units are connected to the clock signal lines in different ways. Figure 2 On the right are three circuit units: circuit unit 1, circuit unit 2, and circuit unit 3. When circuit power supply 1 is driven by CLKA to output a signal, circuit unit 2 is driven by CLKB to output a signal, and circuit unit 3 is driven by CLKA to output a signal, and so on alternately.

[0114] Figure 2 The three circuit units on the right are cascaded together. After cascading, the three circuit units can be used to transmit signals between adjacent circuit units. Given that the first STV signal includes a first positive sub-drive signal and a second positive sub-drive signal, and the second STV signal includes a first negative sub-drive signal and a second negative sub-drive signal, it can be seen that the cascading method between the three circuit units is to transmit the first STV signal from top to bottom and the second STV signal from bottom to top.

[0115] Figure 3 The circuit structure used to characterize a single circuit unit should be noted that... Figure 3 The circuit units in the description can be used to characterize the circuit structure of the first circuit unit or the circuit structure of the second circuit unit. Therefore, the embodiments of this application describe... Figure 3 The circuit structure does not distinguish between the first circuit unit and the second circuit unit, but will be distinguished when describing the working mode of the circuit unit later.

[0116] like Figure 3 As shown, the portion enclosed by dashed box 1 indicates the first or second control module of the aforementioned current circuit unit (e.g., the first or second circuit unit). Dashed box 1 includes the following three parts:

[0117] Part 1: A first STV signal line connected to the output signal line of the previous circuit unit (e.g., the previous first circuit unit or the previous second circuit unit), the first STV signal line being used to output a first STV signal; and a second STV signal line connected to the output signal line of the next circuit unit (e.g., the previous first circuit unit or the previous second circuit unit), the second STV signal line being used to output a second STV signal.

[0118] The second part consists of a signal gate, namely PMOS transistor m15, used to control the first STV signal to the gate drive integrated module (e.g., the first gate drive integrated module or the second gate drive integrated module); and a signal gate, namely PMOS transistor m16, used to control the second STV signal to the gate drive integrated module (e.g., the first gate drive integrated module or the second gate drive integrated module). It is understood that, due to the characteristics of a PMOS transistor—fully conducting when the gate is low and completely cutting off when the gate is high—it can be used to manage the on / off state of power supply and is a contactless switch. In the operation of the circuit unit in this embodiment, different voltage levels can be input to PMOS transistors m15 and m16 to control the on / off state of the first or second STV signal input to the subsequent gate drive integrated module. The specific working process is detailed in the following description and will not be repeated here.

[0119] Part Three: Clock Gate m1. Clock gate m1 is a PMOS transistor. As described above, clock gate m1 can be turned on by a low level and turned off by a high level. In the on state, either the first STV signal or the second STV signal will be introduced. In practical applications, timing pulse signals can be used to control the on and off states of clock gate m1 through intermittent low-level signals.

[0120] like Figure 3 As shown, the portion outside the dashed box 1 indicates the gate driver integrated module (e.g., the first gate driver integrated module or the second gate driver integrated module) of the current circuit unit (e.g., the first circuit unit or the second circuit unit). Specifically, when the input first STV signal is VGH or the input second STV signal is a high-level signal of VGH, the gate driver integrated module will control the low-level voltage output gate m13 to be turned off (i.e., closed) and control the high-level voltage output gate m14 to be turned off (i.e., turned on), so that the gate driver integrated module outputs a high level; when the input first STV signal is a low-level signal of VGL or the input second STV signal is a low-level signal of VGL, the gate driver integrated module will control the low-level voltage output gate m14 to be turned on (i.e., turned on) and control the high-level voltage output gate m13 to be turned on (i.e., turned off), so that the gate driver integrated module outputs a low level. The specific working process is described in detail later and will not be repeated here.

[0121] The following section will explain the above in detail using timing signals. Figure 3 The working process of the circuit unit in the diagram.

[0122] Example 1: Assume the scanning order in the first display panel is from top to bottom (i.e., forward scanning), and the scanning order in the second display panel is from bottom to top (i.e., reverse scanning). Figure 4 As shown, Figure 4 yes Figure 3 The timing signals (i.e., the clock signals mentioned above) correspond to the circuit units (including the first circuit unit and the second circuit unit). The timing signals are the timing signals of CLKA and CLKB, respectively. Since m1 is a PMOS transistor, the circuit unit will be triggered to turn on when the timing signal is at the lower edge of the low level.

[0123] In terms of the scanning order of the display panel, the current scanning order of the display panel is as follows: several first circuit units of the first display panel drive several first display units in the first display panel row by row sequentially by transmitting a first STV signal (i.e., the aforementioned first signal) from top to bottom and according to the control of a timing signal (i.e., the aforementioned clock signal). Correspondingly, several second circuit units of the second display panel drive several first display units in the first display panel row by row sequentially by transmitting a second STV signal (i.e., the aforementioned second signal) from bottom to top and according to the control of a timing signal.

[0124] Next, from the perspective of the working process of the circuit unit, such as Figure 3 , Figure 4 and Figure 5 As shown, assume that the first STV signal is a positive pulse in the forward direction, while the second STV signal is a positive pulse in the reverse direction.

[0125] The following describes the two-scan process of the m-th circuit unit in the first display panel:

[0126] First scanning process: For the m-th circuit unit in the first display panel (m is a positive integer greater than 1), the input signal should be the output signal (Out(m-1)) of the (m-1)-th circuit unit corresponding to the first STV signal 1. The level of m15 at the input terminal of the first STV signal line of the m-th circuit unit is kept at a constant low level (i.e., CN is a constant low voltage), and the level of m16 at the input terminal of the second STV signal line is kept at a constant high level (i.e., CNB is a constant high voltage). Then m15 is in the on state and m16 is in the off state (i.e., the first positive sub-control module is in the on state and the second reverse sub-control module is in the off state). When the m-th circuit unit receives the first STV positive pulse signal output by the (m-1)-th circuit unit and the CLKA corresponding to the m-th circuit unit is at the lower edge of the low level, the lower edge of the low level will make m1 at a low level, thereby allowing the first STV positive pulse signal to be introduced into the gate drive integrated module of the m-th circuit unit. The first STV positive pulse signal will be injected into PU_Pre and PU in the gate driver integrated module, causing m13 to turn off. At this time, CLKA is low, and VGL injects PD_Pre, causing m9 to turn on. Simultaneously, when CLKB is low, PD is negative, causing m14 to turn on, and the output voltage of m14, i.e., out(m), is a high-level signal of VGH. Afterwards, when the first STV signal 1 becomes low, it will cause m13 to turn on. At the same time, through m11, the PD node is set to a high-level signal VGH, and then m14 is in the off state, and the output voltage of m14, i.e., out(m), is a low-level signal of VGL.

[0127] Second scan process: After the first scan process ends, wait for the first STV positive pulse signal output by the (m-1)th circuit unit after the next scan begins. That is, wait for the first STV signal 1 to become a high-level signal again, and when CLKA is at the low-level lower edge, the PU_Pre node and the PU node are at a high level, making m13 in the off state. At the same time, when CLKB is low, PD is negative, making m14 conduct. The output voltage of m14, i.e., out(m), is a high-level signal of VGH. Afterwards, when the first STV signal 1 becomes a low-level signal, m13 will conduct. At the same time, through m11, the PD node is set to a high-level signal VGH, and then m14 is in the off state. The output voltage of m14, i.e., out(m), is a low-level signal of VGL.

[0128] The scanning process of the m-th circuit unit in the subsequent first display panel is similar to the two scanning processes mentioned above, and is repeated cyclically.

[0129] The following describes the two-scan process of the m-th circuit unit in the second display panel.

[0130] First scanning process: For the m-th circuit unit in the second display panel (m is a positive integer greater than 1), the input signal should be the output signal (Out(m-1)) of the (m-1)-th circuit unit corresponding to the second STV signal 1. The level of m16 at the input terminal of the second STV signal line of the m-th circuit unit remains at a constant low level, while the level of m15 at the input terminal of the first STV signal line remains at a constant high level. Then m16 is in the on state and m15 is in the off state (that is, the second positive sub-control module is in the off state and the second reverse sub-control module is in the on state). When the m-th circuit unit receives the STD positive pulse signal output by the (m+1)-th circuit unit and the CLKB corresponding to the m-th circuit unit is at the lower edge of the low level, the lower edge of the low level will make m1 at a low level, thereby allowing the first STD positive pulse signal to be introduced into the gate drive integrated module of the m-th circuit unit. The first STD positive pulse signal will be injected into PU_Pre and PU, causing m13 to turn off. At this time, CLKA is low, and VGL is injected into PD_Pre, causing m9 to turn on. When CLKA is low, PD is negative, causing m14 to turn on, and the output voltage of m14, i.e., out(m), is a high-level signal of VGH. Afterwards, when the second STV signal 1 becomes low, it will cause m13 to turn on. At the same time, through m11, the PD node is set to a high-level signal VGH, and then m14 is in the off state, and the output voltage of m14, i.e., out(m), is a low-level signal of VGL.

[0131] Second scan process: After the first scan process ends, wait for the first STV positive pulse signal output by the (m-1)th circuit unit after the next scan begins. That is, wait for the second STV signal 1 to become high again, and for CLKB to be at the lower edge of low level. At this time, the PU_Pre node and the PU node are at high level, making m13 in the off state. At the same time, when CLKA is low, PD is negative, making m14 conduct. The output voltage of m14, i.e., out(m), is a high level signal of VGH. Afterwards, when the second STV signal 1 becomes low, it will make m13 conduct. At the same time, through m11, the PD node is set to the high level signal VGH, and then m14 is in the off state. The output voltage of m14, i.e., out(m), is a low level signal of VGL.

[0132] The scanning process of the m-th circuit unit in the subsequent second display panel is similar to the two scanning processes mentioned above, and is repeated cyclically.

[0133] It should be noted that:

[0134] First, for the starting first circuit unit (the first circuit unit to start scanning) in the first display panel, the first STV signal input to it is the first STV signal input by the external circuit. The reason is that for the starting first circuit unit, there is no previous first circuit unit outputting a first STV signal to it. Therefore, the external circuit needs to trigger the input of the first STV signal in order to start the scanning process of the starting first circuit unit. Starting from the second first circuit unit after the starting first circuit unit, the scanning process is carried out according to the aforementioned scanning process of "the m-th circuit unit in the first display panel".

[0135] Secondly, similarly, for the starting second circuit unit (the first second circuit unit to start scanning) in the second display panel, the second STV signal input to it is the second STV signal input by the external circuit. The reason is that for the starting second circuit unit, there is no previous second circuit unit outputting a second STV signal to it. Therefore, an external circuit is required to trigger the input of the second STV signal in order to start the scanning process of the starting second circuit unit. Starting from the second second circuit unit after the starting second circuit unit, scanning is performed according to the aforementioned scanning process of "the m-th circuit unit in the second display panel".

[0136] Third, Example 1 above is based on the premise that both the first STV signal 1 and the second STV signal 1 are positive pulse signals. Correspondingly, both the first STV signal 1 and the second STV signal 1 can be negative pulse signals, and the working process is the same as in Example 1, with the working timing as follows: Figure 5 As shown.

[0137] In another embodiment of this application, a gate drive circuit including a first leakage protection module is also provided.

[0138] Optionally, the gate drive circuit described above includes multiple circuit units, each of which includes a first low-voltage terminal and a high-voltage terminal.

[0139] For example, the circuit unit described above also includes a first leakage protection module;

[0140] For example, the first leakage protection module includes: a first low-voltage control, a second low-voltage control, a first high-voltage control, and a second high-voltage control.

[0141] Furthermore, the first end of the second low-voltage control is disposed between the first high-voltage control and the second high-voltage control, and the second end of the second low-voltage control is connected to the low-voltage output terminal. The second low-voltage control is the second low-voltage terminal; the second high-voltage control is disposed in parallel with the first high-voltage control.

[0142] For example, the second low-voltage control is used to reduce the voltage difference between the first low-voltage terminal and the high-voltage terminal in the circuit unit, and the second high-voltage control is used to isolate the first high-voltage control and the second low-voltage control.

[0143] Understandably, without the aforementioned second low-voltage control and second high-voltage control, the high-voltage signal VGH leaks out through m14, and then through out. <m>The output causes leakage current. At the same time, due to the voltage drop between the low voltage signal VGL and the high voltage signal VGH, leakage current is generated.

[0144] Further explanation of the leakage current cause: In the drive circuit of related technologies, theoretically, m14, which controls the cutoff and on / off of VGL output, and m13, which controls the cutoff and on / off of VGH output, are not turned on simultaneously. Generally, when m14 is on, m13 is off, and vice versa. However, in practical applications, since both m13 and m14 are PMOS transistors, they cannot actually be completely turned off (for example, some PMOS transistors have negative cutoff voltages, requiring special settings). Therefore, when m13 and m14 are off, the voltage is not zero. This causes leakage from VGL at m13 to VGH at m14 when m14 is off and m13 is on, resulting in a decrease in the voltage drop between VGH and VGL. In related technologies, the driving circuit of the display panel is the aforementioned cascaded circuit. Therefore, there are multiple circuit units corresponding to multiple rows of display units, and each circuit unit includes VGH and VGL. The VGH of each of the multiple circuit units is on a VGH bus, and the VGL is also on a VGL bus. Each row has leakage current, which reduces the voltage drop. As the leakage occurs row by row, the voltage drop between VGH and VGL decreases, resulting in uneven color and content in the image displayed on the display panel.

[0145] like Figure 6 As shown, the first low-voltage control is m12, the second low-voltage control is m17, the first high-voltage control is m14, and the second high-voltage control is m14'. When the output terminal out(m) outputs a low-level signal (either a first STV signal or a second STV signal), the second low-voltage control m17 and the second high-voltage control m14' prevent leakage.

[0146] For example, in the output out <m>When the voltage is low, VGL2 is injected between M14 and M14'. Generally, VGL1 and VGL2 are set close to or equal to each other, resulting in a small or almost nonexistent voltage difference across M14. This reduces or prevents leakage current in M14, i.e., leakage current at the output. Conversely, assuming leakage exists, it will leak out from m14', meaning there is leakage at VGL2. However, within the circuit unit, a voltage drop occurs between VGH at m13 and VGL1 at m14. The leakage at m14' will not cause leakage accumulation between all cascaded circuit units.

[0147] In one example, the value of m17 can be set much smaller than that of m14, m14', and m13. Since the leakage current is proportional to the size of the PMOS transistor, the possibility of leakage from VGL1 to VGL2 through m14' and m17 is greatly reduced. Furthermore, even if leakage exists at m17, the power consumption caused by leakage will be significantly reduced, saving energy. Therefore, VGL2 will output through its port due to leakage, and even if a voltage drop occurs, it will not affect the low-level output because it will not be output from out(m).

[0148] In another embodiment of this application, a gate drive circuit that prevents signal attenuation is also provided.

[0149] Optionally, the gate drive circuit includes multiple circuit units, and the circuit units further include a first output cascade module and a second output cascade module.

[0150] For example, the first output cascade module is used to transmit a drive signal, which is used to drive the display unit corresponding to the next circuit unit to start scanning.

[0151] For example, the second output cascade module is used to transmit a scan signal to the next circuit unit of the circuit unit, the scan signal does not include the drive signal, the scan signal is used to cause the next circuit to perform a scan, and the second output cascade module is used to prevent the output signal from attenuating.

[0152] It is understandable that:

[0153] First, the aforementioned first signal includes both a drive signal and a scan signal. Specifically, after the next circuit unit or the previous circuit unit receives the first signal, the drive signal can be used to drive the next circuit unit or the previous circuit unit to receive the scan signal and initiate the scanning process of the display unit in the corresponding row of the next circuit unit or the display unit in the corresponding row of the previous circuit unit.

[0154] Second, in the related technology, when a circuit unit drives an adjacent circuit unit cascaded with it, it needs to be driven by a driving signal (e.g., a first forward sub-driving signal, a first reverse sub-driving signal, a second forward sub-driving signal, and a second reverse sub-driving signal). Since each driving signal and the scanning signal together constitute the first signal, and the first signal is attenuated after each driving signal is output, and this attenuation is cumulative, the signal voltage of the first signal will become smaller and smaller.

[0155] Third, the second output cascade module is used to transmit the scanning signal, but not the drive signal, to ensure that the drive signal does not attenuate.

[0156] like Figure 7 As shown, a second output cascade module is added to the right side of the gate driver integrated module. The second output cascade module includes m13, m14, and out_C. <m>This second output cascade module is only used for signal transmission between uplink and downlink (connecting the uplink STD and the downlink STV), and is not used to drive the gate lines.

[0157] Furthermore, since m13 and m14 are not used to drive the gate lines of the next or previous circuit unit (e.g., m15 or m16), the size of m13 and m14 transistors is generally relatively small.

[0158] Optionally, in this embodiment, the first output cascade module includes a bootstrap capacitor, which is used to change the voltage at the voltage output terminal of the circuit unit, reduce the voltage difference between the voltage input terminal and the voltage output terminal of the circuit unit, and prevent leakage of the circuit model unit by the voltage at the output terminal.

[0159] like Figure 6 and Figure 7 As shown, the self-lifting capacitor includes capacitor C1' and / or capacitor C1.

[0160] In another embodiment of this application, the circuit unit further includes a second leakage protection module.

[0161] For example, the second leakage protection module is connected to the first output cascade module and / or the second output cascade module, and the second leakage protection module is used to reduce voltage drop.

[0162] like Figure 7 As shown, the second leakage protection module is a PMOS transistor m17. The gate of m17 can be connected to the cascaded output out_C(m) or to the gate line drive output out. <m>.

[0163] Further, the bootstrap capacitor can include the capacitor C1 and / or the capacitor C1'.

[0164] Figure 8 A flowchart of a driving method of a gate driving circuit is provided in the embodiments of the present application. The execution subject of the method can be the gate driving circuit described above or a display terminal. The gate driving circuit includes a first circuit module and a second circuit module. The first circuit module is configured to drive a first display panel, and the second circuit module is configured to drive a second display panel. The first display panel and the second display panel are adjacent to each other in a vertical direction. As shown in Figure 8 The method includes the following steps 101 and 102.

[0165] Step 101: The first circuit module drives display units of the first display panel row by row in a first scanning order.

[0166] Step 102: The second circuit module drives display units of the first display panel row by row in a second scanning order.

[0167] The scanning direction of the first scanning order is a first direction, and the scanning direction of the second scanning order is a second direction. The first direction is opposite to the second direction.

[0168] The first circuit module includes a plurality of first circuit units, and the second circuit module includes a plurality of second circuit units. The first circuit units are configured to drive a row of display units in the first display panel, and the second circuit units are configured to drive a row of display units in the second display panel.

[0169] The plurality of first circuit units are driven in a first driving order, and the plurality of second circuit units are driven in a second driving order.

[0170] The first driving order of the plurality of first circuit units matches the first scanning order of the display units of the first display panel, and the second driving order of the plurality of second circuit units matches the second scanning order of the display units of the second display panel.

[0171] In a possible embodiment, the first circuit unit outputs a first signal to a next first circuit unit of the first circuit unit in response to a first driving signal; and the second circuit unit outputs a second signal to a previous first circuit unit of the first circuit module in response to a second driving signal.

[0172] The first signal received by the first circuit unit is used to drive a row of display units in the first display panel corresponding to the first circuit unit.

[0173] The second signal received by the second circuit unit is used to drive a row of display units in the second display panel corresponding to the second circuit unit.

[0174] In a possible embodiment, the first circuit unit comprises a first control module and a first gate drive integrated module; the first control module turns on a first signal source in response to the first driving signal, and controls the first gate drive integrated module to output the first signal under the action of a clock signal;

[0175] The second circuit unit comprises a second control module and a second gate drive integrated module; the second control module turns on a second signal source in response to the second driving signal, and controls the second gate drive integrated module to output the second signal under the action of a clock signal.

[0176] In a possible embodiment, the first control module comprises a first forward sub-control module and a first reverse sub-control module; the first forward sub-control module is responsive to a first forward sub-driving signal output by a previous first circuit unit, and the second reverse sub-control module is responsive to a second reverse sub-driving signal output by a next first circuit unit; the first forward sub-control module is in a conductive state, and the second reverse sub-control module is in a cut-off state; the driving directions of the first forward sub-driving signal and the second reverse sub-driving signal are opposite; and the first signal comprises the first forward sub-driving signal.

[0177] The second control module comprises a second forward sub-control module and a second reverse sub-control module; the second forward sub-control module is responsive to a second forward sub-driving signal output by a next second circuit unit, and the second reverse sub-control module is responsive to a second reverse sub-driving signal output by a previous second circuit unit; the second forward sub-control module is in a cut-off state, and the second reverse sub-control module is in a conductive state; the driving directions of the second forward sub-driving signal and the second reverse sub-driving signal are opposite; and the second signal comprises the second reverse sub-driving signal.

[0178] In a possible embodiment, the gate drive circuit comprises a plurality of circuit units, and each of the circuit units comprises a first low-voltage end and a high-voltage end; and each of the circuit units further comprises a first leakage prevention module.

[0179] The first leakage prevention module comprises a first low-voltage control, a second low-voltage control, a first high-voltage control and a second high-voltage control; a first end of the second low-voltage control is arranged between the first high-voltage control and the second high-voltage control, a second end of the second low-voltage control is arranged to be connected to a low-voltage output end, and the second low-voltage control is a second low-voltage end; and the second high-voltage control is arranged in parallel with the first high-voltage control.

[0180] The second low voltage control is configured to reduce a voltage difference between the first low voltage end and the high voltage end in the circuit unit, and the second high voltage control is configured to isolate the first high voltage control and the second low voltage control.

[0181] In a possible embodiment, the gate drive circuit includes a plurality of circuit units, and each of the circuit units further includes a first output cascade module and a second output cascade module.

[0182] The second output cascade module transmits a scan signal to a next circuit unit of the circuit unit, the scan signal does not include the drive signal, and the scan signal is used to enable the next circuit unit to perform scanning.

[0183] In a possible embodiment, the first output cascade module includes a bootstrap capacitor, and the bootstrap capacitor is used to reduce a voltage difference between a voltage input end and a voltage output end of the circuit unit to change a voltage of the voltage output end, so that the voltage of the output end prevents the circuit model unit from leaking.

[0184] In a possible embodiment, the circuit unit further includes a second anti-leakage module connected with the first output cascade module and / or the second output cascade module, and the second anti-leakage module is used to reduce a voltage drop.

[0185] In the embodiment of the present application, the gate drive circuit includes a first circuit module and a second circuit module, wherein the first circuit module is configured to drive a first display panel, and the second circuit module is configured to drive a second display panel adjacent to the first display panel in a top-bottom direction. The first circuit module drives display units of the first display panel in a first scanning order row by row, and the second circuit module drives display units of the first display panel in a second scanning order opposite to the scanning direction of the first scanning order (i.e., the first direction) row by row. In this way, because the scanning orders of the display units in the display panels adjacent to each other in the top-bottom direction are opposite, the scanning timing of the display units at the joint of the display panels adjacent to each other in the top-bottom direction is the same, and thus the image frame difference between the display units at the joint of the display panels adjacent to each other in the top-bottom direction does not occur, i.e., the image tearing at the joint of the display panels adjacent to each other in the top-bottom direction does not occur.

[0186] The embodiment of the present application provides a computer program product, and the computer program product includes instructions. Figure 8 The instructions are executed by a processor to implement each step of the method shown.

[0187] It should be noted that although the operation of the method of the present invention is described in a specific order in the accompanying drawings, this does not require or imply that the operations must be performed in that specific order, or that all the operations shown must be performed in order to achieve the desired result.

[0188] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the training rule determination method described in this application. For example, it can execute... Figure 8 The steps of the method shown.

[0189] It should be understood that the units described in the driving method of the gate driving circuit correspond to the various steps in the method described in the accompanying drawings. Therefore, the operations and features described above for the method also apply to the gate driving circuit and the units contained therein, and will not be repeated here. The gate driving circuit can be pre-implemented in the browser or other security applications of a computer device, or it can be loaded into the browser or other security applications of a computer device through download or other means. The corresponding units in the gate driving circuit can cooperate with the units in the computer device to implement the solutions of the embodiments of this application.

[0190] The division of modules or units mentioned in the detailed description above is not mandatory. In fact, according to the embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0191] It should be noted that for details not disclosed in the gate drive circuit of the embodiments of this application, please refer to the details disclosed in the above embodiments of this application, which will not be repeated here.

[0192] The following is for reference. Figure 9 , Figure 9 A schematic diagram of a computer device suitable for implementing embodiments of this application is shown. For example... Figure 9 As shown, the computer system 1700 includes a central processing unit (CPU) 1701, which can perform various appropriate actions and processes based on programs stored in read-only memory (ROM) 1702 or programs loaded from storage section 1708 into random access memory (RAM) 1703. RAM 1703 also stores various programs and data required for the system's operating instructions. CPU 1701, ROM 1702, and RAM 1703 are interconnected via bus 1704. Input / output (I / O) interface 1705 is also connected to bus 1704.

[0193] The following components are connected to I / O interface 1705: an input section 1706 including a keyboard, mouse, etc.; an output section 1707 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 1708 including a hard disk, etc.; and a communication section 1709 including a network interface card such as a LAN card, modem, etc. The communication section 1709 performs communication processing via a network such as the Internet. A drive 1710 is also connected to I / O interface 1705 as needed. Removable media 1711, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., are installed on drive 1710 as needed so that computer programs read from them can be installed into storage section 1708 as needed.

[0194] Specifically, according to embodiments of this application, the flowchart above refers to... Figure 8 The described process can be implemented as a computer software program. For example, embodiments of this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowchart. In such an embodiment, the computer program contains program code for performing the methods shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via communication section 1709, and / or installed from removable medium 1711. When the computer program is executed by central processing unit (CPU) 1701, it performs the functions defined in the system of this application.

[0195] It should be noted that the computer-readable medium shown in this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media can also be any computer-readable medium other than computer-readable storage media, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0196] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operational instructions of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two connected blocks may actually be executed substantially in parallel, or they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified functions or operational instructions, or using a combination of dedicated hardware and computer instructions.

[0197] The units or modules described in the embodiments of this application can be implemented in software or hardware. The described units or modules can also be housed in a processor; for example, a processor can be described as including a first receiving module, a second receiving module, and a transmitting module. The names of these units or modules do not, in certain circumstances, constitute a limitation on the unit or module itself.

[0198] In another aspect, this application also provides a computer-readable storage medium, which may be included in the electronic device described in the above embodiments, or may exist independently and not assembled into the electronic device. The computer-readable storage medium stores one or more programs that, when used by one or more processors, execute the driving method of the gate driving circuit described in this application.

[0199] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of disclosure in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the foregoing disclosed concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.< / m> < / m> < / m> < / m>

Claims

1. A gate drive circuit characterized by comprising: The gate drive circuit comprises a first circuit module, a second circuit module and a plurality of circuit units, the circuit unit comprises a first low-voltage end, a high-voltage end and a first anti-creeping module, the first anti-creeping module comprises a low-voltage output gate, a first low-voltage control, a second low-voltage control, a first high-voltage control and a second high-voltage control, the first circuit module is used for driving a first display panel, the second circuit module is used for driving a second display panel, and the first display panel is adjacent to the second display panel in up and down directions; the control end of the first low-voltage control is connected with the first low-voltage end, and the first end is connected with a pull-up node; the control end of the low-voltage output gate is connected with the pull-up node, the first end is connected with the first low-voltage end, and the second end is connected with the first end of the first high-voltage control and the output end of the circuit unit respectively; the control end of the first high-voltage control is connected with a pull-down node, and the second end is connected with the first end of the second high-voltage control; the control end of the second high-voltage control is connected with the pull-down node, and the second end is connected with the high-voltage end; the control end of the second low-voltage control is connected with the output end of the circuit unit, the first end is arranged between the first high-voltage control and the second high-voltage control, and the second end of the second low-voltage control is arranged in connection with a low-voltage output end; The first circuit module is configured to drive display units of the first display panel row by row in a first scanning sequence; The second circuit module is configured to drive display units of the second display panel row by row in a second scanning sequence; The second low-voltage control is configured to, in a case where the output end is at a low level, fill the low-level signal of the low-voltage output end between the first high-voltage control and the second high-voltage control, so that the voltage difference between the two ends of the first high-voltage control is small, thereby reducing the leakage current of the first high-voltage control. The scanning direction of the first scanning sequence is a first direction, and the scanning direction of the second scanning sequence is a second direction, and the first direction is opposite to the second direction.

2. The gate drive circuit according to claim 1, characterized by The first circuit module comprises a plurality of first circuit units, and the second circuit module comprises a plurality of second circuit units, the first circuit unit is configured to drive a row of display units in the first display panel, and the second circuit unit is configured to drive a row of display units in the second display panel; The plurality of first circuit units are driven in a first driving sequence, and the plurality of second circuit units are driven in a second driving sequence; The first driving sequence of the plurality of first circuit units matches the first scanning sequence of the display units of the first display panel, and the second driving sequence of the plurality of second circuit units matches the second scanning sequence of the display units of the second display panel.

3. The gate drive circuit according to claim 2, characterized by The first circuit unit is configured to output a first signal to a next first circuit unit of the first circuit unit in response to a first driving signal; and the second circuit unit is configured to output a second signal to a previous first circuit unit of the first circuit module in response to a second driving signal. The first signal received by the first circuit unit is used to drive a row of display units in the first display panel corresponding to the first circuit unit; The second signal received by the second circuit unit is used to drive a row of display units in the second display panel corresponding to the second circuit unit.

4. The gate drive circuit according to claim 3, characterized by The first circuit unit comprises a first control module and a first gate drive integrated module; The first control module is configured to turn on a first signal source in response to the first driving signal, and control the first gate drive integrated module to output the first signal under the action of a clock signal. The second circuit unit comprises a second control module and a second gate drive integrated module; The second control module is configured to turn on a second signal source in response to the second driving signal, and control the second gate drive integrated module to output the second signal under the action of a clock signal.

5. The gate drive circuit according to claim 4, characterized in that The first control module comprises a first forward sub-control module and a first reverse sub-control module, the first forward sub-control module is configured to respond to a first forward sub-driving signal output by a previous first circuit unit, and the first reverse sub-control module is configured to respond to a first reverse sub-driving signal output by a next first circuit unit; the first forward sub-control module is in a conductive state, the first reverse sub-control module is in a cut-off state, the driving directions of the first forward sub-driving signal and the first reverse sub-driving signal are opposite, and the first signal comprises the first forward sub-driving signal; The second control module comprises a second forward sub-control module and a second reverse sub-control module, the second forward sub-control module is configured to respond to a second forward sub-driving signal output by a next second circuit unit, and the second reverse sub-control module is configured to respond to a second reverse sub-driving signal output by a previous second circuit unit; the second forward sub-control module is in a cut-off state, the second reverse sub-control module is in a conductive state, the driving directions of the second forward sub-driving signal and the second reverse sub-driving signal are opposite, and the second signal comprises the second reverse sub-driving signal.

6. The gate drive circuit according to claim 1, characterized by The gate drive circuit comprises a plurality of circuit units, and each circuit unit further comprises a first output cascade module and a second output cascade module; the first output cascade module is configured to transmit a driving signal, and the driving signal is used to drive a display unit corresponding to a next circuit unit to start scanning; The second output cascade module is configured to transmit a scanning signal to the next circuit unit of the circuit unit, the scanning signal does not comprise the driving signal, and the scanning signal is used to enable the next circuit unit to perform scanning; and the second output cascade module is configured to prevent the output signal from being attenuated.

7. The gate drive circuit according to claim 6, characterized in that The first output cascade module comprises a bootstrap capacitor, and the bootstrap capacitor is configured to change the voltage of a voltage output end of the circuit unit, reduce the voltage difference between a voltage input end and the voltage output end of the circuit unit, and prevent the voltage of the output end from leaking.

8. The gate drive circuit according to claim 6 or 7, characterized in that The circuit unit further comprises a second anti-leakage module, and the second anti-leakage module is connected with the first output cascade module and / or the second output cascade module; and the second anti-leakage module is configured to reduce voltage drop.

9. A driving method of a gate driving circuit, characterized by, The gate drive circuit comprises a first circuit module, a second circuit module and a plurality of circuit units, the circuit unit comprises a first low-voltage end, a high-voltage end and a first anti-creeping module, the first anti-creeping module comprises a low-level voltage output gate, a first low-voltage control, a second low-voltage control, a first high-voltage control and a second high-voltage control, the first circuit module is used for driving a first display panel, the second circuit module is used for driving a second display panel, the first display panel is adjacent to the second display panel, a control end of the first low-voltage control is connected with the first low-voltage end, and a first end is connected with a pull-up node; a control end of the low-level voltage output gate is connected with the pull-up node, a first end is connected with the first low-voltage end, and a second end is connected with a first end of the first high-voltage control and an output end of the circuit unit respectively; a control end of the first high-voltage control is connected with a pull-down node, and a second end is connected with a first end of the second high-voltage control; a control end of the second high-voltage control is connected with the pull-down node, and a second end is connected with the high-voltage end; a control end of the second low-voltage control is connected with the output end of the circuit unit, a first end is arranged between the first high-voltage control and the second high-voltage control, and a second end of the second low-voltage control is arranged in connection with a low-voltage output end, and the method comprises: The first circuit module drives display units of the first display panel row by row in a first scanning sequence; The second circuit module drives display units of the first display panel row by row in a second scanning sequence; In the case that the second low-voltage control is in a low level at the output end, a low-level signal of the low-voltage output end is filled between the first high-voltage control and the second high-voltage control, so that a voltage difference between two ends of the first high-voltage control is small, thereby reducing a leakage current of the first high-voltage control; The first scanning sequence is opposite to the second scanning sequence.

10. A computer device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the program to realize the method in claim 9.

11. A computer readable storage medium having stored thereon a computer program, characterized in that, The program is executed by the processor to realize the method in claim 9.

12. A computer program product, comprising instructions therein, wherein the computer program product is characterised in that, The instructions are executed by the processor to realize the method in claim 9. The instructions are executed by the processor to realize the method in claim 9.

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