Array substrate, display panel and display device

Abstract

The application discloses an array substrate, a display panel and a display device. The array substrate comprises a substrate, a plurality of pixel columns, a driving circuit and a plurality of first wirings. The plurality of pixel columns are arranged on the substrate, and the driving circuit is arranged in the middle of the substrate. The plurality of first wirings are arranged on the substrate, and the plurality of first wirings are connected with the corresponding pixel column and the driving circuit respectively. The driving circuit drives the plurality of pixel columns through the plurality of first wirings, and the loads of the plurality of first wirings are basically the same. The layout of the first wiring on the array substrate can be changed, so that the load of each first wiring is basically consistent. When the driving circuit drives the pixel, the driving current output by the driving circuit to each column of pixels is basically consistent, and the vertical stripe defect of the display panel is relieved or eliminated.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to an array substrate, a display panel, and a display device. Background Technology

[0002] Currently, high refresh rate and ultra-narrow bezel display panels have gradually become the mainstream. In related technologies, multiple source driver ICs are arranged in the middle of the array substrate. Multiple data lines connect the source driver ICs to a corresponding column of pixels. In this way, the source driver ICs can drive the corresponding column of pixels through the data lines.

[0003] Because the Source Driver IC is centered and the distance to multiple columns of pixels varies, and because the ultra-narrow bezel requirement makes it impossible to achieve equal resistance wiring, multiple data lines are routed in a fan-out pattern, with different data lines having different resistances.

[0004] On the other hand, in high refresh rate display panels, the charging time for one frame is relatively short. The pixels in a column corresponding to data lines with different resistances will have uneven pixel charging, which will cause vertical stripe defects (Block Mura) to appear on the display panel. Summary of the Invention

[0005] This invention provides an array substrate, a display panel, and a display device. The array substrate includes a substrate, multiple columns of pixels, a driving circuit, and multiple first traces. The multiple columns of pixels are disposed on the substrate, and the driving circuit is centrally disposed on the substrate. The multiple first traces are disposed on the substrate, and each first trace connects a corresponding column of pixels to the driving circuit. The driving circuit drives the multiple columns of pixels through the multiple first traces, and the loads on the multiple first traces are substantially the same.

[0006] The driving circuit outputs driving current to a column of pixels through a first trace, thereby driving that column of pixels. Each column of pixels corresponds to a load. When the driving circuit outputs driving current to a column of pixels, the magnitude of the output driving current is related to the load. If the loads corresponding to the pixels are basically the same, the driving current output by the driving circuit to the pixels will also be basically the same. Since the loads of each first trace on the array substrate are basically the same, when the driving circuit drives the pixels, the driving current output by the driving circuit to each column of pixels is basically the same, which can alleviate or eliminate the vertical stripe defects that appear on the display panel.

[0007] In some embodiments, each first trace includes a first segment connected to the driving circuit and a second segment connected to the corresponding column of pixels. The plurality of first segments are arranged substantially along the column direction of the array substrate, and the second segments extend substantially along the row direction of the array substrate. Along the row direction, from the middle to both sides, the length of the first segments gradually decreases to compensate for the difference in length of the first traces caused by the gradual increase in length of the corresponding second segments.

[0008] The layout of the first trace can be changed so that the length of the first segment corresponding to the first trace in the middle of the substrate is the longest, and the length of the first segment corresponding to the first trace on both sides of the substrate is the shortest, in order to compensate for the inconsistency in the length of the first trace, and thus compensate for the inconsistency in the load caused by the inconsistency in the length of the first trace.

[0009] In some embodiments, the first segment includes a serpentine portion that gradually shortens in length from the center to both sides along the row direction.

[0010] The serpentine section can compensate for the length of the first segment, and thus compensate for the length of the first trace. By compensating for the length of the first trace, the inconsistency in the length of the first trace is compensated, and the load inconsistency caused by the inconsistency in the length of the first trace is compensated, so that the driving current output by the driving circuit to each column of pixels is basically consistent.

[0011] In some implementations, the parasitic capacitance of the first segment gradually decreases from the middle to both sides along the row direction.

[0012] The different parasitic capacitances resulting from the layout of the first traces can affect their load. By adjusting the layout of the first traces, their parasitic capacitances can be altered, allowing for capacitance compensation for the traces with smaller loads. This ensures that the drive current output by the driving circuit to each column of pixels is essentially consistent.

[0013] In some implementations, the plurality of first segments overlap in pairs, with the overlapping area of ​​each pair of first segments gradually decreasing from the middle to both sides along the row direction.

[0014] The parasitic capacitance value of the first trace is set by overlapping the first segments of every two first traces. Capacitor compensation is performed on the first trace with a smaller load, so that the driving current output by the driving circuit to each column of pixels is basically the same.

[0015] In some implementations, the plurality of first segments overlap sequentially, from the middle to both sides along the row direction, and the area of ​​overlap between each first segment and the two adjacent first segments gradually decreases.

[0016] The parasitic capacitance value corresponding to the first trace is set by the overlapping area of ​​the first segment, and capacitance compensation is performed on the first trace with a smaller load, so that the driving current output by the driving circuit to each column of pixels is basically the same.

[0017] In some embodiments, the display panel further includes a second substrate and a plurality of second traces. The second substrate and the substrate are disposed opposite to each other, and the plurality of first traces are disposed on a side close to the second substrate. The plurality of second traces are disposed on the second substrate on a side close to the substrate, extending from the center to both sides along the row direction, and the area of ​​the overlapping portion of the orthographic projection of the second trace on the substrate and the first trace gradually decreases.

[0018] By introducing a second substrate and a second trace, the parasitic capacitance value of the first trace can also be set by configuring the layout between the second trace and the first trace. Capacitor compensation is performed on the first trace with a smaller load, so that the driving current output by the driving circuit to each column of pixels is basically the same.

[0019] In some embodiments, the portion of the second trace that overlaps with the first trace in the orthographic projection of the substrate is on the first segment.

[0020] The overlapping portion between the second trace and the first trace is on the first segment. Capacitor compensation can be performed on the first segment of the first trace. Capacitor compensation is performed on the first trace with a smaller load, so that the driving current output by the driving circuit to each column of pixels is basically the same.

[0021] In some embodiments, the overlapping portion of the orthographic projection of the second trace on the substrate and the first trace lies on both the first and second segments. Along the row direction from the middle to both sides, the overlapping area of ​​the orthographic projection of the second trace on the substrate and the second segment gradually increases, while the overlapping area of ​​the orthographic projection of the second trace on the substrate and the first segment gradually decreases.

[0022] With the same overlap area, the capacitance compensated by the second trace in the first segment is greater than the capacitance compensated by the first trace in the second segment. Along the row direction from the middle to both sides, the overlap area between the second trace and the second segment gradually increases, while the overlap area between the second trace and the first segment gradually decreases. Therefore, the capacitance compensated on the first trace in the middle of the substrate further increases, while the capacitance compensated on the first traces on both sides of the substrate further decreases. This is beneficial for capacitance compensation on the first trace with a smaller load, ensuring that the driving current output by the driving circuit to each column of pixels is essentially consistent.

[0023] The present invention provides a display panel, the display panel comprising an array substrate according to any of the above embodiments.

[0024] The present invention provides a display device, the display device including a display panel of any of the above embodiments.

[0025] In the array substrate, display panel, and display device of this invention, the array substrate includes a substrate, multiple columns of pixels, a driving circuit, and multiple first traces. The multiple columns of pixels are disposed on the substrate, and the driving circuit is centrally disposed on the substrate. The multiple first traces are disposed on the substrate, and each first trace connects a corresponding column of pixels to the driving circuit. The driving circuit drives the multiple columns of pixels through the multiple first traces, and the loads of the multiple first traces are substantially the same. By changing the layout of the first traces on the array substrate, the load of each first trace can be made substantially consistent. When the driving circuit drives the pixels, the driving current output by the driving circuit to each column of pixels is substantially consistent, thereby alleviating or eliminating vertical stripe defects in the display panel.

[0026] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0027] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0028] Figure 1 This is a schematic diagram of the array substrate according to an embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram of the array substrate according to the first embodiment of the present invention;

[0030] Figure 3 This is a schematic diagram of the array substrate according to the second embodiment of the present invention;

[0031] Figure 4 This is a schematic diagram of the array substrate according to the third embodiment of the present invention;

[0032] Figure 5 This is a schematic diagram of the array substrate according to the fourth embodiment of the present invention;

[0033] Figure 6 This is a schematic diagram of the array substrate according to the fifth embodiment of the present invention;

[0034] Figure 7 This is a schematic diagram of the display panel and display device of the present invention. Detailed Implementation

[0035] Embodiments of the present invention are described in detail below, and these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0036] Currently, high refresh rate and ultra-narrow bezel display panels have gradually become the mainstream. In related technologies, multiple source driver ICs are arranged in the middle of the array substrate. Multiple data lines connect the source driver ICs to a corresponding column of pixels. In this way, the source driver ICs can drive the corresponding column of pixels through the data lines.

[0037] Because the Source Driver IC is centered and the distance to multiple columns of pixels varies, and because the ultra-narrow bezel requirement makes it impossible to achieve equal resistance wiring, multiple data lines are routed in a fan-out pattern, with different data lines having different resistances.

[0038] On the other hand, in high refresh rate display panels, the charging time for one frame is relatively short. The pixels in a column corresponding to data lines with different resistances will have uneven pixel charging, which will cause vertical stripe defects (Block Mura) to appear on the display panel.

[0039] Please see Figure 1 This invention provides an array substrate 100. The array substrate 100 includes a substrate 110, a driving circuit 120, multiple first traces 130, and multiple columns of pixels 140. The multiple columns of pixels 140 are disposed on the substrate 110, and the driving circuit 120 is centrally disposed on the substrate 110. The multiple first traces 130 are disposed on the substrate 110, and each of the multiple first traces 130 connects a corresponding column of pixels 140 to the driving circuit 120. The driving circuit 120 drives the multiple columns of pixels 140 through the multiple first traces 130, and the loads of the multiple first traces 130 are substantially the same.

[0040] The driving circuit 120 outputs driving current to a column of pixels 140 through a first trace 130 to drive the column of pixels 140. Each column of pixels 140 corresponds to a load. When the driving circuit 120 outputs driving current to a column of pixels 140, the magnitude of the output driving current is related to the load. If the loads of the first trace 130 are basically the same, the driving current output by the driving circuit 120 to the pixels 140 will also be basically the same. Since the loads of each first trace 130 on the array substrate 100 are basically the same, when the driving circuit 120 drives the pixels 140, the driving current output by the driving circuit 120 to each column of pixels 140 is basically the same, which can alleviate or eliminate the vertical stripe defects that appear on the display panel.

[0041] The load corresponding to each column of pixels 140 is related to the properties of the first trace 130 to which the pixel 140 is connected and the layout of the trace. On the one hand, the properties of the first trace 130 itself, such as its length and material, will affect the load of the first trace 130 itself. On the other hand, the parasitic capacitances of the first traces 130 are different due to their layout, which in turn affects the load of the first trace 130.

[0042] By changing the layout of the first traces 130 on the array substrate 100, the load of each first trace 130 can be made to be basically the same. When the driving circuit 120 drives the pixel 140, the driving current output by the driving circuit 120 to each column of pixel 140 is basically the same, thereby alleviating or eliminating the vertical stripe defects that appear on the display panel.

[0043] Specifically, in a column of pixels 140, the pixel 140 circuit includes a light-emitting device and a driving transistor for driving the light-emitting device. The driving circuit 120 can be connected to the source of the driving transistor through a first trace 130, or it can be connected to the gate of the driving transistor through a first trace 130. That is, the first trace 130 can be the gate line connecting the driving circuit 120 and the driving transistor, or it can be the data line connecting the driving circuit 120 and the driving transistor.

[0044] When the driving circuit 120 drives a column of pixels 140, the magnitude of the driving current output by the driving circuit 120 to the pixels 140 is related to the load of the corresponding first trace 130. The larger the load of the first trace 130, the smaller the driving current output by the driving circuit 120 to the pixels 140, and vice versa.

[0045] It should be noted that "the load of each first trace 130 is basically consistent" means that the maximum difference in load between each first trace 130 is within a preset range. This preset range can be set according to actual usage requirements. For example, by setting the layout of the first traces 130, the difference between the maximum and minimum loads of the first traces 130 can be less than 1%, 5%, 10%, or other values. This ensures that the difference between the maximum and minimum drive currents output by the drive circuit 120 to each column of pixels 140 is less than 1%, 5%, 10%, or other values, and the drive current of each column of pixels 140 is basically consistent, which can alleviate or eliminate the vertical stripe defects appearing on the display panel.

[0046] This invention provides an array substrate 100, which includes a substrate 110, multiple columns of pixels 140, a driving circuit 120, and multiple first traces 130. The multiple columns of pixels 140 are disposed on the substrate 110, and the driving circuit 120 is centrally disposed on the substrate 110. The multiple first traces 130 are disposed on the substrate 110, and each first trace 130 connects a corresponding column of pixels 140 to the driving circuit 120. The driving circuit 120 drives the multiple columns of pixels 140 through the multiple first traces 130, and the loads of the multiple first traces 130 are substantially the same. By changing the layout of the first traces 130 on the array substrate 100, the load of each first trace 130 can be made substantially consistent. When the driving circuit 120 drives the pixels 140, the driving current output by the driving circuit 120 to each column of pixels 140 is substantially consistent, thereby alleviating or eliminating vertical stripe defects on the display panel.

[0047] In some embodiments, each first trace 130 includes a first segment 131 connected to the driving circuit 120 and a second segment 132 connected to a corresponding column of pixels 140. Multiple first segments 131 are arranged substantially along the column direction of the display panel, and the second segments 132 extend substantially along the row direction of the display panel. Along the row direction, from the center to both sides, the length of the first segments 131 gradually decreases to compensate for the varying lengths of the first traces 130 caused by the gradually increasing length of the corresponding second segments 132.

[0048] The driving circuit 120 is centrally located on the substrate 110. The shortest distance along the row direction is between the driving circuit 120 and a column of pixels 140 located in the middle of the substrate 110, meaning the length of the second segment 132 corresponding to the first trace 130 located in the middle of the substrate 110 is set to the shortest. The longest distance along the row direction is between the driving circuit 120 and a column of pixels 140 located on both sides of the substrate 110, meaning the length of the second segment 132 corresponding to the first trace 130 located in the middle of the substrate 110 is set to the longest. Inconsistent lengths of the second segment 132 will result in inconsistent lengths of the first trace 130, leading to inconsistent loads on each first trace 130, and consequently, inconsistent driving current output by the driving circuit 120 to each column of pixels 140.

[0049] The layout of the first trace 130 can be changed so that the length of the first segment 131 corresponding to the first trace 130 in the middle of the substrate 110 is the longest, and the length of the first segment 131 corresponding to the first trace 130 on both sides of the substrate 110 is the shortest, in order to compensate for the inconsistency in the length of each first trace 130, thereby compensating for the inconsistency in the load caused by the inconsistency in the length of the first trace 130, so that the driving current output by the driving circuit 120 to each column of pixels 140 is basically the same.

[0050] Specifically, the layout of the first routing line 130 can be referred to Figure 2 It should be noted that, Figure 2 This is a layout diagram of the first trace 130 on the left half of the substrate 110, that is, the layout diagram of the first trace 130 located from the left side of the substrate 110 to the middle of the substrate 110. The layout of the first trace 130 on the right half of the substrate 110 is symmetrical to the layout of the first trace 130 on the left half of the substrate 110.

[0051] Each first trace 130 includes a first segment 131 and a second segment 132. The substrate of the second segment 132 is arranged along the row direction of the substrate 110, and the substrate of the first segment 131 is arranged along the column direction of the substrate 110.

[0052] The longest distance along the row direction is between the driving circuit 120 and a column of pixels 140 disposed on both sides of the substrate 110. That is, the length of the second segment 132 corresponding to the first trace 130 disposed in the middle of the substrate 110 can be set to the longest, and the length of the corresponding first segment 131 can be set to the shortest.

[0053] The distance between the driving circuit 120 and the column of pixels 140 disposed in the middle of the substrate 110 along the row direction is minimized. That is, the length of the second segment 132 corresponding to the first trace 130 disposed in the middle of the substrate 110 can be set to the shortest, and the length of the corresponding first segment 131 can be set to the longest to compensate for the length of the second segment 132.

[0054] In some embodiments, the first segment 131 includes a serpentine portion 1311, which gradually shortens in length from the middle to both sides along the direction of travel.

[0055] The serpentine portion 1311 can compensate for the length of the first segment 131, and thus compensate for the length of the first trace 130, in order to compensate for the inconsistency in the length of the first trace 130, and further compensate for the inconsistency in the load caused by the inconsistency in the length of the first trace 130, so that the driving current output by the driving circuit 120 to each column of pixels 140 is basically the same.

[0056] Specifically, refer to Figure 2 The shortest distance is between the driving circuit 120 and the column of pixels 140 disposed in the middle of the substrate 110, while the longest distance is between the driving circuit 120 and the column of pixels 140 disposed on both sides of the substrate 110. The first trace 130 disposed in the middle of the substrate 110 has the shortest length, the first segment 131 corresponding to the first trace 130 has the longest length, and the second segment 132 has the shortest length. The first trace 130 disposed on both sides of the substrate 110 has the longest length, the first segment 131 corresponding to the first trace 130 has the shortest length, and the second segment 132 has the longest length.

[0057] The first segment 131 includes a serpentine portion 1311, which is longer than the straight segment portion in the same area. Therefore, the serpentine portion 1311 of the first segment 131 can compensate for the length of the first trace 130.

[0058] The first trace 130 in the middle of the substrate 110 is the shortest, resulting in the lowest resistance and therefore requiring the most resistance compensation. Conversely, the first traces 130 on both sides of the substrate 110 are the longest, resulting in the highest resistance and therefore requiring the least resistance compensation.

[0059] Therefore, the length of the first segment 131 of the first trace 130 in the middle of the substrate 110 can be set to the longest, and the corresponding serpentine portion 1311 can be set to the longest, resulting in the most resistance compensation for the first trace 130 in the middle of the substrate 110. The length of the first segment 131 of the first trace 130 on both sides of the substrate 110 can be set to the shortest, and the corresponding serpentine portion 1311 can be set to the shortest, resulting in the least resistance compensation.

[0060] By setting the length of the first segment 131 and the length of the serpentine portion 1311, the inconsistency in the length of the first trace 130 is compensated, thereby compensating for the load inconsistency caused by the inconsistency in the length of the first trace 130, so that the driving current output by the driving circuit 120 to each column of pixels 140 is basically the same.

[0061] In some implementations, the parasitic capacitance of the first segment 131 gradually decreases from the middle to both sides along the row direction.

[0062] The different parasitic capacitances resulting from the layout of the first traces 130 can affect their load. By adjusting the layout of the first traces 130, the parasitic capacitance of the first traces 130 can be changed, and capacitance compensation can be performed on the first traces 130 with smaller loads, so that the driving current output by the driving circuit 120 to each column of pixels 140 is basically the same.

[0063] Specifically, the parasitic capacitance of the first trace 130 can be the induced capacitance generated between the first traces 130. The parasitic capacitance of the first trace 130 is related to the layout of the first traces 130, and can be changed by setting the layout between the first traces 130. The load of the first trace 130 is related to the size of the parasitic capacitance; the larger the capacitance value, the larger the load of the first trace 130, and the smaller the capacitance value, the smaller the load of the first trace 130.

[0064] The first trace 130 in the middle of the substrate 110 is the shortest, resulting in the lowest resistance. Therefore, it requires the most capacitance compensation, and thus the parasitic capacitance of the first trace 130 in the middle of the substrate 110 can be set to the maximum. Conversely, the first traces 130 on both sides of the substrate 110 are the longest, resulting in the highest resistance. Therefore, they require the least capacitance compensation, and thus the parasitic capacitance of the first traces 130 on both sides of the substrate 110 can be set to the minimum.

[0065] In some implementations, multiple first segments 131 overlap in pairs, with the overlapping area of ​​each pair of first segments 131 gradually decreasing from the middle to both sides along the row direction.

[0066] By setting the parasitic capacitance value of the first trace 130 by overlapping the first segments 131 of every two first traces 130, capacitance compensation is performed on the first trace 130 with smaller load, so that the driving current output by the driving circuit 120 to each column of pixels 140 is basically the same.

[0067] Specifically, the layout of the first routing line 130 can be referred to Figure 3 It should be noted that, Figure 3This is a layout diagram of the first trace 130 on the left half of the substrate 110, that is, the layout diagram of the first trace 130 located from the left side of the substrate 110 to the middle of the substrate 110. The layout of the first trace 130 on the right half of the substrate 110 is symmetrical to the layout of the first trace 130 on the left half of the substrate 110.

[0068] The overlapping of the first segments 131 in multiple first traces 130 means that every two adjacent first segments 131 form a unit, and the two first segments 131 in a unit overlap with each other. Assuming there are a total of M first traces 130 on the array substrate 100, and these M first traces 130 are labeled D1 to DM from left to right, the overlapping of the first segments 131 is as follows: the first segment 131 of trace D1 overlaps with the first segment 131 of trace D2, and the first segment 131 of trace D3 overlaps with the first segment 131 of trace D4. In the case where the first segment 131 of trace Da overlaps with the second end of trace Da+1, the first segment 131 of trace Da does not overlap with the first segment 131 of trace Da-1.

[0069] The parasitic capacitance of the first trace 130 is related to the size of the overlapping area of ​​each pair of first segments 131. The smaller the overlapping area, the smaller the parasitic capacitance of the first trace 130; the larger the overlapping area, the larger the parasitic capacitance of the first trace 130.

[0070] Along the direction of travel, from the middle to both sides, the overlapping area of ​​each pair of first segments 131 gradually decreases. The parasitic capacitance generated by the overlapping of the first trace 130 in the middle of the substrate 110 is the largest, while the parasitic capacitance generated by the overlapping of the first traces 130 on both sides of the substrate 110 is the smallest.

[0071] Capacitive compensation is applied to the first trace 130 with a smaller load, ensuring that the driving current output by the driving circuit 120 to each column of pixels 140 is essentially the same. The first trace 130 in the middle of the substrate 110 requires the most capacitance compensation; therefore, its parasitic capacitance can be set to the maximum, and the overlap area of ​​the first segments 131 of the first trace 130 in the middle of the substrate 110 can be set to the maximum. Conversely, the first traces 130 on both sides of the substrate 110 require the least capacitance compensation; therefore, their parasitic capacitance can be set to the minimum, and the overlap area of ​​the first segments 131 of the first traces 130 on both sides of the substrate 110 can be set to the minimum.

[0072] In some implementations, multiple first segments 131 overlap sequentially, moving from the middle to both sides along the row direction, with the area of ​​each first segment 131 overlapping with two adjacent first segments 131 gradually decreasing.

[0073] The parasitic capacitance value of the first trace 130 is set by the overlapping area of ​​the first segment 131, and the capacitance compensation is performed on the first trace 130 with a small load, so that the driving current output by the driving circuit 120 to each column of pixels 140 is basically the same.

[0074] Specifically, the layout of the first routing line 130 can be referred to Figure 4 It should be noted that, Figure 4 This is a layout diagram of the first trace 130 on the left half of the substrate 110, that is, the layout diagram of the first trace 130 located from the left side of the substrate 110 to the middle of the substrate 110. The layout of the first trace 130 on the right half of the substrate 110 is symmetrical to the layout of the first trace 130 on the left half of the substrate 110.

[0075] The overlapping of the first segments 131 in multiple first traces 130 refers to the sequential overlap of every two adjacent first segments 131. Assuming there are M first traces 130 on the array substrate 100, labeled D1 to DM from left to right, the first segments 131 overlap in the following ways: the first segment 131 of trace D1 overlaps with the first segment 131 of trace D2, the first segment 131 of trace D2 overlaps with the first segment 131 of trace D3, and the first segment 131 of trace D3 overlaps with the first segment 131 of trace D4. In the case where the first segment 131 of trace Da overlaps with the second end of trace Da+1, the first segment 131 of trace Da also overlaps with the first segment 131 of trace Da-1.

[0076] The parasitic capacitance of the first trace 130 is related to the size of the overlapping area of ​​the first segments 131. The smaller the overlapping area, the smaller the parasitic capacitance of the first trace 130; the larger the overlapping area, the larger the parasitic capacitance of the first trace 130.

[0077] Along the direction of travel, from the middle to both sides, the overlapping area of ​​the first segments 131 gradually decreases. The parasitic capacitance generated by the overlapping of the first trace 130 in the middle of the substrate 110 is the largest, while the parasitic capacitance generated by the overlapping of the first traces 130 on both sides of the substrate 110 is the smallest.

[0078] Capacitive compensation is applied to the first trace 130 with a smaller load, ensuring that the driving current output by the driving circuit 120 to each column of pixels 140 is essentially the same. The first trace 130 in the middle of the substrate 110 requires the most capacitance compensation; therefore, its parasitic capacitance can be set to the maximum, and the overlap area of ​​the first segments 131 of the first trace 130 in the middle of the substrate 110 can be set to the maximum. Conversely, the first traces 130 on both sides of the substrate 110 require the least capacitance compensation; therefore, their parasitic capacitance can be set to the minimum, and the overlap area of ​​the first segments 131 of the first traces 130 on both sides of the substrate 110 can be set to the minimum.

[0079] In some embodiments, the display panel further includes a second substrate and a plurality of second traces. The second substrate and the substrate 110 are disposed opposite to each other, and the plurality of first traces 130 are disposed on one side near the second substrate. The plurality of second traces are disposed on the second substrate on the side near the substrate 110, running from the middle to both sides in the row direction, and the area of ​​the overlapping portion of the second traces on the substrate 110 and the first traces 130 gradually decreases.

[0080] By introducing a second substrate and a second trace, the parasitic capacitance value of the first trace 130 can also be set by setting the layout between the second trace and the first trace 130. Capacitor compensation is performed on the first trace 130 with a smaller load, so that the driving current output by the driving circuit 120 to each column of pixels 140 is basically the same.

[0081] Specifically, the layout of the first routing 130 and the second routing can be referred to Figure 5 as well as Figure 6 It should be noted that, Figure 5 as well as Figure 6 This is a layout diagram of the first trace 130 on the left half of the substrate 110, that is, the layout diagram of the first trace 130 located from the left side of the substrate 110 to the middle of the substrate 110. The layout of the first trace 130 on the right half of the substrate 110 is symmetrical to the layout of the first trace 130 on the left half of the substrate 110.

[0082] The first trace 130 is disposed on the side closer to the second substrate, and the second trace is disposed on the side closer to the substrate 110. The first trace 130 and the second trace are disposed opposite to each other. The overlap between the second trace and the first trace 130 also affects the parasitic capacitance value of the first trace 130. The smaller the overlap area between the second trace and the first trace 130, the smaller the parasitic capacitance value of the first trace 130; the larger the overlap area between the second trace and the first trace 130, the larger the parasitic capacitance value of the first trace 130.

[0083] Along the direction of travel from the middle to both sides, the area of ​​the second trace overlapping the first trace 130 with the orthographic projection of the second trace on the substrate 110 gradually decreases, that is, the overlap area between the second trace and the first trace 130 gradually decreases. The parasitic capacitance generated by the first trace 130 in the middle of the substrate 110 due to the overlap is the largest, while the parasitic capacitance generated by the first traces 130 on both sides of the substrate 110 due to the overlap is the smallest.

[0084] Capacitor compensation is applied to the first trace 130 with a smaller load, ensuring that the driving current output by the driving circuit 120 to each column of pixels 140 is essentially the same. The first trace 130 in the middle of the substrate 110 requires the most capacitor compensation; therefore, its parasitic capacitance and the overlap area between the first trace 130 and the second trace in the middle of the substrate 110 can be maximized. Conversely, the first traces 130 on both sides of the substrate 110 require the least capacitor compensation; therefore, their parasitic capacitance and the overlap area between the first traces 130 and the second trace on both sides of the substrate 110 can be minimized.

[0085] In some embodiments, the portion of the second trace that overlaps with the first trace 130 in the orthographic projection of the substrate 110 is on the first segment 131.

[0086] The overlapping portion between the second trace and the first trace 130 is on the first segment 131. Capacitor compensation can be performed on the first segment 131 of the first trace 130. Capacitor compensation is performed on the first trace 130 with a smaller load, so that the driving current output by the driving circuit 120 to each column of pixels 140 is basically the same.

[0087] Specifically, the layout of the first routing line 130 can be referred to Figure 5 . Figure 5 The shaded area is the orthographic projection of the second substrate onto the substrate 110, and the orthographic projection of the second substrate onto the substrate 110 covers upward from the first segment 131.

[0088] The portion of the second trace projected onto the substrate 110 that overlaps with the first trace 130 is located on the first segment 131. Along the running direction from the middle to both sides, the area of ​​the overlapping portion of the second trace projected onto the substrate 110 and the first segment 131 gradually decreases, that is, the overlap area between the second trace and the first trace 130 gradually decreases. The parasitic capacitance generated by the overlap of the first trace 130 in the middle of the substrate 110 is the largest, while the parasitic capacitance generated by the overlap of the first traces 130 on both sides of the substrate 110 is the smallest.

[0089] In some embodiments, the portion of the second trace's orthographic projection on the substrate 110 that overlaps with the first trace 130 lies on the second segment 132 and the first segment 131. Along the running direction from the center to both sides, the overlapping area of ​​the second trace's orthographic projection on the substrate 110 and the second segment 132 gradually increases, while the overlapping area of ​​the second trace's orthographic projection on the substrate 110 and the first segment 131 gradually decreases.

[0090] The overlapping portion between the second trace and the first trace 130 is on the first segment 131 and the second segment 132. Capacitor compensation can be performed on the first segment 131 and the second segment 132 of the first trace 130 so that the driving current output by the driving circuit 120 to each column of pixels 140 is basically the same.

[0091] Specifically, the layout of the first routing line 130 can be referred to Figure 6 . Figure 6 The shaded area is the orthographic projection of the second substrate onto the substrate 110, and the orthographic projection of the second substrate onto the substrate 110 covers downward from the second segment 132.

[0092] Along the direction of travel from the center to both sides, the overlapping area of ​​the second trace on the first trace 130 gradually decreases, that is, along the direction of travel from the center to both sides, the compensation capacitance of the second trace gradually decreases. The compensation capacitance on the first trace 130 in the middle of the substrate 110 is the largest, and the compensation capacitance on the first traces 130 on both sides of the substrate 110 is the smallest.

[0093] The first segment 131 may include a serpentine portion 1311. Within the same area, the length of the first segment 131 of the first trace 130 is greater than the length of the second segment 132. Therefore, within the same overlap area, the capacitance compensated by the second trace in the first segment 131 is greater than the capacitance compensated by the first trace 130 in the second segment 132. Along the row direction from the middle to both sides, the overlap area of ​​the second trace and the second segment 132 gradually increases, while the overlap area of ​​the second trace and the first segment 131 gradually decreases. Therefore, the capacitance compensated on the first trace 130 in the middle of the substrate 110 further increases, while the capacitance compensated on the first traces 130 on both sides of the substrate 110 further decreases. This is beneficial for capacitance compensation of the first trace 130 with a smaller load, ensuring that the driving current output by the driving circuit 120 to each column of pixels 140 is essentially the same.

[0094] Reference Figure 7 The present invention provides a display panel 1000, which includes the array substrate 100 of any of the above embodiments.

[0095] The implementation of the array substrate 100 can refer to the above implementation. The beneficial effects of the display panel 1000 include all the beneficial effects of the array substrate 100, which will not be elaborated here.

[0096] Specifically, the display panel 1000 may include an array substrate 100 and a color filter substrate. For example, a thin-film transistor liquid crystal display (TFT-LCD) is formed by assembling an array substrate 100 and a color filter substrate (color filter) into a cell and injecting liquid crystal therein. Columnar spacers are typically provided between the array substrate 100 and the color filter substrate to maintain cell thickness.

[0097] Reference Figure 7 The present invention provides a display device 10000, which includes a display panel 1000 of any of the above embodiments.

[0098] Specifically, the display device 10000 can be any device that displays text or images, whether moving (e.g., video) or stationary (e.g., still images). More specifically, the display device 10000 can be one of a variety of electronic devices, and embodiments can be implemented in or associated with a variety of electronic devices. These electronic devices include, but are not limited to, mobile phones, wireless devices, personal data assistants (PS1), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, camera view displays (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc. The embodiments of this disclosure do not impose any particular limitation on the specific form of the aforementioned display device 10000.

[0099] The implementation of the display panel 1000 can refer to the above implementation. The beneficial effects of the display device 10000 include all the beneficial effects of the display panel 1000, which will not be elaborated here.

[0100] In the description of this specification, the terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0101] Furthermore, the term "connection" should be interpreted broadly. For example, it can include fixed connections, detachable connections, or integral connections; it can include direct connections or indirect connections through an intermediate medium; and it can also include internal communication between two elements. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0102] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0103] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which embodiments of the invention pertain.

[0104] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. An array substrate, characterized by, include: Substrate; Multiple columns of pixels, wherein the multiple columns of pixels are disposed on the substrate; The driving circuit is centrally disposed on the substrate. Multiple first traces are disposed on the substrate. The multiple first traces are respectively connected to a corresponding column of pixels and the driving circuit. The driving circuit drives the multiple columns of pixels through the multiple first traces. The loads of the multiple first traces are basically the same. Each first trace includes a first segment connected to the driving circuit and a second segment connected to the corresponding column of pixels. The plurality of first segments are arranged substantially along the column direction of the array substrate, and the second segment extends substantially along the row direction of the array substrate. Along the row direction from the middle to both sides, the length of the first segment gradually decreases to compensate for the difference in length of the first trace caused by the gradual increase in length of the corresponding second segment. Along the row direction from the middle to both sides, the parasitic capacitance of the first segment gradually decreases; The plurality of first segments overlap in pairs, and along the row direction from the middle to both sides, the area of ​​each pair of first segments overlapping gradually decreases; The first segment includes a serpentine portion that gradually shortens in length from the middle to both sides along the row direction.

2. The array substrate of claim 1, wherein, The plurality of first segments overlap sequentially, and along the row direction from the middle to both sides, the area of ​​overlap between each first segment and the two adjacent first segments gradually decreases.

3. The array substrate of claim 1, wherein, The array substrate further includes a second substrate, which is disposed opposite to the substrate, and the plurality of first traces are disposed on the side close to the second substrate; Multiple second traces are disposed on the second substrate on the side close to the substrate. Along the row direction from the middle to both sides, the area of ​​the second trace overlapping with the first trace in the orthographic projection on the substrate gradually decreases.

4. The array substrate of claim 3, wherein, The portion of the second trace that overlaps with the first trace in the orthographic projection of the substrate is on the first segment.

5. The array substrate of claim 3, wherein, The portion of the second trace that overlaps with the first trace in the orthographic projection of the substrate is on the first segment and the second segment; Along the row direction from the middle to both sides, the overlapping area of ​​the second trace's orthographic projection on the substrate and the second segment gradually increases, while the overlapping area of ​​the second trace's orthographic projection on the substrate and the first segment gradually decreases.

6. A display panel, characterized by, The display panel includes the array substrate according to any one of claims 1-5.

7. A display device, characterized by comprising: The display device includes the display panel as described in claim 6.

Images