Semiconductor devices and memories

Abstract

This disclosure relates to the field of semiconductor technology, and proposes a semiconductor device and a memory. The semiconductor device includes non-overlapping pull-up circuit integration areas, pull-down circuit integration areas, and compensation circuit integration areas. The semiconductor device also includes an output circuit, which includes a pull-up circuit, a pull-down circuit, and a compensation circuit. The pull-up circuit is connected to the signal output line and is located in the pull-up circuit integration area; the pull-down circuit is connected to the signal output line and is located in the pull-down circuit integration area; the compensation circuit is used to enhance the driving capability of the output signal on the signal output line and is located in the compensation circuit integration area. This semiconductor device can reduce the parasitic capacitance between the control line connected to the compensation circuit and other structures, thereby facilitating the optimization of the timing of the signal on the control line connected to the compensation circuit.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor device and a memory. Background Technology

[0002] In related technologies, the output circuit in a memory includes pull-up circuits, pull-down circuits, and compensation circuits to improve the driving capability of the output signal. The compensation circuit is generally integrated within the same integration area as the pull-up and pull-down circuits.

[0003] However, the inventors of this disclosure have discovered that the control line connected to the compensation circuit will form a large parasitic capacitance with the pull-up or pull-down circuit, which is not conducive to the optimization of the signal on the control line connected to the compensation circuit.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] According to one aspect of this disclosure, a semiconductor device is provided, comprising non-overlapping pull-up circuit integration regions, pull-down circuit integration regions, and compensation circuit integration regions. The semiconductor device further includes an output circuit comprising a pull-up circuit, a pull-down circuit, and a compensation circuit. The pull-up circuit is connected to a signal output line and is located in the pull-up circuit integration region; the pull-down circuit is connected to the signal output line and is located in the pull-down circuit integration region; the compensation circuit is used to enhance the driving capability of the output signal on the signal output line and is located in the compensation circuit integration region.

[0006] In one exemplary embodiment of this disclosure, the signal output line extends along a first direction and is used to transmit a signal along the first direction; at least a portion of the compensation circuit integration area is located on one side of the pull-up circuit integration area in the first direction, and at least a portion of the compensation circuit integration area is located on one side of the pull-down circuit integration area in the first direction.

[0007] In one exemplary embodiment of this disclosure, the compensation circuit includes at least one first pull-up compensation branch, which is used to pull up the output signal; the compensation circuit integration area includes a first integration area, and the first pull-up compensation branch is located in the first integration area; the first integration area is located on one side of the pull-up circuit integration area in the first direction.

[0008] In one exemplary embodiment of this disclosure, the compensation circuit includes at least one first pull-down compensation branch, which is used to pull down the output signal; the compensation circuit integration area includes a second integration area, and the first pull-down compensation branch is located in the second integration area; the second integration area is located on one side of the pull-down circuit integration area in the first direction.

[0009] In an exemplary embodiment of this disclosure, the first pull-up compensation branch is connected to the signal output line and the first control signal line. The first pull-up compensation branch is used to pull up the output signal in response to the enable signal of the first control signal line. The pull-up circuit includes multiple pull-up branches, each pull-up branch including a first transistor. The first terminal of the first transistor is connected to the signal output line, the second terminal of the first transistor is connected to a first high-level power supply terminal, and the gate of the first transistor is connected to the pull-up control signal line.

[0010] In one exemplary embodiment of this disclosure, the first pull-up compensation branch includes a second transistor, the first terminal of the second transistor is connected to the signal output line, the second terminal of the second transistor is used to receive a high-level power supply voltage, and the gate of the second transistor is connected to the first control signal line; wherein, the size of the first transistor is smaller than the size of the second transistor.

[0011] In one exemplary embodiment of this disclosure, the number of pull-up branches in the pull-up circuit is greater than the number of the first pull-up compensation branches in the compensation circuit.

[0012] In one exemplary embodiment of this disclosure, the first pull-down compensation branch is connected to the signal output line and the second control signal line. The first pull-down compensation branch is used to pull down the output signal in response to the enable signal of the second control signal line. The pull-down circuit includes multiple pull-down branches, each pull-down branch including a third transistor. The first terminal of the third transistor is connected to the signal output line, the second terminal of the third transistor is connected to a first low-level power supply terminal, and the gate of the third transistor is connected to the pull-down control signal line.

[0013] In one exemplary embodiment of this disclosure, the first pull-down compensation branch includes a fourth transistor, the first terminal of the fourth transistor is connected to the signal output line, the second terminal of the fourth transistor is used to receive a low-level power supply voltage, and the gate of the fourth transistor is connected to the second control signal line; wherein, the size of the third transistor is smaller than the size of the fourth transistor.

[0014] In one exemplary embodiment of this disclosure, the number of pull-down branches in the pull-down circuit is greater than the number of the first pull-down compensation branches in the compensation circuit.

[0015] In an exemplary embodiment of this disclosure, the compensation circuit includes at least one first pull-down compensation branch, and the pull-down circuit includes multiple pull-down branches; the first pull-down compensation branch is connected to the signal output line and the second control signal line, and is used to pull down the output signal in response to the enable signal of the second control signal line; the pull-down branch is connected to the signal output line, a first low-level power supply terminal, and a pull-down control signal line, and is used to transmit the signal of the first low-level power supply terminal to the signal output line in response to the signal of the pull-down control signal line; multiple pull-up branches are distributed along the first direction, multiple pull-down branches are distributed along the first direction, and the region where the signal output line is located is located between the integrated region of the pull-up circuit and the integrated region of the pull-down circuit; the first control signal line, the pull-up control signal line, the second control signal line, and the pull-down control signal line extend along the first direction, the region where the first control signal line is located is located between the region where the pull-up control signal line is located and the region where the signal output line is located, and the region where the second control signal line is located is located between the region where the pull-down control signal line is located and the region where the signal output line is located.

[0016] In one exemplary embodiment of this disclosure, the signal output line extends along a first direction and is used to transmit a signal along the first direction; at least a portion of the compensation circuit integration area is located on one side of the pull-up circuit integration area in a second direction, and at least a portion of the compensation circuit integration area is located on one side of the pull-down circuit integration area in the second direction, wherein the second direction is opposite to the first direction.

[0017] In one exemplary embodiment of this disclosure, the compensation circuit includes at least one second pull-up compensation branch; the compensation circuit integration area includes a third integration area, and the second pull-up compensation branch is located in the third integration area; the third integration area is located on one side of the pull-up circuit integration area in the second direction.

[0018] In one exemplary embodiment of this disclosure, the compensation circuit includes at least one second pull-down compensation branch; the compensation circuit integration area includes a fourth integration area, and the second pull-down compensation branch is located in the fourth integration area; the fourth integration area is located on one side of the pull-down circuit integration area in the second direction.

[0019] In one exemplary embodiment of this disclosure, the pull-up circuit includes multiple pull-up branches, each pull-up branch including a first transistor, the first terminal of the first transistor being connected to the signal output line, the second terminal of the first transistor being connected to a first high-level power supply terminal, and the gate of the first transistor being connected to a pull-up control signal line; a second pull-up compensation branch is connected to the pull-up control signal line, and the second pull-up compensation branch is used to synchronously compensate the signal on the pull-up control signal line.

[0020] In one exemplary embodiment of this disclosure, the pull-down circuit includes multiple pull-down branches, each pull-down branch including a third transistor. The first terminal of the third transistor is connected to the signal output line, the second terminal of the third transistor is connected to a first low-level power supply terminal, and the gate of the third transistor is connected to a pull-down control signal line. A second pull-down compensation branch is connected to the pull-down control signal line and is used to synchronously compensate the signal on the pull-down control signal line.

[0021] In one exemplary embodiment of this disclosure, the second pull-up compensation branch is connected to the signal output line and the third control signal line, and is used to pull up the output signal in response to the enable signal of the third control signal line.

[0022] In one exemplary embodiment of this disclosure, the second pull-down compensation branch is connected to the signal output line and the fourth control signal line, and is used to pull down the output signal in response to the enable signal of the fourth control signal line.

[0023] According to one aspect of this disclosure, a memory is provided, the memory comprising the semiconductor device described above.

[0024] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0025] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0026] Figure 1 This is a schematic diagram of the structure of an output circuit in this exemplary embodiment;

[0027] Figure 2 for Figure 1 The equivalent circuit diagram of the output circuit section shown is shown.

[0028] Figure 3 for Figure 1 The output circuit layout shown is shown.

[0029] Figure 4 This is a schematic diagram of the structure of an exemplary embodiment of the semiconductor device disclosed herein;

[0030] Figure 5 for Figure 4 The diagram shows the structural layout of the semiconductor device.

[0031] Figure 6 for Figure 4 The equivalent circuit diagram of the output circuit section of the semiconductor device shown.

[0032] Figure 7 This is a structural layout of another exemplary embodiment of the semiconductor device disclosed herein;

[0033] Figure 8 for Figure 7 The equivalent circuit diagram of the output circuit section of the semiconductor device shown is shown. Detailed Implementation

[0034] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0035] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the icon's arrangement is flipped so that it is upside down, the component described as "up" will become the component described as "down." Other relative terms such as "high," "low," "top," "bottom," "left," and "right" also have similar meanings. When a structure is "up" of another structure, it may mean that the structure is integrally located on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0036] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0037] like Figure 1 , 2 As shown in Figure 3, Figure 1 This is a schematic diagram of the structure of an output circuit in this exemplary embodiment. Figure 2 for Figure 1 The equivalent circuit diagram of the output circuit section shown is shown. Figure 3 for Figure 1The output circuit layout shown is illustrated. This output circuit includes a pull-up electrode, a pull-down circuit, a switching circuit 3, a pull-up compensation circuit, and a pull-down compensation circuit. Specifically, the pull-up circuit includes multiple pull-up branches 11, the pull-down circuit includes multiple pull-down branches 21, the switching circuit 3 includes multiple switching branches 31, the pull-up compensation circuit includes multiple pull-up compensation branches 411, and the pull-down compensation circuit includes multiple pull-down compensation branches 421. Figure 1 , 2 As shown in Figure 3, the pull-up branch 11 may include a first transistor T1, the pull-down branch 21 may include a third transistor T3, the pull-up compensation branch 411 may include a second transistor T2, the pull-down compensation circuit may include a fourth transistor T4, and the switching branch 31 may include a fifth transistor T5. Figure 2 As shown, a pull-up branch 11, a pull-down branch 21, a switch branch 31, a pull-up compensation branch 411, and a pull-down compensation branch 421 can form an output unit. In the same output unit, the first terminal of the first transistor T1 is connected to the signal output line LDQ, the second terminal of the first transistor T1 is connected to the second terminal of the fifth transistor T5, and the gate of the first transistor T1 is connected to the pull-up control signal line MPU; the first terminal of the fifth transistor T5 is connected to the first high-level power supply terminal VDD1; the first terminal of the third transistor T3 is connected to the signal output line LDQ, the second terminal of the third transistor T3 is connected to the first low-level power supply terminal VSS1, and the gate of the third transistor T3 is connected to the pull-down control signal line MPD; the first terminal of the second transistor T2 is connected to the signal output line LDQ, the second terminal of the second transistor T2 is connected to the second high-level power supply terminal VDD2, and the gate of the second transistor T2 is connected to the pull-up compensation control line BPU; the first terminal of the fourth transistor T4 is connected to the signal output line LDQ, the second terminal of the fourth transistor T4 is connected to the second low-level power supply terminal VSS2, and the gate of the fourth transistor T4 is connected to the pull-down compensation control line BPD.

[0038] In this exemplary embodiment, when the switch branch 31 is turned on, the pull-up control signal line MPU and the pull-down control signal line MPD are selected to receive an effective input level, thereby selectively turning on the transistor connected to it. When the pull-up control signal line MPU receives an effective input level to turn on the pull-up branch 11, the pull-down branch 21 is turned off, and the signal output line LDQ outputs a high level; when the pull-down control signal line MPD receives an effective input level to turn on the pull-down branch 21, the pull-up branch 11 is turned off, and the signal output line LDQ outputs a low level, thus the output circuit can controllably output a high or low level.

[0039] Furthermore, the pull-up compensation control line BPU can output an effective level when the pull-up control signal line MPU inputs an effective level to activate the pull-up compensation branch 411. The pull-up compensation branch 411 transmits the high level of the second high-level power supply terminal VDD2 to the signal output line LDQ, thereby enhancing the pull-up drive capability of the input signal on the signal output line LDQ. The pull-down compensation control line BPD can output an effective level when the pull-down control signal line MPD outputs an effective level to activate the pull-down compensation branch 421. The pull-down compensation branch 421 transmits the low level of the second low-level power supply terminal VSS2 to the signal output line LDQ, thereby enhancing the pull-down drive capability of the output signal on the signal output line LDQ. The stronger the pull-up drive capability of the output signal, the steeper the rising edge of the output signal; the stronger the pull-down drive capability of the output signal, the steeper the falling edge of the output signal. Correspondingly, the stronger the pull-up and pull-down drive capabilities of the output signal, the higher the maximum frequency that the output signal can reach.

[0040] In this embodiment, the first high-level power supply terminal VDD1 and the second high-level power supply terminal VDD2 can share the same high-level power supply terminal, and the first low-level power supply terminal VSS1 and the second low-level power supply terminal VSS2 can share the same low-level power supply terminal. The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 can be either N-type or P-type transistors. The effective level can be understood as the conduction level of the target circuit. For example, when the target circuit is an N-type transistor, the effective level is high; when the target circuit is a P-type transistor, the effective level is low. In one embodiment, T3 and T4 are PMOS transistors, and T1, T2, and T5 are NMOS transistors.

[0041] like Figure 3As shown, in the same output circuit, the number of pull-up compensation branches 411 can be the same as the number of pull-up branches 11, and the pull-up compensation branches 411 can be distributed in the pull-up branch integration area 01 where the pull-up branches 11 are located; the number of pull-down compensation branches 421 can be the same as the number of pull-down branches 21, and the pull-down compensation branches 421 can be distributed in the pull-down branch integration area 02 where the pull-down branches 21 are located. In the same output circuit, the number of pull-up branches 11 and pull-down branches 21 can be the same, for example, the number of pull-up branches 11 and pull-down branches 21 can both be 6. However, since the pull-up compensation branches 411 are distributed in the pull-up branch integration area 01 where the pull-up branches 11 are located, the pull-up compensation control line BPU has a very long winding. The long pull-up compensation control line BPU will generate a large parasitic capacitance with other structures, which is not conducive to the optimization of signal timing on the pull-up compensation control line BPU. Similarly, since the pull-down compensation branch 421 is distributed in the pull-down branch integration area 02 where the pull-down branch 21 is located, the pull-down compensation control line BPD has a very long winding. The long pull-down compensation control line BPD will generate a large parasitic capacitance with other structures, which is not conducive to the optimization of signal timing on the pull-down compensation control line BPD.

[0042] Based on this, this exemplary embodiment provides a semiconductor device, such as... Figure 4 , 5 As shown, Figure 4 This is a schematic diagram of the structure of an exemplary embodiment of the semiconductor device disclosed herein. Figure 5 for Figure 4 The diagram shows the structural layout of a semiconductor device. The semiconductor device includes non-overlapping pull-up circuit integration areas 61, 62, and 63, and also includes an output circuit, which may include a pull-up circuit 1, a pull-down circuit 2, and a compensation circuit 4. Pull-up circuit 1 is connected to the signal output line LDQ and is located in the pull-up circuit integration area 61; pull-down circuit 2 is connected to the signal output line LDQ and is located in the pull-down circuit integration area 62; compensation circuit 4 is used to enhance the driving capability of the output signal on the signal output line LDQ and is located in the compensation circuit integration area 63.

[0043] In this exemplary embodiment, the semiconductor device centrally houses the compensation circuit 4 in the compensation circuit integration area 63, thereby reducing the capacity of the parasitic capacitance formed by the compensation control line connected to the compensation circuit 4 and other structures, which is beneficial for optimizing the signal timing on the compensation control line connected to the compensation circuit 4.

[0044] In this exemplary embodiment, as Figure 5As shown, the signal output line LDQ extends along the first direction X and is used to transmit signals along the first direction X; the compensation circuit integration area 63 may be located on the side of the pull-up circuit integration area 61 in the first direction X, and the compensation circuit integration area 63 may be located on the side of the pull-down circuit integration area 62 in the first direction X. Figure 5 As shown, the semiconductor device may further include an output pad integration area 64, which may be located on the side of the compensation circuit integration area 63 away from the pull-up circuit integration area 61. An output pad DQpad may be provided in the output pad integration area 64, which may be connected to the signal output line LDQ. The output pad DQpad is used to output an output signal to the outside of the semiconductor device.

[0045] In this exemplary embodiment, as Figure 5 As shown, the compensation circuit 4 may include at least one first pull-up compensation branch 411, which is used to pull up the output signal; the compensation circuit integration area 63 may include a first integration area 631, and the first pull-up compensation branch 411 may be located in the first integration area 631; the first integration area 631 may be located on one side of the pull-up circuit integration area 61 in the first direction X.

[0046] In this exemplary embodiment, as Figure 5 As shown, the compensation circuit 4 may further include at least one first pull-down compensation branch 421, which is used to pull down the output signal; the compensation circuit integration area 63 may further include a second integration area 632, and the first pull-down compensation branch 421 may be located in the second integration area 632; the second integration area 632 is located on one side of the pull-down circuit integration area 62 in the first direction X.

[0047] In this exemplary embodiment, as Figure 6 As shown, Figure 4 The diagram shows the equivalent circuit structure of the output circuit section in the semiconductor device. The first pull-up compensation branch 411 is connected to the signal output line LDQ and the first control signal line BPU1. The first pull-up compensation branch 411 is used to pull up the output signal in response to the enable signal of the first control signal line BPU1. The pull-up circuit 1 may include multiple pull-up branches 11. Each pull-up branch 11 includes a first transistor T1. The first terminal of the first transistor T1 is connected to the signal output line LDQ, the second terminal is connected to the first high-level power supply terminal VDD1, and the gate is connected to the pull-up control signal line MPU.

[0048] In this exemplary embodiment, as Figure 6As shown, the first pull-up compensation branch 411 may include a second transistor T2. The first terminal of the second transistor T2 is connected to the signal output line LDQ, the second terminal can be connected to the second high-level power supply terminal VDD2, and the gate can be connected to the first control signal line BPU1. The first control signal line BPU1 can output an effective level when the pull-up control signal line MPU outputs an effective level, so as to turn on the first pull-up compensation branch 411. The turned-on first pull-up compensation branch 411 transmits the high-level signal of the second high-level power supply terminal VDD2 to the signal output line LDQ to perform pull-up compensation on the signal output line LDQ. The first control signal line BPU1 can output an effective level at the beginning of the pull-up control signal line MPU outputting an effective level. For example, when the first transistor T1 is a P-type transistor, the first control signal line BPU1 can output an effective level at the falling edge of the signal on the pull-up control signal line MPU to achieve pull-up compensation on the signal output line LDQ.

[0049] The first control signal line BPU1 is connected to the first pull-up compensation branch 411 through a contact hole. This contact hole has a small distance from other conductive structures or other contact holes in the film extension direction, making it easy for the via structure connecting the first control signal line BPU1 to form a large parasitic capacitance with other structures. In this exemplary embodiment, in the same output circuit, the number of pull-up branches 11 in the pull-up circuit 1 can be greater than the number of first pull-up compensation branches 411 in the compensation circuit 4. For example, in this exemplary embodiment, the number of pull-up branches 11 in the pull-up circuit 1 can be 6, and the number of first pull-up compensation branches 411 in the compensation circuit 4 can be 2. By reducing the number of first pull-up compensation branches 411, this exemplary embodiment can reduce the number of vias between the first control signal line BPU1 and the first pull-up compensation branch 411, thereby effectively reducing the parasitic capacitance of the first control signal line BPU1.

[0050] The arrangement direction of the first pull-up compensation branch 411 can be perpendicular to or parallel to the arrangement direction of the pull-up branch 11 in the pull-up circuit. In other words, the arrangement direction of the second transistor T2 can be perpendicular to or parallel to the arrangement direction of the first transistor T1. It should be noted that the limitation on the arrangement direction does not restrict the gate length direction. For example, when the arrangement direction of the second transistor T2 is perpendicular to the arrangement direction of the first transistor T1, the gate length direction of the second transistor T2 can be parallel to or perpendicular to the gate length direction of the first transistor T1.

[0051] This exemplary embodiment reduces the number of first pull-up compensation branches 411. To ensure the pull-up capability of the first pull-up compensation branches 411 for the output signal, this exemplary embodiment can correspondingly increase the size of the second transistor T2, thereby enabling a single first pull-up compensation branch 411 to have a stronger driving capability. Since the compensation circuit integration area 63 is located on one side of the whole formed by the pull-up circuit integration area 61 and the pull-down circuit integration area 62, increasing the size of the second transistor T2 has a small impact on the first transistor T1 in the pull-up circuit 1, that is, it will not excessively encroach on the layout area of ​​a certain first transistor T1. This makes it possible to increase the size of the second transistor T2 and reduce the number of first pull-up compensation branches 411. In this exemplary embodiment, the size of the second transistor T2 can be larger than the size of the first transistor T1.

[0052] In this exemplary embodiment, as Figure 4 , 5 As shown in Figure 6, the first pull-down compensation branch 421 can be connected to the signal output line LDQ and the second control signal line BPD2. The first pull-down compensation branch 421 can be used to pull down the output signal in response to the enable signal of the second control signal line BPD2. The pull-down circuit 2 can include multiple pull-down branches 21. Each pull-down branch 21 can include a third transistor T3. The first terminal of the third transistor T3 is connected to the signal output line LDQ, the second terminal is connected to the first low-level power supply terminal VSS1, and the gate is connected to the pull-down control signal line MPD.

[0053] In this exemplary embodiment, as Figure 4 , 5 As shown in Figure 6, the first pull-down compensation branch 421 may include a fourth transistor T4. The first terminal of the fourth transistor T4 is connected to the signal output line LDQ, and the second terminal is connected to the second low-level power supply terminal VSS2. The second control signal line BPD2 can output a valid level at the start of the pull-down control signal line MPD outputting a valid level, so as to turn on the first pull-down compensation branch 421. The turned-on first pull-down compensation branch 421 can transmit the low-level signal of the second low-level power supply terminal VSS2 to the signal output line LDQ, so as to pull down the signal on the signal output line LDQ.

[0054] In this exemplary embodiment, the second control signal line BPD2 is connected to the first pull-down compensation branch 421 through a contact hole. The contact hole to which the second control signal line BPD2 is connected has a small distance from other conductive structures or other contact holes in the film extension direction, making it easy for the via structure to form a large parasitic capacitance with other structures. In this exemplary embodiment, in the same output circuit, the number of pull-down branches 21 in the pull-down circuit 2 can be greater than the number of first pull-down compensation branches 421 in the compensation circuit 4. For example, in this exemplary embodiment, the number of pull-down branches 21 in the pull-down circuit 2 can be 6, and the number of first pull-down compensation branches 421 in the compensation circuit 4 can be 2. By reducing the number of first pull-down compensation branches 421, this exemplary embodiment can reduce the number of vias between the second control signal line BPD2 and the first pull-down compensation branch 421, thereby effectively reducing the parasitic capacitance of the second control signal line BPD2.

[0055] This exemplary embodiment reduces the number of first pull-down compensation branches 421. To ensure the pull-down capability of the first pull-down compensation branches 421 for the output signal, this exemplary embodiment can correspondingly increase the size of the fourth transistor T4, thereby enabling a single first pull-down compensation branch 421 to have stronger driving capability. For example, in this exemplary embodiment, the size of the fourth transistor T4 can be larger than the size of the third transistor T3. The feasibility principle for increasing the size of the fourth transistor T4 can be referred to the second transistor T2.

[0056] like Figure 4 , 6 As shown, the output circuit may also include a switching circuit 3, which may include multiple switching branches 31. Each switching branch 31 may include a fifth transistor T5. The first terminal of the fifth transistor T5 may be connected to the first high-level power supply terminal VDD1, and the second terminal may be connected to the second terminal of the first transistor T1.

[0057] It should be noted that, in this exemplary embodiment, the first high-level power supply terminal VDD1 and the second high-level power supply terminal VDD2 can share the same high-level power supply terminal, and the first low-level power supply terminal VSS1 and the second low-level power supply terminal VSS2 can share the same low-level power supply terminal.

[0058] In this exemplary embodiment, as Figure 5As shown, multiple pull-up branches 11 can be distributed along the first direction X, and multiple pull-down branches 21 can be distributed along the first direction X. The region where the signal output line LDQ is located can be between the pull-up circuit integration area 61 and the pull-down circuit integration area 62. The first control signal line BPU1, the pull-up control signal line MPU, the second control signal line BPD2, and the pull-down control signal line MPD can extend along the first direction X. The region where the first control signal line BPU1 is located can be between the region where the pull-up control signal line MPU is located and the region where the signal output line LDQ is located. The region where the second control signal line BPD2 is located can be between the region where the pull-down control signal line MPD is located and the region where the signal output line LDQ is located. The first control signal line BPU1 can be used to shield noise interference between the pull-up control signal line MPU and the signal output line LDQ. The second control signal line BPD2 can be used to shield noise interference between the pull-down control signal line MPD and the signal output line LDQ.

[0059] It should be understood that in other exemplary embodiments, Figure 5 The integrated area of ​​the first pull-up compensation branch 411 can also be located on one side of the pull-up circuit integrated area 61 in the second direction, which is opposite to the first direction X. This arrangement can increase the distance between the first control signal line BPU1 and the output pad Dqpad, thereby reducing the parasitic capacitance between the first control signal line BPU1 and the output pad Dqpad. Similarly, the integrated area of ​​the first pull-down compensation branch 421 can also be located on one side of the pull-down circuit integrated area 62 in the second direction. Figure 7 The diagram shown illustrates a structural layout of another exemplary embodiment of the semiconductor device disclosed herein. In this exemplary embodiment, the signal output line LDQ extends along a first direction X and is used to transmit a signal along the first direction X. The compensation circuit integration region 63 may be located on one side of the pull-up circuit integration region 61 in a second direction, and the compensation circuit integration region 63 may be located on one side of the pull-down circuit integration region 62 in the second direction, the second direction being opposite to the first direction X.

[0060] In this exemplary embodiment, the compensation circuit 4 may include at least one second pull-up compensation branch 412; the compensation circuit integration area 63 may also include a third integration area 633, and the second pull-up compensation branch 412 may be located in the third integration area 633; ​​the third integration area 633 may be located on one side of the pull-up circuit integration area 61 in the second direction.

[0061] In this exemplary embodiment, the compensation circuit 4 may further include at least one second pull-down compensation branch 422; the compensation circuit integration area 63 may further include a fourth integration area 634, and the second pull-down compensation branch 422 may be located in the fourth integration area 634; the fourth integration area 634 may be located on one side of the pull-down circuit integration area 62 in the second direction.

[0062] It should be noted that, although in Figure 7 In the structural layout shown, the arrangement direction of the second pull-up compensation branch 412 and the second pull-down compensation branch 422 is parallel to the arrangement direction of the pull-up branch 11 and the pull-down branch 21. However, this is only an example. In fact, the arrangement direction of the second pull-up compensation branch 412 and the second pull-down compensation branch 422 can also be perpendicular to the arrangement direction of the pull-up branch 11 and the pull-down branch 21.

[0063] In this exemplary embodiment, as Figure 8 As shown, Figure 7 The diagram shows the equivalent circuit structure of the output circuit section in the semiconductor device. The second pull-up compensation branch 412 can be connected to the pull-up control signal line MPU, and can be used to synchronously compensate the signal on the pull-up control signal line MPU. The second pull-up compensation branch 412 can be configured in a one-to-one correspondence with the pull-up control signal line MPU, and can be used to synchronously compensate the signal on its corresponding pull-up control signal line MPU. The number of transistors included in each second pull-up compensation branch 412 can be set according to actual needs. Figure 8 The illustrated embodiment includes two transistors, namely the sixth transistor T6 and the seventh transistor T7.

[0064] In this exemplary embodiment, the second pull-down compensation branch 422 is connected to the pull-down control signal line MPD. The second pull-down compensation branch 422 can be used to synchronously compensate the signal on the pull-down control signal line MPD. The second pull-down compensation branch 422 can be configured in a one-to-one correspondence with the pull-down control signal line MPD, and can be used to synchronously compensate the signal on its corresponding pull-down control signal line MPD. The number of transistors included in each second pull-down compensation branch 422 can be set according to actual needs.

[0065] Figure 8 Only one second pull-up compensation branch 412 and one second pull-down compensation branch 422 are shown. In this exemplary embodiment, "synchronous compensation" can be understood as: pulling up the compensated signal on the rising edge of the compensated signal and pulling down the compensated signal on the falling edge of the compensated signal, thereby making the rising and falling edges of the compensated signal steeper.

[0066] like Figure 8As shown, the second pull-up compensation branch 412 may include a sixth transistor T6 and a seventh transistor T7. The first terminal of the sixth transistor T6 can be connected to the pull-up control signal line MPU, and the second terminal of the sixth transistor T6 can be used to receive a high-level power supply signal. The first terminal of the seventh transistor T7 can be connected to the pull-up control signal line MPU, and the second terminal of the seventh transistor T7 can be used to receive a low-level power supply signal. The sixth transistor T6 can be turned on on the rising edge of the signal on the pull-up control signal line MPU to pull up the signal on the pull-up control signal line MPU with a high-level power supply signal. The seventh transistor T7 can be turned on on the falling edge of the signal on the pull-up control signal line MPU to pull down the signal on the pull-up control signal line MPU with a low-level power supply signal.

[0067] Similarly, the second pull-down compensation branch 422 may include an eighth transistor T8 and a ninth transistor T9. The first terminal of the eighth transistor T8 can be connected to the pull-down control signal line MPD, and the second terminal of the eighth transistor T8 can be used to receive a high-level power supply signal. The first terminal of the ninth transistor T9 can be connected to the pull-down control signal line MPD, and the second terminal of the ninth transistor T9 can be used to receive a low-level power supply signal. The eighth transistor T8 can be turned on on the rising edge of the signal on the pull-down control signal line MPD to pull up the signal on the pull-down control signal line MPD with a high-level power supply signal. The ninth transistor T9 can be turned on on the falling edge of the signal on the pull-down control signal line MPD to pull down the signal on the pull-down control signal line MPD with a low-level power supply signal.

[0068] It is understood that this exemplary embodiment only shows that the second pull-up compensation branch 412 and the second pull-down compensation branch 422 each contain two transistors, and one of the two transistors is used for pull-up and the other for pull-down; in other embodiments, the second pull-up compensation branch 412 and the second pull-down compensation branch 422 may each contain one transistor, with the transistor in the second pull-up compensation branch 412 used for pull-up and the transistor in the second pull-down compensation branch used for pull-down; alternatively, the second pull-up compensation branch 412 and the second pull-down compensation branch 422 may each contain multiple transistors (greater than or equal to two), with all transistors in the second pull-up compensation branch 412 used for pull-up and all transistors in the second pull-down compensation branch used for pull-down.

[0069] like Figure 7 As shown, a portion of the pull-up control signal line MPU can be located in the third integrated area 633. The pull-up control signal line MPU can be connected to the sixth transistor T6 and the seventh transistor T7 via via H, respectively. A portion of the pull-down control signal line MPD can be located in the fourth integrated area 634. The pull-down control signal line MPD can be connected to the eighth transistor T8 and the ninth transistor T9 via via H, respectively. This configuration can improve the integration density of the output circuit and reduce the layout space of the output circuit.

[0070] It should be understood that in other exemplary embodiments, the pull-up control signal line MPU may also be located outside the third integrated region 633, and the pull-down control signal line MPD may also be located outside the fourth integrated region 634. For example, in a direction perpendicular to the first direction X, the third integrated region 633 may be located between the pull-up circuit integrated region 61 and the pull-down circuit integrated region 62, and the fourth integrated region 634 may also be located between the pull-up circuit integrated region 61 and the pull-down circuit integrated region 62. Furthermore, in other exemplary embodiments, the semiconductor device may have both the first integrated region 631 and the second integrated region 632, as well as the third integrated region 633 and the fourth integrated region 634.

[0071] Accordingly, the output circuit may include a first pull-up compensation branch 411 located in the first integrated region 631 and a first pull-down compensation branch 421 located in the second integrated region 632, and may also include a second pull-up compensation branch 412 located in the third integrated region 633 and a second pull-down compensation branch 422 located in the fourth integrated region 634. Furthermore, the second pull-up compensation branch 412 located in the third integrated region 633 and the second pull-down compensation branch 422 located in the fourth integrated region 634 can also directly provide pull-up and pull-down compensation for the output signal line LDQ. That is, one terminal of the transistor in the second pull-up compensation branch 412 and the second pull-down compensation branch 422 is directly connected to the output signal line LDQ, and the other terminal is connected to a high-level power supply or a low-level power supply to achieve pull-up or pull-down.

[0072] This exemplary embodiment also provides a memory, which may include the semiconductor devices described above. For example, the memory may be a dynamic random access memory.

[0073] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the generality of this disclosure and include, but are not disclosed herein, common knowledge or customary techniques in the art. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0074] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A semiconductor device, wherein, The semiconductor device includes non-overlapping pull-up circuit integration areas, pull-down circuit integration areas, and compensation circuit integration areas. The semiconductor device also includes an output circuit connected to a signal output line, the output circuit comprising: A pull-up circuit is connected to the signal output line. The pull-up circuit includes multiple pull-up branches and is located in the pull-up circuit integration area. A pull-down circuit is connected to the signal output line. The pull-down circuit includes multiple pull-down branches and is located in the pull-down circuit integration area. A compensation circuit is used to enhance the driving capability of the output signal on the signal output line. The compensation circuit is located in the compensation circuit integration area and is directly connected to the signal output line. The compensation circuit includes a pull-down compensation branch and a pull-up compensation branch. The signal output line extends along a first direction and is used to transmit signals along the first direction; At least a portion of the compensation circuit integration area is located on one side of the pull-up circuit integration area in the first direction, and at least a portion of the compensation circuit integration area is located on one side of the pull-down circuit integration area in the first direction. The compensation circuit includes at least one first pull-up compensation branch, which is used to pull up the output signal; The compensation circuit integration area includes a first integration area, and the first pull-up compensation branch is located in the first integration area; The first integrated area is located on one side of the pull-up circuit integrated area in the first direction; The first pull-up compensation branch is connected to the signal output line and the first control signal line. The first pull-up compensation branch is used to pull up the output signal in response to the enable signal of the first control signal line. The pull-up branch includes a first transistor, the first terminal of the first transistor is connected to the signal output line, the second terminal of the first transistor is connected to the first high-level power supply terminal, and the gate of the first transistor is connected to the pull-up control signal line.

2. The semiconductor device according to claim 1, wherein, The compensation circuit includes at least one first pull-down compensation branch, which is used to pull down the output signal; The compensation circuit integration area includes a second integration area, and the first pull-down compensation branch is located in the second integration area; The second integrated area is located on one side of the pull-down circuit integrated area in the first direction.

3. The semiconductor device according to claim 1, wherein, The first pull-up compensation branch includes a second transistor, the first terminal of the second transistor is connected to the signal output line, the second terminal of the second transistor is used to receive a high-level power supply voltage, and the gate of the second transistor is connected to the first control signal line; The size of the first transistor is smaller than the size of the second transistor.

4. The semiconductor device according to claim 1 or 3, wherein, The number of pull-up branches in the pull-up circuit is greater than the number of the first pull-up compensation branches in the compensation circuit.

5. The semiconductor device according to claim 2, wherein, The first pull-down compensation branch is connected to the signal output line and the second control signal line. The first pull-down compensation branch is used to pull down the output signal in response to the enable signal of the second control signal line. The pull-down branch includes a third transistor, the first terminal of which is connected to the signal output line, the second terminal of which is connected to the first low-level power supply terminal, and the gate of which is connected to the pull-down control signal line.

6. The semiconductor device according to claim 5, wherein, The first pull-down compensation branch includes a fourth transistor, the first terminal of which is connected to the signal output line, the second terminal of which is used to receive a low-level power supply voltage, and the gate of which is connected to the second control signal line. The size of the third transistor is smaller than the size of the fourth transistor.

7. The semiconductor device according to claim 5 or 6, wherein, The number of pull-down branches in the pull-down circuit is greater than the number of the first pull-down compensation branches in the compensation circuit.

8. The semiconductor device according to claim 1, wherein, The compensation circuit includes at least one first pull-down compensation branch, and the pull-down circuit includes multiple pull-down branches; The first pull-down compensation branch is connected to the signal output line and the second control signal line, and is used to pull down the output signal in response to the enable signal of the second control signal line. The pull-down branch connects the signal output line, the first low-level power supply terminal, and the pull-down control signal line, and is used to transmit the signal from the first low-level power supply terminal to the signal output line in response to the signal from the pull-down control signal line. Multiple pull-up branches are distributed along the first direction, multiple pull-down branches are distributed along the first direction, and the area where the signal output line is located is between the pull-up circuit integration area and the pull-down circuit integration area; The first control signal line, the pull-up control signal line, the second control signal line, and the pull-down control signal line extend along the first direction. The area where the first control signal line is located is between the area where the pull-up control signal line is located and the area where the signal output line is located. The area where the second control signal line is located is between the area where the pull-down control signal line is located and the area where the signal output line is located.

9. A semiconductor device, wherein, The semiconductor device includes non-overlapping pull-up circuit integration areas, pull-down circuit integration areas, and compensation circuit integration areas. The semiconductor device also includes an output circuit connected to a signal output line, the output circuit comprising: A pull-up circuit is connected to the signal output line. The pull-up circuit includes multiple pull-up branches and is located in the pull-up circuit integration area. A pull-down circuit is connected to the signal output line. The pull-down circuit includes multiple pull-down branches and is located in the pull-down circuit integration area. A compensation circuit is used to enhance the driving capability of the output signal on the signal output line. The compensation circuit is located in the compensation circuit integration area and is directly connected to the signal output line. The compensation circuit includes a pull-down compensation branch and a pull-up compensation branch. The signal output line extends along a first direction and is used to transmit signals along the first direction. At least a portion of the compensation circuit integration area is located on one side of the pull-up circuit integration area in the second direction, and at least a portion of the compensation circuit integration area is located on one side of the pull-down circuit integration area in the second direction, wherein the second direction is opposite to the first direction. The compensation circuit includes at least one second pull-up compensation branch; The compensation circuit integration area includes a third integration area, and the second pull-up compensation branch is located in the third integration area; The third integrated area is located on one side of the pull-up circuit integrated area in the second direction; The pull-up branch includes a first transistor, the first terminal of the first transistor is connected to the signal output line, the second terminal of the first transistor is connected to the first high-level power supply terminal, and the gate of the first transistor is connected to the pull-up control signal line. The second pull-up compensation branch is connected to the pull-up control signal line, and the second pull-up compensation branch is used to synchronously compensate the signal on the pull-up control signal line.

10. The semiconductor device according to claim 9, wherein, The compensation circuit includes at least one second pull-down compensation branch; The compensation circuit integration area includes a fourth integration area, and the second pull-down compensation branch is located in the fourth integration area; The fourth integrated area is located on one side of the pull-down circuit integrated area in the second direction.

11. The semiconductor device according to claim 10, wherein, The pull-down branch includes a third transistor, the first terminal of which is connected to the signal output line, the second terminal of which is connected to the first low-level power supply terminal, and the gate of which is connected to the pull-down control signal line. The second pull-down compensation branch is connected to the pull-down control signal line, and the second pull-down compensation branch is used to synchronously compensate the signal on the pull-down control signal line.

12. The semiconductor device according to claim 9, wherein, The second pull-up compensation branch is connected to the signal output line and the third control signal line, and is used to pull up the output signal in response to the enable signal of the third control signal line.

13. The semiconductor device according to claim 10, wherein, The second pull-down compensation branch is connected to the signal output line and the fourth control signal line, and is used to pull down the output signal in response to the enable signal of the fourth control signal line.

14. A memory comprising the semiconductor device according to any one of claims 1-13.

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