A triple negative voltage charge pump and radio frequency switch chip

Abstract

The application discloses a triple negative voltage charge pump and a radio frequency switch chip, and has the advantages of simple and reasonable structure design, reduced capacitor area, and no need of setting an additional auxiliary circuit to meet voltage driving requirements. The triple negative voltage charge pump comprises a first negative voltage charge pump and a second negative voltage charge pump which are connected in cascade, the first negative voltage charge pump comprises a first capacitor, a second capacitor, a first switch unit and a second switch unit, the second negative voltage charge pump comprises a third capacitor, a fourth capacitor, a third switch unit and a fourth switch unit, the first switch unit, the second switch unit, the third switch unit and the fourth switch unit each comprise a MOS tube, diodes D1 and D2, the first switch unit to the fourth switch unit are symmetrically and cross-connected, the cathodes of the diodes D1 and D2 are connected to the outputs of the first switch unit to the fourth switch unit respectively, and the anodes of the diodes D1 and D2 are connected to one end of the capacitors and an output end respectively. The radio frequency switch chip comprises the triple negative voltage charge pump.

Description

Technical Field

[0001] This utility model relates to the field of radio frequency switch technology, specifically a triple negative pressure charge pump and a radio frequency switch chip. Background Technology

[0002] Currently, radio frequency devices used in communication equipment include radio frequency transceivers, amplifiers, switches, power supplies, and antennas. To reduce the overall area of ​​the devices, a single 1.8V or 1.2V power line VIO is often used in the MIPI interface (Mobile Device Processor Interface) to power the radio frequency switch. A negative voltage charge pump is used to boost and reverse the VIO voltage to meet the voltage requirements when the radio frequency switch is turned off.

[0003] Commonly used negative pressure charge pumps include double negative pressure charge pumps and triple negative pressure charge pumps. Triple negative pressure charge pumps are obtained by cascading two double negative pressure pumps. However, currently used triple negative pressure charge pumps suffer from complex structures and large footprints. This is because in the commonly used cascaded double negative pressure charge pump structure, the inverted clock signals CLK1 and CLK2 output by the oscillator require at least four capacitors to achieve signal inversion. To ensure capacitor performance, the areas of the four capacitors must be consistent, which not only increases the complexity of the manufacturing process but also occupies a significant amount of space during actual manufacturing. Furthermore, the driving voltage of the two-stage cascaded circuit is provided by additional auxiliary circuitry, which also increases the overall area of ​​the integrated circuit system, failing to meet the requirements of high integration and miniaturization of integrated circuits. Utility Model Content

[0004] In view of the above-mentioned problems in the prior art, this utility model provides a triple negative pressure charge pump with a simple and reasonable structural design, which can reduce the area occupied by capacitors and meet the voltage drive requirements without the need for additional auxiliary circuits.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A triple negative pressure charge pump includes a primary negative pressure charge pump and a secondary negative pressure charge pump, wherein the primary negative pressure charge pump and the secondary negative pressure charge pump are cascaded. The primary negative pressure charge pump includes a first capacitor C1, a second capacitor C2, a first switching unit, and a second switching unit. The secondary negative pressure charge pump includes a third capacitor C3, a fourth capacitor C4, a third switching unit, and a fourth switching unit. The first switching unit includes MOSFETs M11, M12, M13, and M14, and the second switching unit includes MOSFETs M21, M22, M23, and M24. One end of the first capacitor C1 is connected to a clock signal CLK1, and the other end is connected to... Connect the emitter of MOSFET M11, the collector of MOSFET M12, the emitter of MOSFET M23, the bases of MOSFETs M13 and M14, one end of the third capacitor C3, the collector of MOSFET M41, the emitter of MOSFET M42, and the emitter of MOSFET M44; one end of the second capacitor C2 is connected to the clock signal CLK2, and the other end is connected to the emitter of MOSFET M21, the collector of MOSFET M22, the emitter of MOSFET M14, the bases of MOSFETs M23 and M24, one end of the fourth capacitor C4, the collector of MOSFET M31, the emitter of MOSFET M32, and the emitter of MOSFET M33;

[0007] The other end of the third capacitor C3 is connected to the emitter of MOSFET M31, the collector of MOSFET M32, the emitter of MOSFET M43, the base of MOSFETs M34 and M33, and the cathode of diode D1, respectively. The other end of the fourth capacitor C4 is connected to the emitter of MOSFET M41, the collector of MOSFET M42, the emitter of MOSFET M34, the base of MOSFETs M43 and M44, and the cathode of diode D2, respectively. The anodes of diodes D1 and D2 are connected to one end of capacitor C5 and the output terminal Vneg, respectively. The other end of capacitor C5 is grounded.

[0008] Its further feature is that,

[0009] The MOS transistors M11, M21, M14, M23, M31, M41, M34, and M43 are all NMOS transistors;

[0010] The MOS transistors M12, M22, M13, M24, M32, M42, M33, and M44 are all PMOS transistors.

[0011] The clock signals CLK1 and CLK2 are generated by a clock circuit, which is a non-overlapping clock circuit including MOSFETs M51, M52, M53, and M54, NOR gates F11 and F21, and NOT gates F12, F13, F14, F21, F22, F23, and F24. MOSFETs M51 and M52 form a first inverter, and MOSFETs M53 and M54 form a second inverter. The bases of MOSFETs M51 and M52 are connected to the output of NOT gate M22 and the input of NOT gate F23, respectively. The collectors of MOSFETs M51 and M52 are connected to input port 1 of NOR gate F11, and input port 2 of NOR gate F11 is connected to the clock signal CLK1. MOSFETs M53 and M54... The bases of transistors 4 are connected to the output of NOT gate F12 and the input of NOT gate F13, respectively. The collectors of MOSFETs M53 and M54 are connected to input port 1 of NOT gate F21. Input port 2 of NOT gate F21 is connected to the clock signal CLKb. The output of NOR gate F11 is connected sequentially to NOT gates F12, F13, and F14 connected in series. The output of NOR gate F21 is connected sequentially to NOT gates F22, F23, and F24 connected in series. The output of NOT gate F14 outputs the clock signal CLK2, and the output of NOT gate F24 outputs the clock signal CLK1. The emitters of MOSFETs M51 and M53 are connected to the voltage source Vdd, and the emitters of MOSFETs M52 and M54 are both grounded.

[0012] The MOS transistors M51 and M53 are both PMOS transistors, and the MOS transistors M52 and M54 are both NMOS transistors;

[0013] The complementary clock signal is generated by a complementary clock signal generation circuit, which includes MOSFETs M26 to M30. The gates of MOSFETs M26 and M29 are connected to the clock signal CLK. The sources of MOSFETs M26, M27, and M28 are connected to the voltage source VddH. The drain of MOSFET M26 is connected to the drain of MOSFET M29, the gates of MOSFETs M27 and M30, and outputs the clock signal CLKa. The drain of MOSFET M27 is connected to the drain of MOSFET M30, the gates of MOSFETs M28 and M31, and outputs the clock signal CLKb. The sources of MOSFETs M29, M30, and M31 are all grounded.

[0014] The MOS transistors M26, M27, and M28 are all PMOS transistors, and the MOS transistors M29, M30, and M31 are all NMOS transistors.

[0015] An RF switch chip includes a driving voltage module, a level conversion module, and an RF switch connected in sequence. The driving voltage module includes a positive charge pump and a negative charge pump. The positive charge pump provides a positive voltage to the level conversion module, and the negative charge pump provides a negative voltage to the level conversion module. The level conversion module converts the positive and negative voltages into a control voltage, which controls the opening or closing of the switch in the RF switch. The negative charge pump is a triple negative charge pump as described above, used to provide a triple negative charge pump to the level conversion module.

[0016] The above-described structure of this utility model achieves the following beneficial effects: The first-stage negative pressure charge pump in this triple negative pressure charge pump includes two capacitors: a first capacitor C1 and a second capacitor C2. That is, clock signals CLK1 and CLK2 can be charged and discharged through the corresponding first capacitor C1 and second capacitor C2. Compared to the method requiring four capacitors in a single-stage negative pressure charge pump, the number of capacitors is reduced, thereby reducing the occupied area and manufacturing complexity. In this triple negative pressure charge pump, the driving voltage of the second-stage negative pressure charge pump is provided by the first-stage negative pressure charge pump. Therefore, it does not require additional auxiliary circuitry to meet the driving requirements of the second-stage negative pressure charge pump. The reduction in auxiliary circuitry also reduces the size of the entire integrated circuit system, thus meeting the requirements of high integration and miniaturization of integrated circuits.

[0017] The triple negative voltage charge pump is applied to the radio frequency switch chip. By cascading the first-stage negative voltage charge pump and the second-stage negative voltage charge pump in the triple negative voltage charge pump, a triple negative voltage is generated, thereby providing sufficient voltage for the radio frequency switch to turn on or off, ensuring that the switch in the radio frequency switch chip can be turned on or off stably. Attached Figure Description

[0018] Figure 1 This is the circuit diagram of a commonly used double negative pressure charge pump.

[0019] Figure 2 The circuit diagram of the triple negative pressure charge pump of this application is shown.

[0020] Figure 3 This is the circuit schematic of the non-overlapping clock signal generation circuit of this application;

[0021] Figure 4 This is a circuit schematic of the complementary clock signal generation circuit of this application;

[0022] Figure 5 The simulation results show the triple negative voltage output by the triple negative voltage charge pump of this application, based on the input voltage Vdd, clock signal CLK, and output terminal Vneg. Detailed Implementation

[0023] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0024] It should be noted that the terms "comprising" and "having" and any variations thereof in the specification, claims and accompanying drawings of this utility model are intended to cover non-exclusive inclusion. For example, a process, method, apparatus, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such processes, methods, products or devices.

[0025] Figure 1 The diagram shows a commonly used double negative voltage charge pump circuit structure, which includes four capacitors: C10, C20, C30, and C40. A triple negative voltage circuit is composed of these two double negative voltage charge pumps, each with four capacitors. The use of these four capacitors not only occupies a significant amount of space in the system, but also requires consistent matching, increasing manufacturing complexity. Furthermore, when two double negative voltage charge pumps are cascaded, additional auxiliary circuitry is needed to provide the driving voltage for the secondary pump, further increasing the overall system size.

[0026] To address the issues that existing triple negative pressure charge pumps occupy a significant amount of space in the entire integrated circuit system due to the multiple capacitors and auxiliary circuits, thus failing to meet the requirements for high integration and miniaturization of integrated circuits, and that the matching degree of the four capacitors in each stage of the negative pressure charge pump needs to be consistent, increasing the process complexity, this utility model provides a specific embodiment of a triple negative pressure charge pump.

[0027] See Figure 2The triple negative pressure charge pump includes a first-stage negative pressure charge pump and a second-stage negative pressure charge pump, which are cascaded together. The first-stage negative pressure charge pump includes a first capacitor C1, a second capacitor C2, a first switching unit, and a second switching unit. The second-stage negative pressure charge pump includes a third capacitor C3, a fourth capacitor C4, a third switching unit, and a fourth switching unit. The first switching unit includes MOSFETs M11, M12, M13, and M14, and the second switching unit includes MOSFETs M21, M22, M23, and M24. One end of the first capacitor C1 is connected to the clock signal CLK1, and the other end is connected to the MOSFET M11. The emitter, collector of MOSFET M12, emitter of MOSFET M23, base of MOSFETs M13 and M14, one end of the third capacitor C3, collector of MOSFET M41, emitter of MOSFET M42, and emitter of MOSFET M44; one end of the second capacitor C2 is connected to the clock signal CLK2, and the other end is connected to the emitter of MOSFET M21, collector of MOSFET M22, emitter of MOSFET M14, base of MOSFETs M23 and M24, one end of the fourth capacitor C4, collector of MOSFET M31, emitter of MOSFET M32, and emitter of MOSFET M33.

[0028] The other end of the third capacitor C3 is connected to the emitter of MOSFET M31, the collector of MOSFET M32, the emitter of MOSFET M43, the base of MOSFETs M34 and M33, and the cathode of diode D1. The other end of the fourth capacitor C4 is connected to the emitter of MOSFET M41, the collector of MOSFET M42, the emitter of MOSFET M34, the base of MOSFETs M43 and M44, and the cathode of diode D2. The anodes of diodes D1 and D2 are connected to one end of capacitor C5 and the output terminal Vneg, respectively. The other end of capacitor C5 is grounded.

[0029] In this embodiment, MOS transistors M11, M21, M14, M23, M31, M41, M34, and M43 are all NMOS transistors; MOS transistors M12, M22, M13, M24, M32, M42, M33, and M44 are all PMOS transistors.

[0030] See Figure 3Clock signals CLK1 and CLK2 are generated by a clock circuit, which is a non-overlapping clock circuit. This circuit includes PMOS transistors M51 and M53, NMOS transistors M52 and M54, NOR gates F11 and F21, and NOT gates F12, F13, F14, F21, F22, F23, and F24. MOS transistors M51 and M52 form the first inverter, and MOS transistors M53 and M54 form the second inverter. The bases of MOS transistors M51 and M52 are connected to the output of NOT gate M22 and the input of NOT gate F23, respectively. The collectors of MOS transistors M51 and M52 are connected to input port 1 of NOR gate F11. Input port 2 of NOR gate F11 is connected to the clock signal CLK1. The bases of MOS transistors M53 and M54 are connected to the input of NOT gate F12. The output terminal and input terminal of NOT gate F13 are connected. The collectors of MOSFETs M53 and M54 are connected to input terminal 1 of NOT gate F21. Input terminal 2 of NOT gate F21 is connected to the clock signal CLKb. The output terminal of OR gate F11 is sequentially connected to a series of NOT gates F12, F13, and F14. The output terminal of OR gate F21 is sequentially connected to a series of NOT gates F22, F23, and F24. The output terminal of NOT gate F14 outputs the clock signal CLK2, and the output terminal of NOT gate F24 outputs the clock signal CLK1. The emitters of MOSFETs M51 and M53 are connected to the voltage source Vdd, and the emitters of MOSFETs M52 and M54 are grounded. In this embodiment, MOSFETs M51 and M53 are PMOS transistors, and MOSFETs M52 and M54 are NMOS transistors. The clock signal CLK generates complementary clock signals CLKa and CLKb through a complementary clock signal generation circuit. The specific structure of the complementary clock signal generation circuit is shown in [link to complementary clock signal generation circuit]. Figure 4 The complementary clock signal generation circuit includes PMOS transistors M26-M28 and NMOS transistors M29-M31. PMOS transistors M26 and M29, M27 and M30, and M28 and M31 respectively form NOT gates. These NOT gates invert the clock signals to generate complementary clock signals CLKa and CLKb. These complementary clock signals are then generated by the non-overlapping clock signal generation circuit, producing non-overlapping clock signals CLK+ and CLK-. The non-overlapping clock signal generation circuit is described in [link to circuit description]. Figure 3 This circuit uses logic NOT gates, logic OR gates, logic NOT gates composed of PMOS and NMOS transistors, as well as a crossover structure, to ensure that the complementary clock signals are not output at the same time, thereby generating complementary non-overlapping clock signals CLK+ and CLK-.

[0031] The above-mentioned triple negative voltage charge pump generates triple negative voltage. The specific steps include: S1, the non-overlapping clock signals CLK1 and CLK2 generated by the clock circuit are respectively input to one end of the corresponding first capacitor C1 and second capacitor C2; at the same time, one end of the first capacitor C1 is input with voltage Vdd, and one end of the second capacitor C2 is grounded. In this embodiment, the voltage Vdd is 1.8V, so the voltage at the other end of the first capacitor C1 is 0V. Since one end of the second capacitor C2 is 0V, the voltage at the other end of the second capacitor C2 is -1.8V.

[0032] S2. When the input voltage at one end of the first capacitor C1 is 1.8V and the voltage at one end of the second capacitor C2 is 0V, NMOS transistors M11 and M21 are turned on, while PMOS transistors M13 and M23 and NMOS transistors M14 and M24 are turned off. At this time, the voltage at point C is 0V and the voltage at point D is -1.8V.

[0033] S3. Based on the principle that the voltage of a capacitor cannot change abruptly when the signals at both ends of the capacitor switch, when the signals at the input terminals of the first capacitor C1 and the second capacitor C2 switch, that is, when the first capacitor C1 receives the clock signal CLK2 and a voltage of 0V, and the second capacitor C2 receives the clock signal CLK1 and a voltage of 1.8V, the voltages at the other ends of the first capacitor C1 and the second capacitor C2 are -1.8V and 0V, respectively. At this time, MOSFETs M22, M23, M12, and M14 are turned on, and MOSFETs M11 and M21 are turned off. At this time, the voltage at point C is -1.8V, and the voltage at point D is 0V.

[0034] S4. When the signals at the input terminals of the first capacitor C1 and the second capacitor C2 switch again, that is, when the first capacitor C1 receives the clock signal CLK1 and a voltage of 1.8V, and the second capacitor C2 receives the clock signal CLK2 and a voltage of 0V, the voltages at the other terminals of the first capacitor C1 and the second capacitor C2 are -1.8V and 0V, respectively. At this time, MOSFETs M22, M23, and M24 are off, MOSFETs M12 and M14 are off, MOSFET M13 is on, and MOSFETs M11 and M21 are off. At this time, the voltage at point C is -1.8V and the voltage at point D is 0V.

[0035] Similarly, at point S5, when the voltage at point C is 0V and the voltage at point D is -1.8V, the voltage at the other end of the third capacitor C3 is -1.8V, and the voltage at the other end of the fourth capacitor C4 is -3.6V. NMOS transistors M31 and M41 are turned on, while PMOS transistors M33 and M43 and NMOS transistors M34 and M44 are turned off. The voltage at point A is -1.8V, and the voltage at point B is -3.6V. Diode D2 is cut off, and the output voltage at the output terminal Vneg is -3.6V.

[0036] S6. When the voltage at point C is -1.8V and the voltage at point D is 0V, the voltage at the other end of the third capacitor C3 is -3.6V and the voltage at the other end of the fourth capacitor C4 is -1.8V. At this time, MOSFETs M42, M43, M32, and M34 are turned on, while MOSFETs M31 and M41 are turned off. At this time, the voltage at point A is -3.6V and the voltage at point B is -1.8V. Diode D1 is cut off, diode D2 is turned on, and the output voltage at the output terminal Vneg is -3.6V.

[0037] When the voltage at points S7 and C is -1.8V and the voltage at point D is 0V, the voltage at the other end of the third capacitor C3 is -3.6V, and the voltage at the other end of the fourth capacitor C4 is -1.8V. At this time, MOSFETs M42, M43, and M44 are off, MOSFETs M32 and M34 are off, MOSFET M33 is on, MOSFETs M31 and M41 are off, diode D1 is on, and diode D2 is off. Therefore, the output voltage at the output terminal Vneg is -3.6V + 0.7V + 0.2V = -2.7V. 0.7V is the voltage drop across diode D1 or D2, and 0.2V is the internal loss of the entire triple negative voltage charge pump. Therefore, the final output voltage of the triple negative voltage charge pump is -2.7V.

[0038] By sequentially repeating steps S1, S2, S5, S3, S6, and S4, the output terminal Vneg continuously outputs a voltage of -3.6V. Each of the first-stage and second-stage negative voltage charge pumps contains two capacitors. Compared to a method where each stage of the negative voltage charge pump contains four capacitors, the number of capacitors in this triple negative voltage charge pump is significantly reduced. In the entire triple negative voltage charge pump circuit, the capacitors occupy a larger area. Therefore, the reduction in the area occupied by the capacitors meets the requirements of high integration and miniaturization of integrated circuits. At the same time, it is easier to manufacture two capacitors with consistent performance than to manufacture four capacitors with consistent performance in the same charge pump, thus reducing the process difficulty.

[0039] Figure 5 Simulation results of the input voltage Vdd and output voltage Vneg of the triple negative voltage charge pump using the method described in this application are presented. Figure 5 The horizontal axis represents time dx, and the vertical axis represents the input voltage vdd, the clock signal CLK, and the output triple negative voltage Vneg, respectively. Curve B shows the change of the clock signal CLK, and curves A and C show the changes of the input voltage vdd and the output triple negative voltage Vneg under the control of the non-overlapping clock signals CLK+ and CLK- generated by the clock signal CLK, respectively. Time dx = 253ns is one clock cycle. Figure 5It can be seen that within one clock cycle, as the input voltage vdd changes, the triple negative voltage Vneg output by the triple negative voltage charge pump changes accordingly, and it can continuously output a stable negative voltage signal. Furthermore, this negative voltage signal can reach approximately 2.7V, which meets the control requirements of the subsequent RF switch.

[0040] The aforementioned triple negative voltage charge pump is applied to an RF switch chip. The RF switch chip includes a drive voltage module, a level conversion module, and an RF switch connected in sequence. The drive voltage module includes a positive voltage charge pump and a negative voltage charge pump. The positive voltage charge pump provides positive voltage to the level conversion module, and the triple negative voltage charge pump provides negative voltage to the level conversion module. The level conversion module converts the positive and negative voltages into a control voltage, which is used to control the switching on or off of the RF switch. By cascading the first and second stages of the triple negative voltage charge pump, a triple negative voltage is generated, thereby providing sufficient voltage for the RF switch to turn on or off, ensuring that the switch in the RF switch chip can be stably turned on or off.

[0041] The above are merely preferred embodiments of this application, and the present invention is not limited to the above embodiments. It is understood that other improvements and variations that can be directly derived or conceived by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included within the protection scope of the present invention.

Claims

1. A triple negative pressure charge pump, comprising a primary negative pressure charge pump and a secondary negative pressure charge pump, wherein the primary negative pressure charge pump and the secondary negative pressure charge pump are cascaded, and the primary negative pressure charge pump comprises a first capacitor C1, a second capacitor C2, a first switching unit, and a second switching unit, characterized in that, The secondary negative pressure charge pump includes a third capacitor C3, a fourth capacitor C4, a third switching unit, and a fourth switching unit. The first switching unit includes MOSFETs M11, M12, M13, and M14, and the second switching unit includes MOSFETs M21, M22, M23, and M24. One end of the first capacitor C1 is connected to the clock signal CLK1, and the other end is connected to the emitter of MOSFET M11, the collector of MOSFET M12, the emitter of MOSFET M23, and the junction of MOSFETs M13 and M14. The base of transistor M41, one end of the third capacitor C3, the collector of MOSFET M41, the emitter of MOSFET M42, and the emitter of MOSFET M44 are connected to the base of transistor M41, the collector of MOSFET M22, the emitter of MOSFET M14, the base of MOSFETs M23 and M24, one end of the fourth capacitor C4, the collector of MOSFET M31, the emitter of MOSFET M32, and the emitter of MOSFET M33 are connected to the base of transistor M41, the collector of MOSFET M22, and the emitter of MOSFET M33. The other end of the third capacitor C3 is connected to the emitter of MOSFET M31, the collector of MOSFET M32, the emitter of MOSFET M43, the base of MOSFETs M34 and M33, and the cathode of diode D1, respectively. The other end of the fourth capacitor C4 is connected to the emitter of MOSFET M41, the collector of MOSFET M42, the emitter of MOSFET M34, the base of MOSFETs M43 and M44, and the cathode of diode D2, respectively. The anodes of diodes D1 and D2 are connected to one end of capacitor C5 and the output terminal Vneg, respectively. The other end of capacitor C5 is grounded.

2. The triple negative pressure charge pump according to claim 1, characterized in that, The MOS transistors M11, M21, M14, M23, M31, M41, M34, and M43 are all NMOS transistors; the MOS transistors M12, M22, M13, M24, M32, M42, M33, and M44 are all PMOS transistors.

3. The triple negative pressure charge pump according to claim 1 or 2, characterized in that, The clock signals CLK1 and CLK2 are generated by a clock circuit, which is a non-overlapping clock signal generation circuit, including MOSFETs M51, M52, M53, and M54, NOR gates F11 and F21, and NOT gates F12, F13, F14, F21, F22, F23, and F24. MOSFETs M51 and M52 form a first inverter, and MOSFETs M53 and M54 form a second inverter. The bases of MOSFETs M51 and M52 are connected to the output of NOT gate F22 and the input of NOT gate F23, respectively. The collectors of MOSFETs M51 and M52 are connected to input port 1 of NOR gate F11. Input port 2 of NOR gate F11 is connected to the clock signal CLK1. The bases of MOSFETs M53 and M54 are connected to the output of the second inverter. The output of NOT gate F12 and the input of NOT gate F13 are described. The collectors of MOSFETs M53 and M54 are connected to input port 1 of NOT gate F21. Input port 2 of NOT gate F21 is connected to clock signal CLKb. The output of OR gate F11 is sequentially connected to NOT gates F12, F13, and F14 connected in series. The output of OR gate F21 is sequentially connected to NOT gates F22, F23, and F24 connected in series. The output of NOT gate F14 outputs clock signal CLK2, and the output of NOT gate F24 outputs clock signal CLK1. The emitters of MOSFETs M51 and M53 are connected to voltage source Vdd, and the emitters of MOSFETs M52 and M54 are grounded. The clock signals CLKa and CLKb are complementary clock signals.

4. The triple negative pressure charge pump according to claim 3, characterized in that, The MOS transistors M51 and M53 are both PMOS transistors, and the MOS transistors M52 and M54 are both NMOS transistors.

5. The triple negative pressure charge pump according to claim 3, characterized in that, The complementary clock signal is generated by a complementary clock signal generation circuit, which includes MOSFETs M26 to M31. The gates of MOSFETs M26 and M29 are connected to the clock signal CLK. The sources of MOSFETs M26, M27, and M28 are connected to the voltage source VddH. The drain of MOSFET M26 is connected to the drain of MOSFET M29, the gates of MOSFETs M27 and M30, and outputs the clock signal CLKa. The drain of MOSFET M27 is connected to the drain of MOSFET M30, the gates of MOSFETs M28 and M31, and outputs the clock signal CLKb. The sources of MOSFETs M29, M30, and M31 are all grounded.

6. The triple negative pressure charge pump according to claim 5, characterized in that, The MOS transistors M26, M27, and M28 are all PMOS transistors, and the MOS transistors M29, M30, and M31 are all NMOS transistors.

7. A radio frequency (RF) switch chip, comprising a driving voltage module, a level conversion module, and an RF switch connected in sequence, wherein the driving voltage module includes a positive charge pump and a negative charge pump, the positive charge pump providing a positive voltage to the level conversion module, the negative charge pump providing a negative voltage to the level conversion module, the level conversion module converting the positive and negative voltages into a control voltage, the control voltage controlling the opening or closing of the switch in the RF switch, characterized in that... The negative pressure charge pump is the triple negative pressure charge pump as described in claim 1, used to provide a triple negative pressure charge pump for the level conversion module.

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