A method for generating negative pressure based on a negative pressure charge pump

Abstract

This invention discloses a negative voltage generation method based on a negative voltage charge pump, which can reduce clock feedthrough caused by signal overlap. The method includes: inputting complementary non-overlapping clock signals to a first input terminal, a second input terminal, one end of a third capacitor, and one end of a fourth capacitor of a control circuit; inputting a first voltage and a second voltage to the first input terminal, the second input terminal, one end of the third capacitor, and one end of the fourth capacitor, respectively, wherein the first voltage value and the second voltage value are not equal; outputting a first voltage signal and a second voltage signal to the first output terminal and the second output terminal of the control circuit, respectively; outputting a third voltage signal and a fourth voltage signal to the other end of the third capacitor and the fourth capacitor, respectively; sending the first voltage signal to the second switch unit and the fourth switch unit, respectively; sending the second voltage signal to the first switch unit and the third switch unit, respectively; sending the third voltage signal to the third switch unit; and sending the fourth voltage signal to the fourth switch unit, thereby continuously outputting a negative voltage at the voltage output terminal.

Description

Technical Field

[0001] This invention relates to the field of radio frequency switch technology, specifically to a negative pressure charge pump and a negative pressure generation method for radio frequency switches. Background Technology

[0002] When designing and fabricating radio frequency switching devices using SOI CMOS technology, in order to increase the turn-off strength of transistors, a negative voltage bias needs to be provided to the gate of the transistor when the switching channel is turned off. That is, the positive voltage of the external power supply is converted into a negative voltage. The basic principle of the charge pump generating negative voltage is to take advantage of the characteristic that the voltage of a capacitor cannot change instantaneously. When charging or discharging the capacitor, the potential difference between the two electrodes of the capacitor is kept instantaneously constant. After charging or discharging is completed, the electrodes at both ends of the capacitor are reversed, thereby converting the positive voltage input to the charge pump into a negative voltage.

[0003] In a negative charge pump, the reversal of the electrodes across the capacitor is mainly controlled by the control circuit. However, the control circuits currently used for controlling negative charge pumps suffer from poor reliability and high internal losses. This is because commonly used control circuits are mainly composed of mirrored cross-connected MOSFETs and capacitors, which are prone to signal overlap during clock signal switching. At the moment of overlap, clock feedthrough occurs, meaning that the MOSFETs that need to be turned off are weakly turned on at the same time. The internal losses generated by the weak conduction reduce the output voltage of the negative charge pump, resulting in a negative voltage pull-up at the output. This leads to the problem that the expected voltage for the RF switch to be turned off is not reached, thus reducing the stability of the output voltage. Summary of the Invention

[0004] To address the aforementioned deficiencies in the prior art, this invention provides a negative pressure charge pump that can avoid clock feedthrough caused by signal overlap, improve output voltage stability, and ensure that the output voltage meets the expected voltage requirements for the turn-off of RF switching devices.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: a negative pressure charge pump, comprising a control circuit and a first to a fourth switching unit. The input terminals of the control circuit include a first input terminal and a second input terminal, wherein complementary non-overlapping clock signals CLK1 and CLK2 are input to the first input terminal and the second input terminal, and a high-level voltage Vin and a low-level voltage are input to the second input terminal, respectively. The output terminals of the control circuit include a first output terminal and a second output terminal. The first output terminal is connected to the first signal input terminal of the first switching unit and the first signal input terminal of the third switching unit, respectively. The second output terminal is connected to the first signal input terminal of the second switching unit and the first signal input terminal of the fourth switching unit, respectively. The first input terminal is connected to the second signal input terminal of the first switching unit after series capacitor connection, and the second input terminal is connected to the second signal input terminal of the second switching unit after series capacitor connection. The output terminals of the first and second switching units are connected to the second signal input terminals of the third and fourth switching units, respectively. The output terminals of the third and fourth switching units are voltage output terminals. The clock signals CLK1 and CLK2 are non-overlapping clock signals.

[0006] The control circuit is used to generate complementary, non-overlapping first voltage signal xp and second voltage signal xn;

[0007] The first switching unit is used to adjust the high-level voltage Vin or the low-level voltage to obtain a third voltage signal X1; the second switching unit is used to adjust the low-level voltage or the high-level voltage Vin to obtain a fourth voltage signal X2.

[0008] The third and fourth switching units are used to control the third voltage signals X1 and X2 respectively, so that the voltage output terminal continuously outputs voltage Vneg, and the output voltage Vneg = -Vin.

[0009] A further feature is that the control circuit and the first to fourth switching units all include MOSFETs. The first input terminal is connected to the control circuit through a first capacitor C1, the first input terminal is connected to the first switching unit through a third capacitor C3, the second input terminal is connected to the control circuit through a second capacitor C2, and the second input terminal is connected to the second switching unit through a fourth capacitor C4. The values ​​of the first capacitor C1 and the second capacitor C2 are equal, the values ​​of the third capacitor C3 and the fourth capacitor C4 are equal, and the values ​​of the third capacitor C3 and the fourth capacitor C4 are greater than the values ​​of the first capacitor C1 and the second capacitor C2.

[0010] Furthermore, the control circuit also includes MOS transistors M1 and M2, both of which are NMOS transistors;

[0011] Furthermore, the first switching unit includes MOS transistors M3, M4, M5, and M6, wherein MOS transistors M3 and M6 are NMOS transistors, and MOS transistors M4 and M5 are PMOS transistors;

[0012] Furthermore, the second switching unit includes MOS transistors M7, M8, M9, and M10, wherein MOS transistors M7 and M10 are NMOS transistors, and MOS transistors M8 and M9 are PMOS transistors;

[0013] Furthermore, the third switching unit includes MOS transistors M11, M12, M13, and M14, wherein MOS transistor M11 is an NMOS transistor, and MOS transistors M12, M13, and M14 are PMOS transistors;

[0014] Furthermore, the fourth switching unit includes the fifth capacitor C5, MOS transistors M16, M17, M18, and M19, wherein MOS transistor M18 is an NMOS transistor, and MOS transistors M16, M17, and M19 are PMOS transistors.

[0015] A method for generating negative pressure based on a negative pressure charge pump, wherein the negative pressure charge pump includes a control circuit and a first switching unit to a second switching unit. The control circuit has an input terminal including a first input terminal and a second input terminal, and an output terminal including a first output terminal and a second output terminal. The first output terminal is connected to the first signal input terminal of the first switching unit and the first signal input terminal of the third switching unit, respectively. The second output terminal is connected to the first signal input terminal of the second switching unit and the first signal input terminal of the fourth switching unit, respectively. The first input terminal is connected to the first input terminal of the control circuit after being connected in series with a first capacitor C1. The second input terminal is connected to the second input terminal of the control circuit after being connected in series with a second capacitor C2. The first input terminal is connected to the second signal input terminal of the first switching unit after being connected in series with a third capacitor C3. The second input terminal is connected to the second signal input terminal of the second switching unit after being connected in series with a fourth capacitor C4. The output terminals of the first and second switching units are respectively connected to the second signal input terminals of the third and fourth switching units. The output terminals of the third and fourth switching units are voltage output terminals.

[0016] The method is characterized by comprising: S1, inputting complementary non-overlapping clock signals CLK1 and CLK2 to the first input terminal and the second input terminal of the control circuit, and simultaneously inputting complementary non-overlapping clock signals CLK1 and CLK2 to one end of the third capacitor C3 of the first switching unit and one end of the fourth capacitor C4 of the second switching unit;

[0017] S2. Input a first voltage and a second voltage to the first input terminal and the second input terminal of the control circuit, respectively. At the same time, input the first voltage and the second voltage to one end of the third capacitor C3 and one end of the fourth capacitor C4, respectively. The value of the first voltage and the value of the second voltage are not equal. If the first voltage is high level Vin, then the second voltage is low level. If the first voltage is low level, then the second voltage is high level.

[0018] S3. In the control circuit, under the charging and discharging action of the first capacitor C1 and the second capacitor C2, the first output terminal and the second output terminal of the control circuit respectively output the first voltage signal xp and the second voltage signal xn.

[0019] S4. In the first switching unit and the second switching unit, under the charging and discharging action of the third capacitor C3 and the fourth capacitor C4, the other end of the third capacitor C3 in the first switching unit outputs a third voltage signal X1, and the other end of the fourth capacitor C4 in the second switching unit outputs a fourth voltage signal X2.

[0020] S5. The first voltage signal xp is sent to the first signal input terminals of the second switch unit and the fourth switch unit respectively, and the second voltage signal xn is sent to the first signal input terminals of the first switch unit and the third switch unit respectively; the third voltage signal X1 is sent to the third switch unit, and the fourth voltage signal X2 is sent to the fourth switch unit;

[0021] S6. Under the action of clock signal CLK1, second voltage signal xn, and third voltage signal X1, the first and third switching units are turned on, and the second and fourth switching units are turned off, so that the voltage output terminal outputs voltage Vneg.

[0022] S7. Under the action of clock signal CLK2, first voltage signal xp, and fourth voltage signal X2, the second and fourth switch units are turned on, and the first and third switch units are turned off, so that the voltage output terminal outputs voltage Vneg, realizing the continuous output of output voltage Vneg.

[0023] Its further feature is that,

[0024] If the first voltage is 1, 8V or 2.8V, and the second voltage is 0V, then the first voltage signal xp and the third voltage signal X1 are 0V, the second voltage signal xn and the fourth voltage signal X2 are 1.8V or 2.8V, and the output voltage Vneg is -1.8V or -2.8V.

[0025] The above-described structure and method of the present invention can achieve the following beneficial effects: During the negative voltage generation process of the negative voltage charge pump circuit, clock signals CLK1 and CLK2 are applied to the control circuit, the first switching unit, and the second switching unit, respectively. Clock signals CLK1 and CLK2 are complementary non-overlapping clock signals. By controlling the first switching unit and the second switching unit through non-overlapping complementary signals, the MOS transistors in the first switching unit and the second switching unit are effectively prevented from weakly conducting at the same time, that is, the clock feedthrough caused by signal overlap is avoided. At the same time, the power loss caused by weak conduction is reduced, the output voltage stability is improved, and the output voltage is ensured to meet the expected voltage requirements for the turn-off of the RF switching devices.

[0026] Furthermore, in the first and second switching units, MOSFET M1 and first capacitor C1 work together to generate a first voltage signal xp with a high or low level output, and MOSFET M2 and second capacitor C2 work together to generate a second voltage signal xn with a low or high level output. The first voltage signal xp and the second voltage signal xn serve as control signals for MOSFETs M3 or M7 in the first and second switching units, respectively. Since clock signals CLK1 and CLK2 are non-overlapping complementary clock signals, their high-low level switching will cause high-low level switching between the first voltage signal xp and the second voltage signal xn, as well as high-low level switching between the third voltage signal X1 and the fourth voltage signal X2. The MOSFETs M5 and M9 in the first switching unit, under the action of the first voltage signal xp and the third voltage signal X1, and the MOSFETs M6 and M10 in the second switching unit, under the combined action of the second voltage signal xn and the fourth voltage signal X2, respectively act on the gate terminals of MOSFETs M3 and M7. Therefore, the signals used to control MOSFET M3 in the first switching unit and MOSFET M7 in the second switching unit are also non-overlapping complementary signals, thereby avoiding the weak conduction of MOSFETs in the first or second switching unit at the same time. Attached Figure Description

[0027] Figure 1 The equivalent circuit diagram of a negative pressure charge pump;

[0028] Figure 2 This is a circuit diagram of a commonly used negative pressure charge pump.

[0029] Figure 3 This is a circuit structure block diagram of the negative pressure charge pump of the present invention;

[0030] Figure 4 This is a circuit diagram of the control circuit of the present invention;

[0031] Figure 5 The circuit diagrams for the first and second switching units of this invention are shown below.

[0032] Figure 6 The circuit diagrams for the third and fourth switching units of this invention are shown below.

[0033] Figure 7 The simulation results of the voltage source Vin, clock signal CLK, and output voltage Vneg of this invention are shown in the figure. Detailed Implementation

[0034] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. It should be noted that the terms "comprising" and "having" and any variations thereof in the specification, claims and the above-mentioned drawings of the present invention are intended to cover non-exclusive inclusion. For example, a process, method, apparatus, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products or devices.

[0035] When designing and fabricating RF switching devices using SOI CMOS technology, a negative bias is required. To increase the transistor's turn-off strength, the transistor's gate needs a negative bias when the switching channel is off. Currently, a common method for providing this negative bias is to convert the positive voltage from the external power supply to a negative voltage using a negative charge pump. This involves using a high-speed analog switch to ground the positive terminal after charging. Since the potential difference across the capacitor remains constant, the other end of the capacitor has a negative voltage, the absolute value of which is equal to the absolute value of the voltage across the capacitor after charging. A typical negative charge pump includes an oscillator for generating a high-speed switching signal, an inverter for toggling the switching signal, and a set of high-speed analog switches. The oscillator, acting as the clock source for switching the switch states, generates two out-of-phase control switch switching clock signals through the inverter. Figure 1 The basic principle diagram for generating negative pressure using a negative pressure charge pump is as follows: two clock signals generated by an oscillator control switches S1, S2, S3, and S4 respectively, causing S1 and S2 to switch simultaneously, and S3 and S4 to switch simultaneously, with the two sets of switches in opposite phases. Figure 1 In the middle, when S1 and S2 are closed, S3 and S4 are open, and the input high-level voltage Vin charges capacitor C1. At this time, the polarity of the capacitor is positive at point A and negative at point B. As the clock source changes, S3 and S4 close, and switch S1 and switch S2 open. Capacitor C1 charges capacitor C2. Since the potential difference across capacitor C1 cannot change, the voltage measured at the output terminal is negative. When the oscillator switches at a higher frequency, the output terminal can continuously output a relatively smooth negative voltage.

[0036] Figure 2 Provides an application Figure 1 The basic principle shown is to realize a charge pump structure that converts positive voltage to negative voltage. It is equivalent to two inverters connected to each other for input and output. CLK1 is the clock signal, and CLK2 is the inverted non-overlapping clock signal of CLK1. The clock signals CLK1 and CLK2 are generated by inverting the clock signal CLK through the inverter. Its advantage is that the bias voltage of the switching MOSFET is adaptively provided after reaching steady state. CLK1 is high level Vin, and low level is ground. The expected output voltage Vneg is -Vin. When MOSFETs MP1 and MN2 are on, MOSFETs MP2 and MN1 are off. When MOSFETs MP2 and MN1 are on, MOSFETs MP1 and MN2 are off. However, at the moment of switching (signal flip), the signal will overlap, resulting in clock feedthrough. That is, MOSFETs MP1, MP2, MN1, and MN2 are weakly on at the same time, causing internal loss, reducing efficiency, and the value of the output voltage Vneg is increased, which does not reach the expected voltage.

[0037] To address the issues of clock feedthrough and internal losses that arise in the aforementioned negative voltage charge pump, which reduce output voltage stability, the following provides a specific embodiment of a negative voltage charge pump, which includes a control circuit and a first to a fourth switching unit.

[0038] The control circuit's input terminals include a first input terminal and a second input terminal. The first and second input terminals receive inverted clock signals CLK1 and CLK2, respectively. In this embodiment, one input terminal receives a high-level voltage Vin, while the other input terminal is grounded (Vss). The control circuit's output terminals include a first output terminal and a second output terminal. The first output terminal outputs a first voltage signal xp, and the second output terminal outputs a second voltage signal xn. See [link to relevant documentation]. Figure 3 The first output terminal is connected to the first signal input terminal of the first switch unit and the first signal input terminal of the third switch unit, respectively. The second output terminal is connected to the first signal input terminal of the second switch unit and the first signal input terminal of the fourth switch unit, respectively. The first input terminal and the second input terminal are also connected to the second signal input terminal of the first switch unit and the second signal input terminal of the second switch unit, respectively. The output terminals of the first switch unit and the second switch unit are connected to the second signal input terminals of the third switch unit and the fourth switch unit, respectively. The output terminals of the first switch unit and the second switch unit output the third voltage signal X1 and the fourth voltage signal X2, respectively. The output terminals of the third switch unit and the fourth switch unit are the voltage output terminals of the negative pressure charge pump, and the output voltage is Vneg.

[0039] Figure 4The control circuit includes a first capacitor C1, a second capacitor C2, and MOSFETs M1 and M2. The values ​​of the first capacitor C1 and the second capacitor C2 are equal. The first input terminal and the second input terminal are connected to one end of the first capacitor C1 and the second capacitor C2, respectively. The first capacitor C1 is connected to the collector of MOSFET M1, the base of MOSFET M2, and the first output terminal. The other end of the second capacitor C2 is connected to the collector of MOSFET M2, the base of MOSFET M2, and the second output terminal, respectively. The emitters of MOSFETs M1 and M2 are connected to ground. Both MOSFETs M1 and M2 are NMOS transistors. This control circuit is used to generate a first voltage signal xp and a second voltage signal xn.

[0040] See Figure 5 , Figure 6 Each of the first to fourth switching units includes a MOSFET. The control circuit is connected to the first switching unit through a first capacitor C1 and a third capacitor C3 connected in series. The control circuit is connected to the second switching unit through a second capacitor C2 and a fourth capacitor C4 connected in series. The values ​​of the first capacitor C1 and the second capacitor C2 are equal, the values ​​of the third capacitor C3 and the fourth capacitor C4 are equal, and the values ​​of the third capacitor C3 and the fourth capacitor C4 are greater than the values ​​of the first capacitor C1 and the second capacitor C2.

[0041] See Figure 5 The first switching unit also includes MOSFETs M3, M4, M5, and M6. One end of the third capacitor C3 is connected to the first input terminal, and the other end is connected to the collector of MOSFET M3, the emitter and base of MOSFET M4, and the base of MOSFET M5 is connected to the base of MOSFET M6. The other end of the third capacitor C3 is connected to the collectors of MOSFETs M5 and M6. The emitter of MOSFET M5 is connected to the first output terminal. The emitters of MOSFET M3, the collectors of MOSFET M4, and the emitters of MOSFET M6 are grounded. MOSFETs M3 and M6 are NMOS transistors, and MOSFETs M3 and M5 are PMOS transistors. The second switching unit includes MOSFETs M7, M8, M9, and M10. One end of the fourth capacitor C4 is connected to the second input terminal, and the other end is connected to the collector of MOSFET M7, the emitter of MOSFET M8, and the base. The base of MOSFET M7 is connected to the collectors of MOSFETs M9 and M10. The base of MOSFET M9 is connected to the base of MOSFET M10 and the other end of the fourth capacitor C4. The emitter of MOSFET M9 is connected to the second output terminal. The emitters of MOSFETs M7, M8, and M10 are grounded. MOSFETs M7 and M10 are NMOS transistors, and MOSFETs M8 and M9 are PMOS transistors. The first switching unit is used to adjust the first voltage signal to obtain the third voltage signal X1, and the second switching unit is used to adjust the second voltage signal to obtain the fourth voltage signal X2.

[0042] See Figure 6 The third switching unit includes MOSFETs M11, M12, M13, and M14. The base of MOSFET M11, the base of MOSFET M12, and the collector of MOSFET M13 are all connected to the other end of the third capacitor C3. The emitter of MOSFET M11 is connected to the first output. The collector of MOSFET M11 is connected to the collector of MOSFET M12 and the base of MOSFET M13, respectively. The collector of MOSFET M13 is connected to the collector of MOSFET M14. The emitters of MOSFETs M12, M13, and M14 are connected to the emitters of MOSFETs M16, M17, and M19 in the fourth switching unit, one end of the fifth capacitor C5, the base of MOSFET M16, and the voltage output terminal, respectively. MOSFET M11 is an NMOS transistor, and MOSFETs M12, M13, and M14 are PMOS transistors. The fourth switching unit includes a fifth capacitor C5, MOSFETs M16, M17, and M19, and also includes a MOSFET M18. The collector of MOSFET M16 is connected to the collector of MOSFET M17, and the base of MOSFET M17 is connected to the collectors of MOSFETs M18 and M19 respectively. The emitter of MOSFET M18 is connected to the second output terminal. The bases of MOSFETs M18 and M19, and the collector of MOSFET M17 are all connected to the other end of the fourth capacitor C4. MOSFET M18 is an NMOS transistor, and MOSFETs M16, M17, and M19 are PMOS transistors. The third and fourth switching units are used to control the third voltage signal X1 and the fourth voltage signal X2 respectively, so that the voltage output terminal continuously outputs voltage Vneg, and the output voltage Vneg = -Vin.

[0043] In the method of generating negative pressure using the above-mentioned negative pressure charge pump, the control circuit is used to generate driving voltages: a first voltage signal xp, a second voltage signal xn, and a first switching unit and a second switching unit, which respectively include a third capacitor and a fourth capacitor. Under the action of complementary and non-overlapping clock signals CLK1 and CLK2, the first voltage, the second voltage, the third capacitor, and the fourth capacitor, the other ends of the third capacitor and the fourth capacitor respectively output the third voltage signal X1 and the fourth voltage signal X2. Under the action of clock signals CLK1 and CLK2, the second voltage signal xn, and the third voltage signal X1, the first switching unit and the third switching unit are turned on, and the second switching unit and the fourth switching unit are turned off, so that the voltage output terminal outputs voltage Vneg. Under the action of clock signals CLK1 and CLK2, the first voltage signal xp, and the fourth voltage signal X2, the second switching unit and the fourth switching unit are turned on, and the first switching unit and the third switching unit are turned off, so that the voltage output terminal outputs voltage Vneg, thereby realizing the continuous output of the output voltage Vneg.

[0044] The specific steps for generating negative voltage include: S1, inputting complementary non-overlapping clock signals CLK1 and CLK2 to the first and second input terminals of the control circuit, and simultaneously inputting complementary non-overlapping clock signals CLK1 and CLK2 to one end of the third capacitor of the first switching unit and one end of the fourth capacitor of the second switching unit. Since the values ​​of the third capacitor C3 and the fourth capacitor C4 are greater than the values ​​of the first capacitor C1 and the second capacitor C2, the charging and discharging time of the third capacitor C3 and C4 is delayed compared to that of the first capacitor C1 and the second capacitor C2, so that the first voltage signal xn or the second voltage signal xp has sufficient time to drive the MOSFET M3 or M7 to conduct.

[0045] S2. Simultaneously with step S1, a first voltage and a second voltage are input to the first input terminal and the second input terminal of the control circuit, respectively. At the same time, a first voltage and a second voltage are input to one end of the third capacitor and one end of the fourth capacitor, respectively. The value of the first voltage is not equal to the value of the second voltage. In this embodiment, the value of the first voltage is 2.8V, and the second voltage is grounded to zero.

[0046] S3. In the control circuit, under the action of MOSFETs M1 and M2, the first capacitor C1 and the second capacitor C2 are charged and discharged, so that the first output terminal and the second output terminal of the control circuit output the first voltage signal xp and the second voltage signal xn respectively; in this embodiment, the first voltage signal xp is 2.8V and the second voltage signal xn is 0V.

[0047] S4. In the first and second switching units, under the charging and discharging action of the third capacitor C3 and the fourth capacitor C4, the output voltage of the first switching unit is the third voltage signal X1, and the output voltage of the second switching unit is the fourth voltage signal X2. Specifically, the first voltage signal xp and the second voltage signal xn serve as the voltage drivers for MOSFETs M5 and M9, respectively, turning on MOSFETs M5 and M9. At the same time, under the action of the first voltage signal X1, the second voltage signal X2, and the clock signals CLK11 and CLK12, the third capacitor C3 and the fourth capacitor C4 are charged. After charging, the voltages at the other ends of the third capacitor C3 and the fourth capacitor C4 are 0V and 2.8V, respectively. MOSFET M3 is turned on under the combined action of the first voltage signal xn and the third voltage signal X1, and transmits the third voltage signal to the third switching unit. MOSFETs M7 and M9 are turned off under the combined action of the second voltage signal xp and the fourth voltage signal X2, thereby putting the subsequent fourth switching unit in the off state. When clock signals CLK1 and CLK2 switch, the first switch unit is turned off, the third switch unit is turned off, the second switch unit is turned on, and the fourth switch unit is turned on. MOSFET M4 is used to provide a start signal to MOSFET M3 because the emitter and base of MOSFET M4 are both connected to the third voltage signal X1, while the gate voltage of MOSFET M3 needs to be provided by the voltage after MOSFET M5 is turned on. Therefore, MOSFET M4 turns on before MOSFET M3, thus providing the turn-on voltage for MOSFET M3 and enabling MOSFET M3 to turn on quickly.

[0048] The specific principle behind MOSFET M3 being turned on under the combined action of the first voltage signal xn and the third voltage signal X1, and transmitting the third voltage signal to the third switching unit, is as follows: Clock signals CLK1 / CLK2 are non-overlapping complementary signals, with a high level of Vin and a low level of 0. When CLK1 is high, the first voltage signal X1 is pushed high, Xn is at a low level of -Vin, MOSFET M5, being an NMOS transistor, is turned on. Since MOSFET M3 is a PMOS transistor and its gate is at a low level of -Vin, MOSFET M3 is turned on, and the third voltage signal X1 is pushed high to a higher level of 0V. MOSFET M6, being a PMOS transistor, is turned off at this time. At the same time, the clock signal CLK2 is low, the fourth voltage signal X2 is pulled low, Xp is high at 0V, MOSFET M10 is a PMOS transistor and is turned on, MOSFET M7 is a PMOS transistor and its gate is 0V, so MOSFET M7 is turned off, the fourth voltage signal X2 is pulled low to -Vin, and MOSFET M9 is an NMOS transistor and is turned off.

[0049] When the signal switches, and the clock signal CLK2 is high and CLK1 is low, the principle is the same as the first switching unit. At this time, the MOS transistor M7 in the second switching unit is turned on, and the switches M3 and M5 are turned off. The fourth voltage signal X2 flows into the fourth switching unit through the MOS transistor M7, and the fourth switching unit is turned on.

[0050] S4. The first voltage signal xp is sent to the first signal input terminal of the second switch unit and the fourth switch unit respectively, and the second voltage signal xn is sent to the first signal input terminal of the first switch unit and the third switch unit respectively; the third voltage signal X1 is sent to the third switch unit, and the fourth voltage signal X2 is sent to the fourth switch unit.

[0051] S5. Under the action of clock signal CLK1, second voltage signal xn, and third voltage signal X1, the third switching unit is turned on and the fourth switching unit is turned off, so that the voltage output terminal outputs voltage Vneg; MOS transistors M11, M13, and M14 in the third switching unit are turned on under the combined action of second voltage signal xn and third voltage signal X1. MOS transistors M11 and M12 form an inverter, which inverts the third voltage signal X1, so that the value of the output voltage Vneg at the voltage output terminal is -2.8V.

[0052] S6. Under the action of clock signal CLK2, first voltage signal xp, and fourth voltage signal X2, the fourth switching unit is turned on, and the third switching unit is turned off, causing the voltage output terminal to output voltage Vneg, thus achieving continuous output of voltage Vneg. MOSFETs M18, M17, and M16 in the fourth switching unit are turned off under the combined action of the first voltage signal xp and the fourth voltage signal X2. When the CLK11 and CLK12 signals flip, MOSFETs M11, M13, and M14 in the third switching unit are turned off, while MOSFETs M18, M17, and M16 in the fourth switching unit are turned on, causing the voltage output terminal to continuously output voltage Vneg of -2.8V.

[0053] In this negative voltage charge pump, since the clock signals CLK1 and CLK2 are non-overlapping complementary clock signals, their high-low level switching will cause the high-low level switching of the first voltage signal xp and the second voltage signal xn, as well as the high-low level switching of the third voltage signal X1 and the fourth voltage signal X2. The MOSFETs M5 / M6 and M9 / M10 of the first / second switching unit act together on the gate of the MOSFET M3 / M7 under the first voltage signal xp / second voltage signal xn and the third voltage signal X1 / fourth voltage signal X2. Therefore, the signals used to control the MOSFETs M3 / M7 of the first / second switching unit are non-overlapping complementary signals, thus avoiding the weak conduction of the MOSFETs in the first and second switching units at the same time, i.e., avoiding clock feedthrough caused by signal overlap, reducing power loss caused by weak conduction, improving output voltage stability, and ensuring that the output voltage meets the expected voltage requirements for the turn-off of the RF switching devices.

[0054] The aforementioned negative charge pump is applied to an RF switch chip, which includes a driving voltage module, a level conversion module, and an RF switch connected in sequence. The driving voltage module includes a positive charge pump and the aforementioned negative charge pump. The positive charge pump is used to provide positive voltage to the level conversion module, and the negative charge pump is used to provide negative voltage to the level conversion module. The level conversion module is used to convert the positive and negative voltages into a control voltage, which is used to control the opening or closing of the switch in the RF switch.

[0055] Figure 7 Simulation results of the input voltage Vin and output voltage Vneg using the negative voltage charge pump of this application are presented. Figure 7 The horizontal axis represents time dx, and the vertical axis represents voltage Vin, clock CLK, and output voltage Vneg, respectively. Curve B represents the change of clock signal CLK, and curves A and C represent the changes of voltage Vin and output voltage Vneg under the control of complementary non-overlapping clock signals CLK1 and CLK2 generated by clock signal CLK, respectively. Time dx = 216 ns is one clock cycle. Figure 7 It can be seen that within one clock cycle, as the input voltage Vin changes, the negative voltage Vneg output by the negative voltage charge pump changes accordingly, and it can continuously output a stable negative voltage signal. Furthermore, this negative voltage signal can reach approximately 2.8V, which meets the control requirements of the subsequent RF switch.

[0056] The above are merely preferred embodiments of this application, and the present invention is not limited to the above embodiments. It is understood that other improvements and variations that are directly derived or conceived by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included within the protection scope of the present invention.

Claims

1. A method for generating negative pressure based on a negative pressure charge pump, the method being implemented based on a negative pressure charge pump, the negative pressure charge pump comprising a control circuit and a first switching unit to a second switching unit, the control circuit having an input terminal including a first input terminal and a second input terminal, the control circuit having an output terminal including a first output terminal and a second output terminal, the first output terminal being connected to a first signal input terminal of a first switching unit and a first signal input terminal of a third switching unit, the second output terminal being connected to a first signal input terminal of a second switching unit and a first signal input terminal of a fourth switching unit, the first input terminal being connected to the first input terminal of the control circuit after being connected in series with a first capacitor C1, the second input terminal being connected to the second input terminal of the control circuit after being connected in series with a second capacitor C2, the first input terminal being connected to the second signal input terminal of the first switching unit after being connected in series with a third capacitor C3, the second input terminal being connected to the second signal input terminal of the second switching unit after being connected in series with a fourth capacitor C4, the output terminals of the first switching unit and the second switching unit being connected to the second signal input terminals of the third switching unit and the fourth switching unit, the output terminals of the third switching unit and the fourth switching unit being voltage output terminals; Its features are, The method includes: S1, inputting complementary non-overlapping clock signals CLK1 and CLK2 to the first input terminal and the second input terminal of the control circuit, and simultaneously inputting complementary non-overlapping clock signals CLK1 and CLK2 to one end of the third capacitor C3 of the first switching unit and one end of the fourth capacitor C4 of the second switching unit; S2. Input a first voltage and a second voltage to the first input terminal and the second input terminal of the control circuit, respectively. At the same time, input a first voltage and a second voltage to one end of the third capacitor C3 and one end of the fourth capacitor C4, respectively. The value of the first voltage is not equal to the value of the second voltage. S3. In the control circuit, under the charging and discharging action of the first capacitor C1 and the second capacitor C2, the first output terminal and the second output terminal of the control circuit respectively output the first voltage signal xp and the second voltage signal xn. S4. In the first switching unit and the second switching unit, under the charging and discharging action of the third capacitor C3 and the fourth capacitor C4, the other end of the third capacitor C3 in the first switching unit outputs a third voltage signal X1, and the other end of the fourth capacitor C4 in the second switching unit outputs a fourth voltage signal X2. S5. The first voltage signal xp is sent to the first signal input terminals of the second switch unit and the fourth switch unit respectively, and the second voltage signal xn is sent to the first signal input terminals of the first switch unit and the third switch unit respectively; the third voltage signal X1 is sent to the third switch unit, and the fourth voltage signal X2 is sent to the fourth switch unit; S6. Under the action of clock signal CLK1, second voltage signal xn, and third voltage signal X1, the first and third switching units are turned on, and the second and fourth switching units are turned off, so that the voltage output terminal outputs voltage Vneg. S7. Under the action of clock signal CLK2, first voltage signal xp, and fourth voltage signal X2, the second and fourth switch units are turned on, and the first and third switch units are turned off, so that the voltage output terminal outputs voltage Vneg, realizing the continuous output of output voltage Vneg.

2. The negative pressure generation method based on a negative pressure charge pump according to claim 1, characterized in that, If the first voltage is 1.8V or 2.8V and the second voltage is 0V, then the first voltage signal xp and the third voltage signal X1 are 0V, the second voltage signal xn and the fourth voltage signal X2 are 1.8V or 2.8V, and the output voltage Vneg is -1.8V or -2.8V.

3. The negative pressure generation method based on a negative pressure charge pump according to claim 1 or 2, characterized in that, The control circuit and the first to fourth switching units all include MOSFETs. The first input terminal is connected to the control circuit through a first capacitor C1, and the first input terminal is connected to the first switching unit through a third capacitor C3. The second input terminal is connected to the control circuit through a second capacitor C2, and the second input terminal is connected to the second switching unit through a fourth capacitor C4. The values ​​of the first capacitor C1 and the second capacitor C2 are equal, the values ​​of the third capacitor C3 and the fourth capacitor C4 are equal, and the values ​​of the third capacitor C3 and the fourth capacitor C4 are greater than the values ​​of the first capacitor C1 and the second capacitor C2.

4. The negative pressure generation method based on a negative pressure charge pump according to claim 3, characterized in that, The control circuit also includes MOSFETs M1 and M2. The first input terminal and the second input terminal are respectively connected to one end of the first capacitor C1 and the second capacitor C2. The first capacitor C1 is connected to the collector of MOSFET M1, the base of MOSFET M2, and the first output terminal. The other end of the second capacitor C2 is connected to the collector of MOSFET M2, the base of MOSFET M1, and the second output terminal. The emitters of MOSFETs M1 and M2 are connected to ground. Both MOSFETs M1 and M2 are NMOS transistors.

5. The negative pressure generation method based on a negative pressure charge pump according to claim 4, characterized in that, The first switching unit further includes MOSFETs M3, M4, M5, and M6. One end of the third capacitor C3 is connected to the first input terminal, and the other end is connected to the collector of MOSFET M3, the emitter and base of MOSFET M4, the base of MOSFET M5 and the base of MOSFET M6. The other end of the third capacitor C3 is connected to the collectors of MOSFETs M5 and M6. The emitter of MOSFET M5 is connected to the first output terminal. The emitters of MOSFET M3, the collectors of MOSFET M4, and the emitters of MOSFET M6 are grounded. MOSFETs M3 and M6 are NMOS transistors, and MOSFETs M4 and M5 are PMOS transistors.

6. The negative pressure generation method based on a negative pressure charge pump according to claim 5, characterized in that, The second switching unit includes MOSFETs M7, M8, M9, and M10. One end of the fourth capacitor C4 is connected to the second input terminal, and the other end is connected to the collector of MOSFET M7, the emitter of MOSFET M8, and the base. The base of MOSFET M7 is connected to the collectors of MOSFETs M9 and M10. The base of MOSFET M9 is connected to the base of MOSFET M10 and the other end of the fourth capacitor C4. The emitter of MOSFET M9 is connected to the second output terminal. The emitters of MOSFET M7, M8, and M10 are grounded. MOSFETs M7 and M10 are NMOS transistors, and MOSFETs M8 and M9 are PMOS transistors.

7. The negative pressure generation method based on a negative pressure charge pump according to claim 6, characterized in that, The third switching unit includes MOSFETs M11, M12, M13, and M14. The base of MOSFET M11, the base of MOSFET M12, and the collector of MOSFET M13 are all connected to the other end of the third capacitor C3. The emitter of MOSFET M11 is connected to the first output terminal. The collector of MOSFET M11 is connected to the collector of MOSFET M12 and the base of MOSFET M13, respectively. The collector of MOSFET M13 is connected to the collector of MOSFET M14. The emitters of MOSFETs M12, M13, and M14 are connected to the emitters of MOSFETs M16, M17, M18, and M19 in the fourth switching unit, one end of the fifth capacitor C5, the base of MOSFET M16, and the voltage output terminal, respectively. MOSFET M11 is an NMOS transistor, and MOSFETs M12, M13, and M14 are PMOS transistors.

8. The negative pressure generation method based on a negative pressure charge pump according to claim 7, characterized in that, The fourth switching unit includes the fifth capacitor C5, MOSFETs M16, M17, M18, and M19. The collector of MOSFET M16 is connected to the collector of MOSFET M17. The base of MOSFET M17 is connected to the collectors of MOSFETs M18 and M19 respectively. The emitter of MOSFET M18 is connected to the second output terminal. The bases of MOSFETs M18 and M19 and the collector of MOSFET M17 are all connected to the other end of the fourth capacitor C4. MOSFET M18 is an NMOS transistor, and MOSFETs M16, M17, and M19 are PMOS transistors.

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