processor

Abstract

The present application relates to a processor, comprising: a temperature detection component, configured to detect the temperature of the processor; a vector length level register, configured to store the vector length level of the processor, wherein the processor performs vector calculation with the vector length corresponding to the vector length level stored in the vector length level register; and a vector length level update component, configured to update the vector length level stored in the vector length level register based on the temperature of the processor.

Description

Technical Field

[0001] The present disclosure generally relates to the field of computers, and more particularly to a processor. Background Art

[0002] A Reduced Instruction Set Computer (RISC) processor is a processor that executes fewer types of computer instructions. The basic starting point of a RISC processor is to reduce the complexity of hardware design by streamlining the machine instruction system while increasing the speed of instruction execution. In a RISC processor, both simple and complex operations are completed by blocks of simple instructions. Summary of the invention

[0003] A processor according to an embodiment of the present disclosure includes: a temperature detection component configured to detect the temperature of the processor; a vector length level register configured to store the vector length level of the processor, wherein the processor performs vector calculations with the vector length corresponding to the vector length level stored in the vector length level register; and a vector length level updating component configured to update the vector length level stored in the vector length level register based on the temperature of the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Embodiments of the present disclosure will be illustrated by way of example and not limitation in the accompanying figures in which like reference numerals refer to similar elements.

[0005] Figure 1A An example block diagram of a processor according to an embodiment of the present disclosure is shown.

[0006] Figure 1B Shows Figure 1A A flow chart of an example process by which a processor adaptively changes its vector length is shown.

[0007] Figure 2 A block diagram of an example computing device is shown in which a processor according to various embodiments of the present disclosure may be used. DETAILED DESCRIPTION

[0008] The various aspects of the illustrative embodiments will be described using terms commonly used by those skilled in the art to convey the essence of the present disclosure to other persons skilled in the art. However, it will be apparent to those skilled in the art that many alternative embodiments may be implemented using the parts of the described aspects. For purposes of explanation, specific numbers, materials, and configurations are provided to provide a thorough understanding of the illustrative embodiments. However, it will be apparent to those skilled in the art that alternative embodiments may be implemented without these specific details. In other examples, known features may be omitted or simplified in order to avoid blurring the illustrative embodiments.

[0009] In addition, various operations are described as multiple discrete operations in sequence in a manner that is most helpful for understanding the illustrative embodiments; however, the order of description should not be interpreted as implying that these operations must be order-dependent. In particular, these operations do not need to be performed in the order presented.

[0010] The phrases "in an embodiment," "in one embodiment," and "in some embodiments" are used repeatedly herein. These phrases generally do not refer to the same embodiment; however, they may refer to the same embodiment. Unless the context dictates otherwise, the terms "comprising," "having," and "including" are synonymous. The phrases "A or B" and "A / B" mean "(A), (B), or (A and B)."

[0011] Typically, a central processing unit (CPU) has a dynamic frequency scaling feature, in which the CPU actively reduces the operating frequency and / or voltage when its temperature is too high (this operation is called CPU throttling). Excessive temperature can cause hardware damage to the CPU, and CPU throttling can reduce the heat generated by the CPU's data processing operations, helping the CPU to control its temperature within the operating range. The side effect is that the performance of the entire CPU will be greatly reduced because all components of the CPU (including the CPU core, embedded memory controller, and vector computing components, etc.) must operate at low frequencies and / or voltages.

[0012] The vector computing unit is an important component of the CPU and is crucial for the CPU to perform high-performance computing. Here, the number of data blocks of a specific size that the vector computing unit can process simultaneously is called the vector length of the CPU or the vector computing unit (hereinafter, the vector length of the CPU and the vector length of the vector computing unit can be used interchangeably). Generally, the vector computing unit can support multiple vector length configurations, but always tells the software (for example, the compiler or application) the maximum vector length it supports, so the software will send data to the vector computing unit with the maximum vector length supported by the vector computing unit. Different vector length configurations mean different computing speeds and power consumption when performing calculations on the same vector computing unit. For a data set, the larger the vector length of the CPU and the faster the calculation speed, the more heat generated by the data processing operation, and the higher the temperature of the CPU.

[0013] In order to perform calculations more efficiently, the CPU can choose a larger vector length. However, when the temperature of the CPU is close to the temperature that triggers CPU throttling, a better choice is to reduce the vector length of the CPU to avoid CPU throttling. Because CPU throttling will reduce the performance of all parts of the CPU, while a smaller vector length will only reduce the performance of the vector calculation part.

[0014] In view of the above situation, a processor according to an embodiment of the present disclosure is proposed, which can adaptively change its vector length according to its temperature.

[0015] Figure 1A An example block diagram of a processor according to an embodiment of the present disclosure is shown. Figure 1A As shown, a processor 100 (e.g., a RISC processor) according to an embodiment of the present disclosure includes a temperature detection component 102, a vector length level register 1042, and a vector length level update component 1044, wherein: the temperature detection component 102 is configured to detect the temperature of the processor 100; the vector length level register 1042 is configured to store the vector length level of the processor 100, wherein the processor 100 performs vector calculations with the vector length corresponding to the vector length level stored in the vector length level register 1042; and the vector length level update component 1044 is configured to update the vector length level stored in the vector length level register 1042 based on the temperature of the processor 100.

[0016] In some embodiments, the vector length level updating component 1044 may find the vector length level corresponding to the temperature of the processor 100 in a pre-built temperature-to-vector length level lookup table, and update the vector length level stored in the vector length level register 1042 to the vector length level corresponding to the temperature of the processor 100. For example, when the vector length level corresponding to the temperature of the processor 100 is not equal to the vector length level stored in the vector length level register 1042, the vector length level updating component 1044 may update the vector length level stored in the vector length level register 1042 to the vector length level corresponding to the temperature of the processor 100.

[0017] In some embodiments, the vector length level register 1042 may store a length level change bit, which is used to indicate whether the vector length level stored in the vector length level register 1042 is changed. For example, if the vector length level stored in the vector length level register 1042 is changed, the length level change bit is 1, otherwise the vector length level is preferably changed bit is 0. In this case, the vector length level update component 1044 may update the vector length level stored in the vector length level register 1042 to the vector length level corresponding to the temperature of the processor 100 when the length level change bit indicates that the vector length level stored in the vector length level register 1042 is not changed. In addition, the vector length level update component 1044 may also set the length level change bit to indicate that the vector length level stored in the vector length level register 1042 is changed when updating the vector length level stored in the vector length level register 1042 to the vector length level corresponding to the temperature of the processor 100.

[0018] like Figure 1A As shown, in some embodiments, the temperature detection component 102, the vector length level register 1042, and the vector length level update component 1044 can be hardware components included in the processor 100 and are independent of software programming, which can benefit all users and applications. That is, regardless of the situation of the user and the application, the vector length thereof can be adaptively changed according to the temperature of the processor 100.

[0019] like Figure 1AAs shown, in some embodiments, the vector length level register 1042 and the vector length level update component 1044 may be hardware components included in the vector calculation component 104 of the processor 100. In this case, the vector calculation component 104 may adaptively change its vector length according to the temperature of the processor 100. Specifically, the vector calculation component 104 may check whether its vector length needs to be changed according to the temperature of the processor 100, and change it to a vector length corresponding to the temperature of the processor 100 when it needs to be changed, and then perform vector calculation with the changed vector length.

[0020] like Figure 1A As shown, in some embodiments, the processor 100 according to the embodiment of the present disclosure further includes a vector instruction dispatcher 106, which is configured to reconfigure the vector length of the processor 100 to the vector length corresponding to the vector length level stored in the vector length level register 1042 when the length level change bit indicates that the vector length level stored in the vector length level register 1042 is changed.

[0021] In some embodiments, the vector instruction allocator 106 may also set the length level change bit to indicate that the vector length level stored in the vector length level register 1042 has not been changed when reconfiguring the vector length of the processor 100 to the vector length corresponding to the vector length level stored in the vector length level register 1042.

[0022] In some embodiments, the vector instruction allocator 106 may also continue to execute the current vector instruction or allocate a new vector instruction to the vector computation unit 104 without reconfiguring the vector length of the processor 100 when the length level change bit indicates that the vector length level stored in the vector length level register 1042 has not been changed.

[0023] like Figure 1A As shown, in some embodiments, the processor 100 according to an embodiment of the present disclosure further includes a power control module 108, which is configured to turn on or off each vector computing unit (e.g., vector computing units 1046-1 to 1046-N, N is an integer greater than or equal to 1) in the vector computing component 104 under the control of the vector instruction distributor 106. For example, the vector instruction distributor 106 may control the power control module 108 to turn off a predetermined number of vector computing units in the vector computing component 104 when the temperature of the processor 100 is higher than or equal to a predetermined temperature threshold, and / or control the power control module 108 to turn on all vector computing units in the vector computing component 104 when the hardware temperature of the processor 100 is lower than a predetermined temperature threshold.

[0024] In some embodiments, the vector instruction distributor 106 may check whether the length level change bit indicates that the vector length level stored in the vector length level register 1042 is changed when a preset vector length level checkpoint is reached. Specifically, the vector instruction distributor 106 may be provided with at least one vector length level checkpoint. When any vector length level checkpoint is reached, the vector instruction distributor 106 may check the length level change bit to determine whether to reconfigure the vector length of the processor 100. When the length level change bit indicates that the vector length level stored in the vector length level register 1042 is changed, the vector instruction distributor 106 reconfigures the vector length of the processor 100 and then distributes the next vector instruction.

[0025] In some embodiments, the beginning of a new vector instruction may be used as a vector length level checkpoint. The vector instruction distributor 106 may be a hardware component included in the processor 100. The power control module 108 may include a multi-threshold complementary metal oxide semiconductor (MTCMOS) array (i.e., the MTCMOS array may be used to turn on or off some vector computing units in the vector computing component 104).

[0026] Figure 1B Shows Figure 1A Flowchart of an example process for a processor to adaptively change its vector length. Figure 1B As shown, in some embodiments, the processor 100 according to an embodiment of the present disclosure may adaptively change its vector length through the following two stages:

[0027] The vector length level update phase includes the following steps:

[0028] Step 1.1: The vector length level updating component 1044 receives temperature data indicating the temperature of the processor 100 from the temperature detection component 102, and finds the vector length level corresponding to the temperature of the processor 100 in a pre-built temperature to vector length level lookup table. Table 1 gives an example of the temperature to vector length level lookup table.

[0029] Table 1

[0030]

[0031] Step 1.2: The vector length level updating component 1044 checks whether the vector length level stored in the vector length level register 1042 is equal to the vector length level corresponding to the temperature of the processor 100. If they are equal, the vector length level stored in the vector length level register 1042 is not updated, otherwise it is determined whether the length level change bit indicates that the vector length level stored in the vector length level register 1042 is changed (for example, the length level change bit is 1 or 0). If the vector length level stored in the vector length level register 1042 is changed (for example, the length level change bit is 1), the vector length level stored in the vector length level register 1042 is not updated, otherwise step 1.3 is executed.

[0032] Step 1.3: The vector length level updating component 1044 updates the vector length level stored in the vector length level register 1042 to the vector length level corresponding to the temperature of the processor 100 .

[0033] Step 1.4: The vector length level updating component 1044 changes the length level change bit to indicate that the vector length level stored in the vector length level register 1042 is changed (eg, changes the length level change bit from 0 to 1).

[0034] The vector instruction allocation stage includes the following steps:

[0035] Step 2.1: The vector instruction dispatcher 106 starts executing the current vector instruction or reaches a vector length level checkpoint.

[0036] Step 2.2: The vector instruction dispatcher 106 checks whether the length level change bit indicates that the vector length level stored in the vector length level register 1042 is changed. If the length level change bit indicates that the vector length level stored in the vector length level register 1042 is not changed (for example, the value of the length level change bit is 0), step 2.6 is executed; if the length level change bit indicates that the preferred vector length level stored in the vector length level register 1042 is changed (for example, the value of the length level change bit is 1), step 2.3 is executed.

[0037] Step 2.3: The vector instruction dispatcher 106 reads the vector length level stored in the vector length level register 1042.

[0038] Step 2.4: The vector instruction dispatcher 106 changes the length level change bit to indicate that the vector length level stored in the vector length level register 1042 is not changed (eg, changes the value of the length level change bit from 1 to 0).

[0039] Step 2.5: The vector instruction distributor 106 finds the vector length corresponding to the vector length level read from the vector length level register 1042 from the pre-built vector length level comparison table, and reconfigures the vector length of the processor 100 to the found vector length. Table 2 gives an example of the vector length level comparison table.

[0040] Table 2

[0041]

[0042] Step 2.6: The vector instruction distributor 106 continues to execute the current vector instruction or distributes a new vector instruction to the vector computing unit 104 without reconfiguring the vector length of the processor 100.

[0043] Step 2.7: If the hardware temperature of the processor 100 is higher than the predetermined temperature threshold, the vector instruction distributor 106 controls the power control module 108 to turn off a predetermined number of vector computing units in the vector computing component 104. If the hardware temperature of the processor 100 is lower than the predetermined temperature threshold, the vector instruction distributor 106 controls the power control module 108 to turn on all vector computing units in the vector computing component 104.

[0044] Figure 2 A block diagram of an example computing device in which a processor according to various embodiments of the present disclosure may be used is shown. Specifically, Figure 2 The illustrated computing device 200 includes one or more processors (or processor cores) 210, one or more memory / storage devices 220, and one or more communication resources 230, each of which may be communicatively coupled via a bus 240 or other interface circuitry. For embodiments utilizing node virtualization (e.g., network function virtualization (NFV)), a hypervisor 202 may be executed to provide an execution environment for one or more network slices / subslices to utilize the hardware resources of the computing device 200.

[0045] Processor 210 may include, for example, processor 212 and processor 214. Processor 210 may be, for example, a central processing unit (CPU), a reduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, a graphics processing unit (GPU), a digital signal processor (DSP) such as a baseband processor, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a radio frequency integrated circuit (RFIC), another processor (including those discussed herein), or any suitable combination thereof.

[0046] The memory / storage device 220 may include a main memory, a disk storage device, or any suitable combination thereof. The memory / storage device 220 may include, but is not limited to, any type of volatile, non-volatile, or semi-volatile memory, such as, for example, a dynamic random access memory (DRAM), a static random access memory (SRAM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), flash memory, solid-state memory, etc.

[0047] The communication resources 230 may include interconnect or network interface controllers, components, or other suitable devices to communicate with one or more peripheral devices 204 or one or more databases 206 or other network elements via the network 208. For example, the communication resources 230 may include wired communication components (e.g., for coupling via USB, Ethernet, etc.), cellular communication components, near field communication (NFC) components, Bluetooth® (or Bluetooth® low energy) components, Wi-Fi® components, and other communication components.

[0048] The instructions 250 may include software, programs, applications, applets, applications, or other executable code for causing at least any one of the processors 210 to perform various processing procedures. The instructions 250 may reside in whole or in part in at least one of the processors 210 (e.g., in a cache of the processor), the memory / storage device 220, or any suitable combination thereof. In addition, any portion of the instructions 250 may be transmitted to the hardware resources 200 from any combination of the peripheral device 204 or the database 206. Therefore, the memory of the processor 210, the memory / storage device 220, the peripheral device 204, and the database 206 are examples of computer-readable and machine-readable media.

[0049] Although certain embodiments have been illustrated and described herein for purposes of description, the embodiments illustrated and described may be replaced with a variety of alternative and / or equivalent embodiments or implementations that achieve the same purpose without departing from the scope of the present disclosure. This application is intended to cover any adaptation or variation of the embodiments discussed herein. Therefore, the embodiments described herein are expressly limited only by the appended claims and their equivalents.

Claims

1. A processor, comprising: a temperature detection component configured to detect the temperature of the processor; a vector length level register configured to store a vector length level of the processor, wherein the processor performs vector calculations with a vector length corresponding to the vector length level stored in the vector length level register, wherein the vector length refers to the number of data blocks of a specific size that the processor can process simultaneously; as well as A vector length level updating component is configured to update the vector length level stored in the vector length level register based on the temperature of the processor.

2. The processor according to claim 1, wherein: The vector length level updating component is further configured to find the vector length level corresponding to the temperature of the processor in a pre-built temperature-to-vector length level lookup table, and update the vector length level stored in the vector length level register to the vector length level corresponding to the temperature of the processor.

3. The processor according to claim 1, wherein: The vector length level updating component is also configured to update the vector length level stored in the vector length level register to the vector length level corresponding to the temperature of the processor when the vector length level corresponding to the temperature of the processor is not equal to the vector length level stored in the vector length level register.

4. The processor according to claim 1, wherein: The vector length level register is further configured to store a length level change bit, wherein the length level change bit is used to indicate whether the vector length level stored in the vector length level register is changed.

5. The processor according to claim 4, wherein: The vector length level updating component is further configured to update the vector length level stored in the vector length level register to a vector length level corresponding to the temperature of the processor when the length level change bit indicates that the vector length level stored in the vector length level register has not been changed.

6. The processor according to claim 4, wherein: The vector length level updating component is further configured to, when updating the vector length level stored in the vector length level register to the vector length level corresponding to the temperature of the processor, set the length level change bit to indicate that the vector length level stored in the vector length level register is changed.

7. The processor of claim 4, further comprising: The vector instruction distributor is configured to reconfigure the vector length of the processor to the vector length corresponding to the vector length level stored in the vector length level register when the length level change bit indicates that the vector length level stored in the vector length level register is changed.

8. The processor according to claim 7, wherein: The vector instruction distributor is further configured to, when reconfiguring the vector length of the processor to the vector length corresponding to the vector length level stored in the vector length level register, set the length level change bit to indicate that the vector length level stored in the vector length level register is not changed.

9. The processor according to claim 7, wherein: The vector instruction distributor is further configured to, if the length level change bit indicates that the vector length level stored in the vector length level register has not been changed, continue to execute the current vector instruction or distribute a new vector instruction to the vector computing component of the processor without reconfiguring the vector length of the processor.

10. The processor of claim 7, further comprising: A power control module is configured to, under the control of the vector instruction distributor, turn on or off each vector computing unit in the vector computing component of the processor, wherein the vector instruction distributor is further configured to control the power control module to turn off a predetermined number of vector computing units in the vector computing component when the temperature of the processor is higher than or equal to a predetermined temperature threshold.

11. The processor of claim 10, wherein: The vector instruction distributor is further configured to control the power control module to turn on all vector computing units in the vector computing component when the temperature of the processor is lower than the predetermined temperature threshold.

12. The processor of claim 7, wherein: The vector instruction dispatcher is further configured to check, when a preset vector length level check point is reached, whether the length level change bit indicates that the vector length level stored in the vector length level register is changed.

13. The processor of claim 12, wherein: The vector length level checkpoint includes the start of a new vector instruction.

14. The processor of claim 1, wherein: The temperature detection unit, the vector length level register, and the vector length level update unit are hardware components included in the processor.

15. The processor of claim 14, wherein: The vector length rank register and the vector length rank update component are hardware components included in a vector calculation component of the processor.

16. The processor of claim 7, wherein: The vector instruction distributor is a hardware component included in the processor.

17. The processor of claim 10, wherein: The power control module includes a multi-threshold complementary metal oxide semiconductor (CMOS) array.

18. The processor of claim 1, wherein: The processor is a Reduced Instruction Set Computer (RISC) processor.

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