A digital-analog hybrid circuit, a control method, a chip, a device and a storage medium

Abstract

The application provides a digital-analog hybrid circuit, a control method, a chip, equipment and a storage medium. The digital-analog hybrid circuit comprises a digital circuit, an analog circuit, a handshake detection circuit and a processor. The handshake detection circuit is connected with the digital circuit and the analog circuit respectively, and the processor is connected with the digital circuit, the analog circuit and the handshake detection circuit respectively. The handshake detection circuit is used for acquiring a digital-analog conversion signal, detecting the digital-analog conversion signal, outputting a corresponding target error signal when it is detected that the digital-analog conversion signal meets a target error condition, acquiring an analog-digital feedback signal, detecting the analog-digital feedback signal, and outputting a corresponding target error signal when it is detected that the analog-digital feedback signal meets the target error condition. The processor is used for acquiring the target error signal and instructing the processor to configure the digital circuit and / or the analog circuit based on the target error signal.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a mixed-signal circuit, control method, chip, device and storage medium. Background Technology

[0002] In modern control, communication, and detection fields, digital computer technology is widely used for signal processing. Since the actual objects processed by these systems are often analog quantities, such as temperature, pressure, displacement, and images, analog signals must be converted into digital signals for the digital computer to recognize and process them. Conversely, the digital quantities output after computer analysis and processing often need to be converted back into corresponding analog signals before they can be received by the actuators. Therefore, digital-to-analog conversion and analog-to-digital conversion are widely used in circuits, such as... Figure 1 As shown, the only connection between digital and analog circuits is the signal connection between the digital logic and analog logic parts. Based on this, when a conversion error occurs between digital and analog circuits during operation, it is usually difficult to detect, which affects the normal operation of the circuit. Summary of the Invention

[0003] This application provides a mixed-signal circuit, control method, chip, device, and storage medium to at least solve the above-mentioned technical problems existing in the prior art.

[0004] According to a first aspect of this application, a mixed-signal circuit is provided, comprising a digital circuit, an analog circuit, a handshake detection circuit, and a processor. The handshake detection circuit is connected to both the digital circuit and the analog circuit, and the processor is connected to both the digital circuit, the analog circuit, and the handshake detection circuit. The digital circuit is configured to generate a digital-to-analog conversion signal and acquire a detected analog-to-digital feedback signal, wherein the digital-to-analog conversion signal is a digital signal. The analog circuit is configured to generate an analog-to-digital feedback signal corresponding to the digital-to-analog conversion signal and acquire a detected digital-to-analog conversion signal, wherein the analog-to-digital feedback signal is a digital signal. The handshake detection circuit is configured to acquire the digital-to-analog conversion signal and detect the digital-to-analog conversion signal. When the digital-to-analog conversion signal is detected to meet a target error condition, a corresponding target error signal is output. The handshake detection circuit is further configured to acquire the analog-to-digital feedback signal and detect the analog-to-digital feedback signal. When the analog-to-digital feedback signal is detected to meet the target error condition, a corresponding target error signal is output. The processor is configured to acquire the target error signal and, based on the target error signal, instruct the processor to configure the digital circuit and / or the analog circuit.

[0005] In one embodiment, the handshake detection circuit includes a verification sub-circuit and a detection sub-circuit; the verification sub-circuit is used to acquire the digital-to-analog conversion signal or analog-to-digital feedback signal, and output a digital-to-analog conversion signal or analog-to-digital feedback signal accompanied by the verification signal; the detection sub-circuit is used to detect the digital-to-analog conversion signal or the analog-to-digital feedback signal accompanied by the verification signal, and determine whether the digital-to-analog conversion signal or the analog-to-digital feedback signal accompanied by the verification signal meets the target error condition; the output sub-circuit is used to output a corresponding target error signal when the digital-to-analog conversion signal or the analog-to-digital feedback signal accompanied by the verification signal meets the target error condition.

[0006] In one embodiment, the handshake detection circuit includes a first detection circuit and a second detection circuit, which are connected. The first detection circuit is integrated on the digital circuit and includes a first verification sub-circuit and a first detection sub-circuit. The first verification sub-circuit is used to acquire the digital-to-analog conversion signal, process the digital-to-analog conversion signal, and output a digital-to-analog conversion signal with a verification signal. The first detection sub-circuit is used to detect the analog-to-digital feedback signal with the verification signal and determine whether the analog-to-digital feedback signal with the verification signal meets the target error condition. The second detection circuit is integrated on the analog circuit and includes a second verification sub-circuit and a second detection sub-circuit. The second verification sub-circuit is used to acquire the analog-to-digital feedback signal, process the analog-to-digital feedback signal, and output an analog-to-digital feedback signal with a verification signal. The second detection sub-circuit is used to detect the digital-to-analog conversion signal with the verification signal and determine whether the digital-to-analog conversion signal with the verification signal meets the target error condition.

[0007] In one embodiment, the verification sub-circuit includes a data signal verification unit and a control signal verification unit. Both the digital-to-analog conversion signal and the analog-to-digital feedback signal include control signals and data signals. The data signal verification unit is used to acquire the data signal, perform Hamming code verification on the data signal, and output a data signal accompanied by a Hamming code verification signal. The control signal verification unit is used to acquire the control signal, perform parity verification on the control signal, and output a control signal accompanied by a parity verification signal.

[0008] In one embodiment, the control signals include a clock control signal, a start control signal, a work control signal, a return control signal, a sampling control signal, and a configuration control signal; the detection sub-circuit includes: a time detection unit, used to start timing when the start control signal is issued, and to determine the timing time based on the return control signal; a first detection unit, connected to the time detection unit, used to determine whether a first error type is met based on a target time threshold and the timing time, the first error type being used to characterize an analog circuit error; a second detection unit, connected to the time detection unit, used to detect the configuration control signal within the timing time, and to determine whether a second error type is met based on the configuration control signal, the second error type being used to characterize a digital circuit error; and a third detection unit, connected to the time detection unit, used to detect the work control signal within the timing time, and to determine whether a first error type is met based on the work control signal, the first error type being used to characterize an analog circuit error.

[0009] In one embodiment, the verification sub-circuit further includes: a data checking unit, used to determine the data transmission error amount of the data signal accompanied by the Hamming code check signal using Hamming code; and a self-correction unit, connected to the data checking unit, which performs self-correction processing on the data signal accompanied by the Hamming code check signal if the data transmission error amount does not exceed a target error amount; the detection sub-circuit further includes: a fourth detection unit, connected to the data checking unit, which determines that the data transmission error amount conforms to a fourth error type if the data transmission error amount exceeds the target error amount, wherein the fourth error type is used to characterize that both the analog circuit and the digital circuit are faulty.

[0010] In one embodiment, the output sub-circuit includes: an interrupt unit connected to the detection sub-circuit, used to generate an interrupt signal when an error is determined in the analog circuit and / or the analog circuit is faulty; a generation unit connected to the detection sub-circuit, used to generate a corresponding error number according to the error type; and an output unit connected to the interrupt unit and the generation unit, used to output the interrupt signal and the error number to the processor.

[0011] In one embodiment, the system further includes an interrupt controller; the interrupt controller is connected to the handshake detection circuit and is configured to receive the interrupt signal and the error number and forward the interrupt signal to the processor; the processor includes a central processing unit and is configured to configure the digital circuit and / or the analog circuit according to the interrupt signal.

[0012] In one embodiment, there are multiple interrupt controllers, and the output unit is connected to the multiple interrupt controllers to output the interrupt signal and the error number to a designated interrupt controller according to the error number; there are multiple processors, and each processor corresponds to an interrupt controller, so that the designated interrupt controller forwards the interrupt signal to a designated processor.

[0013] In one possible implementation, the system further includes: an error test circuit connected to the handshake detection circuit, configured to inject a test error signal into the digital-to-analog conversion signal and / or analog-to-digital feedback signal; and a processor connected to the error test circuit, configured to instruct the error test circuit to inject the test error signal into the handshake detection circuit, and further configured to receive a test interrupt signal corresponding to the handshake detection circuit, and determine the circuit correctness of the handshake detection circuit based on the test interrupt signal.

[0014] In one embodiment, the processor is further configured to determine whether the test error signal has been traversed based on the test error signal, and if the test error signal has been traversed, to stop the error test circuit.

[0015] According to a second aspect of this application, a control method is provided for a mixed-signal circuit, the mixed-signal circuit including a digital circuit, an analog circuit, a handshake detection circuit, and a processor, the handshake detection circuit being connected to both the digital circuit and the analog circuit, and the processor being connected to both the digital circuit, the analog circuit, and the handshake detection circuit; the method includes: generating a digital-to-analog conversion signal through the digital circuit, the digital-to-analog conversion signal being a digital signal; acquiring the digital-to-analog conversion signal through the handshake detection circuit and detecting the digital-to-analog conversion signal, outputting a corresponding target error signal when the digital-to-analog conversion signal is detected to meet a target error condition; acquiring the detected digital-to-analog conversion signal through the analog circuit and generating an analog-to-digital feedback signal corresponding to the digital-to-analog conversion signal, the analog-to-digital feedback signal being a digital signal; acquiring the analog-to-digital feedback signal through the handshake detection circuit and detecting the analog-to-digital feedback signal, outputting a corresponding target error signal when the analog-to-digital feedback signal is detected to meet the target error condition; acquiring the target error signal through the processor and instructing the processor to configure the digital circuit and / or the analog circuit based on the target error signal.

[0016] According to a third aspect of this application, a chip is provided that includes an analog-digital mixed circuit as described in any of the above-described embodiments.

[0017] According to a fourth aspect of this application, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method described in any of the above-described embodiments.

[0018] According to a fifth aspect of this application, a non-transitory computer-readable storage medium is provided that stores computer instructions for causing the computer to perform the methods described in the above-described embodiments.

[0019] This application provides a mixed-signal circuit, control method, chip, device, and storage medium. By setting a handshake detection circuit between the digital circuit and the analog circuit, the handshake detection circuit detects the digital-to-analog conversion signal from the digital circuit and the analog-to-digital feedback signal from the analog circuit. By determining whether the signal meets the target error condition, it realizes real-time detection of the signal and outputs the corresponding target error signal based on the detection result. This enables the processor to promptly instruct the processor to configure the digital circuit and / or analog circuit based on the target error signal, quickly detect circuit errors, improve the working efficiency of the mixed-signal circuit, and enhance security.

[0020] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0021] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of this application are illustrated in the drawings by way of example and not limitation, in which:

[0022] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0023] Figure 1 This diagram illustrates the signal connections between digital and analog circuits in the prior art.

[0024] Figure 2 The diagram shows a block structure of a mixed-signal circuit according to the first embodiment of this application.

[0025] Figure 3 The diagram shows a block structure of a mixed-signal circuit according to a second embodiment of this application.

[0026] Figure 4 This paper shows a handshake detection circuit structure diagram of a mixed-signal circuit according to an embodiment of the present application;

[0027] Figure 5 This paper illustrates a timing diagram of a mixed-signal circuit according to an embodiment of the present application.

[0028] Figure 6 A schematic diagram illustrating the implementation flow of the control method according to an embodiment of this application is shown;

[0029] Figure 7 A schematic diagram of the composition structure of an electronic device according to an embodiment of this application is shown. Detailed Implementation

[0030] To make the objectives, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0031] Figure 2 The diagram shows a module structure diagram of a mixed-signal circuit according to the first embodiment of this application.

[0032] See Figure 2 According to a first aspect of this application, a mixed-signal circuit is provided, including a digital circuit 100, an analog circuit 200, a handshake detection circuit 300, and a processor 400. The handshake detection circuit 300 is connected to both the digital circuit 100 and the analog circuit 200, and the processor 400 is connected to both the digital circuit 100, the analog circuit 200, and the handshake detection circuit 300.

[0033] Digital circuit 100 is used to generate a digital-to-analog conversion signal and acquire a detected analog-to-digital feedback signal, wherein the digital-to-analog conversion signal is a digital signal; analog circuit 200 is used to generate an analog-to-digital feedback signal corresponding to the digital-to-analog conversion signal and acquire a detected digital-to-analog conversion signal, wherein the analog-to-digital feedback signal is a digital signal; handshake detection circuit 300 is used to acquire the digital-to-analog conversion signal and detect the digital-to-analog conversion signal, and output the corresponding target error signal when the digital-to-analog conversion signal is detected to meet the target error condition; handshake detection circuit 300 is also used to acquire the analog-to-digital feedback signal and detect the analog-to-digital feedback signal, and output the corresponding target error signal when the analog-to-digital feedback signal is detected to meet the target error condition; processor 400 is used to acquire the target error signal and instruct processor 400 to configure digital circuit 100 and / or analog circuit 200 based on the target error signal.

[0034] This application provides a mixed-signal circuit that, by setting a handshake detection circuit 300 between a digital circuit 100 and an analog circuit 200, detects the digital-to-analog conversion signal from the digital circuit 100 and the analog-to-digital feedback signal from the analog circuit 200, determines whether the signal meets the target error condition, and achieves real-time detection of the signal. By outputting the corresponding target error signal, the processor 400 can be instructed to configure the digital circuit 100 and / or the analog circuit 200 in a timely manner based on the target error signal, quickly detect circuit errors, improve the working efficiency of the mixed-signal circuit, and enhance security.

[0035] The mixed-signal circuits provided in this application are applicable to mixed-signal chips and multi-chip systems containing both digital and analog chips, such as SOC chips. Application areas of mixed-signal circuits include, but are not limited to, electronic products such as smartphones, tablets, headphones, smart speakers, and digital cameras; smart home products such as televisions, set-top boxes, smart robot vacuums, smart door locks, and smart appliances; network communication products such as routers, switches, and base stations; and industrial control products such as automobiles, rail transportation, smart grids, CNC machine tools, drones, cameras, instruments, power tools, and energy storage, including high-performance safety chips.

[0036] In a scenario where a digital circuit 100 and an analog circuit 200 interact, the digital circuit 100 can be a digital chip, primarily used to process discrete signals obtained by sampling and quantizing analog signals, i.e., digital signals. When the digital circuit 100 interacts with the analog circuit 200, the digital circuit 100 outputs a digital-to-analog conversion signal to the analog circuit 200, and this digital-to-analog conversion signal is a digital signal. For example... Figure 2 In this context, the digital-to-analog conversion signal is represented as d2a_signal_1, d2a_signal_n, etc.

[0037] The handshake detection circuit 300, located between the digital circuit 100 and the analog circuit 200, is used to acquire and detect the digital-to-analog conversion signal from the digital circuit 100, determine whether the digital-to-analog conversion signal meets the target error condition, and output the detected digital-to-analog conversion signal. For example... Figure 2 In the process, the detected digital-to-analog conversion signals are represented as d2a_signal_1_ej, d2a_signal_n_ej, etc.

[0038] The processor 400 is used to acquire the target error signal output by the handshake detection circuit 300, and instruct the processor 400 to configure the digital circuit 100 and / or the analog circuit 200 based on the target error signal, specifically by resetting the digital circuit 100 and / or the analog circuit 200.

[0039] Analog circuit 200 can be an analog chip, primarily used to process signals whose information parameters are continuous within a given time range, i.e., analog signals. In scenarios where digital circuit 100 and analog circuit 200 interact, analog circuit 200 outputs an analog-to-digital feedback signal to digital circuit 100 corresponding to the digital-to-analog conversion signal; this feedback signal is a digital signal. It's important to understand that in mixed-signal scenarios, analog circuit 200 typically has a functional circuit that converts analog signals to digital signals, thereby achieving the output of the analog-to-digital feedback signal. For example... Figure 2 In this context, the digital-to-analog conversion signal is represented as a2d_signal_1, a2d_signal_n, etc.

[0040] The handshake detection circuit 300 is also used to acquire and detect the analog-to-digital feedback signal from the analog circuit 200, determine whether the analog-to-digital feedback signal meets the target error condition, and output the detected digital-to-analog conversion signal. For example... Figure 2 In the process, the detected digital-to-analog conversion signals are represented as a2d_signal_1_ej, a2d_signal_n_ej, etc.

[0041] In the analog-to-digital conversion scenario of this method, since both the analog-to-digital conversion signal and the analog-to-digital feedback signal are digital signals, the same set of target error conditions can be used to detect the analog-to-digital conversion signal and the analog-to-digital feedback signal, and the corresponding target error signal can be output.

[0042] Through the signal interaction between digital circuit 100 and analog circuit 200, digital circuit 100 and analog circuit 200 can cooperate to implement specific algorithms. Furthermore, through the real-time detection of digital-to-analog conversion signals and analog-to-digital feedback signals by handshake detection circuit 300, circuit errors can be quickly detected, improving the working efficiency of mixed-signal circuits, enhancing the operational security of specific algorithms, and achieving self-checking at the hardware level.

[0043] In one embodiment, the handshake detection circuit 300 includes a verification sub-circuit 310 and a detection sub-circuit 320; the verification sub-circuit 310 is used to acquire a digital-to-analog conversion signal or an analog-to-digital feedback signal, and output a digital-to-analog conversion signal or an analog-to-digital feedback signal accompanied by a verification signal; the detection sub-circuit 320 is used to detect the digital-to-analog conversion signal or the analog-to-digital feedback signal accompanied by a verification signal, and determine whether the digital-to-analog conversion signal or the analog-to-digital feedback signal accompanied by a verification signal meets the target error condition; the output sub-circuit 330 is used to output a corresponding target error signal when the digital-to-analog conversion signal or the analog-to-digital feedback signal accompanied by a verification signal meets the target error condition.

[0044] Regarding the specific detection methods of the handshake detection circuit 300 for digital-to-analog conversion signals and analog-to-digital feedback signals, the verification sub-circuit 310 is used to acquire the digital-to-analog conversion signal or analog-to-digital feedback signal and output the digital-to-analog conversion signal or analog-to-digital feedback signal accompanied by a verification signal. Depending on the signal type and the detection method, the verification sub-circuit 310 can generate corresponding accompanying verification signals for different signal types and detection methods. Specifically, the signal types include digital signals and control signals, and the detection methods include, but are not limited to, odd parity, even parity, and Hamming code verification.

[0045] The output sub-circuit 330 is used to detect the digital-to-analog conversion signal or the analog-to-digital feedback signal with a verification signal, and to determine whether the digital-to-analog conversion signal or the analog-to-digital feedback signal with a verification signal meets the target error condition.

[0046] The target error conditions include: a condition with at least one digital circuit error, a condition with at least one analog circuit error, and a condition with both at least one digital circuit and an analog circuit error. Correspondingly, the target error signals include: a signal configuring digital circuit 100, and a signal configuring digital circuit 100 and analog circuit 200. When the target error condition indicates a fault in digital circuit 100, both digital circuit 100 and analog circuit 200 need to be reset simultaneously. When the target error condition indicates a fault in analog circuit 200, analog circuit 200 needs to be reset. Digital circuit 100 can then re-request and reconfigure the digital-to-analog conversion scenario.

[0047] Specific application scenarios include:

[0048] When the handshake detection circuit 300 detects that either the digital-to-analog conversion signal or the analog-to-digital feedback signal satisfies the condition of at least one digital circuit 100 error, it outputs a target error signal for the digital circuit 100, causing the processor 400 to configure the digital circuit 100 and the analog circuit 200.

[0049] When the handshake detection circuit 300 detects that either the digital-to-analog conversion signal or the analog-to-digital feedback signal satisfies the condition of at least one analog circuit 200 error, it outputs a target error signal for the analog circuit 200, causing the processor 400 to configure the analog circuit 200.

[0050] When the handshake detection circuit 300 detects that either the digital-to-analog conversion signal or the analog-to-digital feedback signal satisfies the condition that at least one digital circuit 100 and analog circuit 200 are both faulty, it outputs a target error signal for the digital circuit 100 and analog circuit 200, causing the processor 400 to configure the digital circuit 100 and analog circuit 200.

[0051] Figure 3 The diagram shows a module structure diagram for implementing a mixed-signal circuit according to a second embodiment of this application.

[0052] See Figure 3 In one embodiment, the handshake detection circuit 300 includes a first detection circuit 340 and a second detection circuit 350, which are connected. The first detection circuit 340 is integrated on the digital circuit 100 and includes a first verification sub-circuit 341 and a first detection sub-circuit 342. The first verification sub-circuit 341 is used to acquire the digital-to-analog conversion signal, process the digital-to-analog conversion signal, and output a digital-to-analog conversion signal accompanied by a verification signal. The first detection sub-circuit 342 is used to process the analog-to-digital feedback signal accompanied by the verification signal. The system performs a test to determine whether the analog-to-digital feedback signal with accompanying verification signal meets the target error condition. The second detection circuit 350 is integrated on the analog circuit 200 and includes a second verification sub-circuit 310 and a second detection sub-circuit 320. The second verification sub-circuit 310 is used to acquire the analog-to-digital feedback signal, process the analog-to-digital feedback signal, and output the analog-to-digital feedback signal with accompanying verification signal. The second detection sub-circuit 320 is used to detect the digital-to-analog conversion signal with accompanying verification signal and determine whether the digital-to-analog conversion signal with accompanying verification signal meets the target error condition.

[0053] Combining the verification sub-circuit 310 and the detection sub-circuit 320, in the hardware layout scenario, there is a certain distance between the digital circuit 100 and the analog circuit 200. In signal transmission, if only one handshake detection circuit 300 is set, this handshake detection circuit 300 can only detect signals in two paths: from the digital circuit 100 to the handshake detection circuit 300 and from the analog circuit 200 to the handshake detection module. That is, it cannot detect the digital-to-analog conversion signal from the handshake detection circuit 300 to the analog circuit 200, nor can it detect the analog-to-digital feedback signal from the handshake detection circuit 300 to the digital circuit 100. If an abnormality occurs in the signal in this path, the handshake detection circuit 300 cannot detect it in real time.

[0054] Based on this, in one implementation scenario, the present application embodiment sets up two handshake detection circuits 300, namely a first detection circuit 340 and a second detection circuit 350, so that the first detection circuit 340 is integrated on the digital circuit 100 and the second detection circuit 350 is integrated on the analog circuit 200.

[0055] That is, the first verification circuit 341 is integrated on the digital circuit 100. When the digital circuit 100 generates the digital-to-analog conversion signal, before the digital circuit 100 outputs the digital-to-analog conversion signal to the analog circuit 200, the digital-to-analog conversion signal can be processed by the first verification circuit 341, so as to output the digital-to-analog conversion signal with the verification signal, so that the digital-to-analog conversion signal always carries the accompanying verification signal.

[0056] Similarly, the second verification circuit 310 is integrated on the analog circuit 200. When the analog circuit 200 generates the analog-to-digital feedback signal, before the analog circuit 200 outputs the analog-to-digital feedback signal to the digital circuit 100, the second verification circuit 310 can process the analog-to-digital feedback signal, thereby outputting an analog-to-digital feedback signal with a verification signal, so that the analog-to-digital feedback signal always carries a verification signal.

[0057] It should be added that, since both the digital-to-analog conversion signal and the analog-to-digital feedback signal are digital signals, the first verification circuit 341 and the second verification circuit 310 of this application differ only in their integration location, while their specific circuit structures can remain the same.

[0058] Correspondingly, the first detection sub-circuit 342 is integrated on the digital circuit 100. When the analog-to-digital feedback signal with the accompanying verification signal is sent to the digital circuit 100, that is, when the digital circuit 100 obtains the analog-to-digital feedback signal with the accompanying verification signal, the first detection sub-circuit 342 will detect the analog-to-digital feedback signal with the accompanying verification signal. This can avoid the problem that the analog-to-digital feedback signal will be abnormal and cannot be detected before carrying the verification signal or after the detection has been completed.

[0059] The second detection sub-circuit 320 is integrated on the analog circuit 200. When the digital-to-analog conversion signal with the accompanying verification signal is sent to the analog circuit 200, that is, when the analog circuit 200 acquires the digital-to-analog conversion signal with the accompanying verification signal, the second detection sub-circuit 320 will detect the digital-to-analog conversion signal with the accompanying verification signal. This can avoid the problem that the digital-to-analog conversion signal will be abnormal and cannot be detected before carrying the verification signal or after the detection has been completed.

[0060] By setting up two handshake detection circuits 300, the relative layout between digital circuit 100 and analog circuit 200 in a multi-chip system can be more flexible, and the operation of the circuit can be guaranteed more safely, eliminating the possibility of circuit abnormalities.

[0061] Figure 4 The diagram shows a handshake detection circuit 300 of a mixed-signal circuit according to an embodiment of this application.

[0062] See Figure 4 In one embodiment, the verification sub-circuit 310 includes a data signal verification unit 311 and a control signal verification unit 312. Both the digital-to-analog conversion signal and the analog-to-digital feedback signal include control signals and data signals. The data signal verification unit 311 is used to acquire the data signal, perform Hamming code verification on the data signal, and output a data signal accompanied by a Hamming code verification signal. The control signal verification unit 312 is used to acquire the control signal, perform parity verification on the control signal, and output a control signal accompanied by a parity verification signal.

[0063] Digital signals include control signals and data signals.

[0064] The verification sub-circuit 310 includes a data signal verification unit 311 and a control signal verification unit 312.

[0065] The control signal verification unit 312 is responsible for verifying control signals. The verification signal accompanying the control signal can be an odd parity bit or an even parity bit. The verification signal generated by the control signal verification unit 312 can either allow multiple control signals to use the same parity bit, or allow each control signal to use its own parity bit. The verification signal corresponding to an odd parity bit is obtained by inverting the bitwise XOR operation of all its corresponding control signals. The verification signal corresponding to an even parity bit is obtained by XORing the bitwise XOR operation of all its corresponding control signals.

[0066] The data signal verification unit 311 can use Hamming code verification for data signals (DATA), so that each data signal corresponds to a Hamming code signal, and outputs a data signal with accompanying Hamming code verification signal.

[0067] In one embodiment, the control signals include a clock control signal, a start control signal, a work control signal, a return control signal, a sampling control signal, and a configuration control signal; the detection sub-circuit 320 includes: a time detection unit 321, used to start timing when the start control signal is issued, and to determine the timing time based on the return control signal; a first detection unit 322, connected to the time detection unit 321, used to determine whether a first error type is met based on a target time threshold and the timing time, the first error type being used to characterize an error in the analog circuit 200; a second detection unit 323, connected to the time detection unit 321, used to detect the configuration control signal within the timing time, and to determine whether a second error type is met based on the configuration control signal, the second error type being used to characterize an error in the digital circuit 100; and a third detection unit 324, connected to the time detection unit 321, used to detect the work control signal within the timing time, and to determine whether a first error type is met based on the work control signal, the first error type being used to characterize an error in the analog circuit 200.

[0068] Figure 5 The following is a timing diagram of a specific scenario of a mixed-signal circuit according to an embodiment of this application.

[0069] Combination Figure 4 and Figure 5 In one specific implementation scenario, the control signals include a clock control signal (CLK), a start control signal (START), a work control signal (WORK), a return control signal (DONE), a sampling control signal (SAMPLE), and a configuration control signal (CTRL_SIGNAL).

[0070] The clock control signal (CLK) is used to characterize the shared clock control signal of digital circuit 100 and analog circuit 200.

[0071] The start control signal (START) is a control signal transmitted from the digital circuit 100 to the analog circuit 200, used to indicate that the analog circuit 200 has started working.

[0072] The work control signal (WORK) is a signal transmitted from analog circuit 200 to digital circuit 100. It can be considered a control signal or a status signal, depending on whether it is part of the handshake logic. Here, it can be considered a control signal, used to indicate that analog circuit 200 is working.

[0073] The return control signal (DONE) is a control signal from analog circuit 200 to digital circuit 100, used to indicate that analog circuit 200 has completed its work.

[0074] The sampling control signal (SAMPLE) is a control signal from digital circuit 100 to analog circuit 200, which controls analog circuit 200 to send analog results (DATA) to digital circuit 100.

[0075] The configuration control signal (CTRL_SIGNAL), other than the control signals from digital circuit 100 to analog circuit 200 mentioned above, is only used for the configuration of analog circuit 200 and does not participate in the handshake process.

[0076] Correspondingly, the time detection unit 321 is used to start timing at the departure time of the departure control signal and end timing according to the arrival time of the return control signal, thereby determining the timing time.

[0077] The first detection unit 322, preset with a target time threshold, is connected to the time detection unit 321 to acquire the timing time in real time. When the timing time exceeds the target time threshold and no return control signal is received, it is determined to meet the first error type, i.e., the control signal meets the error condition of the analog circuit 200. The first detection unit 322 can be implemented by a timeout mechanism circuit. The target time threshold can be configured by the processor 400 (CPU) sending control signals to the first detection unit 322 integrated on the digital circuit 100 and the first detection unit 322 integrated on the analog circuit 200.

[0078] The second detection unit 323 is connected to the time detection unit 321, so as to detect the configuration control signal during the time period from the departure control signal to the arrival of the return control signal. If the waveform of the configuration control signal changes, it is determined that it meets the second error type, that is, the control signal meets the condition of digital circuit 100 error.

[0079] The third detection unit 324 is connected to the time detection unit 321, thereby detecting the working control signal during the time period from the departure control signal to the arrival of the return control signal. If the working control signal is low, it is determined that it meets the first error type, that is, the control signal meets the error condition of the analog circuit 200.

[0080] In one embodiment, the verification sub-circuit 310 further includes: a data checking unit 313, used to determine the amount of data transmission error by examining the data signal accompanied by the Hamming code check signal using Hamming code; a self-correction unit 314, connected to the data checking unit 313, which performs self-correction processing on the data signal accompanied by the Hamming code check signal if the amount of data transmission error does not exceed the target error amount; and a detection sub-circuit 320, further including: a fourth detection unit 325, connected to the data checking unit 313, which determines that the data transmission error conforms to the fourth error type if the amount of data transmission error exceeds the target error amount, the fourth error type being used to characterize that both the analog circuit 200 and the digital circuit 100 are faulty.

[0081] In one specific implementation scenario, the data signal is a DATA signal. The detection sub-circuit 320 detects the data signal through a data checking unit 313, a self-correction unit 314, and a fourth detection unit 325. The data signal can be self-checked according to the Hamming code verification method, accompanied by a Hamming code signal corresponding to the data signal.

[0082] During the Hamming code generation process, if the data transmission error does not exceed the target error amount, the self-correction unit 314 can perform self-correction processing on the data signal accompanied by the Hamming code check signal. The self-corrected data signal is the detected data signal, eliminating the need to send the target error signal, thereby improving work efficiency. Specifically, the target error amount can be 1 bit, i.e., a 1-bit error, which can be corrected using Hamming codes.

[0083] If the amount of data transmission error exceeds the target error amount, the self-correction unit 314 cannot perform self-correction, and the accompanying Hamming code signal data signal is output to the fourth detection unit 325. The fourth detection unit 325 detects the amount of error data in the accompanying Hamming code signal data signal. If the amount of data error is 2 bits or more, it is determined that it conforms to the fourth error type. The fourth error type is used to characterize that both the analog circuit 200 and the digital circuit 100 are wrong, and the digital and analog modules need to be configured to work again to generate correct data.

[0084] It should be added that, in one implementation scenario, the analog circuit 200 also integrates a hardware operating parameter detection device such as a temperature sensor and a voltage sensor. When the hardware operating parameters do not meet the safety range, such as excessive voltage or excessive temperature, it can be identified as the fifth error type. The corresponding target error signal needs to be sent to the processor 400, which will instruct the analog circuit 200 to perform a power-off process, or the analog circuit 200 will automatically perform a power-off process.

[0085] It should be added that the above error types are only examples. The embodiments of this application also have other error types, which can be detected by other detection units of the detection sub-circuit 320.

[0086] In one embodiment, the output sub-circuit 330 includes: an interrupt unit connected to the detection sub-circuit 320, used to generate an interrupt signal corresponding to the error type when an error is determined in the analog circuit 200 and / or the analog circuit 200 is faulty; a generation unit connected to the detection sub-circuit 320, used to generate a corresponding error number according to the error type; and an output unit connected to the interrupt unit and the generation unit, used to output the interrupt signal to the processor 400.

[0087] The target error signal is mainly output through the interrupt unit, generation unit and output unit of the output sub-circuit 330.

[0088] The interrupt unit is used to generate an interrupt signal when the detection sub-circuit 320 determines that the signal meets the target error condition. The generation unit is connected to the detection sub-circuit 320, thereby determining the error type based on the detection of the detection sub-circuit 320 and generating an error number corresponding to the error type. For example, the error number for the first error type is 001, the error number for the second error type is 002, and so on. The details will not be elaborated below.

[0089] In the generation unit, based on inherent hardware behavior, it can send the corresponding interrupt signal to the interrupt controller 500 according to the error type.

[0090] The output unit is used to output interrupt signals and error numbers to the interrupt controller 500.

[0091] The circuit also includes an interrupt controller 500; the interrupt controller 500 is connected to the handshake detection circuit 300 and is used to receive interrupt signals and error numbers and forward interrupt signals to the processor 400; the processor 400 includes a central processing unit 400 (CPU) for configuring the digital circuit 100 and / or analog circuit 200 according to the error number. The specific configuration method is typically to reset the digital circuit 100 and / or analog circuit 200.

[0092] In one embodiment, there are multiple interrupt controllers 500, and an output unit is connected to multiple interrupt controllers 500 to output an interrupt signal and an error number to a designated interrupt controller 500 according to the error number; there are multiple processors 400, and each processor 400 corresponds to an interrupt controller 500, so that the designated interrupt controller 500 forwards the interrupt signal and the error number to the designated processor 400.

[0093] The mixed-signal circuit provided in this application embodiment can also be applied to multi-core heterogeneous architecture chips. Specifically, in a multi-core heterogeneous architecture chip, there are multiple central processing units 400 (CPUs) to achieve multi-threaded operation. In this implementation scenario, this method can connect the output unit to multiple interrupt controllers 500, such as connecting to interrupt controller 1 and interrupt controller 2 respectively, and make the output unit send the interrupt signal and error number to the designated interrupt controller 500 according to the error number. The designated interrupt controller 500 then sends the interrupt signal and error number to the designated CPU 400. For example, CPU1 is used to reset the digital circuit 100, and CPU2 is used to reset the analog circuit 200. Or, CPU1 is used to reset the digital circuit 100, CPU2 is used to reset the analog circuit 200, and CPU3 is used to reset both the digital circuit 100 and the analog circuit 200. This operation, by providing interrupt signals to specific CPUs for differentiated processing, improves the working efficiency of the mixed-signal circuit. Through the collaborative work of multiple CPUs, efficiency is higher, and error state correction is faster.

[0094] In one embodiment, the system further includes: an error test circuit 600 connected to the handshake detection circuit 300, used to inject a test error signal into the digital-to-analog conversion signal and / or the analog-to-digital feedback signal; a processor 400 connected to the error test circuit 600, used to instruct the error test circuit 600 to inject a test error signal into the handshake detection circuit 300, and also used to receive a test interrupt signal corresponding to the handshake detection circuit 300, and determine the circuit correctness of the handshake detection circuit 300 based on the test interrupt signal; the processor 400 is also used to determine whether the test error signal has completed traversal based on the test error signal, and if it is determined that the test error signal has completed traversal, to stop the error test circuit 600.

[0095] This application embodiment also adds an error injection function through an error test circuit 600. The error test module is used to inject test error signals into the digital-to-analog conversion signal and / or analog-to-digital feedback signal, pre-simulating errors that may occur when the digital circuit 100 and analog circuit 200 interact, thereby improving the efficiency of verification testing.

[0096] The specific steps of the mixed-signal circuit error testing process include: First, the central processing unit 400 configures the digital circuit 100 and the analog circuit 200 to start working and perform signal interaction.

[0097] Then, the CPU activates the error test circuit 600, which injects a test error signal into the digital-to-analog conversion signal and / or the analog-to-digital feedback signal. Specifically, the error test signal is XORed with the corresponding signal, causing the original control signal to flip and generating an error. The handshake detection circuit 300 then detects and determines the interrupt signal and the error number, and sends them to the CPU through the interrupt controller 500. The CPU shuts down the unit in the error test circuit 600 corresponding to the test error signal based on the interrupt signal. This cycle continues until the CPU completely shuts down the error test circuit 600, indicating that the error test circuit 600 has completed the error traversal and the mixed-signal circuit error test process has ended.

[0098] Figure 6 A schematic diagram illustrating the implementation flow of the control method according to an embodiment of this application is shown.

[0099] See Figure 6 According to a second aspect of this application, a control method is provided, applied to a mixed-signal circuit. The mixed-signal circuit includes a digital circuit, an analog circuit, a handshake detection circuit, and a processor. The handshake detection circuit is connected to both the digital and analog circuits, and the processor is connected to the digital, analog, and handshake detection circuits. The method includes: operation 601, generating a digital-to-analog conversion signal through the digital circuit, wherein the digital-to-analog conversion signal is a digital signal; operation 602, acquiring the digital-to-analog conversion signal through the handshake detection circuit and detecting the digital-to-analog conversion signal, and outputting a corresponding target error signal when the digital-to-analog conversion signal meets a target error condition; operation 603, acquiring the detected digital-to-analog conversion signal through the analog circuit and generating an analog-to-digital feedback signal corresponding to the digital-to-analog conversion signal, wherein the analog-to-digital feedback signal is a digital signal; operation 604, acquiring the analog-to-digital feedback signal through the handshake detection circuit and detecting the analog-to-digital feedback signal, and outputting a corresponding target error signal when the analog-to-digital feedback signal meets a target error condition; operation 605, acquiring the target error signal through the processor and instructing the processor to configure the digital and / or analog circuits based on the target error signal.

[0100] According to a third aspect of this application, a chip is provided that includes an analog-digital mixed circuit according to any of the above-described embodiments.

[0101] According to a fourth aspect of this application, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method of any of the above-described embodiments.

[0102] According to a fifth aspect of this application, a non-transitory computer-readable storage medium is provided that stores computer instructions for causing a computer to perform the methods described in the above-described embodiments.

[0103] According to embodiments of this application, this application also provides an electronic device and a readable storage medium.

[0104] Figure 7 A schematic block diagram of an example electronic device 700 that can be used to implement embodiments of this application is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the application described and / or claimed herein.

[0105] like Figure 7 As shown, device 700 includes a computing unit 701, which can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) 702 or a computer program loaded from storage unit 708 into random access memory (RAM) 703. RAM 703 may also store various programs and data required for the operation of device 700. The computing unit 701, ROM 702, and RAM 703 are interconnected via bus 704. Input / output (I / O) interface 705 is also connected to bus 704.

[0106] Multiple components in device 700 are connected to I / O interface 705, including: input unit 706, such as keyboard, mouse, etc.; output unit 707, such as various types of monitors, speakers, etc.; storage unit 708, such as disk, optical disk, etc.; and communication unit 709, such as network card, modem, wireless transceiver, etc. Communication unit 709 allows device 700 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0107] The computing unit 701 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 701 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 701 performs the various methods and processes described above, such as control methods applied to mixed-signal circuits. For example, in some embodiments, the control methods applied to mixed-signal circuits can be implemented as computer software programs tangibly contained in a machine-readable medium, such as storage unit 708. In some embodiments, part or all of the computer program can be loaded and / or installed on device 700 via ROM 702 and / or communication unit 709. When the computer program is loaded into RAM 703 and executed by the computing unit 701, one or more steps of the control methods applied to mixed-signal circuits described above can be performed. Alternatively, in other embodiments, the computing unit 701 may be configured by any other suitable means (e.g., by means of firmware) to perform control methods applied to mixed-signal circuits.

[0108] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0109] The program code used to implement the methods of this application may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing device, such that when executed by the processor or controller, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0110] In the context of this application, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0111] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display, monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0112] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with embodiments of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0113] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0114] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0115] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0116] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A mixed-signal circuit, characterized in that, It includes digital circuits, analog circuits, handshake detection circuits, and a processor. The handshake detection circuits are connected to the digital circuits and the analog circuits, respectively, and the processors are connected to the digital circuits, the analog circuits, and the handshake detection circuits, respectively. The digital circuit is used to generate a digital-to-analog conversion signal and to acquire a detected analog-to-digital feedback signal, wherein the digital-to-analog conversion signal is a digital signal; The analog circuit is used to generate an analog-to-digital feedback signal corresponding to the digital-to-analog conversion signal, and to acquire the detected digital-to-analog conversion signal, wherein the analog-to-digital feedback signal is a digital signal; The handshake detection circuit is used to acquire the digital-to-analog conversion signal and detect the digital-to-analog conversion signal. When the digital-to-analog conversion signal is detected to meet the target error condition, the corresponding target error signal is output. The handshake detection circuit is also used to acquire the analog-to-digital feedback signal and detect the analog-to-digital feedback signal. When the analog-to-digital feedback signal is detected to meet the target error condition, the corresponding target error signal is output. A processor is configured to acquire a target error signal and, based on the target error signal, instruct the processor to configure the digital and / or analog circuits. The handshake detection circuit includes a verification sub-circuit and a detection sub-circuit. The verification sub-circuit is used to acquire the digital-to-analog conversion signal or analog-to-digital feedback signal, and output the digital-to-analog conversion signal or analog-to-digital feedback signal accompanied by the verification signal; The detection sub-circuit is used to detect the digital-to-analog conversion signal with the accompanying verification signal or the analog-to-digital feedback signal with the accompanying verification signal, and to determine whether the digital-to-analog conversion signal with the accompanying verification signal or the analog-to-digital feedback signal meets the target error condition. The output sub-circuit is used to output the corresponding target error signal when the digital-to-analog conversion signal or analog-to-digital feedback signal accompanied by the verification signal meets the target error condition.

2. The circuit according to claim 1, characterized in that, The handshake detection circuit includes a first detection circuit and a second detection circuit, and the first detection circuit and the second detection circuit are connected. The first detection circuit is integrated on the digital circuit and includes a first verification sub-circuit and a first detection sub-circuit. The first verification sub-circuit is used to acquire the digital-to-analog conversion signal, process the digital-to-analog conversion signal, and output a digital-to-analog conversion signal with a verification signal. The first detection sub-circuit is used to detect the analog-to-digital feedback signal with accompanying verification signal and determine whether the analog-to-digital feedback signal with accompanying verification signal meets the target error condition. The second detection circuit is integrated on the analog circuit and includes a second verification sub-circuit and a second detection sub-circuit; The second verification sub-circuit is used to acquire the analog-to-digital feedback signal, process the analog-to-digital feedback signal, and output an analog-to-digital feedback signal accompanied by a verification signal; The second detection sub-circuit is used to detect the digital-to-analog conversion signal with accompanying verification signal and determine whether the digital-to-analog conversion signal with accompanying verification signal meets the target error condition.

3. The circuit according to claim 1, characterized in that, The verification sub-circuit includes a data signal verification unit and a control signal verification unit. The digital-to-analog conversion signal and the analog-to-digital feedback signal both include control signals and data signals. The data signal verification unit is used to acquire data signals, perform Hamming code verification on the data signals, and output data signals accompanied by Hamming code verification signals. The control signal verification unit is used to acquire the control signal, perform parity verification on the control signal, and output a control signal accompanied by the parity verification signal.

4. The circuit according to claim 3, characterized in that, The control signals include clock control signals, start control signals, work control signals, return control signals, sampling control signals, and configuration control signals; The detection sub-circuit includes: The time detection unit is used to start timing when the departure control signal is issued and to determine the timing time according to the return control signal; A first detection unit, connected to the time detection unit, determines whether a first error type is met based on a target time threshold and the timing time. The first error type is used to characterize an error in the analog circuit. The second detection unit, connected to the time detection unit, is used to detect the configuration control signal within the timing period and determine whether the configuration control signal conforms to the second error type, which is used to characterize the digital circuit error. The third detection unit, connected to the time detection unit, is used to detect the working control signal within the timing period and determine whether the working control signal conforms to the first error type, which is used to characterize the analog circuit error.

5. The circuit according to claim 3 or 4, characterized in that, The verification sub-circuit further includes: The data inspection unit is used to determine the amount of data transmission error by examining the data signal accompanied by the Hamming code check signal using Hamming code. The self-correction unit is connected to the data inspection unit. If the amount of data transmission error does not exceed the target error amount, the self-correction processing is performed on the data signal with the accompanying Hamming code check signal. The detection sub-circuit also includes: The fourth detection unit is connected to the data inspection unit. If the amount of data transmission error exceeds the target error amount, it determines that it conforms to the fourth error type. The fourth error type is used to characterize that both the analog circuit and the digital circuit are faulty.

6. The circuit according to claim 4, characterized in that, The output sub-circuit includes: An interrupt unit, connected to the detection sub-circuit, is used to generate an interrupt signal corresponding to the error type when an error is determined in the analog circuit and / or the analog circuit. The generation unit is connected to the detection sub-circuit and generates a corresponding error number according to the error type. The output unit is connected to the interrupt unit and the generation unit, and outputs the interrupt signal and the error number to the processor.

7. The circuit according to claim 6, characterized in that, It also includes the interrupt controller; The interrupt controller is connected to the handshake detection circuit and is used to receive the interrupt signal and the error number and forward the interrupt signal to the processor. The processor includes a central processing unit for configuring the digital circuits and / or the analog circuits according to the interrupt signal.

8. The circuit according to claim 7, characterized in that, There are multiple interrupt controllers, and the output unit is connected to the multiple interrupt controllers to output the interrupt signal and the error number to a designated interrupt controller according to the error number. There are multiple processors, and each processor corresponds to an interrupt controller, causing the designated interrupt controller to forward the interrupt signal to the designated processor.

9. The hybrid circuit according to claim 1, characterized in that, Also includes: An error test circuit, connected to the handshake detection circuit, is used to inject a test error signal into the digital-to-analog conversion signal and / or analog-to-digital feedback signal; The processor, connected to the error test circuit, is used to instruct the error test circuit to inject the test error signal into the handshake detection circuit, and is also used to receive a test interrupt signal from the handshake detection circuit, and determine the circuit correctness of the handshake detection circuit based on the test interrupt signal.

10. The hybrid circuit according to claim 9, characterized in that, The processor is further configured to determine whether the test error signal has been traversed, and if the test error signal has been traversed, to stop the error test circuit.

11. A control method, characterized in that, The method is applied to a mixed-signal circuit, which includes a digital circuit, an analog circuit, a handshake detection circuit, and a processor. The handshake detection circuit is connected to both the digital circuit and the analog circuit, and the processor is connected to both the digital circuit, the analog circuit, and the handshake detection circuit. The method includes: The digital circuit generates a digital-to-analog conversion signal, which is a digital signal. The digital-to-analog conversion signal is acquired through a handshake detection circuit, and a digital-to-analog conversion signal with a verification signal is generated. The digital-to-analog conversion signal with the verification signal is detected. When the digital-to-analog conversion signal with the verification signal is detected to meet the target error condition, the corresponding target error signal is output. The analog circuit acquires the detected digital-to-analog conversion signal and generates an analog-to-digital feedback signal corresponding to the digital-to-analog conversion signal, wherein the analog-to-digital feedback signal is a digital signal. The analog-to-digital feedback signal is obtained through the handshake detection circuit, and an analog-to-digital feedback number with a verification signal is generated. The analog-to-digital feedback signal with the verification signal is detected. When the analog-to-digital feedback signal with the verification signal is detected to meet the target error condition, the corresponding target error signal is output. The processor acquires a target error signal and instructs the processor to configure the digital and / or analog circuits based on the target error signal.

12. A chip comprising a mixed-signal circuit according to any one of claims 1-9.

13. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the control method of claim 11.

14. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the control method of claim 11.

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