Display substrate and display device

Abstract

A display substrate includes a substrate (100), a plurality of first light emitting elements (21) in a first display area (A1), a plurality of first pixel circuits (31) and a plurality of second pixel circuits (32), and a plurality of second light emitting elements (22) in a second display area (A2). The first display area (A1) includes a first first sub-display area to an Nth first sub-display area arranged in order along a side away from the second display area (A2) in a first direction, where N is an integer greater than 1. The second display area (A2) includes at least one second sub-display area. The second light emitting elements (22) of the second sub-display area are electrically connected to the second pixel circuits (32) of the nth first sub-display area, and the first light emitting elements (21) of the nth first sub-display area are electrically connected to the first pixel circuits (31) of the nth+i first sub-display area. n and i are both integers greater than 0 and less than N.

Description

TECHNICAL FIELD

[0001] The present document relates to, but is not limited to, the technical field of display, in particular to a display substrate and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) and quantum dot light emitting diode (QLED) are active light emitting display devices, which have the advantages of self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, lightness, flexibility and low cost. Under-screen camera technology is a new technology proposed to improve the screen ratio of display devices. SUMMARY

[0003] The following is an overview of the subject matter of the detailed description herein. This overview is not intended to limit the scope of the claims.

[0004] Embodiments of the present disclosure provide a display substrate and a display device.

[0005] In one aspect, the present disclosure provides a display substrate, comprising: a substrate, a plurality of pixel circuits and a plurality of light emitting elements. The substrate comprises a first display area and a second display area, the first display area is located at least one side of the second display area. The plurality of pixel circuits comprises a plurality of first pixel circuits and a plurality of second pixel circuits located in the first display area, and the plurality of light emitting elements comprises a plurality of first light emitting elements located in the first display area and a plurality of second light emitting elements located in the second display area. At least one first pixel circuit in the plurality of first pixel circuits is electrically connected with at least one first light emitting element in the plurality of first light emitting elements, and the at least one first pixel circuit is configured to drive the at least one first light emitting element to emit light. At least one second pixel circuit in the plurality of second pixel circuits is electrically connected with at least one second light emitting element in the plurality of second light emitting elements, and the at least one second pixel circuit is configured to drive the at least one second light emitting element to emit light. The first display area comprises a first first sub-display area to an Nth first sub-display area arranged in sequence along a side away from the second display area in a first direction, wherein N is an integer greater than 1. The second display area comprises at least one second sub-display area, the second light emitting element of the second sub-display area is electrically connected with the second pixel circuit of the nth first sub-display area, and the first light emitting element of the nth first sub-display area is electrically connected with the first pixel circuit of the nth+i first sub-display area, wherein n and i are both integers greater than 0 and less than N.

[0006] In some example embodiments, the first light emitting element of the nth+i first sub-display region is electrically connected with the first pixel circuit of the nth+i+j first sub-display region, where j is an integer greater than 0 and less than N.

[0007] In some example embodiments, j is equal to i.

[0008] In some example embodiments, the at least one first pixel circuit and the at least one first light emitting element are electrically connected by a first conductive line, and the at least one second pixel circuit and the at least one second light emitting element are electrically connected by a second conductive line.

[0009] In some example embodiments, the first conductive line or the second conductive line to which the at least one pixel circuit in the at least one first sub-display region is electrically connected and the first conductive line to which the at least one first light emitting element is electrically connected are in different layers.

[0010] In some example embodiments, the second conductive line electrically connecting the second pixel circuit of the nth first sub-display region and the second light emitting element of the second sub-display region and the first conductive line electrically connecting the first light emitting element of the nth first sub-display region and the first pixel circuit of the nth+i first sub-display region are in different layers.

[0011] In some example embodiments, the first conductive line electrically connecting the first light emitting element of the nth+i first sub-display region and the first pixel circuit of the nth+i+j first sub-display region and the first conductive line electrically connecting the first pixel circuit of the nth+i first sub-display region and the first light emitting element of the nth first sub-display region are in different layers.

[0012] In some example embodiments, the number of pixel circuits in the at least one first sub-display region is greater than the number of first light emitting elements.

[0013] In some example embodiments, the pixel circuits in the nth first sub-display region are all second pixel circuits.

[0014] In some example embodiments, the number of pixel circuits of the nth first sub-display region is greater than or equal to the number of pixel circuits of the nth+1 first sub-display region, and the number of first light emitting elements of the nth first sub-display region is greater than or equal to the number of first light emitting elements of the nth+1 first sub-display region.

[0015] In some example embodiments, the second light emitting element in the second sub-display region close to the nth first sub-display region is electrically connected to the second pixel circuit in the nth first sub-display region close to the second sub-display region, and the second light emitting element in the second sub-display region away from the nth first sub-display region is electrically connected to the second pixel circuit in the nth first sub-display region away from the second sub-display region.

[0016] In some example embodiments, the pixel circuit array of the first display region is arranged in the first direction.

[0017] In some example embodiments, the second display region comprises: an Mth second sub-display region to a first second sub-display region arranged in sequence along a side away from the first sub-display region in the first direction, wherein M is an integer greater than 1 and less than N. The first sub-display region in which the second pixel circuit electrically connected to the second light emitting element in the mth second sub-display region is located is close to the side of the second display region, and the first sub-display region in which the second pixel circuit electrically connected to the second light emitting element in the m+1th second sub-display region is located is close to the side of the second display region, m is an integer greater than 0 and less than M.

[0018] In some example embodiments, the second conductive lines electrically connected to the second light emitting elements in adjacent second sub-display regions are located in different conductive layers, and the first conductive lines electrically connected to the first light emitting elements in adjacent first sub-display regions are located in different conductive layers.

[0019] In some example embodiments, the second conductive lines electrically connected to the plurality of second light emitting elements in the second sub-display region are of a same layer structure.

[0020] In some example embodiments, the second conductive lines electrically connected to the second light emitting elements adjacent in the first direction in the second sub-display region are of a different layer structure.

[0021] In some example embodiments, the first conductive lines and the second conductive lines are transparent conductive lines.

[0022] In some example embodiments, the first display region further comprises: a first third sub-display region to an Hth third sub-display region arranged in sequence along a side away from the second display region in a second direction, wherein H is an integer greater than 1. The second display region further comprises: at least one fourth sub-display region, the second light emitting element of the fourth sub-display region is electrically connected to the second pixel circuit of the hth third sub-display region, and the first light emitting element of the hth third sub-display region is electrically connected to the first pixel circuit of the h+s th third sub-display region, wherein h and s are both integers greater than 0 and less than H.

[0023] In some example embodiments, the second direction is parallel to the first direction, or the second direction intersects the first direction.

[0024] In some example embodiments, the first display area further comprises: a first fifth sub-display area to an Rth fifth sub-display area arranged in a third direction along a side away from the second display area, where R is an integer greater than 1. The second display area further comprises: at least one sixth sub-display area, a second light emitting element of the sixth sub-display area is electrically connected to a second pixel circuit of an rth fifth sub-display area, and a first light emitting element of the rth fifth sub-display area is electrically connected to a first pixel circuit of an r+kth fifth sub-display area, where r and k are both integers greater than 0 and less than R.

[0025] In some example embodiments, the first display area further comprises: a first seventh sub-display area to a Gth seventh sub-display area arranged in a fourth direction along a side away from the second display area, where G is an integer greater than 1. The second display area further comprises: at least one eighth sub-display area, a second light emitting element of the eighth sub-display area is electrically connected to a second pixel circuit of a gth seventh sub-display area, and a first light emitting element of the gth seventh sub-display area is electrically connected to a first pixel circuit of a g+dth seventh sub-display area, where g and d are both integers greater than 0 and less than G.

[0026] In some example embodiments, a density of the second light emitting element is less than or equal to a density of the first light emitting element.

[0027] In some example embodiments, a resolution of the first display area is less than or equal to a resolution of the second display area.

[0028] In another aspect, the embodiments of the present disclosure provide a display device including the display substrate as described above.

[0029] Other aspects can become apparent from the following detailed description when read in conjunction with the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0030] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification. The drawings, together with the embodiments of the present disclosure, are used to explain the technical solutions of the present disclosure, and do not constitute a limitation to the technical solutions of the present disclosure. The shape and size of one or more components in the drawings do not reflect the true proportion, and the purpose is only to schematically illustrate the present disclosure.

[0031] Figure 1 A schematic diagram of a display substrate of at least one embodiment of the present disclosure;

[0032] Figure 2Equivalent circuit diagram of the pixel circuit of at least one embodiment of the present disclosure;

[0033] Figure 3 The pixel circuit is provided Figure 2 The working timing diagram of the pixel circuit is provided

[0034] Figure 4 The top view schematic diagram of a pixel circuit of at least one embodiment of the present disclosure is provided

[0035] Figure 5 The pixel circuit is provided Figure 4 The local cross-sectional schematic diagram in the direction of Q-Q' is provided

[0036] Figure 6A The pixel circuit is provided Figure 4 The top view of the pixel circuit after forming the semiconductor layer is provided

[0037] Figure 6B The pixel circuit is provided Figure 4 The top view of the pixel circuit after forming the first conductive layer is provided

[0038] Figure 6C The pixel circuit is provided Figure 4 The top view of the pixel circuit after forming the second conductive layer is provided

[0039] Figure 6D The pixel circuit is provided Figure 4 The top view of the pixel circuit after forming the third insulating layer is provided

[0040] Figure 7 The local schematic diagram of the first display area of at least one embodiment of the present disclosure is provided

[0041] Figure 8 The schematic diagram of the display area of at least one embodiment of the present disclosure is provided

[0042] Figure 9 The connection schematic diagram of the first display area and the second display area of at least one embodiment of the present disclosure is provided

[0043] Figure 10 The schematic diagram of the transparent conductive line of at least one embodiment of the present disclosure is provided

[0044] Figure 11A The connection schematic diagram of the transparent conductive line of the first second sub-display area of at least one embodiment of the present disclosure is provided

[0045] Figure 11B The connection schematic diagram of the transparent conductive line of the second second sub-display area of at least one embodiment of the present disclosure is provided

[0046] Figure 11C The connection schematic diagram of the transparent conductive line of the first first sub-display area of at least one embodiment of the present disclosure is provided

[0047] Figure 11D A connection diagram of transparent conductive lines of a second first sub-display area of at least one embodiment of the present disclosure;

[0048] Figure 11E A connection diagram of transparent conductive lines of a third first sub-display area and a fourth first sub-display area of at least one embodiment of the present disclosure;

[0049] Figure 11F A connection diagram of transparent conductive lines of a fifth first sub-display area and a sixth first sub-display area of at least one embodiment of the present disclosure;

[0050] Figure 11G A connection diagram of transparent conductive lines of a seventh first sub-display area to a tenth first sub-display area of at least one embodiment of the present disclosure;

[0051] Figure 12 A diagram of a first transparent conductive layer of at least one embodiment of the present disclosure;

[0052] Figure 13 A diagram of a second transparent conductive layer of at least one embodiment of the present disclosure;

[0053] Figure 14 A diagram of a third transparent conductive layer of at least one embodiment of the present disclosure;

[0054] Figure 15 A diagram of three transparent conductive layers of at least one embodiment of the present disclosure;

[0055] Figure 16 Another connection diagram of a first sub-display area and a second sub-display area of at least one embodiment of the present disclosure;

[0056] Figure 17 Another connection diagram of a first sub-display area and a second sub-display area of at least one embodiment of the present disclosure;

[0057] Figure 18 Another connection diagram of a first sub-display area and a second sub-display area of at least one embodiment of the present disclosure;

[0058] Figure 19 Another connection diagram of a first sub-display area and a second sub-display area of at least one embodiment of the present disclosure;

[0059] Figure 20 Another connection diagram of a first display area and a second display area of at least one embodiment of the present disclosure;

[0060] Figure 21 Another connection diagram of a first display area and a second display area of at least one embodiment of the present disclosure;

[0061] Figure 22 Another connection diagram of the first display area and the second display area for at least one embodiment of the present disclosure;

[0062] Figure 23 Another connection diagram of the first display area and the second display area for at least one embodiment of the present disclosure;

[0063] Figure 24 Another connection diagram of the first display area and the second display area for at least one embodiment of the present disclosure;

[0064] Figure 25 Another connection diagram of the first display area and the second display area for at least one embodiment of the present disclosure;

[0065] Figure 26 Another connection diagram of the first display area and the second display area for at least one embodiment of the present disclosure;

[0066] Figure 27 Another connection diagram of the first display area and the second display area for at least one embodiment of the present disclosure;

[0067] Figure 28 Another connection diagram of the first display area and the second display area for at least one embodiment of the present disclosure;

[0068] Figure 29 Another connection diagram of the first display area and the second display area for at least one embodiment of the present disclosure;

[0069] Figure 30 Another connection diagram of the first display area and the second display area for at least one embodiment of the present disclosure;

[0070] Figure 31 A diagram of a display device for at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0071] The embodiments of the present disclosure will be described in detail with reference to the drawings. The embodiments can be implemented in various forms. It is obvious to those skilled in the art that the embodiments and features thereof can be modified in various ways without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the embodiments described below. The embodiments of the present disclosure and the features thereof can be combined with each other without conflict.

[0072] In the drawings, the size, the thickness, or the region of one or a plurality of components is sometimes exaggerated for the sake of clarity. Thus, one embodiment of the present disclosure is not necessarily limited to such a scale. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0073] The ordinal numbers such as "first", "second", and "third" in this specification are used for the purpose of avoiding confusion among components, and are not for the purpose of numbering the components in the order of their importance. "A plurality of" in the present disclosure indicates a number of two or more.

[0074] In this specification, terms of "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicating the orientation or positional relationship are used to describe the positional relationship of components with reference to the drawings, for the convenience of the description of this specification and simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus cannot be understood as a limitation on the present disclosure. The positional relationship of components is appropriately changed according to the direction of the components described. Therefore, it is not limited to the terms described in the specification, and can be appropriately changed depending on the situation.

[0075] In this specification, unless explicitly stated and limited otherwise, the terms "mount", "connected", and "linked" are to be interpreted broadly. For example, it can be fixed connection, or detachable connection, or integral connection; can be mechanical connection, or connection; can be direct connection, or indirect connection through an intermediate component, or communication between two elements inside. The above terms in the present disclosure can be understood according to the situation by those skilled in the art.

[0076] In this specification, "electrically connected" includes the case where components are connected through an element having some electrical effect. The element having some electrical effect is not particularly limited as long as it can transmit an electrical signal between the components to be connected. Examples of the element having some electrical effect include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having multiple functions, and the like.

[0077] In this specification, a transistor refers to an element including at least a gate, a drain, and a source. A transistor has a channel region between a drain (a drain electrode terminal, a drain region, or a drain electrode) and a source (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to a region where current flows mainly.

[0078] In this specification, the first electrode can be a drain electrode, the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. The functions of "source" and "drain" are sometimes interchanged with each other in cases of transistors whose polarities are opposite or in cases where the direction of current flowing in a circuit is changed, and the like. Therefore, in this specification, "source" and "drain" can be interchanged with each other. In addition, a gate can also be referred to as a control electrode.

[0079] In this specification, "parallel" means a state where the angle formed by two straight lines is -10° or more and 10° or less, and thus a state where the angle is -5° or more and 5° or less is also included. In addition, "perpendicular" means a state where the angle formed by two straight lines is 80° or more and 100° or less, and thus a state where the angle is 85° or more and 95° or less is also included.

[0080] The "light transmittance" in the present disclosure refers to the ability of light to pass through a medium, and is the percentage of the light flux that passes through a transparent or translucent body to the incident light flux.

[0081] The "about" and "approximately" in the present disclosure mean that the limit is not strictly defined, and the range within the process and measurement error is allowed. In the present disclosure, "approximately the same" means that the numerical value differs by 10% or less.

[0082] The embodiment provides a display substrate, comprising: a substrate, a plurality of pixel circuits and a plurality of light emitting elements. The substrate comprises a first display area and a second display area, and the first display area is located on at least one side of the second display area. The plurality of pixel circuits comprises a plurality of first pixel circuits and a plurality of second pixel circuits located in the first display area. The plurality of light emitting elements comprises a plurality of first light emitting elements located in the first display area and a plurality of second light emitting elements located in the second display area. At least one first pixel circuit in the plurality of first pixel circuits is electrically connected with at least one first light emitting element in the plurality of first light emitting elements, and the at least one first pixel circuit is configured to drive the at least one first light emitting element to emit light. At least one second pixel circuit in the plurality of second pixel circuits is electrically connected with at least one second light emitting element in the plurality of second light emitting elements, and the at least one second pixel circuit is configured to drive the at least one second light emitting element to emit light. The first display area comprises a first first sub-display area to an Nth first sub-display area arranged in sequence along a side away from the second display area in a first direction, wherein N is an integer greater than 1. The second display area comprises at least one second sub-display area, the second light emitting element of the second sub-display area is electrically connected with the second pixel circuit of the nth first sub-display area, and the first light emitting element of the nth first sub-display area is electrically connected with the first pixel circuit of the nth+i first sub-display area, wherein n and i are both integers greater than 0 and less than N. For example, i can be 1 or 2, etc. In the example, the nth first sub-display area is located on a side of the nth+1 first sub-display area close to the second display area.

[0083] In some examples, the second display area can only comprise one second sub-display area. Alternatively, the second display area can comprise a plurality of second sub-display areas. For example, the plurality of second sub-display areas can be arranged in sequence along a side away from the first sub-display area in the first direction. However, the embodiment is not limited in this regard.

[0084] The display substrate provided by the embodiment partitions the first display area and the second display area, the second light emitting element of the second sub-display area of the second display area is electrically connected with the second pixel circuit of one first sub-display area of the first display area, and the first light emitting element of the first sub-display area is electrically connected with the first pixel circuit in another first sub-display area, so as to realize the staggered connection of the pixel circuits and the light emitting elements in different partitions. The embodiment can reduce the length difference of the conductive wires electrically connected with the second light emitting element and the second pixel circuit. The length of the conductive wire determines the overlapping area size of the conductive wire and other signal wires, thereby affecting the size of the parasitic capacitance, and the large difference of the parasitic capacitance will cause the display picture to be uneven. The embodiment reduces the length difference of the conductive wire through the staggered connection of the pixel circuits and the light emitting elements in different partitions, so as to improve the situation that the display picture uniformity is poor, improve the display uniformity, and realize a more uniform full-screen visual display effect.

[0085] In some example embodiments, the at least one first pixel circuit and the at least one first light emitting element can be electrically connected by a first conductive line, and the at least one second pixel circuit and the at least one second light emitting element can be electrically connected by a second conductive line. For example, the first conductive line and the second conductive line can each be a transparent conductive line. The first conductive line and the second conductive line can be made of a transparent conductive material (e.g., indium tin oxide (ITO)). However, the present embodiments are not limited thereto. In other examples, the first conductive line can be a non-transparent conductive line, and the second conductive line can be a transparent conductive line. For example, the first conductive line can be made of a metal material, and the second conductive line can be made of a transparent conductive material (e.g., ITO).

[0086] In some example embodiments, the first light emitting element of the nth+i first sub-display region can be electrically connected to the first pixel circuit of the nth+i+j first sub-display region, where j is an integer greater than 0 and less than N. In the present example, the first light emitting element of the first sub-display region of the first display region can be electrically connected to the first pixel circuit of other first sub-display regions in a staggered manner to support the second pixel circuit being disposed in the vicinity or surrounding of the second display region, thereby improving the situation that the length difference of the second conductive line electrically connecting the second pixel circuit and the second light emitting element is too large.

[0087] In some examples, j can be equal to i. For example, i and j can each be 1 or 2. For example, the first light emitting element of the nth+i first sub-display region can be electrically connected to the first pixel circuit of the nth+2xi first sub-display region, and the first light emitting element of the nth+2xi first sub-display region can be electrically connected to the first pixel circuit of the nth+3xi first sub-display region. However, the present embodiments are not limited thereto. For example, j can be different from i. For example, i can be 2, and j can be 1.

[0088] In some example embodiments, the first conductive line or the second conductive line to which the at least one pixel circuit in the at least one first sub-display area is electrically connected and the first conductive line to which the at least one first light emitting element is electrically connected can be in a different layer structure. In the present disclosure, A and B in a different layer structure means that A and B are in different conductive layers. In this way, interference between different conductive lines can be avoided. In some examples, the second conductive line electrically connecting the second light emitting element of the second sub-display area and the second pixel circuit of the nth first sub-display area, and the first conductive line electrically connecting the first light emitting element of the nth first sub-display area and the first pixel circuit of the (n+i)th first sub-display area can be in a different layer structure. In some examples, the first conductive line electrically connecting the first light emitting element of the (n+i)th first sub-display area and the first pixel circuit of the (n+i+j)th first sub-display area, and the first conductive line electrically connecting the first light emitting element of the nth first sub-display area and the first pixel circuit of the (n+i)th first sub-display area can be in a different layer structure.

[0089] In some example embodiments, the pixel circuits of the nth first sub-display area can all be second pixel circuits. In the present example, by concentrating the second pixel circuits near the second display area, the length of the second conductive line electrically connecting the second light emitting element and the second pixel circuit can be reduced.

[0090] In some example embodiments, the number of pixel circuits in the at least one first sub-display area can be greater than the number of first light emitting elements. In some examples, by compressing the pixel circuits in the first display area to form a space for the second pixel circuits, the number of pixel circuits in the first display area is greater than the number of first light emitting elements.

[0091] In some example embodiments, the number of pixel circuits of the nth first sub-display area can be greater than or equal to the number of pixel circuits of the (n+1)th first sub-display area, and the number of first light emitting elements of the nth first sub-display area can be greater than or equal to the number of first light emitting elements of the (n+1)th first sub-display area. In some examples, along the side away from the second display area in the first direction, the number of pixel circuits in the plurality of first sub-display areas can gradually decrease, and the number of first light emitting elements can also gradually decrease.

[0092] In some example embodiments, the second light emitting element in the second sub-display region close to the nth first sub-display region can be electrically connected with the second pixel circuit in the nth first sub-display region close to the second sub-display region, and the second light emitting element in the second sub-display region far from the nth first sub-display region can be electrically connected with the second pixel circuit in the nth first sub-display region far from the second sub-display region. The connection mode of the second light emitting element and the second pixel circuit in the corresponding region provided in this example can help arrange the conductive lines and reduce the mutual interference caused by the overlapping of the conductive lines. However, this example is not limited thereto.

[0093] In some example embodiments, the plurality of pixel circuits in the first display region can be arranged in an array, and the first direction can be the row direction of the pixel circuits. However, this example is not limited thereto. For example, the first direction can be the column direction of the pixel circuits, or can be a direction intersecting the row direction, or can be a direction intersecting the column direction.

[0094] In some example embodiments, the second display region can include: the Mth second sub-display region to the first second sub-display region arranged in sequence along the side far from the first sub-display region in the first direction. Wherein, M is an integer greater than 1 and less than N. The first sub-display region where the second pixel circuit electrically connected with the second light emitting element in the mth second sub-display region is located can be located close to the side of the second display region of the first sub-display region where the second pixel circuit electrically connected with the second light emitting element in the m+1th second sub-display region is located, and m is an integer greater than 0 and less than M. In this example, the second light emitting element in the second sub-display region far from the first display region can be electrically connected with the second pixel circuit in the first sub-display region close to the second display region, and the second light emitting element in the second sub-display region close to the first display region can be electrically connected with the second pixel circuit in the first sub-display region far from the second display region. In this way, it can help reduce the length difference between the second conductive lines electrically connecting the second light emitting element and the second pixel circuit. In some examples, the entire second display region can be divided into a plurality of second sub-display regions, or a part of the second display region can be divided into a plurality of second sub-display regions. However, this example is not limited thereto.

[0095] In some example embodiments, the second conductive lines electrically connecting the second light emitting elements in the adjacent second sub-display regions can be located in different conductive layers, and the first conductive lines electrically connecting the first light emitting elements in the adjacent first sub-display regions can be located in different conductive layers. In this way, it can reduce the mutual interference caused by the overlapping of the conductive lines.

[0096] In some example embodiments, the second conductive lines to which the plurality of second light emitting elements in the second sub-display area are electrically connected can be in a same layer structure. Alternatively, the second conductive lines to which the second light emitting elements adjacent in the first direction in the second sub-display area are electrically connected can be in a different layer structure. However, the present embodiments are not limited thereto. In other examples, the second conductive lines to which the second light emitting elements are electrically connected can be connected by a plurality of conductive line segments, and adjacent conductive line segments can be located in different conductive layers.

[0097] In some example embodiments, the first display area can further include: a first third sub-display area to an Hth third sub-display area arranged in sequence along a side away from the second display area in a second direction, where H is an integer greater than 1. The second display area can further include: at least one fourth sub-display area, the second light emitting elements of the fourth sub-display area being electrically connected to the second pixel circuit of the hth third sub-display area, the first light emitting elements of the hth third sub-display area being electrically connected to the first pixel circuit of the h+s th third sub-display area, where h and s are both integers greater than 0 and less than H. For example, h and s can both be 1, or h can be 1 and s can be 2. In some examples, the second direction can be parallel to the first direction, or the second direction can intersect the first direction. The present example is advantageous in reducing the length difference of the conductive lines electrically connecting the second light emitting elements and the second pixel circuit by dividing the first display area and the second display area into a plurality of sub-areas in the first direction and the second direction, and performing staggered connection of the light emitting elements and the pixel circuit in the plurality of sub-areas.

[0098] In some example embodiments, the first display area can further include: a first fifth sub-display area to an Rth fifth sub-display area arranged in sequence along a side away from the second display area in a third direction, where R is an integer greater than 1. The second display area can further include: at least one sixth sub-display area. The second light emitting elements of the sixth sub-display area are electrically connected to the second pixel circuit of the rth fifth sub-display area, and the first light emitting elements of the rth fifth sub-display area are electrically connected to the first pixel circuit of the r+kth fifth sub-display area, where r and k are both integers greater than 0 and less than R. For example, r and k can both be 1, or r can be 1 and k can be 2. In some examples, the third direction can be parallel to the first direction or the second direction, or the third direction can intersect the first direction, or the third direction can intersect the second direction. The present example is advantageous in reducing the length difference of the conductive lines electrically connecting the second light emitting elements and the second pixel circuit by dividing the first display area and the second display area into a plurality of sub-areas, and performing staggered connection of the light emitting elements and the pixel circuit in the plurality of sub-areas.

[0099] In some exemplary embodiments, the first display area may further include: a first seventh sub-display area to a Gth seventh sub-display area arranged sequentially along the side away from the second display area in the fourth direction, where G is an integer greater than 1. The second display area may further include: at least one eighth sub-display area. The second light-emitting element of the eighth sub-display area is electrically connected to the second pixel circuit of the gth seventh sub-display area, and the first light-emitting element of the gth seventh sub-display area is electrically connected to the first pixel circuit of the g+dth seventh sub-display area. Here, g and d are both integers greater than 0 and less than G. For example, g and d can both be 1, or g can be 1 and d can be 2. In some examples, the fourth direction may be parallel to the first direction, the second direction, or a third direction; or, the fourth direction may intersect the first direction, the second direction, or a third direction. This example can divide the first and second display areas into multiple partitions through multiple directions and perform staggered connections of light-emitting elements and pixel circuits in multiple partitions, which is beneficial for reducing the length difference of the conductive lines electrically connecting the second light-emitting element and the second pixel circuit.

[0100] In some examples, N, H, R, and G can be the same; or, at least two of N, H, R, and G can be the same; or, N, H, R, and G can all be different. However, this embodiment is not limited in this respect.

[0101] In some examples, i, s, k, and d can be the same, or at least two of i, s, k, and d can be the same, or i, s, k, and d can all be different. However, this embodiment is not limited in this respect.

[0102] The following examples illustrate the solution of this embodiment.

[0103] Figure 1 This is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as Figure 1 As shown, the display substrate may include a display area AA and a peripheral area BB surrounding the display area AA. The display area AA of the display substrate may include a first display area A1 and a second display area A2, with the first display area A1 located on at least one side of the second display area A2. For example, the first display area A1 may surround the second display area A2. However, this embodiment is not limited to this. For example, the first display area A1 may partially surround the second display area A2.

[0104] In some exemplary implementations, such as Figure 1As shown, the second display area A2 is a light-transmitting display area, which can also be called the under-display camera (UDC) area; the first display area A1 is a non-light-transmitting display area, which can also be called the normal display area. For example, the orthographic projection of a photosensor (such as a camera) onto the display substrate can be located within the second display area A2 of the display substrate. In some examples, such as... Figure 1 As shown, the second display area A2 can be circular, and the size of the orthographic projection of the photosensor onto the display substrate can be less than or equal to the size of the second display area A2. However, this embodiment is not limited to this. In other examples, the second display area A2 can be rectangular, and the size of the orthographic projection of the photosensor onto the display substrate can be less than or equal to the size of the inscribed circle of the second display area A2.

[0105] In some exemplary implementations, such as Figure 1 As shown, the second display area A2 can be located at the top center of the display area AA. The first display area A1 can surround the second display area A2. However, this embodiment is not limited in this respect. For example, the second display area A2 can be located at other positions such as the upper left or upper right corner of the display area AA. For example, the first display area A1 can surround at least one side of the second display area A2.

[0106] In some exemplary implementations, such as Figure 1 As shown, the display area AA can be rectangular, such as a rounded rectangle. The second display area A2 can be circular or elliptical. However, this embodiment is not limited to this. For example, the second display area A2 can be other shapes such as rectangle, semicircle, pentagon, etc.

[0107] In some exemplary embodiments, the display area AA may be provided with multiple sub-pixels. At least one sub-pixel may include a pixel circuit and a light-emitting element. The pixel circuit may be configured to drive the connected light-emitting element. For example, the pixel circuit may be configured to provide a drive current to drive the light-emitting element to emit light. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C (i.e., 3 transistors and 1 capacitor) structure, a 7T1C (i.e., 7 transistors and 1 capacitor) structure, a 5T1C (i.e., 5 transistors and 1 capacitor) structure, an 8T1C (i.e., 8 transistors and 1 capacitor) structure, or an 8T2C (i.e., 8 transistors and 2 capacitors) structure, etc. In some examples, the light-emitting element may be an organic light-emitting diode (OLED), which emits red, green, blue, or white light under the drive of its corresponding pixel circuit. The color emitted by the light-emitting element may be determined as needed. In some examples, the light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited in this respect.

[0108] In some exemplary embodiments, a pixel unit of the display area AA may include three sub-pixels, which may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, which may be a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, respectively.

[0109] In some exemplary embodiments, the shape of the light-emitting element can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement; when a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited in this respect.

[0110] Figure 2 This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. Figure 3 for Figure 2 The provided pixel circuit timing diagram is shown. The pixel circuit of this exemplary embodiment is described using a 7T1C structure as an example. However, this embodiment is not limited thereto.

[0111] In some exemplary implementations, such as Figure 2 As shown, the pixel circuit of this example may include six switching transistors (T1, T2, T4 to T7), a driving transistor T3, and a storage capacitor Cst. The six switching transistors are a data write transistor T4, a threshold compensation transistor T2, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a first reset transistor T1, and a second reset transistor T7. The light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer disposed between the anode and the cathode.

[0112] In some exemplary embodiments, the driving transistor and the six switching transistors can be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the processing difficulty of the display substrate, and improve product yield. In some possible implementations, the driving transistor and the six switching transistors may include both P-type and N-type transistors.

[0113] In some example embodiments, the driving transistor and the six switching transistors can adopt low temperature poly-silicon thin film transistors, or can adopt oxide thin film transistors, or can adopt low temperature poly-silicon thin film transistors and oxide thin film transistors. The active layer of the low temperature poly-silicon thin film transistor adopts low temperature poly-silicon (LTPS, Low Temperature Poly-Silicon), and the active layer of the oxide thin film transistor adopts oxide semiconductor (Oxide). The low temperature poly-silicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantage of low leakage current. Integrating the low temperature poly-silicon thin film transistor and the oxide thin film transistor on one display substrate forms a low temperature poly-crystalline oxide (LTPO, Low Temperature Polycrystalline Oxide) display substrate, which can take advantage of both, can achieve low frequency driving, can reduce power consumption, and can improve display quality.

[0114] In some example embodiments, as Figure 2As shown, the display substrate can include scan lines GL, data lines DL, a first power line PL1, a second power line PL2, an emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a first reset control line RST1, and a second reset control line RST2. In some examples, the first power line PL1 can be configured to provide a constant first voltage signal VDD to the pixel circuit, the second power line PL2 can be configured to provide a constant second voltage signal VSS to the pixel circuit, and the first voltage signal VDD is greater than the second voltage signal VSS. The scan line GL can be configured to provide a scan signal SCAN to the pixel circuit, the data line DL can be configured to provide a data signal DATA to the pixel circuit, the emission control line EML can be configured to provide an emission control signal EM to the pixel circuit, the first reset control line RST1 can be configured to provide a first reset control signal RESET1 to the pixel circuit, and the second reset control line RST2 can be configured to provide a second reset control signal RESET2 to the pixel circuit. In some examples, in the zth row of pixel circuits, the first reset control line RST1 can be electrically connected to the scan line GL of the (z-1)th row of pixel circuits to be input with the scan signal SCAN(z-1), i.e., the first reset control signal RESET1(z) is the same as the scan signal SCAN(z-1). The second reset control line RST2 can be electrically connected to the scan line GL of the zth row of pixel circuits to be input with the scan signal SCAN(z), i.e., the second reset control signal RESET2(z) is the same as the scan signal SCAN(z). In some examples, the second reset control line RST2 electrically connected to the zth row of pixel circuits and the first reset control line RST1 electrically connected to the (z+1)th row of pixel circuits can be a one-piece structure. Here, z is an integer greater than 0. In this way, the number of signal lines of the display substrate can be reduced, and a narrow-frame design of the display substrate can be achieved. However, the present embodiment is not limited in this regard.

[0115] In some example embodiments, the first initial signal line INIT1 can be configured to provide a first initial signal to the pixel circuit, and the second initial signal line INIT2 can be configured to provide a second initial signal to the pixel circuit. For example, the first initial signal can be different from the second initial signal. The first initial signal and the second initial signal can be constant voltage signals, which can be, for example, between the first voltage signal VDD and the second voltage signal VSS, but are not limited thereto. In other examples, the first initial signal and the second initial signal can be the same, and only the first initial signal line can be provided to provide the first initial signal.

[0116] In some example embodiments, as Figure 2As shown, the driving transistor T3 is electrically connected with the light emitting element EL, and outputs a driving current under the control of signals such as the scan signal SCAN, the data signal DATA, the first voltage signal VDD, the second voltage signal VSS, etc. to drive the light emitting element EL to emit light. The gate of the data writing transistor T4 is electrically connected with the scan line GL, the first pole of the data writing transistor T4 is electrically connected with the data line DL, and the second pole of the data writing transistor T4 is electrically connected with the first pole of the driving transistor T3. The gate of the threshold compensation transistor T2 is electrically connected with the scan line GL, the first pole of the threshold compensation transistor T2 is electrically connected with the gate of the driving transistor T3, and the second pole of the threshold compensation transistor T2 is electrically connected with the second pole of the driving transistor T3. The gate of the first light emitting control transistor T5 is electrically connected with the light emitting control line EML, the first pole of the first light emitting control transistor T5 is electrically connected with the first power supply line PL1, and the second pole of the first light emitting control transistor T5 is electrically connected with the first pole of the driving transistor T3. The gate of the second light emitting control transistor T6 is electrically connected with the light emitting control line EML, the first pole of the second light emitting control transistor T6 is electrically connected with the second pole of the driving transistor T3, and the second pole of the second light emitting control transistor T6 is electrically connected with the anode of the light emitting element EL. The first reset transistor T1 is electrically connected with the gate of the driving transistor T3, and is configured to reset the gate of the driving transistor T3. The second reset transistor T7 is electrically connected with the anode of the light emitting element EL, and is configured to reset the anode of the light emitting element EL. The gate of the first reset transistor T1 is electrically connected with the first reset control line RST1, the first pole of the first reset transistor T1 is electrically connected with the first initial signal line INIT1, and the second pole of the first reset transistor T1 is electrically connected with the gate of the driving transistor T3. The gate of the second reset transistor T7 is electrically connected with the second reset control line RST2, the first pole of the second reset transistor T7 is electrically connected with the second initial signal line INIT2, and the second pole of the second reset transistor T7 is electrically connected with the anode of the light emitting element EL. The first capacitor pole plate of the storage capacitor Cst is electrically connected with the gate of the driving transistor T3, and the second capacitor pole plate of the storage capacitor Cst is electrically connected with the first power supply line PL1.

[0117] In the present example, the first node N1 is the connection point of the storage capacitor Cst, the first reset transistor T1, the driving transistor T3 and the threshold compensation transistor T2, the second node N2 is the connection point of the first light emitting control transistor T5, the data writing transistor T4 and the driving transistor T3, the third node N3 is the connection point of the driving transistor T3, the threshold compensation transistor T2 and the second light emitting control transistor T6, and the fourth node N4 is the connection point of the second light emitting control transistor T6, the second reset transistor T7 and the light emitting element EL.

[0118] The working process of the pixel circuit will be described below with reference to Figure 3 The working process of the pixel circuit will be described below with reference to Figure 2 The working process of the pixel circuit will be described below with reference toFigure 2 The pixel circuit shown includes a plurality of transistors, all of which are P-type transistors, and will be described by way of example.

[0119] In some example embodiments, as Figure 3 As shown, in a frame display period, the working process of the pixel circuit can include a first stage S1, a second stage S2, and a third stage S3.

[0120] The first stage S1 is referred to as a reset stage. A first reset control signal RESET1 provided by a first reset control line RST1 is a low-level signal, causing the first reset transistor T1 to be turned on. A first initial signal provided by a first initial signal line INIT1 is provided to the first node N1, initializing the first node N1 and clearing the original data voltage in the storage capacitor Cst. A scan signal SCAN provided by a scan line GL is a high-level signal, and an emission control signal EM provided by an emission control line EML is a high-level signal, causing the data write transistor T4, the threshold compensation transistor T2, the first emission control transistor T5, the second emission control transistor T6, and the second reset transistor T7 to be turned off. The light emitting element EL does not emit light in this stage.

[0121] In the second stage S2, referred to as a data writing stage or threshold compensation stage, the scan signal SCAN provided by the scan line GL is a low level signal, the first reset control signal RESET1 provided by the first reset control line RST1 and the emission control signal EM provided by the emission control line EML are high level signals, and the data signal DATA is output by the data line DL. In this stage, the first capacitor plate of the storage capacitor Cst is at a low level, so the driving transistor T3 is turned on. The scan signal SCAN is a low level signal, which turns on the threshold compensation transistor T2, the data writing transistor T4 and the second reset transistor T7. The threshold compensation transistor T2 and the data writing transistor T4 are turned on, so that the data voltage Vdata output by the data line DL is provided to the first node N1 through the second node N2, the turned-on driving transistor T3, the third node N3 and the turned-on threshold compensation transistor T2, and the difference between the data voltage Vdata output by the data line DL and the threshold voltage of the driving transistor T3 is charged into the storage capacitor Cst, so that the voltage of the first capacitor plate (i.e. the first node N1) of the storage capacitor Cst is Vdata-|Vth|, wherein Vdata is the data voltage output by the data line DL, and Vth is the threshold voltage of the driving transistor T3. The second reset transistor T7 is turned on, so that the second initial signal provided by the second initial signal line INIT2 is provided to the anode of the light emitting element EL, the anode of the light emitting element EL is initialized (reset), the pre-stored voltage in the anode of the light emitting element EL is emptied, the initialization is completed, and it is ensured that the light emitting element EL does not emit light. The first reset control signal RESET1 provided by the first reset control line RST1 is a high level signal, which turns off the first reset transistor T1. The emission control signal EM provided by the emission control line EML is a high level signal, which turns off the first emission control transistor T5 and the second emission control transistor T6.

[0122] In the third stage S3, referred to as an emission stage, the emission control signal EM provided by the emission control line EML is a low level signal, and the scan signal SCAN provided by the scan line GL and the first reset control signal RESET1 provided by the first reset control line RST1 are high level signals. The emission control signal EM provided by the emission control line EML is a low level signal, which turns on the first emission control transistor T5 and the second emission control transistor T6, and the first voltage signal VDD output by the first power supply line PL1 provides a driving voltage to the anode of the light emitting element EL through the turned-on first emission control transistor T5, the driving transistor T3 and the second emission control transistor T6, so as to drive the light emitting element EL to emit light.

[0123] In the driving process of the pixel circuit, the driving current flowing through the driving transistor T3 is determined by the voltage difference between the gate and the first electrode of the driving transistor T3. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the driving transistor T3 is:

[0124] I = K x (Vgs - Vth) 2 = K x [(VDD - Vdata + |Vth|) - Vth] 2 = K x [VDD - Vdata] 2 .

[0125] wherein I is a drive current flowing through the drive transistor T3, that is, a drive current for driving the light emitting element EL, K is a constant, Vgs is a voltage difference between the gate and the first electrode of the drive transistor T3, Vth is a threshold voltage of the drive transistor T3, Vdata is a data voltage outputted from the data line DL, and VDD is a first voltage signal outputted from the first power line PL1.

[0126] As can be seen from the above equation, the current flowing through the light emitting element EL is independent of the threshold voltage of the drive transistor T3. Therefore, the pixel circuit of the present embodiment can compensate for the threshold voltage of the drive transistor T3.

[0127] Figure 4 FIG. 1 is a top view of a pixel circuit according to an embodiment of the present disclosure. Figure 5 FIG. 2 is a cross-sectional view of the pixel circuit along the direction of Q-Q’ in FIG. 1. Figure 4 FIG. 3 is a top view of the pixel circuit after forming a semiconductor layer in FIG. 1. Figure 6A FIG. 4 is a cross-sectional view of the pixel circuit along the direction of Q-Q’ in FIG. 3. Figure 4 FIG. 5 is a top view of the pixel circuit after forming a first conductive layer in FIG. 3. Figure 6B FIG. 6 is a cross-sectional view of the pixel circuit along the direction of Q-Q’ in FIG. 5. Figure 4 FIG. 7 is a top view of the pixel circuit after forming a second conductive layer in FIG. 5. Figure 6C FIG. 8 is a cross-sectional view of the pixel circuit along the direction of Q-Q’ in FIG. 7. Figure 4 FIG. 9 is a top view of the pixel circuit after forming a third insulating layer in FIG. 7. Figure 6D FIG. 10 is a cross-sectional view of the pixel circuit along the direction of Q-Q’ in FIG. 9. Figure 4 FIG. 11 is a top view of the pixel circuit after forming a fourth insulating layer in FIG. 9.

[0128] In some example embodiments, as shown in FIG. 1, a pixel circuit 100 includes a drive transistor T3, a light emitting element EL, a first power line PL1, a second power line PL2, a data line DL, a first electrode EL1, and a second electrode EL2. Figures 4 to 6DAs shown, the display substrate may include: a substrate 100, and a semiconductor layer 10, a first conductive layer 11, a second conductive layer 12, and a third conductive layer 13 sequentially disposed on the substrate 100. A first insulating layer 101 is disposed between the semiconductor layer 10 and the first conductive layer 11, a second insulating layer 102 is disposed between the first conductive layer 11 and the second conductive layer 12, and a third insulating layer 103 is disposed between the second conductive layer 12 and the third conductive layer 13. The first insulating layer 101, the second insulating layer 102, and the third insulating layer 103 may be inorganic insulating layers. The first insulating layer 101 and the second insulating layer 102 may also be referred to as gate insulating layers, and the third insulating layer 103 may also be referred to as interlayer insulating layers. In some examples, a fourth conductive layer may also be disposed on the side of the third conductive layer away from the substrate 100. The fourth conductive layer may include an anode connection electrode, which may connect a pixel circuit and a light-emitting element. At least one transparent conductive layer may also be disposed on the side of the fourth conductive layer away from the substrate. The transparent conductive layer may include transparent conductive lines configured to connect the anode connection electrode and the anode of the light-emitting element. A planarization layer may be disposed between the fourth conductive layer and the transparent conductive layer, and a planarization layer may be disposed between adjacent transparent conductive layers. An anode layer, a pixel definition layer, an organic light-emitting layer, and a cathode layer may be sequentially disposed on the side of the transparent conductive layer away from the substrate. However, this embodiment is not limited in this respect.

[0129] In some exemplary embodiments, such as Figures 4 to 6A As shown, the semiconductor layer 10 of the display substrate may include: active layers of multiple transistors in a pixel circuit (e.g., a first active layer T10 of a first reset transistor T1, a second active layer T20 of a threshold compensation transistor T2, a third active layer T30 of a driving transistor T3, a fourth active layer T40 of a data writing transistor T4, a fifth active layer T50 of a first light-emitting control transistor T5, a sixth active layer T60 of a second light-emitting control transistor T6, and a seventh active layer T70 of a second reset transistor T7). The active layers of multiple transistors in a pixel circuit may be a single, integral structure. At least one active layer may include: a channel region, a first doped region, and a second doped region. The channel region may be undoped and has semiconductor properties. The first and second doped regions may be located on opposite sides of the channel region and are doped with impurity particles, thus exhibiting conductivity. The impurities may vary depending on the type of transistor. The first or second doped region of the semiconductor layer may be interpreted as the source or drain electrode of the transistor.

[0130] In some exemplary embodiments, such as Figures 4 to 6BAs shown, the first conductive layer 11 of the display substrate may include: control electrodes of multiple transistors in the pixel circuit (e.g., control electrode T11 of the first reset transistor T1, control electrode T21 of the threshold compensation transistor T2, control electrode T31 of the driving transistor T3, control electrode T41 of the data writing transistor T4, control electrode T51 of the first light-emitting control transistor T5, control electrode T61 of the second light-emitting control transistor T6, and control electrode T71 of the second reset transistor T7), a light-emitting control line EML, a scan line GL, a first reset control line (including the first reset control line RST1 electrically connected to the current row of pixel circuits and the first reset control line RST1' electrically connected to the next row of pixel circuits), and the first electrode Cst-1 of the storage capacitor Cst. The control electrode T11 of the first reset transistor T1 in the current row of pixel circuits, the control electrode of the second reset transistor in the previous row of pixel circuits, and the first reset control line RST1 can be an integral structure. The control electrode T21 of the threshold compensation transistor T2, the control electrode T41 of the data writing transistor T4, and the scan line GL can also be an integral structure. The control electrode T31 of the driving transistor T3 and the first electrode Cst-1 of the storage capacitor Cst can be a single integrated structure. The control electrode T51 of the first light-emitting control transistor T5, the control electrode T61 of the second light-emitting control transistor T6, and the light-emitting control line EML can be a single integrated structure. The control electrode T71 of the second reset transistor T7 of the current row pixel circuit, the control electrode of the first reset transistor of the next row pixel circuit, and the first reset control line RST1' can be a single integrated structure. However, this embodiment is not limited to this.

[0131] In some exemplary embodiments, such as Figures 4 to 6C As shown, the second conductive layer 12 of the display substrate may include: a first initial signal line (e.g., first initial signal lines INIT1a and INIT1b), a second initial signal line (e.g., second initial signal lines INIT2a and INIT2b), a second electrode Cst-2 of the storage capacitor Cst, and a shielding electrode BK. The second electrode Cst-2 of the storage capacitor Cst has a cutout region. The orthographic projection of the control electrode T31 of the driving transistor T3 onto the substrate can cover the orthographic projection of the cutout region onto the substrate. The orthographic projection of the cutout region onto the substrate can be a polygon. However, this embodiment is not limited to this.

[0132] In some exemplary embodiments, such as Figures 4 to 6DAs shown, the third insulating layer 103 of the display substrate has multiple vias, including, for example, the first via V1 to the fifteenth via V15. Specifically, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 within the first via V1 to the eighth via V6 are removed, exposing the surface of the semiconductor layer 10. The third insulating layer 103 and the second insulating layer 102 within the ninth via V9 are removed, exposing the surface of the first conductive layer 11. The third insulating layer 103 within the tenth via V10 to the fifteenth via V15 is removed, exposing the surface of the second conductive layer 12.

[0133] In some exemplary implementations, such as Figures 4 to 6D As shown, the third conductive layer 13 of the display substrate may include: a data line DL, a first power line PL1, and multiple connection electrodes (e.g., first connection electrodes CP1 to sixth connection electrodes CP6). The data line DL can be electrically connected to the first doped region of the active layer T40 of the data writing transistor T4 through the third via V3. The first power line PL1 can be electrically connected to the shielding electrode BK through the twelfth via V12, and can also be electrically connected to the second electrode Cst-2 of the storage capacitor Cst through the thirteenth via V13. The shielding electrode BK is configured to shield the impact of data voltage jumps on critical nodes, preventing data voltage jumps from affecting the potential of critical nodes in the pixel circuit and improving the display effect. The first connection electrode CP1 can be electrically connected to the first doped region of the active layer T10 of the first reset transistor T1 through the first via V1, and can also be electrically connected to the first initial signal line INIT1a through the tenth via V10. The second connection electrode CP2 can be electrically connected to the first doped region of the active layer T20 of the threshold compensation transistor T2 through the second via V2, and can also be electrically connected to the control electrode T31 of the driving transistor T3 through the ninth via V9. The third connection electrode CP3 can be electrically connected to the second doped region of the active layer T60 of the second light-emitting control transistor T6 through the fifth via V5. The fourth connection electrode CP4 can be electrically connected to the first doped region of the active layer T70 of the second reset transistor T7 through the sixth via V6, and can also be electrically connected to the second initial signal line INIT2b through the fifteenth via V15. The fifth connection electrode CP5 can be electrically connected to the first doped region of the active layer of the second reset transistor of the previous row pixel circuit through the seventh via V7, and can also be electrically connected to the second initial signal line INIT2a through the eleventh via V11. The sixth connection electrode CP6 can be electrically connected to the first doped region of the active layer of the first reset transistor of the next row pixel circuit through the eighth via V8, and can also be electrically connected to the first initial signal line INIT1b through the fourteenth via V14.

[0134] The above is merely an example of a top view of a pixel circuit. However, this embodiment is not limited thereto.

[0135] In some exemplary implementations, such as Figure 1 As shown, the first display area A1 can be provided with multiple first light-emitting elements 21 and multiple pixel circuits, and the second display area A2 can be provided with multiple second light-emitting elements 22. The multiple pixel circuits may include multiple first pixel circuits 31, multiple second pixel circuits 32, and multiple invalid pixel circuits. At least one first pixel circuit 31 is electrically connected to at least one first light-emitting element 21 via a first conductive line L1, and the at least one first pixel circuit 31 is configured to drive at least one first light-emitting element 21 to emit light. At least one second pixel circuit 32 is electrically connected to at least one second light-emitting element 22 via a second conductive line L2, and the at least one second pixel circuit 32 is configured to drive at least one second light-emitting element 22 to emit light. Providing invalid pixel circuits can help improve the uniformity of components in multiple film layers during the etching process. For example, the invalid pixel circuit has the same structure as the first pixel circuit 31 and second pixel circuit 32 in its row or column, except that it is not connected to any light-emitting element. In this example, the light transmittance of the first display area A1 is less than the light transmittance of the second display area A2. By setting pixel circuits only in the first display area A1 and not in the second display area A2, the light transmittance of the second display area A2 can be improved.

[0136] In some examples, to improve the display effect, the density of the second light-emitting element 22 in the second display area A2 may be less than or equal to the density of the first light-emitting element 21 in the first display area A1. However, this embodiment is not limited to this.

[0137] In some examples, the resolution of the first display area A1 may be less than or equal to the resolution of the second display area A2. However, this embodiment is not limited to this.

[0138] Figure 7 This is a partial schematic diagram of the first display area according to at least one embodiment of the present disclosure. Figure 7 The following diagram illustrates a plurality of first light-emitting elements 21 and pixel circuits 30 in the first display area A1. In this example, a plurality of pixel circuits arranged sequentially along the row direction X can be referred to as a row of pixel circuits, and a plurality of pixel circuits arranged sequentially along the column direction Y can be referred to as a column of pixel circuits. The row direction X intersects the column direction Y; for example, the row direction X can be perpendicular to the column direction Y.

[0139] In some exemplary implementations, such as Figure 1 and Figure 7As shown, since the first display area A1 is provided not only with the first pixel circuit 31 electrically connected with the first light emitting element 21, but also with the second pixel circuit 32 electrically connected with the second light emitting element 22, the number of the pixel circuits 30 in the first display area A1 is greater than the number of the first light emitting elements 21. In the present example, the area in which the second pixel circuit is arranged is obtained by reducing the size of the first pixel circuit in the first direction. For example, the size of the pixel circuit in the first direction can be smaller than the size of the first light emitting element in the first direction. In the present example, the first direction can be the row direction X. As shown, the first pixel circuit 31 can be electrically connected with the first light emitting element 21 through the first connection hole 300, and the first light emitting element 21 can be electrically connected with the corresponding first pixel circuit through the second connection hole 210. For example, the first pixel circuit can be electrically connected with the first conductive line through the first connection hole 300, and the first conductive line can be electrically connected with the corresponding first light emitting element 21 through the second connection hole 210. The second pixel circuit can be electrically connected with the second conductive line through the first connection hole 300, and the second conductive line can extend to the second display area and be electrically connected with the second light emitting element in the second display area. Figure 7 As shown, the original a columns of pixel circuits can be compressed along the horizontal direction X, so that a column of pixel circuit arrangement space is newly added, and the space occupied by the a columns of pixel circuits before compression and the a+1 columns of pixel circuits after compression is the same. Here, a can be an integer greater than 1. In the present example, a can be equal to 2. However, the present embodiment is not limited thereto. For example, a can be equal to 3 or 4. In other examples, the first direction can be the column direction Y. The original b rows of pixel circuits can be compressed along the vertical direction Y, so that a row of pixel circuit arrangement space is newly added, and the space occupied by the b rows of pixel circuits before compression and the b+1 rows of pixel circuits after compression is the same. Here, b can be an integer greater than 1. Alternatively, the area in which the second pixel circuit is arranged can be obtained by reducing the size of the first pixel circuit in the row direction and the column direction.

[0140] In the present example embodiment, as shown, Figure 7 As shown, one pixel circuit 30 can be electrically connected with the first light emitting element 21 or the second light emitting element through the first connection hole 300, and the first light emitting element 21 can be electrically connected with the corresponding first pixel circuit through the second connection hole 210. For example, the first pixel circuit can be electrically connected with the first conductive line through the first connection hole 300, and the first conductive line can be electrically connected with the corresponding first light emitting element 21 through the second connection hole 210. The second pixel circuit can be electrically connected with the second conductive line through the first connection hole 300, and the second conductive line can extend to the second display area and be electrically connected with the second light emitting element in the second display area.

[0141] Figure 8 A schematic diagram of the display area of at least one embodiment of the present disclosure. In some example embodiments, as shown, Figure 8As shown, the second display area A2 is substantially symmetrical about the center axis OO' in the row direction X. The second display area A2 can include a first sub-area A21 and a second sub-area A22, which can be substantially symmetrical about the center axis OO'. The first display area A1 can include a first auxiliary area A11 adjacent to the first sub-area A21 of the second display area A2 in the row direction X, and a second auxiliary area A12 adjacent to the second sub-area A22 in the row direction X. The second pixel circuit electrically connected with the second light emitting element of the first sub-area A21 can be arranged in the first auxiliary area A11; the second pixel circuit electrically connected with the second light emitting element of the second sub-area A22 can be arranged in the second auxiliary area A12.

[0142] The conductive lines electrically connecting the pixel circuits and the light emitting elements between the first sub-area A21 and the first auxiliary area A11 are taken as an example for illustration.

[0143] Figure 9 A connection diagram of the second display area and the first display area of at least one embodiment of the present disclosure is shown. In some example embodiments, as shown in Figure 8 and Figure 9 As shown, the first sub-area A21 of the second display area A2 can include a plurality of second sub-display areas arranged in sequence along a side away from the first auxiliary area A11 in the row direction X, for example, including two second sub-display areas (i.e. M can be 2 in the present example). Among them, the first second sub-display area A2a can be located on a side away from the first auxiliary area A11 of the second second sub-display area A2b. The first auxiliary area A11 of the first display area A1 can include a plurality of first sub-display areas arranged in sequence along a side away from the first sub-area A21 in the row direction X, for example, including the first first sub-display area A1a to the tenth first sub-display area A1j (i.e. N can be 10 in the present example), wherein the first first sub-display area A1a is closest to the first sub-area A21, and the tenth first sub-display area A1j is farthest from the first sub-area A21.

[0144] In the present example, the two adjacent first sub-display areas can be continuous regions, i.e., there can be no other pixel circuits and light emitting elements arranged between the two adjacent first sub-display areas. The first first sub-display area A1a and the second second sub-display area A2b can be adjacent and continuous regions, i.e., there can be no other regions arranged between the first sub-display area A1a and the second second sub-display area A2b. In the present example, the second pixel circuits can be arranged next to the second display area A2. However, the present embodiment is not limited thereto. In other examples, the first first sub-display area A1a and the second second sub-display area A2b can be discontinuous regions, e.g., there can be first pixel circuits and first light emitting elements that do not belong to the first sub-display area arranged between the first first sub-display area A1a and the second second sub-display area A2b. The arrangement position of the second pixel circuits is not adjacent to the second display area A2, and the arrangement position of the second pixel circuits can be spaced apart from the second display area A2 by a certain distance.

[0145] In the present example, the first conductive lines electrically connecting the first light emitting elements and the first pixel circuits are taken as the transparent conductive lines, and the second conductive lines electrically connecting the second light emitting elements and the second pixel circuits are taken as the transparent conductive lines. For example, the second conductive lines can include the first transparent conductive line 52a and the second transparent conductive line 52b; and the first conductive lines can include the third transparent conductive line 51a to the twelfth transparent conductive line 51j.

[0146] In some example embodiments, as Figure 9As shown, the second light emitting element in the first second sub-display area A2a can be electrically connected with the second pixel circuit in the first first sub-display area A1a through the first transparent conductive line 52a. The second light emitting element in the second second sub-display area A2b can be electrically connected with the second pixel circuit in the second second sub-display area A1b through the second transparent conductive line 52b. In the present example, the second light emitting element in the second sub-display area (e.g., the second sub-display area A2a) away from the first auxiliary area A11 can be electrically connected with the second pixel circuit in the first sub-display area (e.g., the first sub-display area A1a) close to the first partition A21, and the second light emitting element in the second sub-display area (e.g., the second sub-display area A2b) close to the first auxiliary area A11 can be electrically connected with the second pixel circuit in the first sub-display area (e.g., the first sub-display area A1b) away from the first partition A21. In this way, the length difference of the transparent conductive line to which the second light emitting elements in different areas are electrically connected can be better improved. However, the present embodiment is not limited thereto. In other examples, the second light emitting element in the second sub-display area (e.g., the second sub-display area A2a) away from the first auxiliary area A11 can be electrically connected with the second pixel circuit in the first sub-display area (e.g., the first sub-display area A1b) away from the first partition A21, and the second light emitting element in the second sub-display area (e.g., the second sub-display area A2b) close to the first auxiliary area A11 can be electrically connected with the second pixel circuit in the first sub-display area (e.g., the first sub-display area A1a) close to the first partition A21.

[0147] In some example embodiments, as Figure 9As shown, the first light emitting element of the first first sub-display area A1a can be electrically connected with the first pixel circuit of the third first sub-display area A1c through the third transparent conductive line 51a. The first light emitting element of the second first sub-display area A1b can be electrically connected with the first pixel circuit of the fourth first sub-display area A1d through the fourth transparent conductive line 51b. The first light emitting element of the third first sub-display area A1c can be electrically connected with the first pixel circuit of the fifth first sub-display area A1e through the fifth transparent conductive line 51c. The first light emitting element of the fourth first sub-display area A1d can be electrically connected with the first pixel circuit of the sixth first sub-display area A1f through the sixth transparent conductive line 51d. The first light emitting element of the fifth first sub-display area A1e can be electrically connected with the first pixel circuit of the seventh first sub-display area A1g through the seventh transparent conductive line 51e. The first light emitting element of the sixth first sub-display area A1f can be electrically connected with the first pixel circuit of the eighth first sub-display area A1h through the eighth transparent conductive line 51f. The first light emitting element of the seventh first sub-display area A1g can be electrically connected with the first pixel circuit of the ninth first sub-display area A1i through the ninth transparent conductive line 51g. The first light emitting element of the eighth first sub-display area A1h can be electrically connected with the first pixel circuit of the tenth first sub-display area A1j through the tenth transparent conductive line 51h. By analogy, the first light emitting element of the ninth first sub-display area A1i can be electrically connected with the first pixel circuit in the area far away from the tenth first sub-display area A1j (e.g. the eleventh first sub-display area can be arranged), the first light emitting element of the tenth first sub-display area A1j can be electrically connected with the first pixel circuit in the area far away from the tenth first sub-display area A1j (e.g. the twelfth first sub-display area can be arranged), and so on until the first light emitting element in the first auxiliary area A11 can be electrically connected with the first pixel circuit. The present example is not limited to the number of first sub-display areas. In some examples, the number of first sub-display areas can be determined according to the number of pixel circuits or light emitting elements in the first sub-display area, for example, the number of pixel circuits in the last first sub-display area can be less than or equal to 2. Alternatively, in some examples, the number of first sub-display areas can be determined according to the length of the transparent conductive line to which the light emitting element or pixel circuit in the first sub-display area is electrically connected, for example, the length of the transparent conductive line to which the light emitting element in the last first sub-display area is electrically connected can be less than or equal to a preset value. However, the present embodiment is not limited in this regard.

[0148] In the present example, the first light emitting element of the nth first sub-display area is electrically connected with the first pixel circuit of the n+2th first sub-display area, i.e., i in the present example can be 2. However, the present embodiment is not limited thereto. In other examples, the first light emitting element of the first first sub-display area A1a can be electrically connected with the first pixel circuit of the fourth first sub-display area A1d, the first light emitting element of the second first sub-display area A1b can be electrically connected with the first pixel circuit of the third first sub-display area A1d, and so on.

[0149] In some example embodiments, as shown in FIG. 4A, the pixel circuits in the first first sub-display area A1a and the second first sub-display area A1b can all be second pixel circuits, so as to drive the second light emitting elements in the first sub-region A21. The pixel circuits in the third first sub-display area A1c to the tenth first sub-display area A1j can all be first pixel circuits, so as to drive the first light emitting elements. In the present example, by arranging the second pixel circuits in a concentrated manner near the second display area A2, and arranging the first pixel circuits and the first light emitting elements in a staggered manner, the length of the transparent conductive lines electrically connecting the second pixel circuits and the second light emitting elements can be reduced, and the difference in the length of the transparent conductive lines can be reduced, so as to improve the uniformity of the display effect. Figure 9

[0150] Figure 10 An example diagram of the transparent conductive lines of at least one embodiment of the present disclosure is shown in FIG. 4B. In some example embodiments, as shown in FIG. 4B, the display substrate can include a plurality of transparent conductive layers on the side of the pixel circuit away from the substrate, for example, three transparent conductive layers, i.e., a first transparent conductive layer 41, a second transparent conductive layer 42, and a third transparent conductive layer 43. In some examples, the second transparent conductive layer 42 can be located on the side of the first transparent conductive layer 41 away from the substrate, and the third transparent conductive layer 43 can be located on the side of the second transparent conductive layer 42 away from the substrate. Any one of the transparent conductive layers can include a plurality of transparent conductive lines. For example, the first transparent conductive layer 41 and the second transparent conductive layer 42 can each include a plurality of first conductive lines electrically connecting the first light emitting elements and the first pixel circuits, and a plurality of second conductive lines electrically connecting the second light emitting elements and the second pixel circuits. The third transparent conductive layer 43 can include a plurality of first conductive lines electrically connecting the first light emitting elements and the first pixel circuits. However, the present embodiment is not limited thereto. For example, the second conductive lines electrically connecting the second light emitting elements and the second pixel circuits can be arranged in the second transparent conductive layer and the third transparent conductive layer, or can be arranged in the first transparent conductive layer and the third transparent conductive layer. Figure 10

[0151] ​​In the present example, the transparent conductive lines of the first transparent conductive layer 41 are represented by solid lines, the transparent conductive lines of the second transparent conductive layer 42 are represented by dashed lines, and the transparent conductive lines of the third transparent conductive layer 43 are represented by dot-dashed lines.

[0152] The following will be described in combination with Figure 10 the connection relationship between a row of pixel circuits and light emitting elements. Figure 11A A connection diagram of the transparent conductive lines of a first second sub-display area of at least one embodiment of the present disclosure. Figure 11B A connection diagram of the transparent conductive lines of a second second sub-display area of at least one embodiment of the present disclosure. Figure 11C A connection diagram of the transparent conductive lines of a first first sub-display area of at least one embodiment of the present disclosure. Figure 11D A connection diagram of the transparent conductive lines of a second first sub-display area of at least one embodiment of the present disclosure. Figure 11E A connection diagram of the transparent conductive lines of a third first sub-display area and a fourth first sub-display area of at least one embodiment of the present disclosure. Figure 11F A connection diagram of the transparent conductive lines of a fifth first sub-display area and a sixth first sub-display area of at least one embodiment of the present disclosure. Figure 11G A connection diagram of the transparent conductive lines of a seventh first sub-display area to a tenth first sub-display area of at least one embodiment of the present disclosure. Figures 11A to 11G In the present example, the connection relationship between a row of pixel circuits and light emitting elements is only schematically shown.

[0153] In some example embodiments, as shown in Figures 10 to 11D a plurality of columns of second light emitting elements 22 are arranged in each of the first second sub-display area A2a and the second second sub-display area A2b. However, the present embodiment is not limited thereto. For example, each second sub-display area can include only one column of second light emitting elements.

[0154] In some examples, as shown in Figures 10 to 11DAs shown, the second light emitting elements 22 in the first second sub-display area A2a can be electrically connected with the second pixel circuits 32 in the first first sub-display area A1b through the first transparent conductive lines 52a. The first transparent conductive lines 52a electrically connected with the second light emitting elements 22 in the first second sub-display area A2a can be located in the first transparent conductive layer 41. The first transparent conductive lines 52a can extend from the first second sub-display area A2a through the second second sub-display area A2b to the first first sub-display area A1a. The second light emitting elements 22 in the second second sub-display area A2b can be electrically connected with the second pixel circuits 32 in the second second sub-display area A1b through the second transparent conductive lines 52b. The second transparent conductive lines 52b electrically connected with the second light emitting elements 22 in the second second sub-display area A2b can be located in the second transparent conductive layer 42. The second transparent conductive lines 52b can extend from the second second sub-display area A2b through the first first sub-display area A1a to the second first sub-display area A1b.

[0155] In some example embodiments, as shown in FIG. 1, the second light emitting elements 22 in the first second sub-display area A2a can be electrically connected with the second pixel circuits 32 in the first first sub-display area A1a through the first transparent conductive lines 52a. The first transparent conductive lines 52a electrically connected with the second light emitting elements 22 in the first second sub-display area A2a can be located in the first transparent conductive layer 41. The first transparent conductive lines 52a can extend from the first second sub-display area A2a through the second second sub-display area A2b to the first first sub-display area A1a. The second light emitting elements 22 in the second second sub-display area A2b can be electrically connected with the second pixel circuits 32 in the second second sub-display area A1b through the second transparent conductive lines 52b. The second transparent conductive lines 52b electrically connected with the second light emitting elements 22 in the second second sub-display area A2b can be located in the second transparent conductive layer 42. The second transparent conductive lines 52b can extend from the second second sub-display area A2b through the first first sub-display area A1a to the second first sub-display area A1b. Figures 10 to 11D As shown, the second light emitting elements 22 in the first second sub-display area A2a can be electrically connected with the second pixel circuits 32 in the first first sub-display area A1a through the first transparent conductive lines 52a. The first transparent conductive lines 52a electrically connected with the second light emitting elements 22 in the first second sub-display area A2a can be located in the first transparent conductive layer 41. The first transparent conductive lines 52a can extend from the first second sub-display area A2a through the second second sub-display area A2b to the first first sub-display area A1a. The second light emitting elements 22 in the second second sub-display area A2b can be electrically connected with the second pixel circuits 32 in the second second sub-display area A1b through the second transparent conductive lines 52b. The second transparent conductive lines 52b electrically connected with the second light emitting elements 22 in the second second sub-display area A2b can be located in the second transparent conductive layer 42. The second transparent conductive lines 52b can extend from the second second sub-display area A2b through the first first sub-display area A1a to the second first sub-display area A1b.

[0156] In some example embodiments, as shown in FIG. 1, the second light emitting elements 22 in the first second sub-display area A2a can be electrically connected with the second pixel circuits 32 in the first first sub-display area A1a through the first transparent conductive lines 52a. The first transparent conductive lines 52a electrically connected with the second light emitting elements 22 in the first second sub-display area A2a can be located in the first transparent conductive layer 41. The first transparent conductive lines 52a can extend from the first second sub-display area A2a through the second second sub-display area A2b to the first first sub-display area A1a. The second light emitting elements 22 in the second second sub-display area A2b can be electrically connected with the second pixel circuits 32 in the second second sub-display area A1b through the second transparent conductive lines 52b. The second transparent conductive lines 52b electrically connected with the second light emitting elements 22 in the second second sub-display area A2b can be located in the second transparent conductive layer 42. The second transparent conductive lines 52b can extend from the second second sub-display area A2b through the first first sub-display area A1a to the second first sub-display area A1b. Figures 11A to 11DAs shown, the number of second pixel circuits 32 in the first first sub-display area A1a can be the same as the number of second light emitting elements 22 in the first second sub-display area A2a, and the number of second pixel circuits 32 in the second first sub-display area A1b can be the same as the number of second light emitting elements 22 in the second second sub-display area A2b. In some examples, the number of second light emitting elements 22 in the first second sub-display area A2a can be substantially the same as the number of second light emitting elements 22 in the second second sub-display area A2b. The number of second pixel circuits 32 in the first first sub-display area A1a can be substantially the same as the number of second pixel circuits 32 in the second first sub-display area A1b. However, the present embodiment is not limited thereto. For example, the number of second light emitting elements 22 in the first second sub-display area A2a and the second second sub-display area A2b can be different. The number of second pixel circuits 32 in the first first sub-display area A1a and the second first sub-display area A1b can be different.

[0157] In some example embodiments, as shown in FIG. 1, the first first sub-display area A1a and the second first sub-display area A1b can each include a plurality of columns of second pixel circuits 32 and a plurality of columns of first light emitting elements 21. Since the size of the second pixel circuit 32 in the row direction X is smaller than the size of the first light emitting element 21 in the row direction X, the number of first light emitting elements 21 in the first first sub-display area A1a is smaller than the number of second pixel circuits 32, and the number of first light emitting elements 21 in the second first sub-display area A1b is smaller than the number of second pixel circuits 32. Figures 10 to 11E In some example embodiments, as shown in FIG. 1, the first first sub-display area A1a and the second first sub-display area A1b can each include a plurality of columns of second pixel circuits 32 and a plurality of columns of first light emitting elements 21. Since the size of the second pixel circuit 32 in the row direction X is smaller than the size of the first light emitting element 21 in the row direction X, the number of first light emitting elements 21 in the first first sub-display area A1a is smaller than the number of second pixel circuits 32, and the number of first light emitting elements 21 in the second first sub-display area A1b is smaller than the number of second pixel circuits 32.

[0158] Figures 10 to 11E In some example embodiments, as shown in FIG. 1, the first first sub-display area A1a and the second first sub-display area A1b can each include a plurality of columns of second pixel circuits 32 and a plurality of columns of first light emitting elements 21. Since the size of the second pixel circuit 32 in the row direction X is smaller than the size of the first light emitting element 21 in the row direction X, the number of first light emitting elements 21 in the first first sub-display area A1a is smaller than the number of second pixel circuits 32, and the number of first light emitting elements 21 in the second first sub-display area A1b is smaller than the number of second pixel circuits 32.

[0159] ​In some exemplary implementations, such as Figures 10 to 11E As shown, the first light-emitting element 21 in the first sub-display area A1a, near the second display area A2, is electrically connected to the first pixel circuit 31 in the third sub-display area A1c, away from the second display area A2. Similarly, the first light-emitting element 21 in the second sub-display area A1b, near the second display area A2, is electrically connected to the first pixel circuit 31 in the fourth sub-display area A1d, away from the second display area A2. This connection method of the first light-emitting element 21 and the first pixel circuit 31 in this example avoids problems such as short circuits or interference caused by overlapping transparent conductive lines.

[0160] In some examples, such as Figures 10 to 11GAs shown, the fifth transparent conductive line 51c electrically connecting the first light emitting element 21 in the third first sub-display area A1c and the first pixel circuit 31 in the fifth first sub-display area A1e can be located in the second transparent conductive layer 42. The sixth transparent conductive line 51d electrically connecting the first light emitting element 21 in the fourth first sub-display area A1d and the first pixel circuit 31 in the sixth first sub-display area A1f can be located in the third transparent conductive layer 43. The seventh transparent conductive line 51e electrically connecting the first light emitting element 21 in the fifth first sub-display area A1e and the first pixel circuit 31 in the seventh first sub-display area A1g can be located in the first transparent conductive layer 41. The eighth transparent conductive line 51f electrically connecting the first light emitting element 21 in the sixth first sub-display area A1f and the first pixel circuit 31 in the eighth first sub-display area A1h can be located in the second transparent conductive layer 42. The ninth transparent conductive line 51g electrically connecting the first light emitting element 21 in the seventh first sub-display area A1g and the first pixel circuit 31 in the ninth first sub-display area A1i can be located in the third transparent conductive layer 43. The tenth transparent conductive line 51h electrically connecting the first light emitting element 21 in the eighth first sub-display area A1h and the first pixel circuit 31 in the tenth first sub-display area A1j can be located in the first transparent conductive layer 41. The eleventh transparent conductive line 51i electrically connecting the first light emitting element 21 in the ninth first sub-display area A1i can be located in the second transparent conductive layer 42, and the twelfth transparent conductive line 51j electrically connecting the first light emitting element 21 in the tenth first sub-display area A1j can be located in the third transparent conductive layer 43. The connection mode of the first light emitting element 21 of one first sub-display area and the first pixel circuit 31 of another first sub-display area can refer to the connection mode of the second light emitting element 22 and the second pixel circuit 32, and thus will not be described here.

[0161] In the present example, the pixel circuits in the first first sub-display area A1a and the second first sub-display area A1b can both be second pixel circuits. The pixel circuits in the third first sub-display area A1c to the tenth first sub-display area A1j can all be first pixel circuits. By concentrating the second pixel circuits together and close to the second display area, the length of the transparent conductive line electrically connecting the second light emitting element and the second pixel circuit can be reduced.

[0162] In the present example, the number of first light emitting elements in any one first sub-display region can be less than or equal to the number of first light emitting elements in the adjacent first sub-display region on the side of the first sub-display region closer to the second display region. For example, the number of first light emitting elements 21 in the second first sub-display region A1b can be less than the number of first light emitting elements in the first first sub-display region A1a, and the number of first light emitting elements 21 in the third first sub-display region A1c can be less than the number of first light emitting elements in the second first sub-display region A1a. In the present example, the size of the first sub-display region can decrease as it is further away from the side of the first partition A21.

[0163] In the present example, the third first sub-display region A1c and the pixel circuit in the first sub-display region on the side of the third first sub-display region A1c further away from the second display region can all be first pixel circuits. The number of first pixel circuits 31 in the third first sub-display region A1c can be less than the number of first pixel circuits 31 in the first first sub-display region A1a. In the third first sub-display region A1c to the tenth first sub-display region A1j, the number of first pixel circuits 31 in any one first sub-display region can be less than or equal to the number of first pixel circuits 31 in the adjacent first sub-display region on the side of the first sub-display region closer to the second display region.

[0164] In the present example, the transparent conductive lines to which the plurality of first light emitting elements 21 in one first sub-display region are electrically connected can be in the same layer structure. The transparent conductive lines to which the first light emitting elements 21 in one first sub-display region are electrically connected and the transparent conductive lines to which the pixel circuits in the first sub-display region are electrically connected can be in different layer structures. For example, the third transparent conductive line 51a to which the first light emitting elements 21 in the first first sub-display region A1a are electrically connected can be in the third transparent conductive layer, and the first transparent conductive line 52a to which the second pixel circuit 32 in the first first sub-display region A1a is electrically connected can be in the first transparent conductive layer. In this way, the mutual interference between the transparent conductive lines can be reduced.

[0165] Figure 12 A schematic diagram of the first transparent conductive layer of at least one embodiment of the present disclosure. Figure 13 A schematic diagram of the second transparent conductive layer of at least one embodiment of the present disclosure. Figure 14 A schematic diagram of the third transparent conductive layer of at least one embodiment of the present disclosure. Figure 15 A schematic diagram of the three transparent conductive layers of at least one embodiment of the present disclosure. Figures 12 to 15 The connection relationship of multiple rows of pixel circuits and light emitting elements is illustrated in FIG. 1, and the connection relationship of a single row of pixel circuits and light emitting elements can be referred to FIG. 2. Figures 11A to 11G

[0166] In some example embodiments, as shown in FIG. 1, the first display region A1 can include a first sub-display region A1a, a second first sub-display region A1b, a third first sub-display region A1c, a fourth first sub-display region A1d, a fifth first sub-display region A1e, a sixth first sub-display region A1f, a seventh first sub-display region A1g, an eighth first sub-display region A1h, a ninth first sub-display region A1i, and a tenth first sub-display region A1j. Figures 10 to 15 ​As shown, the first transparent conductive line 52a, the fourth transparent conductive line 51b, the seventh transparent conductive line 51e, and the tenth transparent conductive line 51h can be located in the first transparent conductive layer 41. The second transparent conductive line 52b, the fifth transparent conductive line 51c, the eighth transparent conductive line 51f, and the eleventh transparent conductive line 51i can be located in the second transparent conductive layer 42. The third transparent conductive line 51a, the sixth transparent conductive line 51d, the ninth transparent conductive line 51g, and the twelfth transparent conductive line 51j can be located in the third transparent conductive layer 43. However, this embodiment is not limited in this respect. For example, the first transparent conductive line 52a, the fourth transparent conductive line 51b, the seventh transparent conductive line 51e, and the tenth transparent conductive line 51h can be located in the second transparent conductive layer 42; the second transparent conductive line 52b, the fifth transparent conductive line 51c, the eighth transparent conductive line 51f, and the eleventh transparent conductive line 51i can be located in the third transparent conductive layer 43; and the third transparent conductive line 51a, the sixth transparent conductive line 51d, the ninth transparent conductive line 51g, and the twelfth transparent conductive line 51j can be located in the first transparent conductive layer 41. Alternatively, in some other examples, the display substrate may include four transparent conductive layers. The first transparent conductive lines 52a to the twelfth transparent conductive lines 51j can be arranged in the four transparent conductive layers respectively.

[0167] like Figures 10 to 15 As shown, in this example, the longest transparent conductive line can be the first transparent conductive line 52a that electrically connects the second light-emitting element farthest from the first display area A1 within the first second sub-display area A2a to the second pixel circuit farthest from the second display area A2 within the first first sub-display area A1a. Compared to some implementations that electrically connect the second light-emitting element within the second sub-display area A2a to the second pixel circuit of the tenth first sub-display area via a transparent conductive line, this example can reduce the length of the transparent conductive line connecting the second light-emitting element 22 and the second pixel circuit 32, improving the situation where the length difference between transparent conductive lines is too large. This can improve the problem of poor uniformity of the under-screen display area and achieve a more uniform full-screen visual display effect.

[0168] In some exemplary implementations, such as Figure 8As shown, the second auxiliary area A12 of the first display area A1 can include a plurality of third sub-display areas arranged in the second direction (parallel to the row direction X in this example) in sequence along a side away from the second sub-area A22. The second sub-area A22 can include a plurality of fourth sub-display areas arranged in the second direction in sequence along a side away from the second auxiliary area A12. A second light emitting element in a fourth sub-display area can be electrically connected to a second pixel circuit in one third sub-display area through a second conductive line, and a first light emitting element in the third sub-display area can be electrically connected to a first pixel circuit in another third sub-display area away from the side of the second sub-area A22. In some examples, the connection manner between the second sub-area A22 and the second auxiliary area A12 can be mirrored about the middle axis OO' according to the connection manner between the first sub-area A21 and the first auxiliary area A11. At this time, the number of third sub-display areas can be the same as the number of first sub-display areas, and the number of second sub-display areas can be the same as the number of fourth sub-display areas. In other examples, the connection manner between the second sub-area A22 and the second auxiliary area A12 can be obtained according to the connection rule between the first sub-area A21 and the first auxiliary area A11. At this time, the number of third sub-display areas can be different from the number of first sub-display areas, the number of second sub-display areas can be different from the number of fourth sub-display areas, and the connection manner of the pixel circuits and the light emitting elements of the third sub-display areas and the fourth sub-display areas can be different from the connection manner of the pixel circuits and the light emitting elements of the first sub-display areas and the second sub-display areas. For example, the first sub-display areas and the second display areas can adopt the connection manner as shown in FIG. 6A, and the third sub-display areas and the fourth sub-display areas can adopt the connection manner as shown in FIG. 6B. Figure 9 Figure 18 Figure 19 However, the present embodiment is not limited in this regard.

[0169] The preparation process of the display substrate is exemplarily described below. The "patterning process" of the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and the like for metal materials, inorganic materials or transparent conductive materials, and includes coating organic materials, mask exposure and development and the like for organic materials. Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition, coating can use any one or more of spraying, spin coating and inkjet printing, and etching can use any one or more of dry etching and wet etching, without limitation of the present disclosure. "Thin film" refers to a thin film of a certain material on a substrate made by deposition, coating or other processes. If the "thin film" does not need to be patterned during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" needs to be patterned during the entire manufacturing process, it is referred to as a "thin film" before patterning, and a "layer" after patterning. The "layer" after patterning includes at least one "pattern". ​​

[0170] In some example embodiments, the manufacturing process of the display substrate can include the following operations.

[0171] (1) Forming a semiconductor layer.

[0172] In some example embodiments, forming the semiconductor layer can include depositing a semiconductor thin film on the substrate substrate 100, patterning the semiconductor thin film through a patterning process, and forming the semiconductor layer 10 in the first display area Al, as shown in FIG. 1A. Figure 6A The active layers of the seven transistors of one pixel circuit can be an integrated structure connected to each other.

[0173] In some example embodiments, the material of the semiconductor layer 10 can include, for example, polysilicon. The active layer can include at least one channel region and a plurality of doped regions. The channel region can not be doped with impurities and have semiconductor properties. The plurality of doped regions can be on both sides of the channel region and doped with impurities and thus have electrical conductivity. The impurities can vary depending on the type of transistor. In some examples, the doped regions of the active layer can be interpreted as the source electrode or the drain electrode of the transistor. The portion of the active layer between the transistors can be interpreted as a wire doped with impurities and can be used to electrically connect the transistors.

[0174] In some example embodiments, the substrate substrate 100 can be a rigid substrate, such as a glass substrate. However, the present embodiments are not limited thereto. For example, the substrate substrate can be a flexible substrate.

[0175] (2) Forming a first conductive layer.

[0176] In some example embodiments, on the substrate substrate 100 on which the above structure is formed, a first insulating thin film and a first conductive thin film are sequentially deposited, the first conductive thin film is patterned through a patterning process, a first insulating layer 101 covering the semiconductor layer 10 is formed, and a first conductive layer 11 is disposed on the first insulating layer 101 in the first display area Al, as shown in FIG. 1B. Figure 6B

[0177] (3) Forming a second conductive layer.

[0178] In some example embodiments, on the substrate substrate 100 on which the above structure is formed, a second insulating thin film and a second conductive thin film are sequentially deposited, the second conductive thin film is patterned through a patterning process, a second insulating layer 102 covering the first conductive layer 11 is formed, and a second conductive layer 12 is disposed on the second insulating layer 102 in the first display area Al, as shown in FIG. 1C. Figure 6C

[0179] (4) Forming a third insulating layer.

[0180] ​​In some example embodiments, a third insulating film is deposited on the substrate 100 having the foregoing pattern, and the third insulating film is patterned by a patterning process to form a third insulating layer 103, as shown in FIG. 3B. Figure 6D

[0181] (5) Forming a third conductive layer.

[0182] In some example embodiments, a third conductive film is deposited on the substrate having the foregoing pattern, and the third conductive film is patterned by a patterning process to form a third conductive layer 13 on the third insulating layer 103 of the first display area Al, as shown in FIG. 3B. Figure 4

[0183] At this point, the pixel circuit of the first display area Al is completed. The second display area A2 can include the substrate 100, and the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103 stacked on the substrate 100.

[0184] (6) Forming a first planar layer, a first transparent conductive layer, a second planar layer, a second transparent conductive layer, a third planar layer, a third transparent conductive layer, a fourth planar layer, an anode layer, a pixel definition layer, an organic light-emitting layer, and a cathode layer in sequence.

[0185] In some example embodiments, a first planar film is coated on the substrate 100 having the foregoing pattern, and the first planar film is patterned by a patterning process to form a first planar layer. Subsequently, a first transparent conductive film is deposited on the substrate having the foregoing pattern, and the first transparent conductive film is patterned by a patterning process to form a first transparent conductive layer. Subsequently, a second planar film is coated on the substrate having the foregoing pattern, and the second planar film is patterned by a patterning process to form a second planar layer. Subsequently, a second transparent conductive film is deposited on the substrate having the foregoing pattern, and the second transparent conductive film is patterned by a patterning process to form a second transparent conductive layer. Subsequently, a third planar film is coated on the substrate having the foregoing pattern, and the third planar film is patterned by a patterning process to form a third planar layer. Subsequently, a third transparent conductive film is deposited on the substrate having the foregoing pattern, and the third transparent conductive film is patterned by a patterning process to form a third transparent conductive layer. The arrangement of the transparent conductive lines of the first transparent conductive layer, the second transparent conductive layer, and the third transparent conductive layer can refer to FIG. 3B. Figures 10 to 15

[0186] ​​​Subsequently, an anode thin film is deposited on the substrate base on which the aforementioned pattern is formed, and the anode thin film is patterned by a patterning process to form an anode layer. Subsequently, a pixel definition thin film is coated on the substrate base on which the aforementioned pattern is formed, and a pixel definition layer is formed by a mask, exposure and development process. The pixel definition layer is formed with a plurality of pixel openings exposing the anode layer. Subsequently, an organic light emitting layer is formed in the aforementioned pixel openings, and the organic light emitting layer is connected to the anode. Subsequently, a cathode thin film is deposited, and the cathode thin film is patterned by a patterning process to form a cathode layer, which is electrically connected to the organic light emitting layer and the second power supply line, respectively. In some examples, an encapsulation layer is formed on the cathode layer, and the encapsulation layer can include a stacked structure of inorganic material / organic material / inorganic material.

[0187] In some example embodiments, the first conductive layer 11, the second conductive layer 12 and the third conductive layer 13 can employ a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material of the above-mentioned metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), which can be a single layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer 101, the second insulating layer 102 and the third insulating layer 103 can employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), which can be a single layer, a multi-layer or a composite layer. The first insulating layer 101 and the second insulating layer 102 can be referred to as gate insulating (GI) layers, and the third insulating layer 103 can be referred to as an interlayer insulating (ILD) layer. The first to fourth planar layers can employ an organic material such as polyimide, acrylic or polyethylene terephthalate, etc. The pixel definition layer can employ an organic material such as polyimide, acrylic or polyethylene terephthalate, etc. The anode layer can employ a reflective material such as metal, and the cathode layer can employ a transparent conductive material. However, the present embodiments are not limited thereto.

[0188] The structure of the display substrate of the present embodiments and the preparation process thereof are merely exemplary descriptions. In some example embodiments, the corresponding structure can be changed and the patterning process can be increased or reduced according to actual needs. For example, a fourth insulating layer and a fourth conductive layer can be provided on the side of the third conductive layer away from the substrate base, and the fourth conductive layer can include an anode connection electrode connecting the pixel circuit and the transparent conductive line. In some examples, the first conductive line electrically connecting the first light emitting element and the first pixel circuit can be provided in the fourth conductive layer. In other examples, one or two transparent conductive layers can be provided. However, the present embodiments are not limited thereto.

[0189] The preparation process of this exemplary embodiment can be realized using currently mature preparation equipment, is well compatible with existing preparation processes, is simple to implement, has high production efficiency, low production cost, and high yield.

[0190] Figure 16 This is another schematic diagram illustrating the connection between the first sub-display area and the second sub-display area, representing at least one embodiment of the present disclosure. In this example, the first second sub-display area A2a and the first first sub-display area A1a are used as examples. Figure 16 As shown, within the first second sub-display area A2a, the second conductive lines electrically connecting adjacent second light-emitting elements 22 can be of a heterogeneous structure. For example, one second light-emitting element 22 can be electrically connected to a second pixel circuit 32 within the first first sub-display area A1a via a thirteenth transparent conductive line 52a, and another second light-emitting element 22 adjacent to this second light-emitting element 22 in the row direction X can be electrically connected to another second pixel circuit 32 within the first first sub-display area A1a via a fourteenth transparent conductive line 52b. The thirteenth transparent conductive line 52a and the fourteenth transparent conductive line 52b can be of a heterogeneous structure, i.e., located in different transparent conductive layers. For example, the thirteenth transparent conductive line 52a can be located in the first transparent conductive layer, and the fourteenth transparent conductive line 52b can be located in the fourth transparent conductive layer, which can be located on the side of the third transparent conductive layer away from the substrate. However, this embodiment is not limited in this respect. In this example, the connection between the first light-emitting element in one first sub-display area and the first pixel circuit in another first sub-display area can be similar to the connection between the second light-emitting element 22 and the second pixel circuit 32 in this example, so it will not be described again here.

[0191] The remaining connection methods of the pixel circuit and light-emitting element of the display substrate in this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0192] Figure 17 This is another schematic diagram illustrating the connection between the first sub-display area and the second sub-display area, representing at least one embodiment of the present disclosure. In this example, the first second sub-display area A2a and the first first sub-display area A1a are used as examples. Figure 17As shown, the second light-emitting element 22 in the first second sub-display area A2a, near the first display area, can be electrically connected to the second pixel circuit 32 in the first first sub-display area A1a, away from the second display area. Similarly, the second light-emitting element 22 in the first second sub-display area A2a, away from the first display area, can be electrically connected to the second pixel circuit 32 in the first first sub-display area A1a, near the second display area. Within the first second sub-display area A2a, the second light-emitting element 22 can be electrically connected to the second pixel circuit 32 in the first first sub-display area A1a via a fifteenth transparent conductive line 52c. In some examples, the fifteenth transparent conductive line 52c can be formed by connecting multiple conductive segments. These multiple conductive segments can be located in different transparent conductive layers. For example, a fifteenth transparent conductive line 52c may include: a first conductive segment located in a first transparent conductive layer, a second conductive segment located in a second transparent conductive layer, and a third conductive segment located in the first transparent conductive layer. The first conductive segment can be electrically connected to the second light-emitting element 22, and the third conductive segment can be electrically connected to the second pixel circuit 32. The second conductive segment can connect the first conductive segment and the third conductive segment. However, this embodiment is not limited in this respect.

[0193] In this example, the connection between the first light-emitting element in one first sub-display area and the first pixel circuit in another first sub-display area can be similar to the connection between the second light-emitting element 22 and the second pixel circuit 32 in this example, so it will not be described again here.

[0194] The remaining connection relationships of the pixel circuit and light-emitting element of the display substrate in this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0195] Figure 18 This is another schematic diagram showing the connection between the first sub-display area and the second sub-display area, which is at least one embodiment of this disclosure. (See diagram below.) Figure 18 As shown, the second light-emitting element of the first second sub-display area A2a can be electrically connected to the second pixel circuit of the second first sub-display area A1b via the sixteenth transparent conductive line 53a. The second light-emitting element of the second second sub-display area A2b can be electrically connected to the second pixel circuit of the first second sub-display area A1a via the seventeenth transparent conductive line 53b. In some examples, the sixteenth transparent conductive line 53a and the seventeenth transparent conductive line 53b can be located in the same transparent conductive layer, for example, in the first transparent conductive layer. However, this embodiment is not limited to this. In other examples, the sixteenth transparent conductive line 53a and the seventeenth transparent conductive line 53b can be located in different transparent conductive layers.

[0196] The remaining connection relationships of the pixel circuit and light-emitting element of the display substrate in this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0197] Figure 19 This is another schematic diagram illustrating the connection between the first sub-display area and the second sub-display area, representing at least one embodiment of this disclosure. In this example, as... Figure 19 As shown, the first partition A21 of the second display area can be considered as a second sub-display area. The first auxiliary area A11 adjacent to the second sub-display area may include multiple first sub-display areas (e.g., first to fifth first sub-display areas A1-1 arranged sequentially along the side away from the first partition A21 in the row direction X). The second light-emitting element within the first partition A21 can be electrically connected to the second pixel circuit within the first first sub-display area A1-1 via the eighteenth transparent conductive line 61a. The first light-emitting element within the first first sub-display area A1-1 can be electrically connected to the first pixel circuit within the second first sub-display area A1-2 via the nineteenth transparent conductive line 61b. The first light-emitting element within the second first sub-display area A1-2 can be electrically connected to the first pixel circuit within the third first sub-display area A1-3 via the twentieth transparent conductive line 61c. The first light-emitting element within the third first sub-display area A1-3 can be electrically connected to the first pixel circuit within the fourth first sub-display area A1-4 via the twenty-first transparent conductive line 61d. The first light-emitting element in the fourth first sub-display area A1-4 can be electrically connected to the first pixel circuit in the fifth first sub-display area A1-5 via the twenty-second transparent conductive line 61e. The first light-emitting element in the fifth first sub-display area A1-5 can be electrically connected to the first pixel circuit in the area of ​​the fifth first sub-display area A1-5 away from the second display area via the twenty-third transparent conductive line 61f. In this example, the first light-emitting element of one first sub-display area can be electrically connected to the first pixel circuit in the adjacent first sub-display area away from the second display area. In this example, n can be 1, and i can be 1. The connection method of the light-emitting elements and pixel circuits in different areas in this example can be referred to the description of the foregoing embodiment, and will not be repeated here.

[0198] In this example, the second conductive line may include an eighteenth transparent conductive line 61a and a nineteenth transparent conductive line 61b; the first conductive line may include twentieth transparent conductive lines 61c to twenty-third transparent conductive lines 61f. The eighteenth transparent conductive line 61a and the nineteenth transparent conductive line 61b may be heterogeneous structures, i.e., located in different transparent conductive layers. This example may provide two transparent conductive layers. For example, the eighteenth transparent conductive line 61a, the twentieth transparent conductive line 61c, and the twenty-second transparent conductive line 61e may be co-layered and located in the first transparent conductive layer, and the nineteenth transparent conductive line 61b, the twenty-first transparent conductive line 61d, and the twenty-third transparent conductive line 61f may be co-layered and located in the second transparent conductive layer. The second transparent conductive layer may be located on the side of the first transparent conductive layer away from the substrate. However, this embodiment is not limited in this respect. The film layer configuration of the transparent conductive lines in this embodiment can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0199] Figure 20 This is another schematic diagram showing the connection between the first display area and the second display area according to at least one embodiment of the present disclosure. In this example, the area where the second pixel circuit is disposed can be obtained by reducing the size of the first pixel circuit in the column direction Y. In this example, the first direction can be the column direction Y. Figure 20 As shown, the first display area A1 may include a third auxiliary area A13 adjacent to the second display area A2 in the column direction Y. The third auxiliary area A13 may include a plurality of first sub-display areas sequentially arranged in the column direction Y along the side away from the second display area A2. The second display area A2 may include a plurality of second sub-display areas divided along the column direction Y, such as two second sub-display areas. The second light-emitting element of the second sub-display area can be electrically connected to the second pixel circuit of the first sub-display area through the second conductive line 52. The first light-emitting element of the first sub-display area can be electrically connected to the first pixel circuit in another first sub-display area in the column direction Y away from the second display area A2 through the first conductive line 51. The connection relationship between the first sub-display area and the second sub-display area, and the connection method between the pixel circuit and the light-emitting element in this embodiment can be obtained by referring to the description of the foregoing embodiment and making a simple change in direction, so it will not be repeated here.

[0200] Figure 21 This is another schematic diagram illustrating the connection between the first display area and the second display area, representing at least one embodiment of this disclosure. In this example, as... Figure 21 As shown, the second display area A2 can be located at the top of the display area and on one side of the first display area A1 in the column direction Y. In some examples, the area for setting the second pixel circuit can be obtained by reducing the size of the first pixel circuit in the column direction Y. However, this embodiment is not limited to this.

[0201] In some examples, as shown in FIG. 1A, the first display area A1 can include a plurality of first sub-display areas A11a arranged in sequence along a side away from the second display area A2 in the first direction (parallel to the column direction Y in this example). The second display area A2 can include a plurality of second sub-display areas divided in the column direction Y, or can be a whole second sub-display area. The second light emitting element in the second sub-display area can be electrically connected to the second pixel circuit in the first sub-display area A11a closest to the second display area A2 through the second conductive line 52, and the first light emitting element in the first sub-display area A11a can be electrically connected to the first pixel circuit in another first sub-display area A11a away from the second display area A2 through the first conductive line 51. The connection relationship between the first sub-display area and the second sub-display area, and the connection mode between the pixel circuit and the light emitting element of this embodiment can be referred to the description of the foregoing embodiments, and will not be described here again. Figure 21

[0202] Figure 22 Another connection diagram of the first display area and the second display area of at least one embodiment of the present disclosure is shown in FIG. 1C. In this example, as shown in FIG. 1C, the second display area A2 can be located in the left half of the display area, and on one side of the first display area A1 in the row direction X. In some examples, the area where the second pixel circuit is arranged can be obtained by reducing the size of the first pixel circuit in the row direction X. However, this embodiment is not limited thereto. Figure 22

[0203] In some examples, as shown in FIG. 1D, the first display area A1 can include a plurality of first sub-display areas A11a arranged in sequence along a side away from the second display area A2 in the first direction (parallel to the row direction X in this example). The second display area A2 can include a plurality of second sub-display areas divided in the row direction X, or can be a whole second sub-display area. The second light emitting element in the second sub-display area can be electrically connected to the second pixel circuit in the first sub-display area A11a closest to the second display area A2 through the second conductive line 52, and the first light emitting element in the first sub-display area A11a can be electrically connected to the first pixel circuit in another first sub-display area A11a away from the second display area A2 through the first conductive line 51. The connection relationship between the first sub-display area and the second sub-display area, and the connection mode between the pixel circuit and the light emitting element of this embodiment can be referred to the description of the foregoing embodiments, and will not be described here again. Figure 22

[0204] Figure 23 Another connection diagram of the first display area and the second display area of at least one embodiment of the present disclosure is shown in FIG. 1C. In this example, as shown in FIG. 1C, the second display area A2 can be located in the left half of the display area, and on one side of the first display area A1 in the row direction X. In some examples, the area where the second pixel circuit is arranged can be obtained by reducing the size of the first pixel circuit in the row direction X. However, this embodiment is not limited thereto. Figure 23 ​​​As shown, the second display area A2 can be located in the middle of the display area and is adjacent to the first display area A1 on both sides in the row direction X. In some examples, the area for setting the second pixel circuit can be obtained by reducing the size of the first pixel circuit in the row direction X. However, this embodiment is not limited to this.

[0205] In some examples, such as Figure 23 As shown, the second display area A2 may include: a first partition A21 and a second partition A22 divided along the row direction X. The first partition A21 may include: a plurality of second sub-display areas divided along a first direction (parallel to the row direction X in this example), or the first partition A21 may be a single second sub-display area. The second partition A22 may include: a plurality of fourth sub-display areas divided along a second direction (parallel to the row direction X in this example), or the second partition A22 may be a single fourth sub-display area. In some examples, the first partition A21 and the second partition A22 may be approximately symmetrical about the central axis of the second display area A2 in the row direction X. However, this embodiment is not limited to this.

[0206] In some examples, such as Figure 23 As shown, the first display area A1 may include: a plurality of first sub-display areas A11a sequentially arranged along the side away from the first partition A21 in a first direction, and a plurality of third sub-display areas A12a sequentially arranged along the side away from the second partition A22 in a second direction. A second light-emitting element in a second sub-display area can be electrically connected via a second conductive line 52 to a second pixel circuit in a first sub-display area A11a closest to the first partition A21. The first light-emitting element in this first sub-display area A11a can be electrically connected via a first conductive line 51 to a first pixel circuit in another first sub-display area A11a along the side away from the first partition A21. Similarly, a second light-emitting element in a fourth sub-display area can be electrically connected via a second conductive line 52 to a second pixel circuit in a third sub-display area A12a closest to the second partition A22. The first light-emitting element in this third sub-display area A12a can be electrically connected via a first conductive line 51 to a first pixel circuit in another third sub-display area A12a along the side away from the second partition A22.

[0207] The connection relationship between the first and second sub-display areas, the connection relationship between the third and fourth sub-display areas, and the connection method between the pixel circuit and the light-emitting element in this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0208] Figure 24 This is another schematic diagram illustrating the connection between the first display area and the second display area, representing at least one embodiment of this disclosure. In this example, as... Figure 24As shown, the second display area A2 can be located at the upper left corner of the display area, and the second display area A2 is adjacent to the first display area A1 in both the row direction X and the column direction Y. In some examples, the area where the second pixel circuit is arranged can be obtained by reducing the size of the first pixel circuit in the row direction X and the column direction Y. However, the present embodiment is not limited thereto.

[0209] In some examples, as shown in FIG. 1B, the first display area A1 can include a first sub-display area A11 and a second sub-display area A12. The first sub-display area A11 can include a plurality of first sub-display areas divided in the first direction (parallel to the column direction Y in the present example), or the first sub-display area A11 as a whole can be a first sub-display area. The second sub-display area A12 can include a plurality of third sub-display areas divided in the second direction (parallel to the row direction X in the present example), or the second sub-display area A12 as a whole can be a third sub-display area. In some examples, the first sub-display area A11 and the second sub-display area A12 can be substantially symmetrical about the diagonal line of the first display area A1. However, the present embodiment is not limited thereto. For example, the first sub-display area A11 and the second sub-display area A12 can be substantially symmetrical about the middle axis of the first display area A1 in the row direction X or the column direction Y. Figure 24 In some examples, as shown in FIG. 1B, the first display area A1 can include a first sub-display area A11 and a second sub-display area A12. The first sub-display area A11 can include a plurality of first sub-display areas divided in the first direction (parallel to the column direction Y in the present example), or the first sub-display area A11 as a whole can be a first sub-display area. The second sub-display area A12 can include a plurality of third sub-display areas divided in the second direction (parallel to the row direction X in the present example), or the second sub-display area A12 as a whole can be a third sub-display area. In some examples, the first sub-display area A11 and the second sub-display area A12 can be substantially symmetrical about the diagonal line of the first display area A1. However, the present embodiment is not limited thereto. For example, the first sub-display area A11 and the second sub-display area A12 can be substantially symmetrical about the middle axis of the first display area A1 in the row direction X or the column direction Y.

[0210] Figure 24 In some examples, as shown in FIG. 1B, the first display area A1 can include a first sub-display area A11 and a second sub-display area A12. The first sub-display area A11 can include a plurality of first sub-display areas divided in the first direction (parallel to the column direction Y in the present example), or the first sub-display area A11 as a whole can be a first sub-display area. The second sub-display area A12 can include a plurality of third sub-display areas divided in the second direction (parallel to the row direction X in the present example), or the second sub-display area A12 as a whole can be a third sub-display area. In some examples, the first sub-display area A11 and the second sub-display area A12 can be substantially symmetrical about the diagonal line of the first display area A1. However, the present embodiment is not limited thereto. For example, the first sub-display area A11 and the second sub-display area A12 can be substantially symmetrical about the middle axis of the first display area A1 in the row direction X or the column direction Y.

[0211] The connection relationship between the first sub-display area and the second sub-display area, the connection relationship between the third sub-display area and the fourth sub-display area, and the connection mode between the pixel circuit and the light emitting element of the present embodiment can refer to the description of the foregoing embodiments, and will not be described here.

[0212] Figure 25 ​This is another schematic diagram illustrating the connection between the first display area and the second display area, representing at least one embodiment of this disclosure. In this example, as... Figure 25 As shown, the second display area A2 can be located at the top center of the display area, and the first display area A1 surrounds the second display area A2. In some examples, the area for setting the second pixel circuit can be obtained by reducing the size of the first pixel circuit in the row direction X and column direction Y. For example... Figure 25 As shown, the second display area A2 may include a first partition A21 and a second partition A22, which are approximately symmetrical about the central axis OO' of the second display area A2 in the row direction X. The first display area A1 may include a plurality of first sub-display areas A11a arranged sequentially along the side away from the first partition A21 in a first direction (parallel to the row direction X in this example), and a plurality of third sub-display areas A12a arranged sequentially along the side away from the second partition A22 in a second direction (parallel to the column direction Y in this example). The first partition A21 may include a plurality of second sub-display areas divided along the first direction, or the first partition A21 as a whole may be a second sub-display area. The second partition A22 may include a plurality of fourth sub-display areas divided along the second direction, or the second partition A22 as a whole may be a fourth sub-display area. The second light-emitting element in the second sub-display area can be electrically connected via the second conductive line 52 to the second pixel circuit in a first sub-display area A11a closest to the first partition A21. The first light-emitting element in this first sub-display area A11a can be electrically connected via the first conductive line 51 to the first pixel circuit in another first sub-display area A11a along the side away from the first partition A21. Similarly, the second light-emitting element in the fourth sub-display area can be electrically connected via the second conductive line 52 to the second pixel circuit in a third sub-display area A12a closest to the second partition A22. The first light-emitting element in this third sub-display area A12a can be electrically connected via the first conductive line 51 to the first pixel circuit in another third sub-display area A12a along the side away from the second partition A22. The connection relationships between the first and second sub-display areas, between the third and fourth sub-display areas, and between the pixel circuits and the light-emitting elements in this embodiment can be referred to the description in the foregoing embodiments, and therefore will not be repeated here.

[0213] Figure 26 This is another schematic diagram illustrating the connection between the first display area and the second display area, representing at least one embodiment of this disclosure. In this example, as... Figure 26 As shown, the second display area A2 can be located at the top center of the display area, and the first display area A1 surrounds the second display area A2. In some examples, the area for setting the second pixel circuit can be obtained by reducing the size of the first pixel circuit in the row direction X and column direction Y. For example... Figure 26As shown, the second display area A2 may include a first partition A21, a second partition A22, and a third partition A23. For example, the first partition A21, the second partition A22, and the third partition A23 can be obtained by dividing the second display area A2 along the row direction X. However, this embodiment is not limited to this. The first partition A21 may include multiple second sub-display areas divided along a first direction (parallel to the row direction X in this example), or the first partition A21 may be a single second sub-display area. The second partition A22 may include multiple fourth sub-display areas divided along a second direction (parallel to the row direction X in this example), or the second partition A22 may be a single fourth sub-display area. The third partition A23 may include multiple sixth sub-display areas divided along a third direction (parallel to the column direction Y in this example), or the third partition A23 may be a single sixth sub-display area.

[0214] In some examples, such as Figure 26 As shown, the first display area A1 may include: a plurality of first sub-display areas A11a sequentially arranged in a first direction along the side away from the first partition A21; a plurality of third sub-display areas A12a sequentially arranged in a second direction along the side away from the second partition A22; and a plurality of fifth sub-display areas A13a sequentially arranged in a third direction along the side away from the third partition A23. A second light-emitting element in a second sub-display area can be electrically connected via a second conductive line 52 to a second pixel circuit in a first sub-display area A11a closest to the first partition A21. The first light-emitting element in this first sub-display area A11a can be electrically connected via a first conductive line 51 to a first pixel circuit in another first sub-display area A11a along the side away from the first partition A21. A second light-emitting element in a fourth sub-display area can be electrically connected via a second conductive line 52 to a second pixel circuit in a third sub-display area A12a closest to the second partition A22. The first light-emitting element in this third sub-display area A12a can be electrically connected via a first conductive line 51 to a first pixel circuit in another third sub-display area A12a along the side away from the second partition A22. The second light-emitting element in the sixth sub-display area can be electrically connected to the second pixel circuit in a fifth sub-display area A13a closest to the third partition A23 via the second conductive line 52. The first light-emitting element in the fifth sub-display area A13a can be electrically connected to the first pixel circuit in another fifth sub-display area A13a along the side away from the third partition A23 via the first conductive line 51.

[0215] The connection relationship between the first and second sub-display regions, the connection relationship between the third and fourth sub-display regions, the connection relationship between the fifth and sixth sub-display regions, and the connection manner between the pixel circuit and the light emitting element of the present embodiment can refer to the description of the foregoing embodiments, and thus will not be described here.

[0216] Figure 27 Another connection schematic diagram of the first and second display regions of at least one embodiment of the present disclosure is shown in FIG. 6. In the present example, as shown in FIG. 6, the second display region A2 can be located at the middle of the top of the display region, and the first display region A1 surrounds the four sides of the second display region A2. In some examples, the area where the second pixel circuit is arranged can be obtained by reducing the size of the first pixel circuit in the column direction Y and the row direction X. However, the present embodiment is not limited thereto. Figure 27

[0217] In some examples, as shown in FIG. 7, the second display region A2 can include a first sub-region A21, a second sub-region A22, a third sub-region A23, and a fourth sub-region A24. For example, the first sub-region A21, the second sub-region A22, the third sub-region A23, and the fourth sub-region A24 can be obtained by dividing the second display region A2 in the row direction X and the column direction Y, or can be obtained by dividing the second display region A2 along the diagonal direction. However, the present embodiment is not limited thereto. The first sub-region A21 can include a plurality of second sub-display regions divided along a first direction (parallel to the row direction X in the present example), or the first sub-region A21 can be an integral second sub-display region. The second sub-region A22 can include a plurality of fourth sub-display regions divided along a second direction (parallel to the row direction X in the present example), or the second sub-region A22 can be an integral fourth sub-display region. The third sub-region A23 can include a plurality of sixth sub-display regions divided along a third direction (parallel to the column direction Y in the present example), or the third sub-region A23 can be an integral sixth sub-display region. The fourth sub-region A24 can include a plurality of eighth sub-display regions divided along a fourth direction (parallel to the column direction Y in the present example), or the fourth sub-region A24 can be an integral eighth sub-display region. Figure 27

[0218] In some examples, as shown in FIG. 8, the second display region A2 can include a first sub-region A21, a second sub-region A22, a third sub-region A23, and a fourth sub-region A24. For example, the first sub-region A21, the second sub-region A22, the third sub-region A23, and the fourth sub-region A24 can be obtained by dividing the second display region A2 in the row direction X and the column direction Y, or can be obtained by dividing the second display region A2 along the diagonal direction. However, the present embodiment is not limited thereto. The first sub-region A21 can include a plurality of second sub-display regions divided along a first direction (parallel to the row direction X in the present example), or the first sub-region A21 can be an integral second sub-display region. The second sub-region A22 can include a plurality of fourth sub-display regions divided along a second direction (parallel to the row direction X in the present example), or the second sub-region A22 can be an integral fourth sub-display region. The third sub-region A23 can include a plurality of sixth sub-display regions divided along a third direction (parallel to the column direction Y in the present example), or the third sub-region A23 can be an integral sixth sub-display region. The fourth sub-region A24 can include a plurality of eighth sub-display regions divided along a fourth direction (parallel to the column direction Y in the present example), or the fourth sub-region A24 can be an integral eighth sub-display region. Figure 27 ​​As shown, the first display area A1 can include: a plurality of first sub-display areas A11a arranged in the first direction along the side away from the first sub-area A21 in sequence, a plurality of third sub-display areas A12a arranged in the second direction along the side away from the second sub-area A22 in sequence, a plurality of fifth sub-display areas A13a arranged in the third direction along the side away from the third sub-area A23 in sequence, and a plurality of seventh sub-display areas A14a arranged in the fourth direction along the side away from the fourth sub-area A24 in sequence. The second light emitting element in the second sub-display area can be electrically connected to the second pixel circuit in the first sub-display area A11a closest to the first sub-area A21 through the second conductive line 52, and the first light emitting element in the first sub-display area A11a can be electrically connected to the first pixel circuit in another first sub-display area A11a along the side away from the first sub-area A21 through the first conductive line 51. The second light emitting element in the fourth sub-display area can be electrically connected to the second pixel circuit in the third sub-display area A12a closest to the second sub-area A22 through the second conductive line 52, and the first light emitting element in the third sub-display area A12a can be electrically connected to the first pixel circuit in another third sub-display area A12a along the side away from the second sub-area A22 through the first conductive line 51. The second light emitting element in the sixth sub-display area can be electrically connected to the second pixel circuit in the fifth sub-display area A13a closest to the third sub-area A23 through the second conductive line 52, and the first light emitting element in the fifth sub-display area A13a can be electrically connected to the first pixel circuit in another fifth sub-display area A13a along the side away from the third sub-area A23 through the first conductive line 51. The second light emitting element in the eighth sub-display area can be electrically connected to the second pixel circuit in the seventh sub-display area A14a closest to the fourth sub-area A24 through the second conductive line 52, and the first light emitting element in the seventh sub-display area A14a can be electrically connected to the first pixel circuit in another seventh sub-display area A14a along the side away from the fourth sub-area A24 through the first conductive line 51.

[0219] The connection relationship between the first sub-display area and the second sub-display area, the connection relationship between the third sub-display area and the fourth sub-display area, the connection relationship between the fifth sub-display area and the sixth sub-display area, the connection relationship between the seventh sub-display area and the eighth sub-display area, and the connection mode between the pixel circuit and the light emitting element of the present embodiment can refer to the description of the foregoing embodiments, and will not be described here.

[0220] Figure 28 Another connection diagram of the first display area and the second display area of at least one embodiment of the present disclosure is shown. In the present example, as shown in FIG. 16, the first display area A1 can include: a plurality of first sub-display areas A11a arranged in the first direction along the side away from the first sub-area A21 in sequence, a plurality of third sub-display areas A12a arranged in the second direction along the side away from the second sub-area A22 in sequence, a plurality of fifth sub-display areas A13a arranged in the third direction along the side away from the third sub-area A23 in sequence, and a plurality of seventh sub-display areas A14a arranged in the fourth direction along the side away from the fourth sub-area A24 in sequence. Figure 28As shown, the second display area A2 can be located in the middle of the top of the display area, and the first display area A1 surrounds the second display area A2 on three sides. The upper side of the second display area A2 is directly adjacent to the peripheral area BB, and the first display area A1 surrounds the lower side, the left side and the right side of the second display area A2. For the area division and connection relationship of the first display area and the second display area of the embodiment, reference can be made to the description of the first display area and the second display area of the first embodiment. Figure 26 As shown, the second display area A2 can be located in the middle of the top of the display area, and the first display area A1 surrounds the second display area A2 on three sides. The upper side of the second display area A2 is directly adjacent to the peripheral area BB, and the first display area A1 surrounds the lower side, the left side and the right side of the second display area A2. For the area division and connection relationship of the first display area and the second display area of the embodiment, reference can be made to the description of the first display area and the second display area of the first embodiment.

[0221] Figure 29 Another connection diagram of the first display area and the second display area of at least one embodiment of the present disclosure is shown. In some examples, the area where the second pixel circuit is arranged can be obtained by reducing the size of the first pixel circuit in the row direction X and the column direction Y. However, the present embodiment is not limited thereto.

[0222] In some examples, as shown in FIG. 6A, the second display area A2 can be located in the middle of the top of the display area, and the first display area A1 surrounds the second display area A2 on three sides. The upper side of the second display area A2 is directly adjacent to the peripheral area BB, and the first display area A1 surrounds the lower side, the left side and the right side of the second display area A2. For the area division and connection relationship of the first display area and the second display area of the embodiment, reference can be made to the description of the first display area and the second display area of the first embodiment. Figure 29 As shown, the second display area A2 can be located in the middle of the top of the display area, and the first display area A1 surrounds the second display area A2 on three sides. The upper side of the second display area A2 is directly adjacent to the peripheral area BB, and the first display area A1 surrounds the lower side, the left side and the right side of the second display area A2. For the area division and connection relationship of the first display area and the second display area of the embodiment, reference can be made to the description of the first display area and the second display area of the first embodiment.

[0223] In some examples, as shown in FIG. 6A, the second display area A2 can be located in the middle of the top of the display area, and the first display area A1 surrounds the second display area A2 on three sides. The upper side of the second display area A2 is directly adjacent to the peripheral area BB, and the first display area A1 surrounds the lower side, the left side and the right side of the second display area A2. For the area division and connection relationship of the first display area and the second display area of the embodiment, reference can be made to the description of the first display area and the second display area of the first embodiment. Figure 29 As shown, the second display area A2 can be located in the middle of the top of the display area, and the first display area A1 surrounds the second display area A2 on three sides. The upper side of the second display area A2 is directly adjacent to the peripheral area BB, and the first display area A1 surrounds the lower side, the left side and the right side of the second display area A2. For the area division and connection relationship of the first display area and the second display area of the embodiment, reference can be made to the description of the first display area and the second display area of the first embodiment.

[0224] In some examples, such as Figure 29 As shown, the first display area A1 may include: a plurality of first sub-display areas A11a arranged sequentially along the side away from the first partition A21 in a first direction; a plurality of third sub-display areas A12a arranged sequentially along the side away from the second partition A22 in a second direction; a plurality of fifth sub-display areas A13a arranged sequentially along the side away from the third partition A23 in a third direction; and a plurality of seventh sub-display areas A14a arranged sequentially along the side away from the fourth partition A24 in a fourth direction. A second light-emitting element in a second sub-display area can be electrically connected to a second pixel circuit in a first sub-display area A11a closest to the first partition A21 via a second conductive line 52. A first light-emitting element in this first sub-display area A11a can be electrically connected to a first pixel circuit in another first sub-display area A11a along the side away from the first partition A21 via a first conductive line 51. The second light-emitting element in the fourth sub-display area can be electrically connected via the second conductive line 52 to the second pixel circuit in a third sub-display area A12a closest to the second partition A22. The first light-emitting element in this third sub-display area A12a can be electrically connected via the first conductive line 51 to the first pixel circuit in another third sub-display area A12a along the side away from the second partition A22. The second light-emitting element in the sixth sub-display area can be electrically connected via the second conductive line 52 to the second pixel circuit in a fifth sub-display area A13a closest to the third partition A23. The first light-emitting element in this fifth sub-display area A13a can be electrically connected via the first conductive line 51 to the first pixel circuit in another fifth sub-display area A13a along the side away from the third partition A23. The second light-emitting element in the eighth sub-display area can be electrically connected to the second pixel circuit in a seventh sub-display area A14a closest to the fourth partition A24 via the second conductive line 52. The first light-emitting element in the seventh sub-display area A14a can be electrically connected to the first pixel circuit in another seventh sub-display area A14a along the side away from the fourth partition A24 via the first conductive line 51.

[0225] The connection relationships between the first and second sub-display areas, the third and fourth sub-display areas, the fifth and sixth sub-display areas, the seventh and eighth sub-display areas, and the connection methods between the pixel circuit and the light-emitting element in this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0226] Figure 30 This is another schematic diagram showing the connection between the first display area and the second display area according to at least one embodiment of the present disclosure. In this example, the area where the second pixel circuit is disposed can be obtained by reducing the size of the first pixel circuit in the row direction X and the column direction Y. In this example, as... Figure 30As shown, the second display area can be located in the middle of the top of the display area, and the first display area A1 surrounds the second display area. The second display area can include a first sub-area A21, a second sub-area A22, a third sub-area A23, and a fourth sub-area A24. The first sub-area A21 to the fourth sub-area A24 can be divided according to a middle axis OO’ of the second display area in the row direction X and a middle axis UU’ of the second display area in the column direction Y.

[0227] In some examples, as shown in FIG. 2A, the first display area A1 can include a first sub-area A11, a second sub-area A12, a third sub-area A13, and a fourth sub-area A14. The first sub-area A11 to the fourth sub-area A14 can be divided according to a middle axis OO’ of the first display area A1 in the row direction X and a middle axis UU’ of the first display area A1 in the column direction Y. Figure 30 As shown, the first sub-area A21 can include a plurality of second sub-display areas divided along a first direction (parallel to the sixth direction E in this example), or the first sub-area A21 can be a whole second sub-display area. The second sub-area A22 can include a plurality of fourth sub-display areas divided along a second direction (parallel to the fifth direction F in this example), or the second sub-area A22 can be a whole fourth sub-display area. The third sub-area A23 can include a plurality of sixth sub-display areas divided along a third direction (parallel to the sixth direction E in this example), or the third sub-area A23 can be a whole sixth sub-display area. The fourth sub-area A24 can include a plurality of eighth sub-display areas divided along a fourth direction (parallel to the fifth direction F in this example), or the fourth sub-area A24 can be a whole eighth sub-display area.

[0228] In some examples, as shown in FIG. 2A, the first display area A1 can include a first sub-area A11, a second sub-area A12, a third sub-area A13, and a fourth sub-area A14. The first sub-area A11 to the fourth sub-area A14 can be divided according to a middle axis OO’ of the first display area A1 in the row direction X and a middle axis UU’ of the first display area A1 in the column direction Y. Figure 30As shown, the first display area A1 can include: a plurality of first sub-display areas A11a arranged in the first direction along the side away from the first sub-area A21 in sequence, a plurality of third sub-display areas A12a arranged in the second direction along the side away from the second sub-area A22 in sequence, a plurality of fifth sub-display areas A13a arranged in the third direction along the side away from the third sub-area A23 in sequence, and a plurality of seventh sub-display areas A14a arranged in the fourth direction along the side away from the fourth sub-area A24 in sequence. The second light emitting element in the second sub-display area can be electrically connected to the second pixel circuit in the first sub-display area A11a closest to the first sub-area A21 through the second conductive line 52, and the first light emitting element in the first sub-display area A11a can be electrically connected to the first pixel circuit in another first sub-display area A11a along the side away from the first sub-area A21 through the first conductive line 51. The second light emitting element in the fourth sub-display area can be electrically connected to the second pixel circuit in the third sub-display area A12a closest to the second sub-area A22 through the second conductive line 52, and the first light emitting element in the third sub-display area A12a can be electrically connected to the first pixel circuit in another third sub-display area A12a along the side away from the second sub-area A22 through the first conductive line 51. The second light emitting element in the sixth sub-display area can be electrically connected to the second pixel circuit in the fifth sub-display area A13a closest to the third sub-area A23 through the second conductive line 52, and the first light emitting element in the fifth sub-display area A13a can be electrically connected to the first pixel circuit in another fifth sub-display area A13a along the side away from the third sub-area A23 through the first conductive line 51. The second light emitting element in the eighth sub-display area can be electrically connected to the second pixel circuit in the seventh sub-display area A14a closest to the fourth sub-area A24 through the second conductive line 52, and the first light emitting element in the seventh sub-display area A14a can be electrically connected to the first pixel circuit in another seventh sub-display area A14a along the side away from the fourth sub-area A24 through the first conductive line 51.

[0229] The connection relationship between the first sub-display area and the second sub-display area, the connection relationship between the third sub-display area and the fourth sub-display area, the connection relationship between the fifth sub-display area and the sixth sub-display area, the connection relationship between the seventh sub-display area and the eighth sub-display area, and the connection mode between the pixel circuit and the light emitting element of the present embodiment can refer to the description of the foregoing embodiments, and will not be described here.

[0230] The display device of at least one embodiment of the present disclosure also provides a display device including the display substrate as described above.

[0231] Figure 31 A schematic view of a display device of at least one embodiment of the present disclosure. As shown in FIG. 8, the display device includes a display substrate 100, a first display area A1, a second display area A2, a third display area A3, a fourth display area A4, a first conductive line 51, and a second conductive line 52. Figure 31As shown, the embodiment provides a display device, comprising a display substrate 91 and a photosensitive sensor 92 located on the light-out side of the display structure layer away from the display substrate 91. The orthographic projection of the photosensitive sensor 92 on the display substrate 91 overlaps with the second display area A2.

[0232] In some example embodiments, the display substrate 91 can be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device can be an OLED display, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or any product or component with a display function, and the embodiments of the present disclosure are not limited thereto.

[0233] The drawings in the present disclosure only relate to the structures involved in the present disclosure, and other structures can refer to the usual design. In the case of no conflict, the features in the embodiments of the present disclosure can be combined with each other to obtain new embodiments.

[0234] Those skilled in the art should understand that the technical solutions of the present disclosure can be modified or replaced equivalently without departing from the spirit and scope of the technical solutions of the present disclosure, and all should be covered in the scope of the claims of the present disclosure.

Claims

1. A display substrate, comprising: The substrate includes a first display area and a second display area, wherein the first display area is located on at least one side of the second display area; the light transmittance of the first display area is less than the light transmittance of the second display area. Multiple pixel circuits, including multiple first pixel circuits and multiple second pixel circuits located in the first display area; Multiple light-emitting elements, including multiple first light-emitting elements located in the first display area and multiple second light-emitting elements located in the second display area; At least one of the plurality of first pixel circuits is electrically connected to at least one of the plurality of first light-emitting elements, and the at least one first pixel circuit is configured to drive the at least one first light-emitting element to emit light; at least one of the plurality of second pixel circuits is electrically connected to at least one of the plurality of second light-emitting elements, and the at least one second pixel circuit is configured to drive the at least one second light-emitting element to emit light. The first display area includes: a first sub-display area to the Nth first sub-display area arranged sequentially along the side away from the second display area in a first direction, where N is an integer greater than 1; The second display area includes at least one second sub-display area. The second light-emitting element of the second sub-display area is electrically connected to the second pixel circuit of the nth first sub-display area. The first light-emitting element of the nth first sub-display area is electrically connected to the first pixel circuit of the (n+i)th first sub-display area. Here, n and i are both integers greater than 0 and less than N. The at least one first pixel circuit is electrically connected to the at least one first light-emitting element via a first conductive line, and the at least one second pixel circuit is electrically connected to the at least one second light-emitting element via a second conductive line.

2. The display substrate according to claim 1, wherein, The first light-emitting element of the (n+i)th first sub-display area is electrically connected to the first pixel circuit of the (n+i+j)th first sub-display area, where j is an integer greater than 0 and less than N.

3. The display substrate according to claim 2, wherein, j equals i.

4. The display substrate according to claim 2, wherein, The first conductive line or second conductive line electrically connected to at least one pixel circuit in at least one first sub-display area and the first conductive line electrically connected to at least one first light-emitting element are of a heterogeneous structure.

5. The display substrate according to claim 4, wherein, The second conductive line that electrically connects the second pixel circuit of the nth first sub-display area and the second light-emitting element of the second sub-display area is a different layer structure from the first conductive line that electrically connects the first light-emitting element of the nth first sub-display area and the first pixel circuit of the (n+i)th first sub-display area.

6. The display substrate according to claim 4, wherein, The first conductive line that electrically connects the first light-emitting element of the (n+i)th first sub-display area and the first pixel circuit of the (n+i+j)th first sub-display area is a heterogeneous structure with the first conductive line that electrically connects the first pixel circuit of the (n+i)th first sub-display area and the first light-emitting element of the nth first sub-display area.

7. The display substrate according to any one of claims 1 to 6, wherein, The number of pixel circuits in at least one first sub-display area is greater than the number of first light-emitting elements.

8. The display substrate according to any one of claims 1 to 6, wherein, The pixel circuits in the nth first sub-display area are all second pixel circuits.

9. The display substrate according to any one of claims 1 to 6, wherein, The number of pixel circuits in the nth first sub-display area is greater than or equal to the number of pixel circuits in the (n+1)th first sub-display area, and the number of first light-emitting elements in the nth first sub-display area is greater than or equal to the number of first light-emitting elements in the (n+1)th first sub-display area.

10. The display substrate according to any one of claims 1 to 6, wherein, The second light-emitting element in the second sub-display area that is close to the nth first sub-display area is electrically connected to the second pixel circuit in the nth first sub-display area that is close to the second sub-display area, and the second light-emitting element in the second sub-display area that is far from the nth first sub-display area is electrically connected to the second pixel circuit in the nth first sub-display area that is far from the second sub-display area.

11. The display substrate according to any one of claims 1 to 6, wherein, The pixel circuit array of the first display area is arranged in the first direction, which is the row direction of the pixel circuit.

12. The display substrate according to any one of claims 1 to 6, wherein, The second display area includes: the Mth second sub-display area to the first second sub-display area arranged sequentially along the side away from the first sub-display area in the first direction, where M is an integer greater than 1 and less than N; Wherein, the first sub-display area where the second pixel circuit electrically connected to the second light-emitting element in the m-th second sub-display area is located is located on the side of the first sub-display area where the second pixel circuit electrically connected to the second light-emitting element in the (m+1)-th second sub-display area is located, which is closer to the second display area, and m is an integer greater than 0 and less than M.

13. The display substrate according to claim 1, wherein, The second conductive lines electrically connected to the second light-emitting elements in adjacent second sub-display areas are located in different conductive layers, and the first conductive lines electrically connected to the first light-emitting elements in adjacent first sub-display areas are located in different conductive layers.

14. The display substrate according to any one of claims 2 to 6, wherein, The second conductive lines that electrically connect the multiple second light-emitting elements in the second sub-display area are of the same layer structure.

15. The display substrate according to any one of claims 2 to 6, wherein, The second conductive line connecting the second light-emitting elements adjacent to each other in the first direction within the second sub-display area has a heterogeneous structure.

16. The display substrate according to any one of claims 2 to 6, wherein, The first and second conductive lines are transparent conductive lines.

17. The display substrate according to any one of claims 1 to 6, wherein, The first display area further includes: a first third sub-display area to the Hth third sub-display area arranged sequentially along the side away from the second display area in the second direction, where H is an integer greater than 1; The second display area further includes: at least one fourth sub-display area, wherein the second light-emitting element of the fourth sub-display area is electrically connected to the second pixel circuit of the h-th third sub-display area, and the first light-emitting element of the h-th third sub-display area is electrically connected to the first pixel circuit of the h+s-th third sub-display area, wherein h and s are both integers greater than 0 and less than H.

18. The display substrate according to claim 17, wherein, The second direction is parallel to the first direction, or the second direction intersects the first direction.

19. The display substrate according to claim 17, wherein, The first display area further includes: the first fifth sub-display area to the Rth fifth sub-display area arranged sequentially along the side away from the second display area in a third direction, where R is an integer greater than 1; The second display area further includes: at least one sixth sub-display area, wherein the second light-emitting element of the sixth sub-display area is electrically connected to the second pixel circuit of the r-th fifth sub-display area, and the first light-emitting element of the r-th fifth sub-display area is electrically connected to the first pixel circuit of the (r+k)-th fifth sub-display area, wherein r and k are both integers greater than 0 and less than R.

20. The display substrate according to claim 19, wherein, The first display area further includes: a first seventh sub-display area to a Gth seventh sub-display area arranged sequentially along the side away from the second display area in the fourth direction, where G is an integer greater than 1; The second display area further includes: at least one eighth sub-display area, wherein the second light-emitting element of the eighth sub-display area is electrically connected to the second pixel circuit of the g-th seventh sub-display area, and the first light-emitting element of the g-th seventh sub-display area is electrically connected to the first pixel circuit of the g+d-th seventh sub-display area, wherein g and d are both integers greater than 0 and less than G.

21. The display substrate according to claim 1, wherein, The density of the second light-emitting element is less than or equal to the density of the first light-emitting element.

22. The display substrate according to claim 1, wherein, The resolution of the first display area is less than or equal to the resolution of the second display area.

23. A display device, comprising: The display substrate as described in any one of claims 1 to 22.

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