A signal pre-processing synchronous clock system

Abstract

The application provides a signal preprocessing synchronous clock system, which comprises a system clock source, synchronous clock modules in each physical position, synchronous clock modules in each plug-in box, and clock distribution circuits in each circuit board. The system clock source generates a low-speed clock and divides the low-speed clock into equal phases to be input to the synchronous clock modules in each physical position; the synchronous clock modules in each physical position generate a high-speed clock and input the low-speed clock and the high-speed clock in equal phases to the synchronous clock modules in each plug-in box in the physical position. The synchronous clock modules in each plug-in box input the low-speed clock and the high-speed clock in equal phases to each circuit board. The clock distribution circuits in each circuit board generate all the required clocks of the circuit board. The signal preprocessing synchronous clock system of the application eliminates the influence of inconsistent clock jitter, ensures the initial phase determination of each clock, eliminates frequency division ambiguity, and thus meets the requirement of signal preprocessing data transmission deterministic delay.

Description

Technical Field

[0001] This application relates to the field of electronic reconnaissance signal preprocessing technology, and in particular to a signal preprocessing synchronization clock system. Background Technology

[0002] In electronic reconnaissance signal preprocessing, the requirements for array digital beamforming and multi-channel frequency and direction measurement necessitate deterministic delay in signal preprocessing data transmission, with data transmission line rates potentially reaching the 10Gbps level for a single LANE. Currently, deterministic delay in data transmission within circuit boards or cabinets is relatively mature. However, as the scale of preprocessing expands, deterministic delay in data transmission between multiple signal preprocessing boards in multiple signal preprocessing cabinets located in multiple physical locations (such as antenna arrays or processing cabinets) is required.

[0003] The synchronous clock system is a key component for achieving deterministic delay in data transmission. The synchronous clock mainly includes sampling clocks for each node (GHz level), high-speed transmission core clock (100MHz level), high-speed transmission reference clock (MHz to 10MHz level), and FPGA main processing clock (100MHz level). Based on practical needs, it is necessary to design a synchronous clock system to meet the requirement of deterministic delay in data transmission between multiple signal preprocessing boxes in multiple physical locations. Summary of the Invention

[0004] This application provides a signal preprocessing synchronization clock system, the system comprising:

[0005] The system transmits two coherent clocks: a high-speed clock, which is the same frequency as the sampling clock and is in the GHz range; and a low-speed clock, which is the same frequency as the high-speed transmission reference clock and is in the MHz to 10MHz range.

[0006] All clock frequencies in the system satisfy a multiplication relationship relative to the low-speed clock frequency;

[0007] The system includes a system clock source, synchronization clock modules at each physical location, synchronization clock modules for each plug-in box, and clock distribution circuits for each circuit board;

[0008] The system clock source generates a low-speed clock and divides it into equal phases, which are then input to the synchronization clock modules at each physical location. Each physical location synchronization clock module generates a high-speed clock and inputs the low-speed clock and high-speed clock into equal phases to the synchronization clock modules of each module at that physical location. Each module inputs the low-speed clock and high-speed clock into equal phases to each circuit board. The clock distribution circuit of each circuit board generates all the clocks required by the current circuit board.

[0009] Optionally, the clock frequency generated by the system clock source is the same as that of the low-speed clock;

[0010] The system clock source uses a low phase noise temperature-controlled crystal oscillator with an output power of not less than 10dBm and a phase noise better than -150dBc / Hz@1KHz; after clock power division, it is connected to an RF cable and input to the synchronization clock module at each physical location in equal phase.

[0011] Optionally, after receiving the low-speed clock signal from the system clock source frequency input, the synchronization clock module at each physical location splits the original clock signal into two paths. One path is connected to a low phase noise amplifier, and after splitting, it is connected to an RF cable and input to the synchronization clock module of each plug-in box at that physical location in equal phase. The other path multiplies the clock signal to generate a high-speed clock signal, which is then split and connected to an RF cable and input to the synchronization clock module of each plug-in box at that physical location in equal phase.

[0012] Optionally, each module in the inter-module synchronous clock inputs the low-speed clock and high-speed clock to each circuit board; if the circuit board does not have an analog-to-digital converter chip, then a high-speed clock input is not required.

[0013] Optionally, the low-speed clock is converted to MLVS level after level conversion and input to each circuit board via the backplane bus; the high-speed clock is divided and connected to the RF cable and input to each circuit board containing the analog-to-digital converter chip in equal phase.

[0014] Optionally, the clock distribution circuitry on each board generates all the clocks required for that board, including:

[0015] The low-speed clock is distributed by a chip to set the output low-speed clock to be in phase with the input low-speed clock, and the low-speed clock is multiplied to generate the required high-speed transmission core clock and FPGA main processing clock, which are then input to the required chips. The high-speed clock is distributed by a clock chip and input to each analog-to-digital converter chip in phase.

[0016] In this application, all clocks in the signal preprocessing synchronization clock system originate from the same source, eliminating the impact of inconsistencies caused by different clock jitter. All clocks in the clock system are generated by multiplying the same system clock, ensuring the initial phase of each clock is determined and eliminating frequency division ambiguity. The high-speed clock (sampling clock) is generated by synchronization clock modules at each physical location, rather than by the circuit board, ensuring analog-to-digital conversion performance and multi-channel sampling consistency. The clock system primarily transmits two types of coherent clocks, resulting in simple implementation and low cost. The low-speed clock is input to each circuit board via the MLVS bus backplane, conforming to the OpenVPX standard. Attached Figure Description

[0017] Figure 1 A schematic diagram of a signal preprocessing synchronization clock system provided in an embodiment of this application;

[0018] Figure 2 This is a schematic diagram of the synchronization clock modules for each physical location provided in the embodiments of this application;

[0019] Figure 3 This is a schematic diagram of the synchronization clock modules for each socket provided in the embodiments of this application;

[0020] Figure 4 This is a schematic diagram of the clock distribution circuit of each circuit board provided in the embodiments of this application. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0022] like Figure 1 As shown, this application provides a signal preprocessing synchronization clock system, the system comprising:

[0023] The system transmits two coherent clocks: a high-speed clock, which is the same frequency as the sampling clock and is in the GHz range; and a low-speed clock, which is the same frequency as the high-speed transmission reference clock and is in the MHz to 10MHz range.

[0024] All clock frequencies in the system satisfy a multiplication relationship relative to the low-speed clock frequency;

[0025] The system includes a system clock source, synchronization clock modules at each physical location, synchronization clock modules for each plug-in box, and clock distribution circuits for each circuit board;

[0026] The system clock source generates a low-speed clock and divides it into equal phases, which are then input to the synchronization clock modules at each physical location. Each physical location synchronization clock module generates a high-speed clock and inputs the low-speed clock and high-speed clock into equal phases to the synchronization clock modules of each module at that physical location. Each module inputs the low-speed clock and high-speed clock into equal phases to each circuit board. The clock distribution circuit of each circuit board generates all the clocks required by the current circuit board.

[0027] Optionally, the clock frequency generated by the system clock source is the same as that of the low-speed clock;

[0028] The system clock source uses a low phase noise temperature-controlled crystal oscillator with an output power of not less than 10dBm and a phase noise better than -150dBc / Hz@1KHz; after clock power division, it is connected to an RF cable and input to the synchronization clock module at each physical location in equal phase.

[0029] A schematic diagram of the synchronization clock modules at each physical location is shown below. Figure 2 As shown, after receiving the low-speed clock signal from the system clock source frequency input, the synchronization clock module at each physical location splits the original clock signal into two paths. One path is connected to a low phase noise amplifier, and after splitting, it is connected to an RF cable and input to the synchronization clock module of each plug-in box at that physical location in equal phase. The other path multiplies the clock signal to generate a high-speed clock signal, which is then split and connected to an RF cable and input to the synchronization clock module of each plug-in box at that physical location in equal phase.

[0030] The schematic diagram of the synchronization clock module for each module is shown below. Figure 3 As shown, each plug-in synchronous clock module inputs the low-speed clock and high-speed clock to each circuit board; if the circuit board does not have an analog-to-digital converter chip, then a high-speed clock is not required.

[0031] The clock distribution circuit diagrams for each circuit board are as follows: Figure 4 As shown, the clock distribution circuit of each circuit board generates all the clocks required by that circuit board. The low-speed clock is converted to MLVS level after level conversion and input to each circuit board through the backplane bus; the high-speed clock is divided and connected to the RF cable, and input to each circuit board containing the analog-to-digital converter chip in equal phase.

[0032] Optionally, the clock distribution circuitry on each board generates all the clocks required for that board, including:

[0033] The low-speed clock is distributed by a chip to set the output low-speed clock to be in phase with the input low-speed clock, and the low-speed clock is multiplied to generate the required high-speed transmission core clock and FPGA main processing clock, which are then input to the required chips. The high-speed clock is distributed by a clock chip and input to each analog-to-digital converter chip in phase.

[0034] In this application, all clocks in the signal preprocessing synchronization clock system originate from the same source, eliminating the impact of inconsistencies caused by different clock jitter. All clocks in the clock system are generated by multiplying the same system clock, ensuring the initial phase of each clock is determined and eliminating frequency division ambiguity. The high-speed clock (sampling clock) is generated by synchronization clock modules at each physical location, rather than by the circuit board, ensuring analog-to-digital conversion performance and multi-channel sampling consistency. The clock system primarily transmits two types of coherent clocks, resulting in simple implementation and low cost. The low-speed clock is input to each circuit board via the MLVS bus backplane, conforming to the OpenVPX standard.

[0035] The embodiments described above do not constitute a limitation on the scope of protection of this application.

Claims

1. A signal preprocessing synchronization clock system, characterized in that, The system includes: The system transmits two coherent clocks: a high-speed clock, which is the same frequency as the sampling clock and is in the GHz range; and a low-speed clock, which is the same frequency as the high-speed transmission reference clock and is in the MHz to 10MHz range. All clock frequencies in the system satisfy a multiplication relationship relative to the low-speed clock frequency; The system includes a system clock source, synchronization clock modules at each physical location, synchronization clock modules for each plug-in box, and clock distribution circuits for each circuit board; The system clock source generates a low-speed clock and divides it into equal phases, which are then input to the synchronization clock modules at each physical location. Each physical location synchronization clock module generates a high-speed clock and inputs the low-speed clock and high-speed clock into equal phases to the synchronization clock modules of each module at that physical location. Each module inputs the low-speed clock and high-speed clock into equal phases to each circuit board. The clock distribution circuit of each circuit board generates all the clocks required by the current circuit board.

2. The signal preprocessing synchronization clock system according to claim 1, characterized in that: The clock frequency generated by the system clock source is the same as that of the low-speed clock; The system clock source uses a low phase noise temperature-controlled crystal oscillator with an output power of not less than 10dBm and a phase noise better than -150dBc / Hz@1KHz; after clock power division, it is connected to an RF cable and input to the synchronization clock module at each physical location in equal phase.

3. The signal preprocessing synchronization clock system according to claim 1, characterized in that: After receiving the low-speed clock signal from the system clock source, the synchronization clock module at each physical location splits the original clock signal into two paths. One path is connected to a low phase noise amplifier, and after splitting, it is connected to an RF cable and input to the synchronization clock module of each plug-in box at that physical location in equal phase. The other path multiplies the clock signal to generate a high-speed clock signal, which is then split and connected to an RF cable and input to the synchronization clock module of each plug-in box at that physical location in equal phase.

4. The signal preprocessing synchronization clock system according to claim 1, characterized in that: Each module in the socket synchronous clock inputs the low-speed clock and high-speed clock to each circuit board; if the circuit board does not have an analog-to-digital converter chip, then a high-speed clock is not required.

5. A signal preprocessing synchronization clock system according to claim 1, characterized in that: The low-speed clock is converted to MLVDS level after level conversion and then input to each circuit board via the backplane bus; After the high-speed clock power divider is connected to the RF cable, the equal-phase input is sent to each circuit board containing the analog-to-digital converter chip.

6. A signal preprocessing synchronization clock system according to claim 1, characterized in that, The clock distribution circuitry of each circuit board generates all the clocks required for that circuit board, including: The low-speed clock is distributed by a chip to set the output low-speed clock to be in phase with the input low-speed clock, and the low-speed clock is multiplied to generate the required high-speed transmission core clock and FPGA main processing clock, which are then input to the required chips. The high-speed clock is distributed by a clock chip and input to each analog-to-digital converter chip in phase.

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