A dynamic chip power supply circuit and method

Abstract

The application provides a dynamic chip power supply circuit and method. The circuit comprises an input power supply switching module, the input power supply switching module comprising a stabilizing tube D3 and a triode Q6, the negative electrode of the stabilizing tube D3 being connected with the base of the triode Q6; a linear voltage stabilizer, the linear voltage stabilizer being connected with the input power supply switching module, the linear voltage stabilizer comprising a triode Q2, the collector of the triode Q2 being connected with the drain of a PMOS tube Q4; and a DCDC module circuit, the DCDC module circuit being connected with the input power supply switching module. The two modules are combined, the advantages of which are combined, the power-on sequence during starting can be met, low-power operation after normal starting can be met, and heat generation is reduced, so that the endurance of a battery is greatly increased.

Description

Technical Field

[0001] This invention relates to the field of chips, and more particularly to a dynamic chip power supply circuit and method. Background Technology

[0002] In the power supply architecture of a chip, a linear regulator is typically used. A linear regulator achieves voltage stability by creating a voltage drop between the Zener diode and the transistor. Its advantages include high voltage regulation accuracy and low noise. (See attached image) Figure 5 and 6 As shown, the chip's power supply has certain timing requirements. For example, when DRV outputs or VSENSE senses a power input, V_OUT_1 needs a rise time on the order of microseconds to reach a threshold. The linear regulation module of Q1 is used to meet these timing requirements. However, this architecture suffers from high power consumption and extremely low power supply efficiency. If the load is a battery, it will significantly reduce battery life. Furthermore, due to the high power consumption, heat generation will be more severe, requiring additional heat dissipation design or a larger Q1 package to increase power, thus increasing hardware design costs. Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide a dynamic chip power supply circuit and method, which aims to increase battery life by operating with low power consumption and reducing heat generation after normal startup, provided that the power-on sequence at startup is met.

[0004] The technical solution adopted by the present invention to solve the above-mentioned technical problems is as follows:

[0005] A first aspect of the present invention provides a dynamic chip power supply circuit, comprising:

[0006] An input power switching module includes a Zener diode D3 and a transistor Q6. The negative terminal of the Zener diode D3 is connected to the base of the transistor Q6. The Zener diode D3 is used to detect whether the voltage of the input power supply has reached a stable value, and controls the conduction or cutoff of Q6 according to the voltage level, thereby controlling the working state of the subsequent modules.

[0007] A linear regulator is connected to the input power switching module. The linear regulator includes a transistor Q2, and the collector of the transistor Q2 is connected to the drain of the PMOS transistor Q4.

[0008] The DC-DC module circuit is connected to the input power switching module.

[0009] In some embodiments, the linear regulator and the DC-DC module circuit are connected to chip U3.

[0010] In some embodiments, the emitter of the transistor Q6 is connected with the source of the PMOS tube Q4, and the emitter of the transistor Q2 is connected with the power input pin of the chip U3.

[0011] In some embodiments, the negative electrode of the voltage stabilizing tube D3 is connected with the base of the transistor Q8, the emitter of the transistor Q8 is connected with the ground terminal, the collector of the transistor Q8 is connected with the first end of the resistor R14 and the gate of the PMOS tube Q7, the second end of the resistor R14 is connected with the first end of the resistor R10 and the source of the PMOS tube Q7, the drain of the PMOS tube Q7 is connected with the first end of the resistor R5, the second end of the resistor R5 is connected with the second end of the resistor R12 and the base of the transistor Q5, the emitter of the transistor Q5 is connected with the second end of the resistor R12 and the ground terminal, the collector of the transistor Q5 is connected with the first end of the resistor R6, the second end of the resistor R6 is connected with the gate of the PMOS tube Q3, the drain of the PMOS tube Q3 is connected with the input terminal of the DCDC module circuit, and the output terminal of the DCDC module circuit is connected with the power input pin of the chip U3.

[0012] In some embodiments, the drain of the PMOS tube Q7 is connected with the first end of the resistor R13, the second end of the resistor R13 is connected with the enable terminal of the DCDC module circuit and the negative electrode of the voltage stabilizing tube D6, and the positive electrode of the voltage stabilizing tube D6 is connected with the ground terminal.

[0013] In some embodiments, the output terminal of the DCDC module circuit is connected with the positive electrode of the Schottky diode D5, the negative electrode of the Schottky diode D5 is connected with the power input pin of the chip U3, the emitter of the transistor Q2 is connected with the positive electrode of the Schottky diode D4, and the negative electrode of the Schottky diode D4 is connected with the power input pin of the chip U3.

[0014] In some embodiments, the linear voltage regulator adjustment pin of the chip U3 is connected with the first end of the resistor R10, the second end of the resistor R10 is connected with the base of the transistor Q2, the power input detection pin of the chip U3 is connected with the power input terminal and the first end of the resistor R8, the second end of the resistor R8 is connected with the first end of the resistor R4 and the second end of the resistor R6, the second end of the resistor R4 is connected with the first end of the resistor R8 and the source of the PMOS tube Q3.

[0015] In some embodiments, the second end of the resistor R8 is connected with the first end of the resistor R9, the emitter of the transistor Q6 and the source of the PMOS tube Q4, the second end of the resistor R9 is connected with the first end of the resistor R7, the collector of the transistor Q6 and the gate of the PMOS tube Q4, the second end of the resistor R7 is connected with the ground and the first end of the resistor R11, and the second end of the resistor R11 is connected with the positive electrode of the voltage stabilizing tube D3 and the base of the transistor Q8.

[0016] The application also provides a dynamic chip power supply method, comprising the following steps:

[0017] When the input voltage is lower than the voltage stabilizing value, the linear voltage stabilizer is turned on, and the chip is powered by the output voltage of the linear voltage stabilizer;

[0018] When the input voltage is higher than the voltage stabilizing value, the DCDC module circuit is turned on, and the chip is powered by the output voltage of the DCDC module circuit.

[0019] In some embodiments, the following steps are further included:

[0020] During the power supply climbing process, the DCDC module circuit is turned off, the linear voltage stabilizer is turned on and outputs the voltage for the chip power supply;

[0021] After the chip is normally started, the linear voltage stabilizer is turned off, and the DCDC module circuit is turned on and outputs the voltage for the chip power supply.

[0022] The dynamic chip power supply circuit and method provided by the embodiment of the application can provide working voltage for the chip by dynamically switching between the linear voltage stabilizer and the DCDC module circuit, input different voltages to the input power supply switching module, switch the corresponding modules in the linear voltage stabilizer and the DCDC module circuit to work, combine the advantages of the two modules, meet the power-on sequence during starting, meet the low-power running and reduce the heat after normal starting, and greatly increase the endurance of the battery. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 FIG. 1 is a structural schematic diagram of a dynamic chip power supply circuit according to an embodiment of the application;

[0024] Figure 2 FIG. 2 is a structural schematic diagram of a dynamic chip power supply circuit according to an embodiment of the application;

[0025] Figure 3 FIG. 3 is a flowchart of a dynamic chip power supply method according to an embodiment of the application;

[0026] Figure 4 FIG. 4 is a flowchart of a dynamic chip power supply method according to an embodiment of the application;

[0027] Figure 5 A schematic diagram of a chip power supply in the prior art;

[0028] Figure 6 A schematic diagram of a chip power supply in the prior art. DETAILED DESCRIPTION

[0029] In order to make the technical problems to be solved by the present application, technical solutions and beneficial effects more clear, explicit, the present application will be further described in detail below in combination with the drawings and examples. It should be understood that the specific examples described herein are only used to explain the present application, and are not used to limit the present application.

[0030] In the prior art, the chip power supply circuit has low power supply efficiency. If the load end is a battery, the battery endurance will be greatly reduced. Further, due to large power consumption, the heat generation will be more serious, and in hardware design, additional heat dissipation design or increasing the package of Q1 to improve power is needed, which increases the hardware design cost.

[0031] Participation Figure 5 And Figure 6 The power supply architecture of the chip itself is shown in Figure 5 And Figure 6 The power supply of U1 has certain timing requirements, for example, when DRV outputs or VSENSE senses the power input, V_OUT_1 needs to have a microsecond level rise time to reach the threshold value. At this time, the linear regulation module of Q1 meets the timing requirements. However, this architecture has the disadvantage of large power consumption, for example: if the working current of U1 is 20mA, V1 is 50V, and V_OUT_1 is 8V, the power consumption of the chip itself is as follows:

[0032] P_U1 = V_OUT_1 * I = 8V * 0.02A = 0.16W

[0033] P_Q1 = (V1-V_OUT_1) * 0.02A = (50-8) * 0.02 = 0.84W

[0034] η = P_U1 / P_tot = 0.16W / (0.02 * 50) = 16%;

[0035] According to the calculation as above, the following disadvantages are obtained:

[0036] The chip power supply circuit has very low power supply efficiency;

[0037] If the load end is a battery, the battery endurance will be greatly reduced;

[0038] Q1 has large power consumption and serious heat generation. In hardware design, additional heat dissipation design or increasing the package of Q1 to improve power is needed, which increases the hardware design cost.

[0039] Some terms and functions in the text are explained below:

[0040] Input power switching module: This module plays a key role in controlling the input power switching. The voltage stabilizing tube D3 is used to detect whether the input power voltage reaches a stable value, and controls the conduction or cut-off of the triode Q6 according to the voltage level, thereby controlling the working state of the subsequent module.

[0041] Linear voltage regulator: This module is connected with the input power switching module. The linear voltage regulator can provide stable voltage to the chip. It has the advantage of faster power-on compared with the DCDC module circuit, and can meet the power-on timing requirements. The disadvantage is high power consumption.

[0042] DCDC module circuit: This module circuit is connected with the input power switching module. The DCDC module circuit is a circuit design for converting input voltage into stable output voltage required by the chip. It is usually composed of a DC / DC converter, which can convert the voltage of one DC power supply into another DC power supply. In this application, the low power consumption feature is mainly used, but it has the disadvantage of slow power-on and cannot meet the power-on timing.

[0043] In Figure 5 , VSENSE is the chip's power input detection pin, DRV is the linear voltage regulator adjustment pin, V_OUT_1 is the input pin of the power supply, and R2 is the total input end of the power supply. When there is power input, VSENSE senses the power input. At this time, Q1 is controlled by DRV to output V_OUT_1 to supply power to the subsequent U1. R2 is a resistor mainly used for current limiting and power dissipation.

[0044] The specific technical scheme of the first embodiment of the application is described in detail below:

[0045] Embodiment one:

[0046] The application provides a dynamic chip power supply circuit, please refer to Figure 2 , which comprises:

[0047] The input power switching module 200 comprises a voltage stabilizing tube D3 and a triode Q6. The negative electrode of the voltage stabilizing tube D3 is connected with the base of the triode Q6. The voltage stabilizing tube D3 is used to detect whether the input power voltage reaches a stable value, and controls the conduction or cut-off of Q6 according to the voltage level, thereby controlling the working state of the subsequent module.

[0048] The linear voltage regulator 300 is connected with the input power switching module 200. The linear voltage regulator 300 comprises a triode Q2, and the collector of the triode Q2 is connected with the drain of the PMOS tube Q4.

[0049] DCDC module circuit 400, which is connected with the input power switching module 200.

[0050] Referring to Figure 1 The linear regulator 300 and the DCDC module circuit 400 are connected with the chip U3500.

[0051] Referring to Figure 1 The emitter of the transistor Q6 is connected with the source of the PMOS tube Q4, and the emitter of the transistor Q2 is connected with the power input pin of the chip U3500.

[0052] Referring to Figure 1 The negative electrode of the voltage stabilizing tube D3 is connected with the base of the transistor Q8, the emitter of the transistor Q8 is connected with the ground, the collector of the transistor Q8 is connected with the first end of the resistor R14 and the gate of the PMOS tube Q7, the second end of the resistor R14 is connected with the first end of the resistor R10 and the source of the PMOS tube Q7, the drain of the PMOS tube Q7 is connected with the first end of the resistor R5, the second end of the resistor R5 is connected with the second end of the resistor R12 and the base of the transistor Q5, the emitter of the transistor Q5 is connected with the second end of the resistor R12 and the ground, the collector of the transistor Q5 is connected with the first end of the resistor R6, the second end of the resistor R6 is connected with the gate of the PMOS tube Q3, the drain of the PMOS tube Q3 is connected with the input end of the DCDC module circuit 400, and the output end of the DCDC module circuit 400 is connected with the power input pin of the chip U3500.

[0053] Referring to Figure 1 The drain of the PMOS tube Q7 is connected with the first end of the resistor R13, the second end of the resistor R13 is connected with the enable end of the DCDC module circuit 400 and the negative electrode of the voltage stabilizing tube D6, and the positive electrode of the voltage stabilizing tube D6 is connected with the ground.

[0054] Referring to Figure 1 The output end of the DCDC module circuit 400 is connected with the positive electrode of the Schottky diode D5, the negative electrode of the Schottky diode D5 is connected with the power input pin of the chip U3500, the emitter of the transistor Q2 is connected with the positive electrode of the Schottky diode D4, and the negative electrode of the Schottky diode D4 is connected with the power input pin of the chip U3500.

[0055] Referring to Figure 1The linear voltage regulator 300 of the chip U3500 is connected with the first end of the resistor R10, the second end of the resistor R10 is connected with the base of the triode Q2, the power input detection pin of the chip U3500 is connected with the power input 100 and the first end of the resistor R8, the power input detection pin of the chip U3500 is at the input end of the DCDC module circuit 400, so that the chip U3500 can sense the input voltage of the battery end and provide power supply for the linear voltage regulator 300 adjustment pin. The second end of the resistor R8 is connected with the first end of the resistor R4 and the second end of the resistor R6, the second end of the resistor R4 is connected with the first end of the resistor R8 and the source of the PMOS tube Q3.

[0056] Referring to Figure 1 The second end of the resistor R8 is connected with the first end of the resistor R9, the emitter of the triode Q6 and the source of the PMOS tube Q4, the second end of the resistor R9 is connected with the first end of the resistor R7, the collector of the triode Q6 and the gate of the PMOS tube Q4, the second end of the resistor R7 is connected with the ground end and the first end of the resistor R11, and the second end of the resistor R11 is connected with the positive electrode of the voltage stabilizing tube D3 and the base of the triode Q8. The working principle is as follows:

[0057] When the input voltage is lower than the voltage stabilizing value of D3: the voltage stabilizing tube D3 is cut off, the triode Q6 is cut off, the PMOS tube Q4 is turned on, at this time V3 has not reached the voltage stabilizing value of the voltage stabilizing tube D3, so the triode Q8 is cut off, at this time the potential of the resistor R10 is the DRV voltage, at this time the PMOS tube Q4 supplies power to the triode Q2, and the output voltage is the power supply of the chip U3.

[0058] At this time, the PMOS tube Q7 is not turned on, so the triode Q5 is cut off, the PMOS tube Q3 is also cut off, the EN potential of the DCDC is 0V, at this time the DCDC module has no power input and is not enabled, and does not work, and the power consumption is also very low;

[0059] When the input voltage V3 is higher than the voltage stabilizing value of D3: at this time the voltage stabilizing tube D3 is turned on, the triode Q6 is turned on, the PMOS tube Q4 is turned off, the triode Q2 has no power input, and the linear voltage regulator stops working;

[0060] The triode Q8 is turned on, and then the PMOS tube Q7 is turned on, the triode Q5 is turned on, the PMOS tube Q3 is also turned on to input power supply for the DCDC module, and the DRV is input to the EN pin of the DCDC, and then the DCDC module circuit starts to work;

[0061] The two power supplies complete power switching at the diode D4 and the diode D5.

[0062] Next, the performance optimization analysis of the present application is carried out:

[0063] DCDC input 50V, output 8V:

[0064] P_BUCK_OUT = 8V * 0.02A = 0.16W;

[0065] If the efficiency of the DCDC module circuit designed is 80%, the input parameters of the DCDC are as follows:

[0066] P_DCDC_IN = 0.16W / 0.8 = 0.2W;

[0067] I_DCDC_IN = 0.2W / 50V = 4mA;

[0068] Compared with the scheme of Figure 5 , the power consumption is reduced to 1 / 5 of the original, greatly reducing the power consumption of the chip. If V3 is a battery, it will greatly improve the endurance of chip U3, and the optimization effect is quite remarkable.

[0069] Example two:

[0070] The application also provides a dynamic chip power supply method, please refer to Figure 4 , including the following steps during the startup process of the chip and after the startup:

[0071] S100, during the power supply climbing process;

[0072] S200, turned on by the linear voltage regulator and output voltage for chip power supply;

[0073] S300, after the chip is normally started;

[0074] S400, turned on by the DCDC module circuit and output voltage for chip power supply.

[0075] It can be understood that by using the voltage sensing characteristics of the VSENSE pin of the power supply U3 and the action characteristics of the DRV pin, a DCDC module circuit and a linear voltage regulator circuit are ingeniously combined together, which can be adjusted by the external input voltage, so that the two circuits are smoothly switched. Solve the problem of high power consumption, thereby reducing the power consumption of the chip, and at the same time solve the problem of heating of peripheral devices; Q2 circuit module also solves the disadvantages of slow DCDC power-on and cannot meet the power-on timing, and can greatly increase the endurance of the battery.

[0076] When the designer wants V3 power supply in a certain low voltage range, please refer to Figure 3 , including the following steps:

[0077] S110, when the input voltage is lower than the voltage stabilizing value;

[0078] S210, the linear voltage regulator is turned on and outputs voltage to power the chip.

[0079] It can be understood that by turning on the linear voltage regulator and outputting voltage to power the chip, the purpose is to meet the power timing requirements of the chip U3 and ensure that the chip U3 can normally start and enter the NORMAL mode.

[0080] When the designer wants the V3 power supply to be in a certain high-voltage range, please refer to Figure 3 , comprising the following steps:

[0081] S310, when the input voltage is higher than the voltage stabilizing value;

[0082] S410, the DCDC module circuit is turned on and outputs voltage to power the chip,

[0083] It can be understood that by using the input power switching module and the DCDC module circuit, the appropriate working mode can be selected according to the high and low of the input voltage, thereby improving the power supply efficiency. Especially in the high-voltage range, the DCDC module circuit is used for power supply, and the power consumption is lower, which effectively reduces the energy loss.

[0084] The preferred embodiments of the present application are described above with reference to the accompanying drawings, and the scope of the present application is not limited thereto. Those skilled in the art can have various modification schemes to realize the present application without departing from the scope and essence of the present application, such as using the features of one embodiment in another embodiment to obtain another embodiment. Any modification, equivalent replacement and improvement within the technical concept of the present application shall be within the scope of the present application.

Claims

1. A dynamic chip power supply circuit, characterized in that, include: An input power switching module includes a Zener diode D3 and a transistor Q6. The negative terminal of the Zener diode D3 is connected to the base of the transistor Q6. The Zener diode D3 is used to detect whether the voltage of the input power supply has reached a stable value, and controls the conduction or cutoff of Q6 according to the voltage level, thereby controlling the working state of the subsequent modules. A linear regulator is provided, which is connected to the input power switching module. The linear regulator includes a transistor Q2 and a PMOS transistor Q4, with the collector of transistor Q2 connected to the drain of PMOS transistor Q4. The linear regulator and DC-DC module circuit are connected to chip U3. The linear regulator adjustment pin of chip U3 is connected to the first end of resistor R10, the second end of resistor R10 is connected to the base of transistor Q2, and the power input detection pin of chip U3 is connected to the power input terminal and the first end of resistor R8. DCDC module circuit, wherein the DCDC module circuit is connected to the input power switching module; The negative terminal of the Zener diode D3 is connected to the base of the transistor Q8. The emitter of the transistor Q8 is connected to ground. The collector of the transistor Q8 is connected to the first end of resistor R14 and the gate of the PMOS transistor Q7. The second end of resistor R14 is connected to the first end of resistor R10 and the source of the PMOS transistor Q7. The drain of the PMOS transistor Q7 is connected to the first end of resistor R5. The second end of resistor R5 is connected to the first end of resistor R12 and the base of the transistor Q5. The emitter of the transistor Q5 is connected to the second end of resistor R12 and ground. The collector of the transistor Q5 is connected to the first end of resistor R6. The second end of resistor R6 is connected to the gate of the PMOS transistor Q3. The drain of the PMOS transistor Q3 is connected to the input terminal of the DC-DC module circuit. The output terminal of the DC-DC module circuit is connected to the power input pin of the chip U3.

2. The dynamic chip power supply circuit according to claim 1, characterized in that, The emitter of transistor Q6 is connected to the source of PMOS transistor Q4, and the emitter of transistor Q2 is connected to the power input pin of chip U3.

3. The dynamic chip power supply circuit according to claim 2, characterized in that, The drain of the PMOS transistor Q7 is connected to the first end of the resistor R13, the second end of the resistor R13 is connected to the enable terminal of the DC-DC module circuit and the negative terminal of the Zener diode D6, and the positive terminal of the Zener diode D6 is connected to the ground terminal.

4. The dynamic chip power supply circuit according to claim 3, characterized in that, The output terminal of the DC-DC module circuit is connected to the positive terminal of Schottky diode D5, the negative terminal of Schottky diode D5 is connected to the power input pin of chip U3, the emitter of transistor Q2 is connected to the positive terminal of Schottky diode D4, and the negative terminal of Schottky diode D4 is connected to the power input pin of chip U3.

5. A dynamic chip power supply circuit according to claim 4, characterized in that, The second end of resistor R8 is connected to the first end of resistor R4 and the second end of resistor R6. The second end of resistor R4 is connected to the first end of resistor R8 and the source of PMOS transistor Q3.

6. A dynamic chip power supply circuit according to claim 5, characterized in that, The second end of resistor R8 is connected to the first end of resistor R9, the emitter of transistor Q6, and the source of PMOS transistor Q4. The second end of resistor R9 is connected to the first end of resistor R7, the collector of transistor Q6, and the gate of PMOS transistor Q4. The second end of resistor R7 is connected to ground and the first end of resistor R11. The second end of resistor R11 is connected to the positive terminal of Zener diode D3 and the base of transistor Q8.

7. A dynamic chip power supply method using a dynamic chip power supply circuit according to any one of claims 1-6, characterized in that, Includes the following steps: When the input voltage is lower than the regulated value, the linear regulator turns on, and the output voltage of the linear regulator powers the chip. When the input voltage is higher than the regulated value, the DC-DC module circuit is turned on, and the output voltage of the DC-DC module circuit powers the chip.

8. A dynamic chip power supply method according to claim 7, characterized in that, It also includes the following steps: During the power ramp-up process, the DC-DC module circuit is cut off, and the linear regulator is turned on and outputs voltage to power the chip. After the chip starts up normally, the linear regulator is turned off, and the DC-DC module circuit is turned on and outputs voltage to power the chip.

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