Semiconductor device including contact structure

Abstract

A semiconductor device can include a substrate; a plurality of memory cells disposed between a first conductive line and a second conductive line and respectively disposed in intersection regions of the first conductive line and the second conductive line; and a contact structure disposed between the first conductive line and the substrate and including a plurality of upper contacts connected to the first conductive line and lower contacts connected to the substrate and overlapping at least one of the plurality of upper contacts when viewed in a plan view, wherein each of the plurality of upper contacts is in contact with at least two of the first conductive lines, and wherein two of the plurality of upper contacts closest to each other are collectively in contact with one or more of the first conductive lines.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2022-0073954, filed on June 17, 2022, which is incorporated herein by reference in its entirety. Technical Field

[0003] This patent document relates to semiconductor devices and their applications in electronic devices or electronic systems, said semiconductor device comprising: a contact structure commonly connected to one or more conductive lines. Background Technology

[0004] Recently, with the trend towards miniaturization, low power consumption, high performance, and multifunctionality in electronic devices, there has been a demand in the field for semiconductor devices capable of storing information in various electronic devices such as computers and portable communication devices, and research has been conducted on such semiconductor devices. Such semiconductor devices include those capable of storing data by utilizing their characteristic of switching between different resistance states according to applied voltage or current, such as RRAM (Resistive Random Access Memory), PRAM (Phase Change Random Access Memory), FRAM (Ferroelectric Random Access Memory), MRAM (Magnetic Random Access Memory), and electric fuses.

[0005] In order to use such a semiconductor device in electronic appliances, the semiconductor device needs to be implemented in a smaller area. Summary of the Invention

[0006] In an embodiment, a semiconductor device may include: a substrate; a plurality of first conductive lines disposed on the substrate and extending in a first direction; a plurality of second conductive lines disposed above or below the first conductive lines and located on the substrate, and the plurality of second conductive lines extending in a second direction intersecting the first direction, the first and second directions being parallel to an upper surface of the substrate; a plurality of memory cells disposed between the first and second conductive lines in a third direction perpendicular to the first and second directions, and the plurality of memory cells being respectively disposed in the intersection region of the first and second conductive lines; and a contact structure disposed between the first conductive lines and the substrate in a third direction, and including a plurality of upper contacts and lower contacts, the plurality of upper contacts being connected to the first conductive lines, the lower contacts being connected to the substrate and overlapping at least one of the plurality of upper contacts when viewed in a plan view, wherein each of the plurality of upper contacts contacts at least two of the first conductive lines, and wherein the two upper contacts closest to each other among the plurality of upper contacts are in common contact with one or more of the plurality of first conductive lines. Attached Figure Description

[0007] Figures 1 to 5 This is a view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 6 It is shown Figures 1 to 5 A cross-sectional view of an example storage cell.

[0009] Figures 7 to 11 This is a view illustrating a semiconductor device according to another embodiment of the present disclosure. Detailed Implementation

[0010] Various embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0011] The accompanying drawings are not necessarily drawn to scale. In some cases, the scale of at least some structures in the drawings may have been exaggerated to clearly illustrate certain features of the described embodiments. When a specific example is presented in a drawing or description having two or more layers in a multilayer structure, the relative positioning of these layers or the order in which these layers are arranged reflects a particular implementation of the described or illustrated example, and different relative positioning or orders in which these layers are arranged are possible. Furthermore, the examples of descriptions or illustrations of multilayer structures may not reflect all layers present in that particular multilayer structure (e.g., there may be one or more additional layers between the two illustrated layers). As a specific example, when the first layer in a described or illustrated multilayer structure is referred to as being "on" or "above" the second layer, or "on" or "above" the substrate, the first layer may be formed directly on the second layer or the substrate, but it may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or the substrate.

[0012] Figures 1 to 5 This is a view illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 1 This is a plan view showing a semiconductor device according to this embodiment. Figure 2 It is along Figure 1 A cross-sectional view taken from line AA′. Figure 3 It is along Figure 1 A cross-sectional view of line BB′. Figure 4 It is along Figure 1 The cross-sectional view of line CC′, and Figure 5 It is along Figure 1 The cross-sectional view of the line DD′.

[0013] refer to Figures 1 to 5The semiconductor device according to this embodiment may include: a substrate 100; a plurality of first conductive lines 130 disposed on the substrate 100 in a third (or vertical) direction and extending in a first direction substantially parallel to the upper surface of the substrate 100; a plurality of second conductive lines 150 disposed on the first conductive lines 130 in a vertical direction and extending in a second direction substantially parallel to the upper surface of the substrate 100 and intersecting the first direction; and a plurality of memory cells 140 disposed between the first conductive lines 130 and the second conductive lines 150 in a vertical direction and overlapping the intersection region of the first conductive lines 130 and the second conductive lines 150. The plurality of memory cells 140 are respectively disposed in the intersection region. Here, the first direction and the second direction are perpendicular to the vertical direction. The first direction and the second direction may not be fixed directions, and may be relative directions indicating their intersection. In other words, the first conductive lines 130 may extend in the second direction and the second conductive lines 150 may extend in the first direction. Furthermore, for ease of description, the first conductive line 130 is positioned vertically below the second conductive line 150, but this disclosure is not limited thereto. In another embodiment, the first conductive line 130 may be positioned vertically above the second conductive line 150.

[0014] In this disclosure, "overlap" is used to describe the relationship between corresponding elements in a planar diagram.

[0015] The substrate 100 may include a semiconductor material such as silicon. A desired lower structure (not shown) may be formed in the substrate 100. For example, a drive circuit for electrically connecting to the first conductive line 130 and the second conductive line 150 to drive the first conductive line 130 and the second conductive line 150 may be disposed in the substrate 100. Specifically, a metal wire forming part of the drive circuit may be disposed in the uppermost portion of the substrate 100.

[0016] Substrate 100 may include a cell region CA and a peripheral region PA. The cell region CA may be a region in which a plurality of memory cells 140 are arranged. Although only one cell region CA is shown in the figures, a plurality of cell regions CA may be arranged in a semiconductor device to be spaced apart from each other in a matrix along a first direction and a second direction. The peripheral region PA may be formed around the cell region CA, for example, to surround the cell region CA.

[0017] A plurality of first conductive lines 130 may extend in a first direction to cross a unit region CA and peripheral regions PA on both sides of the unit region CA in the first direction. The plurality of first conductive lines 130 may be arranged to be spaced apart from each other in a second direction. The first conductive lines 130 may have a single-layer structure or a multi-layer structure comprising a conductive material, such as a metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), or tantalum (Ta), a metal nitride such as tantalum nitride (TaN) or titanium nitride (TiN), or a combination thereof.

[0018] Multiple second conductive lines 150 may extend in a second direction to cross the cell region CA and the peripheral regions PA on both sides of the cell region CA. The multiple second conductive lines 150 may be arranged to be spaced apart from each other in a first direction. The second conductive lines 150 may have a single-layer or multi-layer structure comprising a conductive material, such as a metal like platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), or tantalum (Ta), a metal nitride such as tantalum nitride (TaN) or titanium nitride (TiN), or a combination thereof. When the first conductive line 130 is used as a word line, the second conductive line 150 may be used as a bit line. Alternatively, when the first conductive line 130 is used as a bit line, the second conductive line 150 may be used as a word line.

[0019] Multiple memory cells 140 can be arranged in a cell region CA. This is likely because the first conductive line 130 and the second conductive line 150 intersect only in the cell region CA, and the memory cells 140 are formed in the intersection region of the first conductive line 130 and the second conductive line 150. Since the memory cells 140 have an island shape in the plan view, adjacent memory cells 140 can be separated from each other.

[0020] In an embodiment, the storage cell 140 may have a quadrilateral shape in a plan view, and thus the two sidewalls of the storage cell 140 in the first direction may be aligned with the two sidewalls of the second conductive line 150, and the two sidewalls of the storage cell 140 in the second direction may be aligned with the two sidewalls of the first conductive line 130. This may be because, during the patterning of the first conductive line 130, the layer used to form the storage cell 140 is patterned to have a line shape overlapping the first conductive line 130, and then, during the patterning of the second conductive line 150, the layer of the line shape is patterned. However, this disclosure is not limited thereto.

[0021] In another embodiment, the storage cell 140 may be patterned separately from the first conductive line 130 and / or the second conductive line 150, and may have one of a variety of planar shapes, such as a circle. The storage cell 140 may have one of a variety of layered structures and data storage methods, as long as it can store different data depending on the voltage applied through the first conductive line 130 and the second conductive line 150. (Refer to the description below.) Figure 6 An example of storage unit 140 is described in more detail.

[0022] refer to Figures 2 to 5 The spaces between the first conductive lines 130, the spaces between the storage cells 140, and the spaces between the second conductive lines 150 can be filled with a third interlayer insulating layer I3. The third interlayer insulating layer I3 can be formed of a variety of insulating materials such as silicon oxide.

[0023] Here, the first conductive line 130 can be connected to a portion of the substrate 100 (e.g., a metal wire formed in the substrate 100) via a contact structure disposed below the first conductive line 130, and can receive the voltage required to be driven via the contact structure. In some cases, the multiple first conductive lines 130 may receive different voltages and / or different signals, or may receive the same voltage and / or the same signal. In this embodiment, contact structures 110 and 120 for supplying the same voltage or the same signal to the multiple first conductive lines 130 will be proposed, such as... Figures 1 to 3 As shown.

[0024] refer to Figure 1 The contact structures 110 and 120 may be disposed in the peripheral region PA at one of the two sides of the cell region CA in the first direction (e.g., the peripheral region PA at the right side of the cell region CA). Furthermore, the contact structures 110 and 120 may include a lower contact 110 and an upper contact 120.

[0025] The upper contact 120 may be disposed below the first conductive line 130 and has an upper surface that contacts the lower surface of the first conductive line 130. Each of the plurality of upper contacts 120 may overlap with two or more first conductive lines 130 arranged in a second direction, such that each upper contact 120 is connected to two or more first conductive lines 130, as shown below. Figure 1 and Figure 3 As shown. Furthermore, as... Figure 1 As shown, the two upper contacts 120 that are closest to each other in the first and second directions can overlap and connect with one or more first conductive lines 130.

[0026] In this embodiment, the plurality of upper contacts 120 includes five upper contacts 120A to 120E. For ease of description, when in Figure 1 When viewed in the plan view, the five upper contacts 120A to 120E are arranged sequentially from bottom to top in the second direction, and they will be referred to as the first upper contact 120A, the second upper contact 120B, the third upper contact 120C, the fourth upper contact 120D, and the fifth upper contact 120E.

[0027] refer to Figure 1 Each of the first upper contact 120A and the fifth upper contact 120E can overlap and contact three first conductive lines 130, and each of the second to fourth upper contacts 120B, 120C, and 120D can overlap and contact four first conductive lines 130. The first upper contact 120A and the second upper contact 120B that are closest to each other in the first and second directions can overlap and contact one first conductive line 130. The first conductive line 130 that overlaps with the first upper contact 120A and the second upper contact 120B can be the one of the three first conductive lines 130 that overlap with the first upper contact 120A that is closest to the second upper contact 120B, and at the same time, the one first conductive line 130 can be the one of the four first conductive lines 130 that overlap with the second upper contact 120B that is closest to the first upper contact 120A. However, this disclosure is not limited thereto, and two or more first conductive lines 130 may overlap with the first upper contact 120A and the second upper contact 120B.

[0028] Similarly, the second upper contact 120B and the third upper contact 120C, which are closest to each other in the first and second directions, can overlap and contact a first conductive line 130. The third upper contact 120C and the fourth upper contact 120D, which are closest to each other in the first and second directions, can overlap and contact a first conductive line 130. The fourth upper contact 120D and the fifth upper contact 120E, which are closest to each other in the first and second directions, can overlap and contact a first conductive line 130.

[0029] Furthermore, in order for two adjacent upper contacts 120 to overlap and contact one or more first conductive lines 130, the two adjacent upper contacts 120 may not be positioned on a straight line extending in the second direction, but rather positioned separately from each other in the first direction. Figure 1 As shown, the second upper contact 120B can be configured to be spaced a predetermined distance from the first upper contact 120A in a first direction at one side of the first upper contact 120A (e.g., to the left of the first upper contact 120A when viewed in a plan view).

[0030] Similarly, the third upper contact 120C can be configured to be spaced apart from the second upper contact 120B by a predetermined distance in the first direction at one side of the second upper contact 120B (e.g., to the right of the second upper contact 120B when viewed in a plan view). Similarly, the fourth upper contact 120D can be configured to be spaced apart from the third upper contact 120C by a predetermined distance in the first direction at one side of the third upper contact 120C (e.g., to the left of the third upper contact 120C when viewed in a plan view). Similarly, the fifth upper contact 120E can be configured to be spaced apart from the fourth upper contact 120D by a predetermined distance in the first direction at one side of the fourth upper contact 120D (e.g., to the right of the fourth upper contact 120D when viewed in a plan view).

[0031] For example, the first to fifth upper contacts 120A, 120B, 120C, 120D and 120E can be arranged in a zigzag shape along the second direction, and thus, the odd-numbered upper contacts (i.e., the first upper contact 120A, the third upper contact 120C and the fifth upper contact 120E) can be located on a first straight line (e.g. line BB′) extending in the second direction, while the even-numbered upper contacts (i.e., the second upper contact 120B and the fourth upper contact 120D) can be located on a second straight line, which is spaced apart from line BB′ in the first direction and extends in the second direction.

[0032] Each of the plurality of upper contacts 120 may have a strip shape having a relatively long length in a second direction and a relatively short length in a first direction. That is, each upper contact 120 has a strip shape extending in the second direction. In this case, the distance between two adjacent upper contacts 120 in the first direction can be reduced, thereby reducing the area occupied by the plurality of upper contacts 120. Furthermore, in this embodiment, the planar shapes of the first to fifth upper contacts 120A, 120B, 120C, 120D, and 120E may be substantially the same as each other. However, this disclosure is not limited thereto. In another embodiment, at least one of the first to fifth upper contacts 120A, 120B, 120C, 120D, and 120E may have a different planar shape than the other upper contacts.

[0033] The lower contact 110 may be disposed below at least one of the plurality of upper contacts 120. The lower contact 110 may have a lower surface that contacts the substrate 100 (particularly a metal line of the substrate 100). Figure 3As shown, a lower contact 110 may be located between at least one of the plurality of upper contacts 120 and the substrate 100 to electrically connect them, and the lower contact 110 may not be present under the remaining upper contacts of the plurality of upper contacts 120. Accordingly, an insulating material may be located between the remaining upper contacts of the plurality of upper contacts 120 and the substrate 100.

[0034] refer to Figures 1 to 3 The lower contact 110 is disposed below the first upper contact 120A. The lower contact 110 may overlap and connect with the first upper contact 120A, and may have an upper surface that contacts the lower surface of the first upper contact 120A. However, this disclosure is not limited thereto.

[0035] In another embodiment, the lower contact 110 may be disposed below at least one of the second to fifth upper contacts 120B, 120C, 120D, and 120E, instead of below the first upper contact 120A, or the lower contact 110 may be disposed below each of the first to fifth upper contacts 120A, 120B, 120C, 120D, and 120E. However, increasing the number of lower contacts 110 means that the number of metal lines connected to the lower contacts 110 in the substrate 100 and / or the area occupied by the metal lines increases. In other words, as the number of lower contacts 110 decreases, the number of metal lines in the substrate 100 and / or the area occupied by the metal lines may decrease. When the area occupied by the metal lines connected to the lower contacts 110 decreases, metal lines for other purposes can be formed in the remaining area, and as a result, the area of ​​the semiconductor device can be reduced. Accordingly, when a lower contact 110 is formed, the number of lower contact 110s can be less than the number of upper contact 120s.

[0036] Each of the upper contact 120 and the lower contact 110 may include one of a variety of conductive materials, such as a metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), or tantalum (Ta), a metal nitride such as tantalum nitride (TaN) or titanium nitride (TiN), or a combination thereof.

[0037] Based on the connections between the lower contact 110, the upper contact 120, and the first conductive lines 130 described above, the voltage or signal supplied from the substrate 100 can be transmitted through the lower contact 110 connected to the substrate 100 and the first upper contact 120A connected to the lower contact 110 to the three first conductive lines 130 connected to the first upper contact 120A. Since one of the three first conductive lines 130 connected to the first upper contact 120A is connected to the second upper contact 120B, the voltage can be transmitted to the second upper contact 120B. Accordingly, the voltage can also be transmitted to the four first conductive lines 130 connected to the second upper contact 120B. Similarly, since one of the four first conductive lines 130 connected to the second upper contact 120B is also connected to the third upper contact 120C, the voltage can be transmitted to the third upper contact 120C, and correspondingly, it can also be transmitted to the four first conductive lines 130 connected to the third upper contact 120C. Similarly, since one of the four first conductive lines 130 connected to the third upper contact 120C is connected to the fourth upper contact 120D, the voltage can be transmitted to the fourth upper contact 120D, and correspondingly, it can also be transmitted to the four first conductive lines 130 connected to the fourth upper contact 120D. Likewise, since one of the four first conductive lines 130 connected to the fourth upper contact 120D is also connected to the fifth upper contact 120E, the voltage can be transmitted to the fifth upper contact 120E, and correspondingly, it can also be transmitted to the three first conductive lines 130 connected to the fifth upper contact 120E.

[0038] In summary, the voltage or signal supplied from the substrate 100 can be transmitted to the first upper contact 120A connected to the lower contact 110. Since the first upper contact to the fifth upper contacts 120A, 120B, 120C, 120D, and 120E form a voltage or signal transmission chain, the voltage or signal can be transmitted to the first upper contacts to the fifth upper contacts 120A, 120B, 120C, 120D, and 120E, as well as the first conductive lines 130 in contact with the first upper contacts to the fifth upper contacts 120A, 120B, 120C, 120D, and 120E. As a result, the same voltage or the same signal can be transmitted to all the first conductive lines 130.

[0039] The method of forming the lower contact 110 and the upper contact 120 will be briefly described below.

[0040] First, a first interlayer insulating layer I1 can be formed on the substrate 100 by depositing an insulating material. Then, the lower contact 110 can be formed by selectively etching the first interlayer insulating layer I1 until a portion of the substrate 100 (e.g., a metal line of the substrate 100) is exposed to form a hole providing space for the formation of the lower contact 110, and filling the hole with a conductive material. As a result, the lower contact 110 can be formed to penetrate the first interlayer insulating layer I1, and the thickness T1 of the lower contact 110 can be substantially the same as the thickness of the first interlayer insulating layer I1.

[0041] Next, a second interlayer insulating layer I2 can be formed on the first interlayer insulating layer I1 on which the lower contact 110 is formed by depositing an insulating material. The upper contact 120 can be formed by selectively etching the second interlayer insulating layer I2 to form a hole that provides space for the formation of the upper contact 120, and filling the hole with a conductive material. Here, the etching process for forming the hole can be performed until the upper surface of the lower contact 110 is exposed. Accordingly, the hole for forming the first upper contact 120A positioned above the lower contact 110 can have a lower surface positioned at substantially the same level as the upper surface of the lower contact 110. The first upper contact 120A can then be formed to penetrate the second interlayer insulating layer I2 by filling the hole with a conductive material, and the thickness T2 of the first upper contact 120A can be substantially the same as the thickness of the second interlayer insulating layer I2.

[0042] On the other hand, since there is no lower contact 110 below the second to fifth upper contacts 120B, 120C, 120D, and 120E, over-etching may occur when performing the etching process for forming the holes. As a result, the holes used to form each of the second to fifth upper contacts 120B, 120C, 120D, and 120E may have a lower surface located below the upper surface of the lower contact 110. Accordingly, as... Figure 3As shown, the thickness T3 of each of the second to fifth upper contacts 120B, 120C, 120D, and 120E can be greater than the thickness T2 of the first upper contact 120A. Each of the second to fifth upper contacts 120B, 120C, 120D, and 120E can be formed to penetrate a portion of the first interlayer insulation layer I1 and completely penetrate the second interlayer insulation layer I2. Since the second to fifth upper contacts 120B, 120C, 120D, and 120E penetrate a portion of the first interlayer insulation layer I1, the remaining portion of the first interlayer insulation layer I1 can remain below each of the second to fifth upper contacts 120B, 120C, 120D, and 120E. The thickness of the remaining portion of the first interlayer insulation layer I1 can correspond to the difference between T3 and (T1+T2).

[0043] When over-etching occurs during the formation of holes for the second to fifth upper contacts 120B, 120C, 120D, and 120E, the substrate 100 may be unintentionally exposed, and thus the second to fifth upper contacts 120B, 120C, 120D, and 120E may be connected to the substrate 100. To prevent this, the first interlayer insulating layer I1 may include a stacked structure of a first insulating layer I11 and a second insulating layer I12. When forming holes for the second to fifth upper contacts 120B, 120C, 120D, and 120E, the first insulating layer I11 may serve as an etch stop layer, and therefore the first insulating layer I11 includes a material having a lower etch rate than the second insulating layer I12. For example, when the second insulating layer I12 includes silicon oxide, the first insulating layer I11 may include silicon nitride. The second interlayer insulating layer I2 may include the same material as the second insulating layer I12, such as silicon oxide. In this configuration, the first upper contact 120A can penetrate the second interlayer insulating layer I2, and the second to fifth upper contacts 120B, 120C, 120D, and 120E can penetrate the second interlayer insulating layer I2 and the second insulating layer I12 through excessive etching. However, this disclosure is not limited thereto.

[0044] In another embodiment, the first insulating layer I11, which serves as an etching barrier layer, can be omitted, allowing the first interlayer insulating layer I1 to be formed as a single layer. When the first insulating layer I11 is omitted, the holes for the second to fifth upper contacts 120B, 120C, 120D, and 120E can be formed without exposing the substrate 100 by appropriately adjusting the etching conditions. In some embodiments, the first interlayer insulating layer I1 and the second interlayer insulating layer I2 can be formed of the same or different materials, and each of the first interlayer insulating layer I1 and the second interlayer insulating layer I2 can have a single-layer structure or a multilayer structure.

[0045] Similarly, the second conductive line 150 can be connected to a portion of the substrate 100 (e.g., a metal wire formed in the substrate 100) via a contact structure disposed below the second conductive line 150, and can receive the voltage required to be driven by the contact structure. In some cases, the multiple second conductive lines 150 can receive different voltages and / or different signals, or they can receive the same voltage and / or the same signal. In this embodiment, contact structures 160, 170, and 180 will be proposed for supplying the same voltage or the same signal to the multiple second conductive lines 150, such as... Figure 1 , Figure 4 and Figure 5 As shown.

[0046] refer to Figure 1 Contact structures 160, 170, and 180 can be disposed in a peripheral region PA at one of the two sides of the unit region CA (e.g., a peripheral region PA at the upper side of the unit region CA) in a second direction. Contact structures 160, 170, and 180 may include a lower contact 160, an intermediate contact 170, and an upper contact 180. In this embodiment, since the second conductive line 150 is positioned above the first conductive line 130, contact structures 160, 170, and 180 can have a three-layer structure, unlike contact structures 110 and 120 which have two-layer structures. The differences between contact structures 160, 170, and 180 and contact structures 110 and 120 will be described in detail below.

[0047] An upper contact 180 may be disposed below the second conductive line 150 and has an upper surface that contacts the lower surface of the second conductive line 150. Each of the plurality of upper contacts 180 may overlap and contact two or more second conductive lines 150 arranged in a first direction, such that each upper contact 180 is connected to two or more second conductive lines 150, as shown below. Figure 1 and Figure 5 As shown. In addition, the two upper contacts 180 that are closest to each other in the first and second directions can overlap and connect with one or more second conductive lines 150.

[0048] In this embodiment, the five upper contacts 180 (i.e., the first upper contact 180A, the second upper contact 180B, the third upper contact 180C, the fourth upper contact 180D, and the fifth upper contact 180E) can be arranged sequentially from left to right in the first direction when viewed in a plan view. To ensure that the two upper contacts 180 closest to each other overlap and contact one or more second conductive lines 150, the two upper contacts 180 closest to each other may not be positioned on a straight line extending in the first direction, but rather spaced apart from each other in the second direction.

[0049] For example, such as Figure 1 As shown, the first to fifth upper contacts 180A, 180B, 180C, 180D, and 180E can be arranged in a zigzag pattern along a first direction. Therefore, the first upper contact 180A, the third upper contact 180C, and the fifth upper contact 180E can be located on a straight line extending in the first direction (e.g., line DD′), while the second upper contact 180B and the fourth upper contact 180D can be located on a different straight line extending in the first direction, distinct from line DD′. Each of the plurality of upper contacts 180 can have a strip shape or a strip-like shape in the plan view, the strip shape having a relatively long length in the first direction and a relatively short length in the second direction. That is, each upper contact 180 has a strip shape extending in the first direction.

[0050] The lower contact 160 may be disposed below at least one of the plurality of upper contacts 180. The lower contact 160 may have a lower surface that contacts the substrate 100 (particularly a metal wire of the substrate 100). The lower contact 160 may be electrically connected to the upper contacts 180 via an intermediate contact 170, described later. When the lower contact 160 is disposed below one of the plurality of upper contacts 180, the lower contact 160 may not be present below the remaining upper contacts of the plurality of upper contacts 180. In this embodiment, the lower contact 160 is disposed below the first upper contact 180A as follows: Figure 1 , Figure 4 and Figure 5 As shown.

[0051] In this embodiment, the intermediate contact 170 can be disposed below each of the plurality of upper contacts 180. (See reference...) Figure 1The first to fifth intermediate contacts 170A, 170B, 170C, 170D, and 170E overlap and connect with the first to fifth upper contacts 180A, 180B, 180C, 180D, and 180E, respectively. The upper surfaces of the first to fifth intermediate contacts 170A, 170B, 170C, 170D, and 170E can contact the lower surfaces of the first to fifth upper contacts 180A, 180B, 180C, 180D, and 180E, respectively. Figure 5 As shown.

[0052] As described above, since the lower contact 160 is disposed below the first upper contact 180A, the first intermediate contact 170A can be positioned vertically between the first upper contact 180A and the lower contact 160. On the other hand, the lower contact 160 may not be present below the second to fifth intermediate contacts 170B, 170C, 170D, and 170E, as... Figure 5 As shown. However, this disclosure is not limited thereto. In another embodiment, the remaining intermediate contacts of intermediate contact 170 may be omitted except for the first intermediate contact 170A that overlaps with the lower contact 160. For example, in addition to the first intermediate contact 170A, at least one of the second to fifth intermediate contacts 170B, 170C, 170D and 170E may be omitted (i.e., may not be formed).

[0053] In the stacked structure of the lower contact 160, the first intermediate contact 170A, the first upper contact 180A, and the second conductive line 150, the voltage or signal supplied from the substrate 100 can be transmitted to the second conductive line 150 via the lower contact 160, the first intermediate contact 170A, and the first upper contact 180A. The first upper contact to the fifth upper contact 180A, 180B, 180C, 180D, and 180E and the first intermediate contact to the fifth intermediate contact 170A, 170B, 170C, 170D, and 170E can form a voltage or signal transmission chain, such that the same voltage or the same signal can be transmitted to all the second conductive lines 150.

[0054] The method of forming the lower contact 160, the intermediate contact 170, and the upper contact 180 will be briefly described below.

[0055] refer to Figure 5A first interlayer insulating layer I1 can be formed on substrate 100 by depositing an insulating material, and then the lower contact 160 can be formed by selectively etching the first interlayer insulating layer I1 to form a hole that provides space for the formation of the lower contact 160, and filling the hole with a conductive material. As a result, the lower contact 160 can be formed to penetrate the first interlayer insulating layer I1, and the thickness of the lower contact 160 can be substantially the same as the thickness of the first interlayer insulating layer I1. The process of forming the lower contact 160 can be performed simultaneously with the above-described process of forming the lower contact 110.

[0056] Next, the second interlayer insulating layer I2 can be formed on the first interlayer insulating layer I1 (on which the lower contact 160 is formed) by depositing an insulating material, and the intermediate contact 170 can be formed by selectively etching the second interlayer insulating layer I2 to form a hole that provides space for the formation of the intermediate contact 170, and filling the hole with a conductive material. Here, the etching process for forming the hole can be performed until the upper surface of the lower contact 160 is exposed. Accordingly, the hole for forming the first intermediate contact 170A positioned on the lower contact 160 can have a lower surface positioned at substantially the same level as the upper surface of the lower contact 160. Then, the first intermediate contact 170A can be formed to penetrate the second interlayer insulating layer I2, and therefore, the thickness of the first intermediate contact 170A can be substantially the same as the thickness of the second interlayer insulating layer I2.

[0057] On the other hand, since there is no lower contact 160 below the second to fifth intermediate contacts 170B, 170C, 170D, and 170E, over-etching may occur during the etching process used to form the hole (in which the first intermediate contact 170A is to be formed). Accordingly, the thickness of each of the second to fifth intermediate contacts 170B, 170C, 170D, and 170E can be greater than the thickness of the first intermediate contact 170A. Each of the second to fifth intermediate contacts 170B, 170C, 170D, and 170E can be formed to penetrate a portion of the first interlayer insulating layer I1 and completely penetrate the second interlayer insulating layer I2. The process of forming the intermediate contact 170 can be performed simultaneously with the above-described process of forming the upper contact 120.

[0058] Next, the third interlayer insulating layer I3 can be formed on the second interlayer insulating layer I2 (where the intermediate contact 170 is formed) by depositing an insulating material, and the upper contact 180 can be formed by selectively etching the third interlayer insulating layer I3 to form a hole that provides space for the formation of the upper contact 180, and filling the hole with a conductive material. Here, the etching process for forming the hole can be performed until the upper surface of the intermediate contact 170 is exposed. In this embodiment, since the first to fifth intermediate contacts 170A, 170B, 170C, 170D and 170E are located below the first to fifth upper contacts 180A, 180B, 180C, 180D and 180E respectively, the first to fifth upper contacts 180A, 180B, 180C, 180D and 180E can be formed to penetrate the third interlayer insulating layer I3 and can have substantially the same thickness. That is, the first upper contact to the fifth upper contact 180A, 180B, 180C, 180D and 180E can have a thickness that is substantially the same as the thickness of the third interlayer insulation layer I3.

[0059] Additionally, as described above, at least one of the second to fifth intermediate contacts 170B, 170C, 170D, and 170E can be omitted. In this case, since over-etching may occur when forming the hole for forming at least one of the second to fifth upper contacts 180B, 180C, 180D, and 180E (below which the intermediate contact 170 is not formed), at least one of the second to fifth upper contacts 180B, 180C, 180D, and 180E can have a lower surface located below the lower surface of the first upper contact 180A, and therefore can have a thickness greater than that of the first upper contact 180A.

[0060] Although not shown, contact structures can be formed, each connected to one of the first conductive lines 130, to supply different voltages or different signals to the plurality of first conductive lines 130. That is, these contact structures can correspond one-to-one with each of the first conductive lines 130. These contact structures can be formed in regions different from those where contact structures 110 and 120 are formed. For example, when in... Figure 1 When viewed in a plan view, these contact structures can be formed in the first direction on the left side of the unit region CA.

[0061] Similarly, in order to supply different voltages or different signals to the plurality of second conductive lines 150, contact structures can be formed respectively connected to the plurality of second conductive lines 150. That is, these contact structures can correspond one-to-one with the second conductive lines 150. These contact structures can be formed in regions different from the regions forming contact structures 160, 170, and 180. For example, when in Figure 1 When viewed in a plan view, these contact structures can be formed in the second direction on the underside of the unit region CA.

[0062] According to the aforementioned semiconductor device, since the upper and lower contacts of the contact structure used to transmit the same signal or voltage to multiple conductive lines have shapes that overlap with at least two of the multiple conductive lines, the manufacturing process can be simplified compared to forming contacts that overlap and connect with each of the multiple conductive lines. This may be because contacts that overlap and connect with two or more conductive lines may have a larger size and a larger spacing than contacts that overlap and connect with each conductive line.

[0063] Furthermore, since multiple upper contacts that contact multiple conductive lines can be chained together, and lower contacts can be positioned below only one of the selected upper contacts to connect to the metal lines of the substrate, the number and / or area of ​​metal lines connected to the lower contacts can be reduced. As a result, the area of ​​the semiconductor device can be reduced.

[0064] Figure 6 It is shown Figures 1 to 5 Cross-sectional view of storage cell 140.

[0065] refer to Figure 6 The storage unit 140 may include a variable resistor element that stores data by switching between different resistance states. For example, the storage unit 140 may include a stacked structure of a lower electrode layer 141, a selector layer 143, an intermediate electrode layer 145, a variable resistor layer 147, and an upper electrode layer 149.

[0066] The lower electrode layer 141 and the upper electrode layer 149 may be located at two ends (e.g., the lower end and the upper end) of the memory cell 140, respectively, and may apply the voltage required for the operation of the memory cell 140. The intermediate electrode layer 145 may electrically connect the selector layer 143 and the variable resistor layer 147 and physically separate them from each other. The lower electrode layer 141, the intermediate electrode layer 145, or the upper electrode layer 149 may comprise one of a variety of conductive materials, such as metals like platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), or tantalum (Ta), metal nitrides such as tantalum nitride (TaN) or titanium nitride (TiN), or combinations thereof. Alternatively, the lower electrode layer 141, the intermediate electrode layer 145, or the upper electrode layer 149 may be carbon electrodes.

[0067] Selector layer 143 can prevent or reduce current leakage between memory cells 140. Because memory cells 140 share the aforementioned first conductive line 130 or second conductive line 150, current leakage may occur. Therefore, selector layer 143 may have threshold switching characteristics, i.e., the characteristic of preventing or substantially limiting current flow in memory cells 140 when the applied voltage is less than a predetermined threshold of the memory cell 140, and the characteristic of allowing a large current to suddenly flow into the memory cell 140 when the applied voltage is equal to or greater than the threshold. The threshold may be referred to as the threshold voltage, and selector layer 143 can implement an on or off state based on the threshold voltage. Selector layer 143 may include diodes, dual-ion threshold switching (OTS) materials such as chalcogenide-based materials, mixed-ion electron conduction (MIEC) materials such as metal-containing chalcogenide-based materials, metal-insulator transition (MIT) materials such as NbO2 or VO2, or tunneling insulating layers with relatively wide gaps such as SiO2 or Al2O3.

[0068] The variable resistance layer 147 can be a component for storing data in the storage cell 140. For this purpose, the variable resistance layer 147 can have variable resistance characteristics that switch between different resistance states according to the applied voltage. The variable resistance layer 147 can have a single-layer structure or a multi-layer structure, comprising at least one of the materials used in RRAM, PRAM, MRAM, and FRAM, i.e., metal oxides such as perovskite-based oxides or transition metal oxides, phase change materials such as chalcogenide-based materials, ferromagnetic materials, or ferroelectric materials.

[0069] However, the memory cell is not limited to the structure 140 shown, and various modifications can be made to the memory cell 140. As long as the memory cell 140 includes the variable resistor layer 147 required for data storage, at least one of the other layers can be omitted. That is, at least one of the lower electrode layer 141, the intermediate electrode layer 145, the upper electrode layer 149, and the selector layer 143 can be omitted. Alternatively, the positions of the variable resistor layer 147 and the selector layer 143 can be reversed. That is, the selector layer 143 can be disposed above the variable resistor layer 147. Alternatively, one or more layers (not shown) can be added to the memory cell 140 to facilitate the manufacturing process of the memory cell 140 or improve the characteristics of the memory cell 140.

[0070] Furthermore, while the above embodiments have described a single-layer storage cell 140, this disclosure is not limited thereto. In another embodiment, two or more layers of storage cells may be stacked vertically. (See also...) Figures 7 to 11 This situation is described exemplarily.

[0071] Figures 7 to 11 This is a view illustrating a semiconductor device according to another embodiment of the present disclosure. Figure 7 This is a plan view showing a semiconductor device according to this embodiment. Figure 8 It is along Figure 7 A cross-sectional view taken from line AA′. Figure 9 yes Figure 7 A cross-sectional view of line BB′. Figure 10 It is along Figure 7 The cross-sectional view of line CC′, and Figure 11 It is along Figure 7 A cross-sectional view taken from line DD′. The main description will be related to the above. Figures 1 to 5 The implementation methods differ.

[0072] refer to Figures 7 to 11The semiconductor device according to this embodiment may include: a substrate 100; a plurality of first conductive lines 130 disposed on the substrate 100 and extending in a first direction substantially parallel to the upper surface of the substrate 100; a plurality of second conductive lines 150 disposed on the first conductive lines 130 and extending in a second direction substantially parallel to the upper surface of the substrate 100 and intersecting the first direction; and a plurality of first memory cells 140 disposed between the first conductive lines 130 and the second conductive lines 150 in a vertical direction perpendicular to the first and second directions and adjacent to the first conductive lines. The first conductive line 130 overlaps with the intersection area of ​​the second conductive line 150; a plurality of third conductive lines 250 are disposed above the second conductive line 150 and extend in a second direction to overlap and contact the second conductive line 150 respectively; a plurality of fourth conductive lines 230 are disposed above the third conductive line 250 and extend in a first direction to overlap the first conductive line 130 respectively; and a plurality of second storage units 240 are disposed vertically between the third conductive line 250 and the fourth conductive line 230 and overlap with the intersection area of ​​the third conductive line 250 and the fourth conductive line 230.

[0073] The second conductive line 150 and the third conductive line 250 are in contact with each other and therefore can perform the same function. For example, when each of the first conductive line 130 and the fourth conductive line 230 is used as a word line, the second conductive line 150 and the third conductive line 250 can be used as a common bit line. Alternatively, when each of the first conductive line 130 and the fourth conductive line 230 is used as a bit line, the second conductive line 150 and the third conductive line 250 can be used as a common word line. In another embodiment, the third conductive line 250 can be omitted. In this case, the second memory cell 240 can be disposed between the second conductive line 150 and the fourth conductive line 230 and overlap with their intersection area.

[0074] The substrate 100, the first conductive line 130, the second conductive line 150, and the first memory cell 140 can be connected to... Figures 1 to 5 The corresponding components in the above embodiments shown are the same. However, Figures 1 to 5 The storage unit 140 in the above embodiment shown will be referred to as the first storage unit 140 in order to distinguish it from the second storage unit 240.

[0075] The contact structures 110 and 120 connected to and disposed below the first conductive line 130, and the contact structures 160, 170, and 180 connected to and disposed below the second conductive line 150, can be coupled with... Figures 1 to 5 The contact structure described in the above embodiments is the same.

[0076] Because the third conductive line 250 contacts the second conductive line 150, the same voltage or the same signal can be supplied to the third conductive line 250 through contact structures 160, 170, and 180 and the second conductive line 150, such as Figure 10 and Figure 11 As shown.

[0077] The fourth conductive line 230 can receive the same voltage or the same signal from the substrate 100 through contact structures 210, 220, and 222, such as Figure 8 and Figure 9 As shown.

[0078] Contact structures 210, 220, and 222 can be disposed in the peripheral region PA on one side of the unit region CA in the first direction, for example, when in Figure 7 When viewed in the plan view, it is located in the peripheral region PA to the right of the cell region CA. In this case, in order not to overlap with the contact structures 110 and 120 connected to the first conductive line 130, the contact structures 210, 220, and 222 can be positioned further away from the cell region CA than the contact structures 110 and 120. Similarly, for the arrangement of the contact structures 210, 220, and 222, the fourth conductive line 230 can extend further to the right compared to the first conductive line 130, such as... Figure 7 and Figure 8 As shown.

[0079] Contact structures 210, 220, and 222 may include a lower contact 210, an intermediate contact 220, and an upper contact 222. Since the fourth conductive line 230 is positioned above the first conductive line 130 in a vertical direction perpendicular to the upper surface of the substrate 100, contact structures 210, 220, and 222 connected to the fourth conductive line 230 can have a three-layer structure, unlike contact structures 110 and 120 which have two-layer structures. Otherwise, contact structures 210, 220, and 222 may be similar to contact structures 110 and 120. The differences between contact structures 210, 220, and 222 and contact structures 110 and 120 will be described in detail below.

[0080] The upper contact 222 may have an upper surface that contacts the lower surface of the fourth conductive line 230 below it. Each of the plurality of upper contacts 222 may be connected to the two or more fourth conductive lines 230 by mutually overlapping with them in the second direction. Furthermore, the two upper contacts 222 that are closest to each other in the first and second directions may mutually overlap and connect with one or more fourth conductive lines 230.

[0081] In this embodiment, when in Figure 7 When viewed in a plan view, the five upper contacts 222 (i.e., the first upper contact 222A, the second upper contact 222B, the third upper contact 222C, the fourth upper contact 222D, and the fifth upper contact 222E) can be arranged sequentially from bottom to top in the second direction. To allow the two closest upper contacts 222 to overlap and contact one or more fourth conductive lines 230, the two closest upper contacts 222 may not be positioned on a straight line extending in the second direction, but rather spaced apart from each other in the first direction.

[0082] For example, such as Figure 7 As shown, the first to fifth upper contacts 222A, 222B, 222C, 222D, and 222E can be arranged in a zigzag shape along the second direction. Therefore, the first upper contact 222A, the third upper contact 222C, and the fifth upper contact 222E can be positioned on a straight line extending in the second direction (e.g., line BB'), and the second upper contact 222B and the fourth upper contact 222D can be positioned on another straight line extending in the second direction. Each of the upper contacts 222 can have a strip shape or a strip-like shape in the plan view, the strip shape having a relatively long length in the second direction and a relatively short length in the first direction. That is, each upper contact 222 has a strip shape extending in the second direction.

[0083] The lower contact 210 may be disposed below at least one of the plurality of upper contacts 222. The lower contact 210 may have a lower surface that contacts the substrate 100 (particularly a metal wire of the substrate 100). The lower contact 210 may be electrically connected to the upper contacts 222 via an intermediate contact 220, described later. When the lower contact 210 is disposed below one of the plurality of upper contacts 222, the lower contact 210 may not be present below the remaining upper contacts of the plurality of upper contacts 222. In this embodiment, the lower contact 210 is disposed below the first upper contact 222A as follows: Figure 8 and Figure 9 As shown.

[0084] In this embodiment, the intermediate contact 220 can be disposed below each of the plurality of upper contacts 222. (See reference...) Figure 7The first to fifth intermediate contacts 220A, 220B, 220C, 220D, and 220E are configured to overlap and connect with the first to fifth upper contacts 222A, 222B, 222C, 222D, and 222E, respectively. The upper surfaces of the first to fifth intermediate contacts 220A, 220B, 220C, 220D, and 220E can contact the lower surfaces of the first to fifth upper contacts 222A, 222B, 222C, 222D, and 222E, respectively. Figure 9 As shown.

[0085] As described above, since the lower contact 210 is disposed below the first upper contact 222A, the first intermediate contact 220A can be positioned vertically between the first upper contact 222A and the lower contact 210. On the other hand, the lower contact 210 may not be present below the second to fifth intermediate contacts 220B, 220C, 220D, and 220E, as... Figure 9 As shown. However, this disclosure is not limited thereto. In another embodiment, the remaining intermediate contacts 220B, 220C, 220D, and 220E may be omitted, except for the first intermediate contact 220A that overlaps with the lower contact 210. For example, at least one of the second to fifth intermediate contacts 220B, 220C, 220D, and 220E may be omitted (i.e., may not be formed).

[0086] In the aforementioned stacked structure of the lower contact 210, the first intermediate contact 220A, the first upper contact 222A, and the fourth conductive line 230, the voltage or signal supplied from the substrate 100 can be transmitted to the fourth conductive line 230 via the lower contact 210, the first intermediate contact 220A, and the first upper contact 222A. Furthermore, the first upper contact to the fifth upper contact 222A, 222B, 222C, 222D, and 222E, and the first intermediate contact to the fifth intermediate contact 220A, 220B, 220C, 220D, and 220E can form a voltage or signal transmission chain, such that the same voltage or the same signal can be transmitted to all the fourth conductive lines 230.

[0087] Although not shown, when three layers of memory cells are stacked, multiple fifth conductive lines overlapping the second conductive line 150 can be vertically positioned above the fourth conductive line 230. Figure 7When viewed in a plan view, compared to the second conductive line 150, the plurality of fifth conductive lines can extend further upward toward the upper side of the cell region CA in the second direction, and a contact structure connecting the plurality of fifth conductive lines to the substrate 100 can be disposed vertically between the plurality of fifth conductive lines and the substrate 100. This contact structure can be the same as or similar to contact structures 160, 170, and 180, except that it has a higher height than contact structures 160, 170, and 180.

[0088] In this way, storage cells can be stacked in multiple layers, and a common contact structure can be set up to connect to additional conductive lines.

[0089] According to the above embodiments of this disclosure, the manufacturing difficulty of semiconductor devices can be reduced and the area of ​​semiconductor devices can be decreased.

[0090] Although various embodiments have been described for illustrative purposes, various changes and modifications may be made by those skilled in the art without departing from the spirit and scope of the teachings as defined by the appended claims.

Claims

1. A semiconductor device, comprising: Substrate; A plurality of first conductive lines are disposed on the substrate and extend in a first direction; A plurality of second conductive lines are disposed above or below the first conductive line and located on the substrate, and the plurality of second conductive lines extend in a second direction intersecting the first direction, the first direction and the second direction being parallel to the upper surface of the substrate; A plurality of storage cells are disposed between the first conductive line and the second conductive line in a third direction perpendicular to the first direction and the second direction, and the plurality of storage cells are respectively disposed in the intersection region of the first conductive line and the second conductive line; as well as A contact structure is disposed between the first conductive line and the substrate in a third-order orientation, and the contact structure includes a plurality of upper contacts and lower contacts, the plurality of upper contacts being connected to the first conductive line, and the lower contacts being connected to the substrate and overlapping at least one of the plurality of upper contacts when viewed in a plan view. Wherein, each of the plurality of upper contacts is in contact with at least two of the first conductive wires, and Among the plurality of upper contacts, the two upper contacts that are closest to each other are in contact with one or more of the plurality of first conductive lines.

2. The semiconductor device according to claim 1, further comprising: An insulating material layer is provided between one of the plurality of upper contacts that does not overlap with the lower contact and the substrate.

3. The semiconductor device according to claim 2, wherein, The etching rate of the insulating material layer is lower than that of the insulating material filling the space between the plurality of upper contacts.

4. The semiconductor device according to claim 1, wherein, The two upper contacts that are closest to each other are located on different straight lines extending in the second direction.

5. The semiconductor device according to claim 1, wherein, The plurality of upper contacts are arranged in a zigzag shape along the second direction.

6. The semiconductor device according to claim 1, wherein, The plurality of upper contacts include: odd-numbered upper contacts and even-numbered upper contacts arranged alternately along the second direction. The odd-numbered upper contact is positioned on a first straight line extending in the second direction, and The even-numbered upper contact is positioned on a second straight line extending in the second direction, the second straight line being spaced apart from the first straight line in the first direction.

7. The semiconductor device according to claim 1, wherein, Each of the plurality of upper contacts has a strip shape in which the length in the second direction is longer than the length in the first direction.

8. The semiconductor device according to claim 1, wherein, The thickness of one of the plurality of upper contacts that overlaps with the lower contact is less than the thickness of one of the plurality of upper contacts that does not overlap with the lower contact.

9. The semiconductor device according to claim 1, wherein, The same voltage or the same signal is transmitted to the plurality of first conductive lines through the lower contact and the plurality of upper contacts.

10. The semiconductor device according to claim 1, wherein, The substrate includes: a cell region in which the plurality of memory cells are arranged; and a peripheral region disposed around the cell region. The contact structure is disposed in the peripheral region on one side of the unit region in the first direction.

11. The semiconductor device according to claim 1, wherein, The contact structure is a first contact structure, the plurality of upper contacts are plurality of first upper contacts, and the lower contact is a first lower contact. The semiconductor device further includes: A second contact structure is disposed between the second conductive line and the substrate in the third-order direction, and includes a plurality of second upper contacts and a second lower contact. The plurality of second upper contacts are connected to the second conductive line, and the second lower contacts are connected to the substrate and overlap with at least one of the plurality of second upper contacts when viewed in the plan view. Wherein, the second contact structure is disposed in the peripheral region on one side of the unit region in the second direction, and The second contact structure further includes a first intermediate contact, which is located between one of the plurality of second upper contacts that overlaps with the second lower contact and the second lower contact.

12. The semiconductor device according to claim 11, wherein, The second contact structure also includes: The second intermediate contact is disposed below one of the plurality of second upper contacts that does not overlap with the second lower contact.

13. The semiconductor device according to claim 12, further comprising: An insulating material layer is provided between the second intermediate contact and the substrate.

14. The semiconductor device according to claim 13, wherein, The etching rate of the insulating material layer is lower than that of the insulating material filling the space between the first intermediate contact and the second intermediate contact.

15. The semiconductor device according to claim 12, wherein, The thickness of the first intermediate contact is less than the thickness of the second intermediate contact.

16. The semiconductor device according to claim 12, wherein, The plurality of second upper contacts have the same thickness as each other.

17. The semiconductor device according to claim 1, further comprising: A plurality of third conductive lines are disposed on the first conductive line and extend in the first direction, and overlap with the first conductive line when viewed in the plan view; as well as A third contact structure is disposed between the plurality of third conductive lines and the substrate, and includes a plurality of third upper contacts and a third lower contact. The plurality of third upper contacts are connected to the third conductive lines, and the third lower contacts are connected to the substrate and, when viewed in the plan view, overlap with at least one of the plurality of third upper contacts. Wherein, each of the plurality of third upper contacts is in contact with at least two of the plurality of third conductive lines, and Among the plurality of third upper contacts, the two closest third upper contacts are in contact with one or more of the plurality of third conductive lines.

18. The semiconductor device according to claim 17, wherein, The substrate includes: a cell region in which the plurality of memory cells are arranged; and a peripheral region disposed around the cell region. The contact structure and the third contact structure are located in the peripheral region on one side of the unit region in the first direction, and The distance between the third contact structure and the unit region is greater than the distance between the contact structure and the unit region.

19. The semiconductor device according to claim 1, further comprising: A first intermediate contact is located between one of the upper contacts that overlaps with the lower contact and the lower contact.

20. The semiconductor device of claim 19, further comprising: The second intermediate contact is disposed below one of the upper contacts that does not overlap with the lower contact.

21. The semiconductor device of claim 20, further comprising: An insulating material layer is provided between the second intermediate contact and the substrate.

22. The semiconductor device according to claim 20, wherein, The thickness of the first intermediate contact is less than the thickness of the second intermediate contact.

23. The semiconductor device according to claim 20, wherein, The upper contact elements have the same thickness as each other.

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