Word line drive circuit based on composite dielectric gate dual crystal transistor photosensitive detector
By designing a multi-channel word line driving circuit, the problem of unstable voltage switching in traditional circuits in composite dielectric gate dual transistor photodetectors was solved, achieving fast voltage switching and reducing leakage risk, thereby improving the device's performance and compatibility.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NANJING UNIV
- Filing Date
- 2023-09-15
- Publication Date
- 2026-06-09
AI Technical Summary
Traditional word line driving circuits cannot effectively support voltage switching of composite dielectric gate dual transistor photodetectors in multiple states such as standby, reset, exposure, readout, programming and erasure, and there are risks of leakage and voltage fluctuations.
A multi-channel word line driving circuit based on a composite dielectric gate dual transistor photodetector was designed, including a positive high voltage level conversion circuit, a positive voltage level conversion circuit, a negative voltage level conversion circuit, and a voltage selection switch circuit. This circuit enables rapid switching between the three voltages and incorporates a built-in voltage switch, avoiding the influence of the inductance and capacitance of the external switching pin.
This invention enables rapid voltage switching in a composite dielectric gate dual transistor photodetector, reducing the risk of leakage current and voltage disturbance, and improving the device's performance and compatibility.
Smart Images
Figure CN117278873B_ABST
Abstract
Description
Technical Field
[0001] This invention proposes a word line driving circuit based on a composite dielectric gate dual transistor photodetector, belonging to the field of analog integrated circuits. Background Technology
[0002] CCD and CMOS-APS are the two mainstream imaging devices, but both have certain limitations. The complex control timing and long-distance charge transfer result in the slower operating speed of CCD and make it difficult to integrate; CMOS-APS uses photodiodes with low fill factor and small overall full-well charge.
[0003] In existing patent CN201210442007.X, a composite dielectric gate dual-transistor photodetector was proposed. This sensor is characterized by a single semiconductor device capable of performing complete reset, photosensitive, and readout functions, thus forming a complete pixel and significantly improving the pixel fill factor. As a next-generation imaging device, the composite dielectric gate dual-transistor photodetector offers advantages such as faster operating speed, larger fill factor, more full-well charge, and integration with CMOS processes, making it superior to CCD and CMOS-APS.
[0004] Traditional word line driving circuits only support a single level or level shifting and switching within a single channel, which cannot adequately support voltage switching in multiple states such as standby, reset, exposure, readout, programming, and erasure of composite dielectric gate dual transistor photodetectors. Therefore, it is necessary to design a multi-channel word line driving circuit for composite dielectric gate dual transistor photodetectors. Summary of the Invention
[0005] In view of this, the present invention provides a word line driving circuit based on a composite dielectric gate dual transistor photodetector.
[0006] The technical solution adopted in this invention is as follows:
[0007] The word line driving circuit based on a composite dielectric gate dual transistor photodetector includes a detector unit comprising a MOS-C section and a MOSFET section with a composite dielectric gate structure. The control gate port of the MOSFET section is connected to the word line driving circuit, which includes a positive high voltage level conversion circuit, a positive voltage level conversion circuit, a negative voltage level conversion circuit, and a voltage selection switch circuit. The positive high voltage level conversion circuit, the positive voltage level conversion circuit, and the negative voltage level conversion circuit are used to drive the switches of the three voltage channels, respectively. The output terminals of these three circuits are connected to the input terminal of the voltage selection switch circuit, and the output terminal of the voltage selection switch circuit is connected to the control gate port of the MOSFET section.
[0008] Furthermore, the positive-high voltage level conversion circuit includes two digital input signals, two analog input signals, and one analog output signal; wherein the two digital input signals are the level conversion control signal EN_RAMP and its inverted signal ENB_RAMP, the two analog input signals are the first power supply signal AVDD_1P2 and the second power supply signal AVDD_12P0, and the one analog output signal is a high-level signal VHH, wherein the high-level signal VHH and the inverted signal ENB_RAMP are synchronized in timing.
[0009] Furthermore, the second power signal AVDD_12P0 is connected to ground via a capacitor to form a decoupling circuit.
[0010] Furthermore, the positive voltage level conversion circuit includes two digital input signals, one analog input signal, and one analog output signal; wherein the two digital input signals are the level conversion control signal EN_EXP and its inverted signal ENB_EXP, the one analog input signal is the third power supply signal AVDD_2P5, and the one analog output signal is the positive level signal EN_EXP25, wherein the positive level signal EN_EXP25 and the level conversion control signal EN_EXP are synchronized in timing.
[0011] Furthermore, the negative voltage level conversion circuit is multiplexed, including a first negative voltage conversion circuit and a second negative voltage conversion circuit;
[0012] The first negative voltage conversion circuit includes two digital input signals, two analog input signals, and one analog output signal; wherein the two digital input signals are the level conversion control signal EN_RST and its inverted signal ENB_RST, the two analog input signals are the first power supply signal AVDD_1P2 and the fourth power supply signal AVDD_N3P0, and the one analog output signal is the first negative level signal VLL, and the first negative level signal VLL is in the same timing as the level conversion signal EN_RST;
[0013] The second negative voltage conversion circuit includes two digital input signals, two analog input signals, and one analog output signal. The two digital input signals are shared with the positive voltage level conversion circuit and are the level conversion control signal EN_EXP and its inverted signal ENB_EXP. The two analog input signals are the first power supply signal AVDD_1P2 and the fourth power supply signal AVDD_N3P0. The one analog output signal is the second negative level signal VL, and the second negative level signal VL and the inverted signal ENB_EXP are synchronized in timing.
[0014] Furthermore, the fourth power supply signal AVDD_N3P0 is connected to ground via a capacitor to form a decoupling circuit.
[0015] Furthermore, the voltage selection switch circuit includes eight analog input signals and one analog output signal; wherein the eight analog input signals are the first channel voltage HVWLPC1, the second channel voltage HVWLPC2, the third channel voltage HVWLNC1, the power supply voltage AVDD_1P2, the high-level signal VHH, the level signal EN_EXP25, the first negative level signal VLL, and the second negative level signal VL, and the one analog output signal is the word line driver circuit output signal HVWL.
[0016] Furthermore, the level signal EN_EXP25 and the second negative level signal VL control the first voltage channel switch, the high level signal VHH controls the second voltage channel switch, and the first negative level signal VLL controls the third voltage channel switch.
[0017] Furthermore, multiple detector units form an array, and the gate ends of each row of detector units are connected to form word lines, and all word lines are connected to a word line driving circuit.
[0018] Furthermore, multiple detector units form an array, and the gate ends of each row of detector units are connected to form a word line, and each word line is connected to a word line driving circuit.
[0019] This invention employs a three-channel voltage selection circuit for output voltage switching, enabling pairwise switching between positive, negative, and zero-potential voltages. This allows for rapid switching of various drive voltages, satisfying the switching needs of device operating modes—something a single-level drive circuit cannot achieve. Furthermore, compared to single-channel word line drive circuits, this invention's multi-channel drive circuit avoids using the same channel to transmit both positive and negative high voltages, reducing the risk of leakage or voltage fluctuations. Simultaneously, this invention utilizes a multi-channel voltage switch to integrate the voltage switch onto the chip, avoiding the influence of pin inductance and capacitance during external switching, resulting in advantages in power consumption, performance, and compatibility. Attached Figure Description
[0020] Figure 1 This is a schematic diagram of the structure of the composite dielectric gate dual transistor photodetector in an embodiment of the present invention;
[0021] Figure 2 This is a block diagram of the word line driving circuit in an embodiment of the present invention;
[0022] Figure 3 This is a circuit diagram of the positive high voltage level conversion in Embodiment 1 of the present invention;
[0023] Figure 4 This is a circuit diagram of the positive voltage level conversion in Embodiment 1 of the present invention;
[0024] Figure 5This is a circuit diagram of the negative voltage level conversion in Embodiment 1 of the present invention;
[0025] Figure 6 This is a circuit diagram of the voltage selection switch in Embodiment 1 of the present invention;
[0026] Figure 7 This is a block diagram of the word line driving circuit used to drive the photodetector array in Embodiment 2 of the present invention. Detailed Implementation
[0027] The structural schematic diagram of the composite dielectric gate dual transistor photodetector used in this embodiment is shown below. Figure 1 As shown. The MOS-C portion of the composite dielectric gate dual-transistor photodetector includes a first dielectric layer, a charge-coupled layer, a second dielectric layer, and a first control gate, stacked sequentially on a P-type semiconductor substrate. The MOSFET portion of the composite dielectric gate dual-transistor photodetector includes a first dielectric layer, a charge-coupled layer, a second dielectric layer, and a second control gate, stacked sequentially on a P-type semiconductor substrate. The dielectric layer, charge-coupled layer, and control gate of the MOS-C portion and the MOSFET portion can be independently configured or shared. An N-type source region S and an N-type drain region D are provided in the P-type semiconductor substrate near the bottom dielectric layer, and a threshold adjustment injection region is provided below the bottom dielectric layer in the P-type semiconductor substrate.
[0028] The composite dielectric gate dual-transistor photodetector is placed in an N-type well. The specific fabrication process is as follows: First, an N-type well is formed on a P-type substrate of a wafer. Then, a P-type semiconductor substrate is formed in the N-type well. Finally, the composite dielectric gate photodetector is fabricated on the P-type semiconductor substrate. The N-type well and the P-type semiconductor substrate within the N-type well are in contact to form a PN junction.
[0029] The gate of the composite dielectric gate dual transistor (CDGD) photodetector corresponds to the second control gate of the MOSFET portion of the CDGD photodetector. The gate of the CDGD photodetector is connected to the word line drive circuit.
[0030] For the aforementioned composite dielectric gate dual transistor photodetector, this embodiment provides a word line driving circuit, including a positive high voltage level conversion circuit, a positive voltage level conversion circuit, a negative voltage level conversion circuit, and a voltage selection switch circuit, such as... Figure 2 As shown.
[0031] The positive-to-high voltage level conversion circuit includes two digital input signals, two analog input signals, and one analog output signal. The two digital input signals are the level conversion control signal EN_RAMP and its inverted signal ENB_RAMP. The two analog input signals are the power supply signals AVDD_1P2 and AVDD_12P0. The analog output signal is a high-level signal VHH, which is time-sequential with the inverted signal ENB_RAMP. In this embodiment, the power supply signal AVDD_1P2 can be 1.2V, the power supply signal AVDD_12P0 can be 12V, and the high-level signal VHH can be 12V.
[0032] The positive voltage level conversion circuit includes two digital input signals, one analog input signal, and one analog output signal. The two digital input signals are the level conversion control signal EN_EXP and its inverted signal ENB_EXP. The analog input signal is the 2.5V power supply signal AVDD_2P5. The analog output signal is the 2.5V level signal EN_EXP25. The 2.5V level signal EN_EXP25 and the level conversion control signal EN_EXP are synchronized in timing.
[0033] The negative voltage level conversion circuit is multiplexed, including negative voltage level conversion circuit 1 and negative voltage level conversion circuit 2. Negative voltage level conversion circuit 1 includes two digital input signals, two analog input signals, and one analog output signal; the two digital input signals are the level conversion control signal EN_RST and its inverted signal ENB_RST; the two analog input signals are the 1.2V power supply signal AVDD_1P2 and the -3V power supply signal AVDD_N3P0; and the one analog output signal is the -3V negative level signal VLL. The negative level signal VLL is synchronized with the level conversion signal EN_RST in timing. The negative voltage level conversion circuit 2 includes two digital input signals, two analog input signals, and one analog output signal. The two digital input signals are shared with the positive voltage level conversion circuit and are the level conversion control signal EN_EXP and its inverted signal ENB_EXP. The two analog input signals are the 1.2V power supply signal AVDD_1P2 and the -3V power supply signal AVDD_N3P0. The one analog output signal is the -3V negative level signal VL. The -3V negative level signal VL and the inverted signal ENB_EXP are synchronized in timing.
[0034] The voltage selection switch circuit includes eight analog input signals and one analog output signal; the eight analog input signals are the first channel voltage HVWLPC1, the second channel voltage HVWLPC2, the third channel voltage HVWLNC1, the 1.2V power supply voltage AVDD_1P2, the 12V high-level signal VHH, the 2.5V level signal EN_EXP25, the -3V negative level signal VLL, and the -3V negative level signal VL; the one analog output signal is the word line driver circuit output signal HVWL.
[0035] Example 1
[0036] In this embodiment, a positive high voltage level conversion circuit is provided, such as... Figure 3 As shown. The control signal EN_RAMP is connected to the input terminal of inverter I2, and the control signal ENB_RAMP is connected to the input terminal of inverter I1. The output terminal of inverter I1 is connected to the source terminal of transistor M1, and the output terminal of inverter I2 is connected to the source terminal of transistor M2. The gate terminals of transistors M1 and M2 are connected to the 1.2V power supply AVDD_1P2. The drain terminal of transistor M1 is connected to the drain terminal of transistor M3, the gate terminal of transistor M5, and the gate terminal of transistor M4. The drain terminal of transistor M2 is connected to the drain terminal of transistor M4, the gate terminal of transistor M3, and the gate terminal of transistor M6. The source terminal of transistor M3 is connected to the drain terminal of transistor M5, and the source terminal of transistor M4 is connected to the drain terminal of transistor M6. The source terminals of transistors M5 and M6 are connected to the 12V power supply AVDD_12P0. The 12V power supply AVDD_12P0 is connected to ground through capacitor C1 to form a decoupling circuit. The output signal VHH is output through the drain terminal of transistor M2.
[0037] In this embodiment, a positive voltage level conversion circuit is provided, such as... Figure 4 As shown. The control signal EN_EXP is connected to the gate of transistor M8, and the control signal ENB_EXP is connected to the gate of transistor M7. The sources of transistor M7 and M8 are grounded. The drain of transistor M7 is connected to the drain of transistor M9 and the gate of transistor M10. The drain of transistor M8 is connected to the gates of transistors M9, M10, M12, and M11. The sources of transistors M9 and M10 are connected to the 2.5V power supply AVDD_2P5. The source of transistor M11 is grounded, and its drain is connected to the drain of transistor M12. The source of transistor M12 is connected to the 2.5V power supply AVDD_2P5. The output signal EN_EXP25 is output through the drain of transistor M11.
[0038] In this embodiment, a negative voltage level conversion circuit 1 is provided, such as... Figure 5As shown. The gray area represents a deep N-well device. The control signal EN_RST is connected to the gate of transistor M22, and the control signal ENB_RST is connected to the gate of transistor M21. The sources of transistors M21 and M22 are connected to a 1.2V power supply AVDD_1P2. The drain of transistor M21 is connected to the source of transistor M19, and the drain of transistor M22 is connected to the source of transistor M20. The gates of transistors M19, M20, M17, and M18 are connected to ground through resistor R1. The drain of transistor M19 is connected to the drain of transistor M17, and the drain of transistor M20 is connected to the source of transistor M18. The drain of transistor M18 is connected to the gate of transistor M13, the drain of transistor M15, and the gate of transistor M16. The source of transistor M18 is connected to the gate of transistor M14, the drain of transistor M16, and the gate of transistor M15. The source of transistor M15 is connected to the drain of transistor M13, and the source of transistor M16 is connected to the drain of transistor M14. The sources of transistors M13 and M14 are connected to the -3V power supply AVDD_N3P0, which is connected to ground through capacitor C2 to form a decoupling circuit. The output signal VLL is output through the drain of transistor M15. For the negative voltage level conversion circuit 2, the structure is the same as the above circuit, except that the output is at the drain of the corresponding transistor of transistor M18.
[0039] In this embodiment, a voltage selective switch circuit is provided, such as... Figure 6 As shown. The gray area represents a deep N-well device. The third channel voltage HVWLNC1 is connected to the drain of transistor M33, and the drain of transistor M33 is connected to the source of transistor M34. The control signal VLL is connected to the gate of transistor M33 through resistor R3. The drain of transistor M34 is connected to the drains of transistors M36 and M38, and the gate of transistor M34 is connected to ground through resistor R4. The first channel voltage HVWLPC1 is connected to the source of transistor M35, and the drain of transistor M35 is connected to the source of transistor M36. The control signal E... N_EXP25 is connected to the gate of transistor M35 through resistor R5; the control signal VL is connected to the gate of transistor M36 through resistor R6; the second channel voltage HVWLPC2 is connected to the source of transistor M37, the drain of transistor M37 is connected to the source of transistor M38, the control signal VHH is connected to the gate of transistor M37 through resistor R7; the gate of transistor M38 is connected to ground through resistor R8; the output signal HVWL is output from the drain of transistor M38, the drain of transistor M36, and the drain of transistor M34.
[0040] The first channel voltage HVWLPC1 is 0~1.5V, the second channel voltage HVWLPC2 is a 1-5V ramp voltage or 1~10V, and the third channel voltage HVWLNC1 is -2~-4V. When HVWL<2:0> is 3'b001, the first channel voltage is turned on, and HVWL outputs HVWLPC1. When HVWL<2:0> is 3'b010, the second channel voltage is turned on, and HVWL outputs HVWLPC2. When HVWL<2:0> is 3'b100, the third channel voltage is turned on, and HVWL outputs HVWLNC1.
[0041] Example 2
[0042] In this embodiment, the word line driving circuit described above is used to drive a composite dielectric gate dual transistor photodetector array, such as... Figure 7 As shown, the photodetector array consists of two columns and two rows. The gate terminals of the composite dielectric gate dual transistor photodetectors in each row are connected to form word lines. The outputs HVWL#1 and HVWL#2 of the word line drive circuits #1 and #2 are respectively connected to the word lines of the corresponding rows of composite dielectric gate dual transistor photodetector arrays, providing them with drive voltages.
Claims
1. A word line driving circuit based on a composite dielectric gate dual-transistor photodetector, wherein the detector unit comprises a MOS-C section and a MOSFET section having a composite dielectric gate structure, characterized in that, The control gate port of the MOSFET section is connected to the word line driving circuit. The word line driving circuit includes a positive high voltage level conversion circuit, a positive voltage level conversion circuit, a negative voltage level conversion circuit, and a voltage selection switch circuit. The positive high voltage level conversion circuit, the positive voltage level conversion circuit, and the negative voltage level conversion circuit are used to drive the switches of the three voltage channels, respectively. The output terminals of the three circuits are connected to the input terminal of the voltage selection switch circuit, and the output terminal of the voltage selection switch circuit is connected to the control gate port of the MOSFET section. The voltage selection switch circuit includes eight analog input signals and one analog output signal; wherein the eight analog input signals are the first channel voltage HVWLPC1, the second channel voltage HVWLPC2, the third channel voltage HVWLNC1, the power supply voltage AVDD_1P2, the high-level signal VHH, the level signal EN_EXP25, the first negative level signal VLL, and the second negative level signal VL; and the one analog output signal is the word line driver circuit output signal HVWL; the level signal EN_EXP25 and the second negative level signal VL control the first voltage channel switch, the high-level signal VHH controls the second voltage channel switch, and the first negative level signal VLL controls the third voltage channel switch.
2. The word line driving circuit based on a composite dielectric gate dual-transistor photodetector according to claim 1, characterized in that, The positive-to-high voltage level conversion circuit includes two digital input signals, two analog input signals, and one analog output signal. The two digital input signals are the level conversion control signal EN_RAMP and its inverted signal ENB_RAMP. The two analog input signals are the first power supply signal AVDD_1P2 and the second power supply signal AVDD_12P0. The one analog output signal is a high-level signal VHH. The high-level signal VHH and the inverted signal ENB_RAMP are synchronized in timing.
3. The word line driving circuit based on a composite dielectric gate dual-transistor photodetector according to claim 2, characterized in that, The second power signal AVDD_12P0 is connected to ground through a capacitor to form a decoupling circuit.
4. The word line driving circuit based on a composite dielectric gate dual-transistor photodetector according to claim 1, characterized in that, The positive voltage level conversion circuit includes two digital input signals, one analog input signal, and one analog output signal; the two digital input signals are the level conversion control signal EN_EXP and its inverted signal ENB_EXP, the one analog input signal is the third power supply signal AVDD_2P5, and the one analog output signal is the positive level signal EN_EXP25. The positive level signal EN_EXP25 and the level conversion control signal EN_EXP are synchronized in timing.
5. The word line driving circuit based on a composite dielectric gate dual-transistor photodetector according to claim 1, characterized in that, The negative voltage level conversion circuit is multiplexed, including a first negative voltage conversion circuit and a second negative voltage conversion circuit; The first negative voltage conversion circuit includes two digital input signals, two analog input signals, and one analog output signal; wherein the two digital input signals are the level conversion control signal EN_RST and its inverted signal ENB_RST, the two analog input signals are the first power supply signal AVDD_1P2 and the fourth power supply signal AVDD_N3P0, and the one analog output signal is the first negative level signal VLL, and the first negative level signal VLL is in the same timing as the level conversion signal EN_RST; The second negative voltage conversion circuit includes two digital input signals, two analog input signals, and one analog output signal. The two digital input signals are shared with the positive voltage level conversion circuit and are the level conversion control signal EN_EXP and its inverted signal ENB_EXP. The two analog input signals are the first power supply signal AVDD_1P2 and the fourth power supply signal AVDD_N3P0. The one analog output signal is the second negative level signal VL, and the second negative level signal VL and the inverted signal ENB_EXP are synchronized in timing.
6. The word line driving circuit based on a composite dielectric gate dual-transistor photodetector according to claim 5, characterized in that, The fourth power supply signal AVDD_N3P0 is connected to ground via a capacitor to form a decoupling circuit.
7. The word line driving circuit based on a composite dielectric gate dual-transistor photodetector according to any one of claims 1-6, characterized in that, Multiple detector units form an array, and the gate terminals of each row of detector units are connected to form word lines. All word lines are connected to a word line driving circuit.
8. The word line driving circuit based on a composite dielectric gate dual transistor photodetector according to any one of claims 1-6, characterized in that, An array of multiple detector units is formed, and the gate terminals of each row of detector units are connected to form a word line. Each word line is connected to a word line driving circuit.