Image sensor pixel with stable reset of a lateral overflow integrating capacitor

Abstract

This application relates to a high-dynamic-range CMOS image sensor pixel having reduced metal-insulator-metal lateral overflow integration capacitor reset settling. A pixel circuit includes a transfer transistor coupled between a photodiode and a floating diffusion. A lateral overflow integration capacitor (LOFIC) includes an insulating region disposed between a first metal electrode coupled to a bias voltage source and a second metal electrode selectively coupled to the floating diffusion. A multifunctional reset transistor includes a gate, a drain, a first source, and a second source. The drain, the first source, and the second source are coupled to each other in response to turning on the multifunctional reset transistor by a multifunctional reset control signal. The drain, the first source, and the second source are decoupled from each other in response to turning off the multifunctional reset transistor by the multifunctional reset control signal. The drain is coupled to a reset voltage source, the first source is coupled to the first metal electrode, and the second source is coupled to the second metal electrode.

Description

Technical Field

[0001] The present disclosure generally relates to image sensors, and more particularly but not exclusively to high dynamic range (HDR) complementary metal oxide semiconductor (CMOS) image sensors. Background Art

[0002] Image sensors have become ubiquitous and are now widely used in digital cameras, cellular phones, security cameras, and in medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, it is desirable to enhance the functionality, performance metrics, and the like (e.g., resolution, power consumption, dynamic range, etc.) of the image sensors in as many ways as possible, both through device architecture design and image acquisition processing. The technology for manufacturing image sensors has continued to progress rapidly. For example, the demand for higher resolution and lower power consumption has driven further miniaturization and integration of these devices.

[0003] A typical complementary metal oxide semiconductor (CMOS) image sensor operates in response to incident image light from an external scene onto the image sensor. The image sensor includes a pixel array having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and photogenerate image charge immediately after absorbing the image light. The image charge photogenerated by the pixels can be measured as an analog output image signal that varies with the incident image light on the column bit lines. In other words, the amount of the photogenerated image charge is proportional to the intensity of the image light, which is read out as an analog signal from the column bit lines and converted into a digital value to produce a digital image (i.e., image data) representing the external scene.

[0004] Standard image sensors have a limited dynamic range of approximately 60 dB to 70 dB. However, the luminance dynamic range of the real world is much larger. For example, natural scenes typically span a range of 90 dB and above. To capture details in both bright highlights and dark shadows simultaneously, high dynamic range (HDR) techniques have been used in image sensors to increase the captured dynamic range. A common technique for increasing the dynamic range is to merge multiple exposures captured using a standard (low dynamic range) image sensor at different exposure settings into a single linear HDR image, resulting in an image with a much larger dynamic range than a single exposure image. Summary of the Invention

[0005] In one aspect, the present application relates to a pixel circuit, comprising: a photodiode configured to photogenerate image charges in response to incident light; a floating diffusion section coupled to receive the image charges from the photodiode; a transfer transistor coupled between the photodiode and the floating diffusion section, wherein the transfer transistor is configured to transfer the image charges from the photodiode to the floating diffusion section; a lateral overflow integrating capacitor (LOFIC) comprising an insulating region disposed between a first metal electrode and a second metal electrode, wherein the first metal electrode is coupled to a bias voltage source, wherein the second metal electrode is selectively coupled to the floating diffusion section; and a multi-functional reset transistor having a gate, a drain, a first source, and a second source, wherein the gate is coupled to a multi-functional reset control signal, wherein the drain, the first source, and the second source are coupled to each other in response to turning on the multi-functional reset transistor by the multi-functional reset control signal, wherein the drain, the first source, and the second source are decoupled from each other in response to turning off the multi-functional reset transistor by the multi-functional reset control signal, wherein the drain is coupled to a reset voltage source, wherein the first source is coupled to the first metal electrode, and wherein the second source is coupled to the second metal electrode.

[0006] In another aspect, the present application relates to an imaging system comprising: a pixel array including a plurality of pixel circuits arranged in a plurality of rows and a plurality of columns, wherein each of the pixel circuits includes: a photodiode configured to photogenerate image charge in response to incident light; a floating diffusion coupled to receive the image charge from the photodiode; a transfer transistor coupled between the photodiode and the floating diffusion, wherein the transfer transistor is configured to transfer the image charge from the photodiode to the floating diffusion; a lateral overflow integrating capacitor (LOFIC) including an insulating region disposed between a first metal electrode and a second metal electrode, wherein the second metal electrode is selectively coupled to the floating diffusion; and a multi-functional reset transistor having a gate, a drain, a first source, and a second source, wherein the gate is coupled to a multi-functional reset control signal, wherein the drain, the first source, and the second source are coupled to each other in response to turning on the multi-functional reset transistor by the multi-functional reset control signal, wherein the drain, the first source, and the second source are decoupled from each other in response to turning off the multi-functional reset transistor by the multi-functional reset control signal, wherein the drain is coupled to a reset voltage source, wherein the first source is coupled to the first metal electrode, wherein the second source is coupled to the second metal electrode; a bias voltage source coupled to the first metal electrode; control circuitry coupled to the pixel array to control the operation of the pixel array; and readout circuitry coupled to the pixel array to read out image data from a plurality of pixel units. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like components throughout the various views unless otherwise specified.

[0008] Figure 1 FIG. illustrates an example of an imaging system including a pixel array in accordance with the teachings of the present invention.

[0009] Figure 2 FIG. illustrates a schematic diagram of an example of a pixel circuit including a lateral overflow integrating capacitor (LOFIC) coupled to a multi-functional reset transistor to be reset in accordance with the teachings of the present disclosure.

[0010] Figure 3 FIG. illustrates a diagram of an example of a buffer of a bias voltage source showing an example LOFIC and an example multi-functional reset transistor coupled to a pixel circuit in accordance with the teachings of the present disclosure.

[0011] Figure 4An example timing diagram illustrating example signal values during idle, pre-charge, integration, and readout cycles in an example pixel circuit including an example LOFIC coupled to an example multi-functional reset transistor in accordance with the teachings of the present disclosure.

[0012] Throughout several views of the drawings, corresponding reference characters indicate corresponding components. Those skilled in the art will appreciate that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, to help improve understanding of the various embodiments of the present invention, the dimensions of some of the elements in the figures may be enlarged relative to other elements. Additionally, commonly known elements that are useful or necessary in a commercially viable embodiment are often not depicted to facilitate an unobstructed view of these various embodiments of the present invention. Detailed Description

[0013] Examples are described herein for an imaging system having a pixel array that includes pixel circuits having a LOFIC that provides reduced image lag. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the examples. However, those skilled in the relevant art will recognize that the techniques described herein may be practiced without one or more of the specific details or may be practiced using other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

[0014] References to "an example" or "an embodiment" in the specification throughout mean that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present invention. Thus, the appearances of the phrases "in an example" or "in an embodiment" throughout the specification are not necessarily all referring to the same example. Additionally, the particular features, structures, or characteristics may be combined in any suitable manner in one or more examples.

[0015] For ease of explanation in this document, spatial relative terms (such as "beneath", "below", "above", "under", "on top", "upper", "top", "bottom", "left", "right", "center", "middle", and the like) may be used to describe the relationship of one element or feature to another (other) element or feature, as illustrated in the various figures. It should be understood that, in addition to the orientation depicted in the figures, spatial relative terms are also intended to encompass different orientations of the device during use or operation. For example, if the device in the figures is rotated or flipped, an element described as "beneath" or "below" or "under" another element or feature will then be oriented "above" the other element or feature. Thus, the exemplary terms "below" and "under" can encompass both an above and a below orientation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptors used herein can be interpreted accordingly. Additionally, it should be understood that when an element is referred to as being "between" two other elements, it can be the only element between the two other elements, or there can also be one or more intervening elements.

[0016] Throughout this specification, several technical terms are used. These terms will assume their ordinary meaning in the art to which they pertain, unless specifically defined otherwise herein or the context in which they are used clearly implies otherwise. It should be noted that in this document, element names and symbols may be used interchangeably (e.g., Si and silicon); however, both have the same meaning.

[0017] As will be discussed, the disclosure includes various examples of imaging systems having a pixel array with pixel circuits that include a lateral overflow integration capacitor (LOFIC) configured to provide reduced image lag. It should be understood that the LOFIC can be included in the pixel circuit to increase the full well capacity of the pixel circuit and thereby increase the high dynamic range capability of the corresponding image sensor. The LOFIC capacitance is positively correlated with the full well capacity. Thus, as the capacitance of the LOFIC employed in the pixel circuit increases, the full well capacity of the pixel circuit also increases. For this reason, a higher LOFIC capacitance is generally desirable. However, due to the significant RC load associated with increasing the capacitance of the LOFIC, the time required for the row driver of the imaging system to charge and / or reset the LOFIC also increases. Thus, as the capacitance of the LOFIC in the pixel circuit increases, image lag increases, which results in a slower frame rate.

[0018] It should be understood that the image lag caused by the LOFIC can be associated with high dielectric constant or high-k materials contained in the insulating material of a metal-insulator-metal (MIM) LOFIC, due to the hysteresis characteristics and slow relaxation behavior of the high-k materials. The relaxation behavior of the high-k materials can lead to degraded image quality (such as image lag), which is attributed to many mechanisms including trap-to-trap tunneling, structural relaxation, and phonon energy coupling.

[0019] It should be understood that, in accordance with the teachings of the present invention, at a fixed readout speed and a frame readout speed of an image sensor, a pixel circuit including a LOFIC can be reset during an idle period and during a precharge period and a reset level signal readout operation to reduce image lag. Thus, as will be shown in various examples below, an example pixel circuit includes a photodiode configured to generate image charges in response to incident light. A floating diffusion is coupled to receive the image charges from the photodiode. A transfer transistor is coupled between the photodiode and the floating diffusion and is configured to transfer the image charges from the photodiode to the floating diffusion. A lateral overflow integrating capacitor (LOFIC) including an insulating region is disposed between a first metal electrode and a second metal electrode. The first metal electrode is coupled to a bias voltage source and the second metal electrode is selectively coupled to the floating diffusion, thereby allowing excess photo-generated charges (e.g., generated under strong light conditions) to overflow from the photodiode to the lateral overflow integrating capacitor. The pixel circuit further includes a multi-functional reset transistor including a gate, a drain, a first source, and a second source. The gate of the multi-functional reset transistor is coupled to receive a multi-functional reset control signal. The drain, the first source, and the second source of the multi-functional reset transistor are coupled to each other in response to turning on the multi-functional reset transistor by the multi-functional reset control signal, while the drain, the first source, and the second source are decoupled from each other in response to turning off the multi-functional reset transistor by the multi-functional reset control signal. In various examples, the drain is coupled to a reset voltage source, the first source is coupled to the first metal electrode, and the second source is coupled to the second metal electrode.

[0020] Thus, in accordance with the teachings of the present invention, during operation, the multi-functional reset transistor included in the pixel circuit is configured to internally couple the photodiode, the floating diffusion, and the first and second metal electrodes to the reset voltage source within the pixel circuit through the multi-functional reset transistor during a precharge period and during a reset level signal readout operation of the pixel circuit. It should be understood that since the LOFIC is locally reset within the pixel circuit through the multi-functional reset transistor rather than through a row driver of an imaging system, image lag is reduced because there is no longer a large RC load on the row driver of the imaging system when resetting the LOFIC in the imaging system.

[0021] For illustration, Figure 1 FIG. 100 shows an example of an imaging system 100 having a pixel array in accordance with the teachings of the present invention, the pixel array having pixel circuits including LOFICs configured to provide reduced image lag. Specifically, Figure 1The example depicted in FIG. illustrates an imaging system 100 that includes a pixel array 102, bit lines 112, control circuitry 110, a readout circuit 106, and functional logic 108. In one example, the pixel array 102 is a two-dimensional (2D) array that includes a plurality of pixel circuits 104 (e.g., P1, P2, …, Pn), which are arranged in a number of rows (e.g., R1 to Ry) and a number of columns (e.g., C1 to Cx) to acquire image data of a person, place, object, etc., and the image data can then be used to reproduce an image of the person, place, object, etc.

[0022] In various examples, each pixel circuit 104 can include one or more photodiodes configured to photogenerate image charge in response to incident light. The image charge generated in the one or more photodiodes is transferred to a floating diffusion included in each pixel circuit 104 and can be converted into an image signal, which is then read out by the readout circuit 106 from each pixel circuit 104 through the column bit lines 112. As will be discussed, in various examples, the pixel circuit 104 is also configured to provide an HDR image signal, in which case the image charge generated by the one or more photodiodes under bright illumination conditions can also overflow into a corresponding LOFIC and / or additional floating diffusion in each pixel circuit 104 to store the image charge. As will be discussed, in various examples, in accordance with the teachings of the present invention, each pixel circuit 104 also includes a multi-functional reset transistor to locally reset the LOFIC as well as the photodiodes and floating diffusions to achieve reduced image lag. In various examples, the readout circuit 106 can be configured to read out the image signal through the column bit lines 112. In various examples, the readout circuit 106 can include a current source, wiring circuitry, and a comparator or others that can be included in an analog-to-digital converter.

[0023] In the example, the digital image data value generated by the analog-to-digital converter in the readout circuit 106 can then be received by the functional logic 108. The functional logic 108 can either only store the digital image data or even manipulate the digital image data by applying post-image effects (e.g., cropping, rotation, red-eye removal, brightness adjustment, contrast adjustment, or others).

[0024] In one example, the control circuitry 110 is coupled to the pixel array 102 to control the operation of the plurality of photodiodes in the pixel array 102. For example, the control circuitry 110 can generate a rolling shutter or shutter signal for controlling image acquisition. In other examples, the image acquisition is synchronized with an illumination effect such as a flash.

[0025] In one example, the imaging system 100 is implemented on a single semiconductor wafer. In another example, the imaging system 100 is located on a stacked semiconductor wafer. For example, the pixel array 102 is implemented on a pixel wafer, and the readout circuit 106, the control circuit 110, and the functional logic are implemented on an application specific integrated circuit (ASIC) wafer, where the pixel wafer and the ASIC wafer are interconnected by bonding (hybrid bonding, oxide bonding, or the like) or one or more through-substrate vias (TSVs). As another example, the pixel array 102 and the control circuit 110 are implemented on a pixel wafer, and the readout circuit 106 and the functional logic 108 are implemented on an ASIC wafer, where the pixel wafer and the ASIC wafer are stacked and interconnected by bonding (hybrid bonding, oxide bonding, or the like) or one or more TSVs.

[0026] In one example, the imaging system 100 can be included in a digital camera, a mobile phone, a laptop computer, an endoscope, a security camera, an automotive camera, or the like. Additionally, the imaging system 100 can be coupled to other hardware such as a processor (general or otherwise), memory elements, outputs (USB port, wireless transmitter, HDMI port, etc.), lighting devices / flashlights, electrical inputs (keyboard, touch display, track pad, mouse, microphone, etc.), and / or a display. The other hardware can deliver instructions to the imaging system 100, extract image data from the imaging system 100, or manipulate the image data supplied by the imaging system 100.

[0027] Figure 2 A schematic diagram illustrating an example of a pixel circuit 204 including a lateral overflow integrating capacitor (LOFIC) coupled to a multi-functional reset transistor to be reset. It should be understood that Figure 2 the pixel circuit 204 can be an example of one of the pixel circuits 104 included in the pixel array 102 as shown in Figure 1 and the similarly named and numbered elements described above are coupled and operate in a similar manner hereinafter.

[0028] As shown in the depicted example, the pixel circuit 204 includes a photodiode 214 configured to photogenerate image charge in response to incident light. In the depicted example, the pixel circuit 204 further includes a first floating diffusion FD1 218, which is coupled to receive image charge from the photodiode 214 via a transfer transistor 216, for example, during a readout period associated with the pixel circuit 204. In the example, the transfer transistor 216 is coupled to be controlled in response to a transfer control signal TX 236 to transfer the image charge from the photodiode 214 to the first floating diffusion FD1 218. In Figure 2In the example depicted, it should be noted that the pixel circuit 204 is configured such that during the exposure or integration period of the pixel circuit 204, excess image charge photo-generated in the photodiode 214 in response to bright illumination conditions is configured to overflow from the photodiode 214 through the transfer transistor 216 to the first floating diffusion FD1 218 to reach the lateral overflow integrating capacitor (LOFIC) 232 through the low conversion gain transistor 230, as shown. The LOFIC 232 may have a capacitance higher than that of the first floating diffusion FD1 218 and the second capacitor 228. In one example, the capacitance (or charge storage capacity) of the first floating diffusion FD1 218 is configured to be the same as the capacitance (or charge storage capacity) of the second capacitor 228. In another example, the capacitance of the first floating diffusion FD1 218 is configured to be less than the capacitance of the second capacitor 228. The charge storage capacity of the LOFIC 232 may be greater than the charge storage capacity of the photodiode 214. The source follower transistor SF 220 has a gate coupled to the first floating diffusion FD1 218, and the row select transistor 222 is coupled to the source follower transistor SF 220 such that the source follower transistor SF 220 and the row select transistor 222 are coupled between the voltage supply and the bit line 212 to output an image signal from the pixel circuit 204 in response to the row select control signal RS246 and the amount of charge at the gate of the source follower transistor SF 220.

[0029] In Figure 2 In the example illustrated, the dual floating diffusion transistor 224 is coupled between the first floating diffusion FD1 218 and the second capacitor 228 (e.g., an additional floating diffusion). The second capacitor 228 is coupled to receive the floating diffusion capacitor signal FDC 240. In various examples, the floating diffusion capacitor signal FDC 240 is independent of the row driver signal VCAP and may range from 0 to 3V. The dual floating diffusion transistor 224 is configured to be controlled in response to the dual floating diffusion DFD control signal 238. The low conversion gain transistor 230 is coupled between the first floating diffusion FD1 218 and the second metal electrode of the lateral overflow integrating capacitor (LOFIC) 232. The low conversion gain transistor 230 is configured to be controlled in response to the low conversion gain control signal LCG 242. As Figure 2 shown in the example depicted, the first metal electrode of the LOFIC 232 is coupled to the bias voltage source 248.

[0030] In the described example, the LOFIC 232 is implemented using a metal-insulator-metal capacitor that includes a high dielectric or high-k insulating material disposed between a first metal electrode and a second metal electrode. In various examples, depending on the desired LOFIC capacitance, the insulating material disposed between the first and second metal electrodes of the LOFIC 232 can be a single high-k material layer or a multi-layer stack. In various examples, the high-k material can include one of aluminum oxide (Al2O3), zirconium dioxide (ZrO2), hafnium oxide (HfO), or a combination thereof. In one example, it should be understood that the first metal electrode of the LOFIC 232 can be referred to as the capacitor top metal (CTM) and the second metal electrode of the LOFIC 232 can be referred to as the capacitor bottom metal (CBM).

[0031] In the depicted example, the bias voltage source 248 is configured to provide a bias voltage VCAP. In various examples, the bias voltage source 248 is a row driver of the imaging system and includes a buffer 249. In one example, the buffer 249 can be configured to provide a high impedance state (e.g., HiZ) and a low capacitor voltage (e.g., VCAPLO) or a high capacitor voltage (e.g., VCAPHI) from the bias voltage source 248 in response to a control signal. For example, in Figure 2 the example depicted in, it should be noted that, for explanatory purposes, the buffer 249 of the bias voltage source 248 is thus illustrated as a switch that can be opened or turned off to provide a high impedance state from the bias voltage source 248 and closed or turned on to provide the bias voltage VCAP, such as VCAPLO or VCAPHI. In various examples, VCAPLO can be from 0 to 2.0 V and VCAPHI can be from 2.0 V to 3.4 V. It should be understood that, in various examples, the VCAPLO and VCAPHI bias voltage levels can be determined considering the stable range of the high-k material.

[0032] Figure 2 The example illustrated in also shows that the example pixel circuit 204 includes a multi-functional reset transistor 234 according to the teachings of the present invention. As shown in the depicted example, the multi-functional reset transistor 234 includes a gate 264, a drain 262, a first source 258, and a second source 260. For explanatory purposes, it should be noted that the multi-functional reset transistor 234 is illustrated as two transistors sharing the drain 262 and the gate 264, and one of the transistors includes the first source 258 and the other transistor includes the second source 260. As will be shown, it should be understood that instead of using two separate transistors as depicted in Figure 2 for explanatory purposes, the multi-functional reset transistor 234 can be implemented by adding one more junction to a single transistor, which thus reduces the size required to implement the multi-functional reset transistor 234 compared to two separate transistors according to the teachings of the preset invention.

[0033] As shown in the depicted example, the gate 264 of the multi-functional reset transistor 234 is coupled to receive the multi-functional reset MRSTG control signal 244, the drain 262 is coupled to a reset voltage source to receive a reset voltage, such as the voltage PIXVDD, the first source 258 is coupled to the first metal electrode (e.g., CTM) of the LOFIC 232, and the second source 260 is coupled to the second metal electrode (e.g., CBM) of the LOFIC 232. In various examples, the PIXVDD voltage can range from 1.2V to 3.6V. The second source 260 is also coupled to the first floating diffusion region FD1 218 through the low conversion gain transistor 230. In operation, the drain 262, the first source 258, and the second source 260 of the multi-functional reset transistor 234 are all coupled to each other in response to turning on the multi-functional reset transistor 234 by the multi-functional reset MRSTG control signal 244. The drain 262, the first source 258, and the second source 260 of the multi-functional reset transistor 234 are all decoupled from each other in response to turning off the multi-functional reset transistor 234 by the multi-functional reset MRSTG control signal 244.

[0034] Thus, in accordance with the teachings of the present invention, the multi-functional reset transistor 234 can be turned on during the pre-charge cycle and the reset level signal readout operation to locally reset the reset LOFIC 232 within the pixel circuit 204 by shorting the first metal electrode (e.g., CTM) and the second metal electrode (e.g., CBM) of the LOFIC 232 to the reset voltage supply, which reduces image lag in the pixel circuit 204. It should be understood that, in accordance with the teachings of the present invention, the photodiode 214, the first floating diffusion section FD1 218, and the second capacitor 228 can also be reset simultaneously through the multi-functional reset transistor 234 during these cycles.

[0035] Figure 3 A diagram illustrating a schematic of an example buffer 349 of a bias voltage source coupled to an example LOFIC and an example multi-functional reset transistor 334 coupled to a pixel circuit in accordance with the teachings of the present disclosure. It should be understood that Figure 3 the example buffer 349 and the example multi-functional reset transistor 334 can be examples of the buffer 249 and the multi-functional reset transistor 234 of the pixel circuit as shown in Figure 2 and the similarly named and numbered elements described above are coupled and operate in a similar manner hereinafter.

[0036] As Figure 3As shown in the example depicted, the buffer 349 of the bias voltage source is configured to provide a high impedance state, a high voltage value, or a low voltage value at the output 382 of the buffer 349. In one example, the output 382 of the buffer 349 is configured to provide the output VCAP 348 of the bias voltage source. In one example, the buffer 349 includes a first transistor 370, a second transistor 372, a third transistor 374, and a fourth transistor 376 serially coupled between VCAPHI (e.g., a higher bias voltage) and VCAPLO (e.g., a lower bias voltage), as shown. In this example, the gate of the second transistor 372 is coupled to receive the active low high impedance enable signal HiZ’380, and the gate of the first transistor 370 is coupled to receive the active low high impedance enable signal HiZ’380 through an inverter 378. In this example, the gates of the third transistor 374 and the fourth transistor 376 are coupled to receive the active low input signal IN’381. The operation of the buffer 359 can be controlled by a control circuit (e.g., Figure 1 the control circuit 110) of an imaging system that includes the pixel circuit. In one example, the control circuit provides the active low high impedance enable signal HiZ’380 and the active low input signal IN’381 to the buffer 349 of the bias voltage source.

[0037] Thus, during operation, when the active low high impedance enable signal HiZ’380 is set to enable the high impedance state of the buffer 349, the active low high impedance enable signal HiZ’380 is at a low value, which turns off the first transistor 370 and the second transistor 372, causing the output 382 to be in a high impedance (e.g., HiZ) state.

[0038] When the active low high impedance enable signal HiZ’380 is set to disable the high impedance state of the buffer 349, the output 382 of the buffer 349 is a high voltage value or a low voltage value provided by the bias voltage source (e.g., the capacitor bias voltage VCAPHI or VCAPLO). Thus, the active low high impedance enable signal HiZ’380 is at a high voltage value, which turns on the first transistor 370 and the second transistor 372. When the active low input signal IN’381 is at a low voltage value, the third transistor 374 turns on and the fourth transistor 376 turns off, which provides a high voltage value (e.g., the capacitor bias voltage VCAPHI) as the voltage VCAP 348 at the output 382. When the active low input signal IN’381 is high, the third transistor 374 turns off and the fourth transistor 376 turns on, which provides a low voltage value (e.g., the capacitor bias voltage VCAPLO) as the bias voltage VCAP348 at the output 382.

[0039] Continue Figure 3In the example depicted, LOFIC 332 is illustrated as including a first metal electrode (e.g., CTM) and a second metal electrode (e.g., CBM). In the example, a high dielectric or high-k insulating material is disposed between the first and second metal electrodes of LOFIC 332.

[0040] Figure 3 The example illustrated also shows an example of a multifunctional reset transistor 334 in accordance with the teachings of the present invention. As shown in the depicted example, the multifunctional reset transistor 334 is disposed in a semiconductor material 366, which may be, for example, a silicon substrate, a silicon-germanium alloy, germanium, a silicon carbide alloy, an indium gallium arsenide alloy, any other alloy formed from III-V compounds, other suitable semiconductor materials or alloys, combinations thereof, bulk substrates thereof, or wafers thereof. A drain 362, a first source 358, and a second source 360 are disposed in the semiconductor material 366, as shown. In the example, the drain 362, the first source 358, and the second source 360 are depicted as N+ doped regions (e.g., arsenic or phosphorus doped regions). In various examples, the multifunctional reset transistor 334 and the low conversion gain transistor 230 may be arranged adjacent to each other in a region between adjacent photodiodes to achieve pixel scaling benefits. The drain 362, the first source 358, and the second source 360 may be disposed (e.g., via implantation) in a P-type doped well region (not illustrated) in the semiconductor material 366. In various examples, the multifunctional reset transistor 334, the low conversion gain transistor 230, and the source follower transistor 220 may be formed within a P-type doped well region coupled to ground. It should of course be understood that in other examples, in accordance with the teachings of the present invention, other materials and other dopant polarities may be utilized through corresponding updates to the logic of the circuitry coupled to the multifunctional reset transistor 334. As Figure 3 shown in the example depicted, the drain 362 is coupled to a reset voltage source to receive a reset voltage (e.g., voltage PIXVDD), the first source 358 is coupled to the first metal electrode of LOFIC 332 (e.g., CTM), which is also coupled to the output 382 of buffer 349 to receive voltage VCAP 348, and the second source 360 is coupled to the second metal electrode of LOFIC 332 (e.g., CBM). Figure 3

[0041] Continuing the example, a gate 364 is disposed over the semiconductor material 366 (as Figure 3 shown), thereby selectively coupling the drain 362, the first source 358, and the second source 360. In various examples, it should be understood that a thin gate oxide layer (e.g., having a thickness between from to ​a gate oxide thickness within the range of) or the like (not shown) disposed between the gate 364 and the semiconductor material 366. The gate 364 of the multifunctional reset transistor 334 is coupled to receive a multifunctional reset control signal MRSTG 344 (e.g., from Figure 1 the control circuit 110). In operation, when the multifunctional reset control signal MRSTG 344 turns on the multifunctional reset transistor 334, an inversion channel 368 is formed in the semiconductor material 366 under the gate 364 and between the drain 362, the first source 358, and the second source 360. Thus, when the multifunctional reset transistor 334 is turned on, the drain 362, the first source 358, and the second source 360 are all coupled to each other. Therefore, when the multifunctional reset transistor 334 is turned on, the reset voltage source is coupled to the first metal electrode (e.g., CTM) and the first metal electrode (e.g., CTM) and the second metal electrode (e.g., CBM) of the LOFIC 332 are biased with the reset voltage PIXVDD, which resets or auto-zeros the LOFIC 332.

[0042] It should also be understood that, in accordance with the teachings of the present invention, when the LOFIC 332 is reset or auto-zeroed by the multifunctional reset transistor 334 as described, the buffer 349 is configured to be in a high impedance state. Therefore, it should be further understood that when the LOFIC 332 is reset or auto-zeroed, the LOFIC 332 is not driven by the row driver or the bias voltage source. Instead, the LOFIC 332 is reset as described by the multifunctional reset transistor 334 driven by the reset voltage source, and there is no RC load problem for the row driver because the buffer 349 of the bias voltage source operates in a high impedance state and the LOFIC 232 is short-circuited and acts as a common metal wire. Thus, in accordance with the teachings of the present invention, the LOFIC 332 is locally reset or auto-zeroed pixel by pixel quickly using the multifunctional reset transistor 334 included in each pixel circuit, thereby reducing the row driver load and there is no power short circuit problem between the bias voltage source and the reset voltage source.

[0043] It should be further understood that the multifunctional reset transistor 334 can be disposed in the transistor region between the photodiodes (e.g., photodiode 214) and the adjacent photodiodes, and the multifunctional reset transistor 334 can be isolated from the photodiodes by a shallow isolation trench structure, an isolation implant region, and / or a combination thereof. For example, a shallow isolation trench structure having an isolation depth greater than the junction depth of the drain 362, the first source 358, and the second source 360 of the multifunctional reset transistor 334 is disposed between the drain 362, the first source 358, and the second source 360 and the photodiodes (e.g., photodiode 214 and the adjacent photodiodes) to provide electrical isolation.

[0044] Figure 4 An example timing diagram illustrating example signal values during idle, precharge, integration, and readout cycles in an example pixel circuit including an example LOFIC coupled to an example multifunctional reset transistor in accordance with the teachings of the present disclosure. It should be understood that Figure 4 the signals depicted in Figures 2 to 3 may be examples of the signals depicted in

[0045] Referring now to the depicted example, Figure 4 illustrates a multifunctional reset control signal MRSTG444, a bias voltage VCAP line 448, a dual floating diffusion control signal DFD 438, a low conversion gain control signal LCG 442, a transfer control signal TX 436, a floating diffusion capacitor signal FDC 440, and a row select control signal RS 446 that are configured to control the respective circuit elements discussed in detail above in Figures 2 to 3 and that may be provided by a control circuit coupled to the example pixel circuit. Figure 4 The example depicted in

[0046] also illustrates, as in Figure 4As shown during the idle period depicted in, most signals are configured to have a low voltage value. The transfer control signal TX 436 is configured to be at an intermediate voltage level (e.g., zero voltage) to allow some photo-generated image charge to overflow from the photodiode to the first floating diffusion FD1. Next, during the pre-charge period that occurs after the idle period, the row select signal RS 446 turns on the row select transistor 222, and then the multi-functional reset control signal MRSTG 444 turns on the multi-functional reset transistor 234 and the bias voltage VCAP line 448 is set to be in a high impedance state (e.g., HiZ), which decouples the bias voltage source 248 (e.g., row driver) from the LOFIC 232 during the pre-charge period and shorts both the first metal electrode CTM and the second metal electrode CBM of the LOFIC 232 to the reset voltage (e.g., PIXVDD) through the multi-functional reset transistor 234. The voltage level of the multi-functional reset control signal MRSTG 444 for turning on the multi-functional reset transistor 234 can be configured to be greater than the voltage level of the reset voltage (e.g., PIXVDD), such that the multi-functional reset transistor 234 operates in linear operation, thereby ensuring that the first source and the second source of the multi-functional reset transistor 234 (e.g., the first metal electrode CTM and the second metal electrode CBM) have the same potential. According to the teachings of the present invention, by shorting both the first metal electrode CTM and the second metal electrode CBM of the LOFIC 232 to the reset voltage (e.g., PIXVDD), the LOFIC 232 is locally auto-zeroed and forced to discharge within the pixel circuit 204, which reduces image lag. Next, the low conversion gain control signal LCG 442 turns on the low conversion gain transistor 230, and then the double floating diffusion control signal DFD 438 turns on the double floating diffusion transistor 224, and then the transfer control signal TX 436 (e.g., a high bias voltage level at the gate of the transfer transistor 216) turns on the transfer transistor 216. At this time during the pre-charge period, the photodiode 214, the first floating diffusion FD1 218, the second capacitor 228, and the LOFIC 232 are all reset through the multi-functional reset transistor 234.

[0047] Thereafter, the transfer control signal TX 436 (e.g., a low bias voltage level or a negative bias voltage) turns off the transfer transistor 216, and then the multi-functional reset control signal MRSTG 444 turns off the multi-functional reset transistor 234, and then the bias voltage VCAP line 448 transitions from a high impedance state (e.g., HiZ) to a low bias voltage value (e.g., VCAPLO), and then the dual floating diffusion control signal DFD 438 turns off the dual floating diffusion transistor 224, and then the low conversion gain control signal LCG 442 turns off the low conversion gain transistor 230, and then the row select signal RS 446 turns off the row select transistor 222. It should be understood that before the bias voltage VCAP line 448 transitions from a high impedance state (e.g., HiZ) to a normal voltage supply state (e.g., a low bias voltage level), the multi-functional reset control signal MRSTG 444 transitions from a high voltage level to a low voltage level, thereby biasing the second metal electrode (e.g., CBM) of the LOFIC 232 to prevent a power short circuit problem (e.g., a short circuit between the bias voltage source and the reset voltage source).

[0048] Figure 4 The example depicted in shows that during the integration period that occurs after the pre-charge period, all signals are low and integration occurs, during which time the photodiode 214 generates image charge in response to incident light. During the integration period, excess photo-generated image charge can be configured to first overflow to the first floating diffusion section FD1 218, and then reach the LOFIC 232 through the low conversion gain transistor 230 and / or reach the second capacitor 228 through the dual floating diffusion transistor 224 for storage. For example, under strong light conditions (e.g., LED light or infrared light), when the photodiode is saturated, excess photo-generated image charge can first overflow to the first floating diffusion section FD1 218, reach the second capacitor 228 through the dual floating diffusion transistor 224 when the first floating diffusion section FD1 218 is full, and reach the LOFIC 232 through the low conversion gain transistor 230 for storage when the second capacitor 228 is also full.

[0049] Figure 4 The example depicted in shows that during the readout period that occurs after the integration period, the row select signal RS 446 turns on the row select transistor 222, and then the low conversion gain control signal LCG 442 is pulsed to turn on the low conversion gain transistor 230, and then the dual floating diffusion control signal DFD 438 turns on the dual floating diffusion transistor 224, and then the bias voltage VCAP line 448 transitions to a high bias voltage value (e.g., VCAPHI).

[0050] Next, a dual conversion gain (DCG) readout occurs in the photodiode, during which time a medium conversion gain (MCG) readout of the reset value (R) occurs from the photodiode 214. Next, the floating diffusion capacitor signal FDC 440 is pulsed while the dual floating diffusion control signal DFD 438 turns off the dual floating diffusion transistor 224. Next, a high conversion gain (HCG) readout of the reset value (R) occurs from the photodiode 214. Next, the floating diffusion capacitor signal FDC 440 transitions to a high voltage value and the transfer control signal TX 436 turns on the transfer transistor 216, during which time the image charge in the photodiode 214 is transferred to the first floating diffusion section FD1 218. Next, a high conversion gain (HCG) readout of the signal value (S) may occur, i.e., the signal is read from the first floating diffusion section FD1 218 based on the effective capacitance of the first floating diffusion section FD1 218. Next, the dual floating diffusion control signal DFD 438 turns on the dual floating diffusion transistor 224, the floating diffusion capacitor signal FDC 440 transitions to a high value, and the transfer control signal TX 436 turns on the transfer transistor 216, during which time the image charge in the photodiode 214 is transferred to the first floating diffusion section FD1 218 and the second capacitor 228. Next, a medium conversion gain (MCG) readout of the signal value (S) may occur, i.e., the signal is read from the first floating diffusion section FD1 218 and the second capacitor 228 based on the effective capacitance of the first floating diffusion section FD1 218 and the second capacitor 228.

[0051] Next, LOFIC readout of the photodiode 214 and the LOFIC 232 occurs. During this time period, the low conversion gain control signal LCG 442 turns on the low conversion gain transistor 230, and then the transfer control signal TX 436 turns on the transfer transistor 216. During this time period, the image charge in the photodiode 214 is transferred to the first floating diffusion FD1 218, the second capacitor 228, and the LOFIC 232. Next, a low conversion gain (LCG) readout of the signal value (S) can occur, that is, a signal readout from the first floating diffusion FD1 218, the second capacitor 228, and the LOFIC 232 based on the effective capacitance of the first floating diffusion FD1 218, the second capacitor 228, and the LOFIC 232. Next, the multifunctional reset control signal MRSTG 444 turns on the multifunctional reset transistor 234 and the bias voltage VCAP line 448 is set to be in a high impedance state (e.g., HiZ), which decouples the bias voltage source 248 (e.g., row driver) from the LOFIC 232 and shorts both the first metal electrode CTM and the second metal electrode CBM of the LOFIC 232 to the reset voltage (e.g., PIXVDD) through the multifunctional reset transistor 234 during this reset signal readout period. By shorting both the first metal electrode CTM and the second metal electrode CBM of the LOFIC 232 to the reset voltage (e.g., PIXVDD), the LOFIC 232 is locally auto-zeroed and forced to perform a discharge operation within the pixel circuit 204. Additionally, during this time period, the photodiode 214, the first floating diffusion FD1 218, the second capacitor 228, and the LOFIC 232 are all reset through the multifunctional reset transistor 234. After that, the multifunctional reset control signal MRSTG 444 turns off the multifunctional reset transistor 234, and then the bias voltage VCAP line 448 transitions from the high impedance state (e.g., HiZ) to a high bias voltage value (e.g., VCAPHI) to decouple the bias voltage VCAP line 448 and the LOFIC 232, and then a low conversion gain (LCG) readout of the reset value (R) occurs. After this time, the transfer control signal TX 436 turns off the transfer transistor 216, and then the bias voltage VCAP line 448 transitions to a low bias voltage value (e.g., VCAPLO), and then the double floating diffusion control signal DFD 438 turns off the double floating diffusion transistor 224, and then the low conversion gain control signal LCG 442 turns off the low conversion gain transistor 230.It should be understood that before or at the same time as the bias voltage VCAP line 448 transitions from a high impedance state (e.g., HiZ) to a normal voltage supply state (e.g., a high bias voltage level), the multi-functional reset control signal MRSTG 444 is configured to transition from a high voltage level to a low voltage level, thereby biasing the second metal electrode (e.g., CBM) of the LOFIC 232 to prevent a power short circuit problem (e.g., a short circuit between the bias voltage source and the reset voltage source).

[0052] Next, in accordance with the teachings of the present invention, Figure 4 the process described in returns to the idle period for the next frame capture operation and the cycle repeats.

[0053] The foregoing description of the illustrated examples of the invention, which includes what is described in the abstract of the invention, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific examples of the invention have been described herein for illustrative purposes, as will be recognized by those of ordinary skill in the relevant art, various modifications can be made within the scope of the invention.

[0054] These modifications can be made in view of the foregoing detailed description. The terms used in the appended claims should not be construed as limiting the invention to the specific examples disclosed in this specification. Rather, the scope of the invention will be determined entirely by the appended claims, which are to be construed in accordance with the principles of claim interpretation as they are created.

Claims

1. A pixel circuit, comprising: A photodiode configured to generate an image charge in response to incident light; A floating diffusion section coupled to receive the image charge from the photodiode; A transfer transistor coupled between the photodiode and the floating diffusion section, wherein the transfer transistor is configured to transfer the image charge from the photodiode to the floating diffusion section; A lateral overflow integrating capacitor (LOFIC) comprising an insulating region disposed between a first metal electrode and a second metal electrode, wherein the first metal electrode is coupled to a bias voltage source, and wherein the second metal electrode is selectively coupled to the floating diffusion section; And A multi-functional reset transistor having a gate, a drain, a first source, and a second source, wherein the gate is coupled to a multi-functional reset control signal, and wherein the drain, the first source, and the second source are coupled to each other in response to the multi-functional reset control signal turning on the multi-functional reset transistor, and the drain, the first source, and the second source are decoupled from each other in response to the multi-functional reset control signal turning off the multi-functional reset transistor, wherein the drain is coupled to a reset voltage source, wherein the first source is coupled to the first metal electrode, and wherein the second source is coupled to the second metal electrode.

2. The pixel circuit according to claim 1, wherein during a pre-charge period and during a readout period, the multi-functional reset transistor is configured to be turned on, and a buffer of the bias voltage source coupled to the first metal electrode is configured to be in a high impedance state to provide a zero bias across the LOFIC to discharge the LOFIC while resetting the pixel circuit, wherein the pre-charge period occurs before an integration period, and wherein the pre-charge period and the integration period occur between an idle period and the readout period.

3. The pixel circuit according to claim 2, wherein during the pre-charge period, the multi-functional reset transistor is configured to be turned off before the buffer of the bias voltage source is configured to transition from the high impedance state to providing a first bias voltage to the first metal electrode during the pre-charge period.

4. The pixel circuit according to claim 3, wherein during the readout period, the multi-functional reset transistor is configured to be turned off, and the bias voltage source is configured to provide a second bias voltage to the first metal electrode, wherein the first bias voltage is a low capacitor bias voltage, and wherein the second bias voltage is a high capacitor bias voltage greater than the low capacitor bias voltage.

5. The pixel circuit according to claim 4, wherein a voltage level of the multi-functional reset control signal for turning on the multi-functional reset transistor is greater than a voltage level of the reset voltage source.

6. The pixel circuit according to claim 5, wherein during the readout period, before reading the reset signal value from the LOFIC, the multifunctional reset transistor is configured to be turned on, and the buffer of the bias voltage source is configured to be in the high impedance state to provide a zero bias across the LOFIC while resetting the pixel circuit.

7. The pixel circuit according to claim 1, wherein the pixel circuit further comprises: A dual floating diffusion (DFD) transistor coupled to the floating diffusion section, wherein the DFD transistor is configured to switch in response to a DFD control signal; A second capacitor, wherein the DFD transistor is coupled between the floating diffusion section and the second capacitor; And A low conversion gain (LFG) transistor coupled between the floating diffusion section and the second metal electrode, wherein the LFG transistor is configured to switch in response to an LFG control signal.

8. The pixel circuit according to claim 7, further comprising: A source follower transistor having a gate coupled to the floating diffusion section; And A row selection transistor coupled to the source follower transistor, wherein the source follower transistor and the row selection transistor are coupled between a power supply line and a bit line.

9. An imaging system, comprising: A pixel array including a plurality of pixel circuits arranged in a plurality of rows and a plurality of columns, wherein each of the pixel circuits comprises: A photodiode configured to generate an image charge in response to incident light; A floating diffusion section coupled to receive the image charge from the photodiode; A transfer transistor coupled between the photodiode and the floating diffusion section, wherein the transfer transistor is configured to transfer the image charge from the photodiode to the floating diffusion section; A lateral overflow integration capacitor (LOFIC) including an insulating region disposed between a first metal electrode and a second metal electrode, wherein the second metal electrode is selectively coupled to the floating diffusion section; And A multifunctional reset transistor having a gate, a drain, a first source, and a second source, wherein the gate is coupled to a multifunctional reset control signal, wherein the drain, the first source, and the second source are coupled to each other in response to turning on the multifunctional reset transistor by the multifunctional reset control signal, and the drain, the first source, and the second source are decoupled from each other in response to turning off the multifunctional reset transistor by the multifunctional reset control signal, wherein the drain is coupled to a reset voltage source, wherein the first source is coupled to the first metal electrode, and wherein the second source is coupled to the second metal electrode; A bias voltage source coupled to the first metal electrode; A control circuit system coupled to the pixel array to control the operation of the pixel array; And A readout circuit system coupled to the pixel array to read out image data from a plurality of pixel circuits.

10. The imaging system according to claim 9, further comprising functional logic coupled to the readout circuitry to store the image data from each of the plurality of pixel circuits.

11. The imaging system according to claim 9, wherein during a precharge period and during a readout period, the multifunctional reset transistor is configured to be turned on, and a buffer of the bias voltage source is configured to be in a high impedance state to provide a zero bias across the LOFIC to discharge the LOFIC while resetting the pixel circuit, wherein the precharge period occurs before an integration period, and wherein the precharge period and the integration period occur between an idle period and the readout period.

12. The imaging system according to claim 11, wherein during the precharge period, the multifunctional reset transistor is configured to be turned off before the buffer of the bias voltage source is configured to transition from the high impedance state to provide a first bias voltage to the first metal electrode during the precharge period.

13. The imaging system according to claim 12, wherein during the readout period, the multifunctional reset transistor is configured to be turned off, and the bias voltage source is configured to provide a second bias voltage to the first metal electrode, wherein the first bias voltage is a low capacitor bias voltage, and wherein the second bias voltage is a high capacitor bias voltage greater than the low capacitor bias voltage.

14. The imaging system according to claim 13, wherein a voltage level of the multifunctional reset control signal for turning on the multifunctional reset transistor is greater than a voltage level of the reset voltage source.

15. The imaging system according to claim 14, wherein during the readout period, before reading a reset signal value from the LOFIC, the multifunctional reset transistor is configured to be turned on, and the buffer of the bias voltage source is configured to be in the high impedance state to provide a zero bias across the LOFIC while resetting the pixel circuit.

16. The imaging system according to claim 9, wherein each of the pixel circuits further comprises: a dual floating diffusion (DFD) transistor coupled to the floating diffusion, wherein the DFD transistor is configured to switch in response to a DFD control signal; a second capacitor, wherein the DFD transistor is coupled between the floating diffusion and the second capacitor; and a low conversion gain (LFG) transistor coupled between the floating diffusion and the second metal electrode, wherein the LFG transistor is configured to switch in response to an LFG control signal.

17. The imaging system according to claim 16, wherein each of the pixel circuits further comprises: a source follower transistor having a gate coupled to the floating diffusion; and a row selection transistor coupled to the source follower transistor, wherein the source follower transistor and the row selection transistor are coupled between a power line and a bit line.

Images