Analyzing method and device, electronic equipment and storage medium

Abstract

The present disclosure relates to the technical field of compiling, and provides a parsing method and device, electronic equipment and a storage medium. The parsing method is used for determining whether a compiler's compilation instruction sequence is optimizable, and includes: parsing the compilation instruction sequence to determine a field included in each instruction, the field indicating one or more of a type of the instruction, a source operand address, and a destination operand address; parsing the field to determine resource use rationality of the compilation instruction sequence; when the resource use of the compilation instruction sequence is not rational, determining that the compilation instruction sequence is optimizable, and outputting an optimization mode of the compilation instruction sequence. The parsing method of the present disclosure can detect the compilation instruction sequence of the compiler, automatically determine the resource use rationality, and automatically output the optimization mode of the compilation instruction sequence when the resource use is not rational, thereby reducing the cost of human resources, improving work efficiency, and improving the accuracy of the optimization mode and the parsing effect.

Description

Technical Field

[0001] The present disclosure relates to the field of compilation technology, and in particular to a parsing method, device, electronic device, and storage medium. Background Art

[0002] Program code written in a programming language typically needs to be compiled by a compiler into a machine-executable instruction sequence before it can be run on a specific machine. The quality of an instruction sequence is related to its rational use of resources. Existing techniques can analyze instruction sequences through methods such as instruction execution time or specific performance benchmarks. Visually observing the analysis results can determine the quality of the instruction sequence and how to optimize it.

[0003] However, in actual applications, the compilation instruction sequence usually contains many instructions. Relying entirely on visual analysis to determine the quality of the compilation instruction sequence and the optimization method of the compilation instruction sequence has high human resource costs and low efficiency. Secondly, the accuracy may not be enough, and the parsing effect still needs to be improved. Summary of the Invention

[0004] In view of this, the present disclosure proposes a parsing method, device, electronic device and storage medium. The parsing method of the embodiment of the present disclosure can detect the compilation instruction sequence of the compiler, automatically determine the rationality of resource utilization, and automatically output the optimization method of the compilation instruction sequence when resource utilization is unreasonable. It can reduce human resource costs and improve work efficiency. The optimization method provided is more accurate and improves the parsing effect.

[0005] According to one aspect of the present disclosure, a parsing method is provided for parsing and determining whether a compilation instruction sequence of a compiler is optimizable, the method comprising: obtaining the compilation instruction sequence obtained by the compiler compiling a current program code, the compilation instruction sequence comprising a plurality of instructions; parsing the compilation instruction sequence to determine fields included in each instruction, the fields indicating one or more of the type of the instruction, a source operand address, and a destination operand address; parsing the fields to determine the rationality of resource usage of the compilation instruction sequence, the resources comprising a module with a storage function; when the resource usage of the compilation instruction sequence is unreasonable, determining that the compilation instruction sequence is optimizable, and outputting an optimization method for the compilation instruction sequence.

[0006] In one possible implementation, parsing the field and determining the rationality of resource usage of the compilation instruction sequence include: for each resource, counting the maximum number of the resource used by the compilation instruction sequence based on the source operand address and the destination operand address; determining, based on preset resource configuration parameters, the number of tasks allowed to be started when the resource is allocated to the compilation instruction sequence according to the maximum number, and the tasks are used to execute the compilation instruction sequence; when the minimum number of tasks allowed to be started corresponding to each resource is less than the number of active tasks required for task scheduling, determining that the resource usage of the compilation instruction sequence is unreasonable.

[0007] In one possible implementation, when the minimum number of tasks allowed to be started corresponding to each resource is less than the number of active tasks required for task scheduling, and the resources corresponding to the minimum value include vertex memory, the tasks include vertex tasks, and the optimization method includes reducing the amount of vertex memory required to be occupied by a single vertex task; when the minimum number of tasks allowed to be started corresponding to each resource is less than the number of active tasks required for task scheduling, and the resources corresponding to the minimum value include general data registers, the optimization method includes moving out invalid data in the general data registers.

[0008] In one possible implementation, parsing the field and judging the rationality of resource usage of the compilation instruction sequence include: determining the lifecycle of resources used by the compilation instruction sequence based on the type of the instruction, the source operand address, and the destination operand address; determining the number of resources used when executing each instruction based on the lifecycle of the resources used by the compilation instruction sequence; determining the minimum number of resources used to execute the compilation instruction sequence based on the number of resources used when executing each instruction; and judging that the resource usage of the compilation instruction sequence is unreasonable when the minimum number is less than the actual number of resources used to execute the compilation instruction sequence.

[0009] In one possible implementation, when the minimum number is less than the actual number of resources used to execute the compiled instruction sequence, the optimization method includes: selecting a resource whose life cycle is less than a first threshold and is only used as the source operand address, and replacing the resource that is only used as the destination operand address.

[0010] In one possible implementation, parsing the field and determining the rationality of resource usage of the compilation instruction sequence include: determining the dependency relationship of each instruction in the compilation instruction sequence based on the source operand address and the destination operand address; determining whether the instructions with the dependency relationship are compressible based on the source operand address and the destination operand address of the instructions with the dependency relationship; and determining that the resource usage of the compilation instruction sequence is unreasonable when the instructions with the dependency relationship are compressible.

[0011] In one possible implementation, when the instructions with dependencies are compressible, the optimization method includes: compressing the instructions with dependencies, wherein the resources that are only used as source operand addresses in the instructions with dependencies are used as source operand addresses of the compressed instructions; the resources that are only used as destination operand addresses in the instructions with dependencies are used as destination operand addresses of the compressed instructions; and determining the type of the compressed instructions according to the type of the dependencies.

[0012] In one possible implementation, parsing the field and determining the rationality of resource usage of the compilation instruction sequence includes: for any instruction in the compilation instruction sequence, determining, based on the type of the instruction, that the execution time of the instruction is greater than a second threshold, and when, in the compilation instruction sequence, there are other instructions following the instruction that have no dependency on the instruction, determining that the resource usage of the compilation instruction sequence is unreasonable; and the optimization method includes moving the execution order of the other instructions that have no dependency on the instruction forward.

[0013] In one possible implementation, when the compilation instruction sequence is a multi-layer nested structure, the method further includes: taking any instruction in the compilation instruction sequence as the current instruction, and tracking other instructions in the compilation instruction sequence that are executed before the current instruction and involve the source operation address of the current instruction based on the source operand address of the current instruction; judging whether a read / write behavior conflict occurs in the source operand address of the current instruction based on the tracked instructions; and when a read / write behavior conflict occurs, outputting the read / write behavior conflict in the form of a log.

[0014] In one possible implementation, the method further includes: determining a tag value of a nested level corresponding to each instruction of the compilation instruction sequence; determining visualization data of the nested hierarchy structure of the compilation instruction sequence based on the tag value, and outputting the visualization data in a log format.

[0015] In one possible implementation, the resources include temporary registers and relay registers, and when the temporary registers store integer data and / or floating-point data used when the compiled instruction sequence is executed, the optimization method includes: using the relay registers instead of the temporary registers to store the integer data and / or the floating-point data.

[0016] According to another aspect of the present disclosure, a parsing device is provided for parsing and determining whether a compilation instruction sequence of a compiler is optimizable, the device comprising: an acquisition module for acquiring the compilation instruction sequence obtained by the compiler compiling a current program code, the compilation instruction sequence comprising a plurality of instructions; a first parsing module for parsing the compilation instruction sequence and determining fields included in each instruction, the fields indicating one or more of the type, source operand address, and destination operand address of the instruction; a second parsing module for parsing the fields and judging the rationality of resource usage of the compilation instruction sequence, the resources comprising a module with a storage function; and a first output module for determining, when the resource usage of the compilation instruction sequence is unreasonable, that the compilation instruction sequence is optimizable and outputting an optimization method for the compilation instruction sequence.

[0017] In one possible implementation, parsing the field and determining the rationality of resource usage of the compilation instruction sequence include: for each resource, counting the maximum number of the resource used by the compilation instruction sequence based on the source operand address and the destination operand address; determining, based on preset resource configuration parameters, the number of tasks allowed to be started when the resource is allocated to the compilation instruction sequence according to the maximum number, and the tasks are used to execute the compilation instruction sequence; when the minimum number of tasks allowed to be started corresponding to each resource is less than the number of active tasks required for task scheduling, determining that the resource usage of the compilation instruction sequence is unreasonable.

[0018] In one possible implementation, when the minimum number of tasks allowed to be started corresponding to each resource is less than the number of active tasks required for task scheduling, and the resources corresponding to the minimum value include vertex memory, the tasks include vertex tasks, and the optimization method includes reducing the amount of vertex memory required to be occupied by a single vertex task; when the minimum number of tasks allowed to be started corresponding to each resource is less than the number of active tasks required for task scheduling, and the resources corresponding to the minimum value include general data registers, the optimization method includes moving out invalid data in the general data registers.

[0019] In one possible implementation, parsing the field and judging the rationality of resource usage of the compilation instruction sequence include: determining the lifecycle of resources used by the compilation instruction sequence based on the type of the instruction, the source operand address, and the destination operand address; determining the number of resources used when executing each instruction based on the lifecycle of the resources used by the compilation instruction sequence; determining the minimum number of resources used to execute the compilation instruction sequence based on the number of resources used when executing each instruction; and judging that the resource usage of the compilation instruction sequence is unreasonable when the minimum number is less than the actual number of resources used to execute the compilation instruction sequence.

[0020] In one possible implementation, when the minimum number is less than the actual number of resources used to execute the compiled instruction sequence, the optimization method includes: selecting a resource whose life cycle is less than a first threshold and is only used as the source operand address, and replacing the resource that is only used as the destination operand address.

[0021] In one possible implementation, parsing the field and determining the rationality of resource usage of the compilation instruction sequence include: determining the dependency relationship of each instruction in the compilation instruction sequence based on the source operand address and the destination operand address; determining whether the instructions with the dependency relationship are compressible based on the source operand address and the destination operand address of the instructions with the dependency relationship; and determining that the resource usage of the compilation instruction sequence is unreasonable when the instructions with the dependency relationship are compressible.

[0022] In one possible implementation, when the instructions with dependencies are compressible, the optimization method includes: compressing the instructions with dependencies, wherein the resources that are only used as source operand addresses in the instructions with dependencies are used as source operand addresses of the compressed instructions; the resources that are only used as destination operand addresses in the instructions with dependencies are used as destination operand addresses of the compressed instructions; and determining the type of the compressed instructions according to the type of the dependencies.

[0023] In one possible implementation, parsing the field and determining the rationality of resource usage of the compilation instruction sequence includes: for any instruction in the compilation instruction sequence, determining, based on the type of the instruction, that the execution time of the instruction is greater than a second threshold, and when, in the compilation instruction sequence, there are other instructions following the instruction that have no dependency on the instruction, determining that the resource usage of the compilation instruction sequence is unreasonable; and the optimization method includes moving the execution order of the other instructions that have no dependency on the instruction forward.

[0024] In one possible implementation, when the compilation instruction sequence is a multi-layer nested structure, the device further includes: a tracking module, which is used to take any instruction of the compilation instruction sequence as the current instruction, and track other instructions in the compilation instruction sequence that are executed before the current instruction and involve the source operation address of the current instruction based on the source operand address of the current instruction; a judgment module, which is used to judge whether a read / write behavior conflict occurs in the source operand address of the current instruction based on the tracked instructions; and a second output module, which is used to output the read / write behavior conflict in the form of a log when a read / write behavior conflict occurs.

[0025] In one possible implementation, the device further includes: a determination module for determining a tag value of a nested level corresponding to each instruction of the compiled instruction sequence; and a third output module for determining visual data of the nested hierarchical structure of the compiled instruction sequence based on the tag value, and outputting the visual data in the form of a log.

[0026] In one possible implementation, the resources include temporary registers and relay registers, and when the temporary registers store integer data and / or floating-point data used when the compiled instruction sequence is executed, the optimization method includes: using the relay registers instead of the temporary registers to store the integer data and / or the floating-point data.

[0027] According to another aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to implement the above method when executing the instructions stored in the memory.

[0028] According to another aspect of the present disclosure, a non-volatile computer-readable storage medium is provided, on which computer program instructions are stored, wherein the computer program instructions implement the above method when executed by a processor.

[0029] According to another aspect of the present disclosure, a computer program product is provided, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

[0030] According to the parsing method of the embodiment of the present disclosure, by obtaining the compilation instruction sequence obtained by the compiler when compiling the current program code, the compilation instruction sequence includes multiple instructions, and then parsing the compilation instruction sequence, the fields included in each instruction can be determined, so as to obtain one or more of the type of instruction indicated by the field, the source operand address, and the destination operand address, and complete the restoration of the information included in the current program code; by parsing the field, the rationality of resource utilization of the compilation instruction sequence can be judged, and the rationality of resource utilization can be automatically determined, which can reduce human resource costs and improve work efficiency; the rationality of resource utilization of the compilation instruction sequence is related to the quality of the compilation instruction sequence, so when the resource utilization of the compilation instruction sequence is unreasonable, it can be determined that the compilation instruction sequence can be optimized, and the accuracy of the optimization method given is higher, thereby improving the parsing effect.

[0031] The parsing method of the disclosed embodiment can detect whether there is a problem with the compiled instruction sequence before the compiled instruction sequence is executed, thereby facilitating the optimization of the compiled instruction sequence.

[0032] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0034] Figure 1 An exemplary application scenario of the parsing method according to an embodiment of the present disclosure is shown.

[0035] Figure 2 A schematic diagram showing the process of the parsing method according to an embodiment of the present disclosure.

[0036] Figure 3 An example of instructions having dependency relationships in a compilation instruction sequence according to an embodiment of the present disclosure is shown.

[0037] Figure 4 A schematic diagram showing the structure of a parsing device according to an embodiment of the present disclosure.

[0038] Figure 5 A block diagram of an apparatus 1900 according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0039] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0040] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0041] In addition, numerous specific details are provided in the following detailed description to better illustrate the present disclosure. Those skilled in the art will appreciate that the present disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main points of the present disclosure.

[0042] Figure 1 An exemplary application scenario of the parsing method according to an embodiment of the present disclosure is shown.

[0043] like Figure 1As shown, the parsing method of the embodiment of the present disclosure can be performed by a parsing device, which can be run by a processor that also runs a compiler. A user writes multiple program code segments and inputs them into the compiler. Any of these segments is used as the current program code. When the compiler compiles the current program code, it outputs a corresponding compilation instruction sequence, which includes multiple instructions.

[0044] The processor also exchanges data with resources available to the compiled instruction sequence. Resources can be various registers, memories, or other modules with storage capabilities.

[0045] The analyzing device obtains the compilation instruction sequence of the compiler, analyzes and determines the resource utilization rationality of the compilation instruction sequence, and further determines whether the compilation instruction sequence can be optimized and the optimization method based on the resource utilization rationality.

[0046] Figure 2 A schematic diagram showing the process of the parsing method according to an embodiment of the present disclosure.

[0047] like Figure 2 As shown, in a possible implementation, the present disclosure proposes a parsing method for parsing and determining whether a compilation instruction sequence of a compiler is optimizable, the method comprising:

[0048] Step S21, obtaining a compilation instruction sequence obtained by a compiler from compiling the current program code, where the compilation instruction sequence includes multiple instructions;

[0049] Step S22, parsing the compiled instruction sequence to determine the fields included in each instruction, where the fields indicate one or more of the instruction type, source operand address, and destination operand address;

[0050] Step S23, parsing the fields to determine the rationality of resource usage of the compiled instruction sequence, where the resources include modules with storage functions;

[0051] Step S24 : When the resource usage of the compilation instruction sequence is unreasonable, determining that the compilation instruction sequence can be optimized and outputting an optimization method for the compilation instruction sequence.

[0052] For example, first in step S21 , a compilation instruction sequence obtained by compiling a current program code by a compiler is obtained, wherein the current program code may be one of multiple program codes written by a user.

[0053] The compiler may be a compiler implemented based on prior art, and thus the manner in which it compiles the current program code may be known. Therefore, in step S22, when parsing the compilation instruction sequence to determine the fields included in each instruction, the fields included in the instruction may be inferred based on the known manner in which the current program code is compiled.

[0054] An instruction typically includes multiple fields, such as an opcode field, an addressing mode field, a register number field, and an operand field. The fields identified in the present disclosure may indicate one or more of the instruction type, source operand address, and destination operand address. The instruction type is typically recorded in the opcode field, and the source operand address and destination operand address are typically recorded in the operand field. Therefore, when executing step S22, it is sufficient to parse the opcode field and the operand field.

[0055] The parsed fields can be stored in the instruction sequence fragment information table (see Table 1 for an example). The data structure of the instruction sequence fragment information table can be predefined to store the instruction number, instruction type, source operand address, destination operand address, and other content that can be determined by parsing the compiled instruction sequence and fields.

[0056] It is understandable that the field division of the instruction should be more than the above example. When executing step S22, more or fewer fields can also be parsed. It is sufficient to parse out the field indicating the type of instruction, source operand address, and destination operand address, or one or more of them. The embodiment of the present disclosure does not limit the specific content recorded in the parsed field.

[0057] In step S23, the fields may be parsed to determine the rationality of resource usage by the compiled instruction sequence. Resource usage may include the amount of resources used by the instructions, the order in which the instructions use resources, and so on. When determining the rationality of resource usage by the compiled instruction sequence, the results of the field parsing may be used to determine whether the amount of resources used by the instructions is reasonable, whether the order in which the instructions use resources is reasonable, and so on. For an exemplary implementation, see the further description of step S23 below.

[0058] Whether the resource usage of the compilation instruction sequence is reasonable or not is related to the quality of the compilation instruction sequence. In step S24, when the resource usage of the compilation instruction sequence is unreasonable, it can be determined that the compilation instruction sequence can be optimized, and the optimization method of the compilation instruction sequence is output. The output optimization method may be related to the specific judgment basis when judging the rationality of the resource usage of the compilation instruction sequence in step S23. For example, assuming that when executing step S23, the resource usage of the compilation instruction sequence is judged to be unreasonable based on the unreasonable number of resources used by the instructions, the optimization method may be to adjust the number of resources used by the instructions. Assuming that when executing step S23, the resource usage of the compilation instruction sequence is judged to be unreasonable based on the unreasonable order of resources used by the instructions, the optimization method may be to adjust the order of resources used by the instructions. More examples of optimization methods are given later.

[0059] According to the parsing method of the embodiment of the present disclosure, by obtaining the compilation instruction sequence obtained by the compiler when compiling the current program code, the compilation instruction sequence includes multiple instructions, and then parsing the compilation instruction sequence, the fields included in each instruction can be determined, so as to obtain one or more of the type of instruction indicated by the field, the source operand address, and the destination operand address, and complete the restoration of the information included in the current program code; by parsing the field, the rationality of resource utilization of the compilation instruction sequence can be judged, and the rationality of resource utilization can be automatically determined, which can reduce human resource costs and improve work efficiency; the rationality of resource utilization of the compilation instruction sequence is related to the quality of the compilation instruction sequence, so when the resource utilization of the compilation instruction sequence is unreasonable, it can be determined that the compilation instruction sequence can be optimized, and the accuracy of the optimization method given is higher, thereby improving the parsing effect.

[0060] The parsing method of the disclosed embodiment can detect whether there is a problem with the compiled instruction sequence before the compiled instruction sequence is executed, thereby facilitating the optimization of the compiled instruction sequence.

[0061] The parsing method of the embodiment of the present disclosure has multiple implementations for determining the rationality of resource usage of a compilation instruction sequence (step S23). Several examples of determining the rationality of resource usage of a compilation instruction sequence are given below.

[0062] In a possible implementation, step S23 includes:

[0063] For each resource, based on the source operand address and the destination operand address, calculate the maximum number of resources used by the compiled instruction sequence;

[0064] Determine, based on preset resource configuration parameters, the number of tasks allowed to be started when the resource is allocated to the compilation instruction sequence according to the maximum number, the tasks being used to execute the compilation instruction sequence;

[0065] When the minimum number of tasks allowed to be started corresponding to each resource is less than the number of active tasks required for task scheduling, it is determined that the resource usage of the compilation instruction sequence is unreasonable.

[0066] For example, resources may include General Purpose Registers (GPR), Vertex Storage, Internal Registers, etc. The size of the resources can be pre-configured, that is, the preset resource configuration parameters. The resources at the source operand address and the destination operand address are all resources used by the instruction. For each resource, the maximum number of the resource used by the compiled instruction sequence can be counted separately, and the number of tasks allowed to be started when the resource is allocated to the compiled instruction sequence according to the maximum number can be determined. Tasks are used to execute the compiled instruction sequence. The more tasks allowed to be started, the better the execution effect of the compiled instruction sequence.

[0067] Assume that the task being executed is a Single Instruction Multiple Data (SMID) task. An instruction can be jointly executed by multiple SIMD tasks. A common SIMD32 task can be jointly executed by 32 thread SIMD tasks. When a single SIMD task is executed, it can be aligned to the specific allocation granularity of the general data register. Therefore, for the general data register, based on the source operand address and the destination operand address, the maximum number of resources used by the compiled instruction sequence can be counted, and the maximum number of general data registers required to be occupied by a single SIMD task can be calculated. According to the preset resource configuration parameters, the number of tasks allowed to be started when allocating resources for the compiled instruction sequence according to the maximum number can be determined. The result can be the number of tasks allowed to be started supported by the general data register resources, divided by the configured general data register size.

[0068] A SIMD task usually includes multiple bound vertex task groups. A vertex task group is generally bound to 4 vertex tasks (it may also be other values, without restriction). The vertex task output needs to occupy vertex memory. For vertex memory, based on the source operand address and the destination operand address, the maximum number of resources used by the compiled instruction sequence is counted, which can be the maximum number of vertex memories required for a single vertex task. According to the preset resource configuration parameters, the number of tasks allowed to be started when resources are allocated to the compiled instruction sequence according to the maximum number can be determined. The result can be the number of tasks allowed to be started supported by the vertex memory resources, divided by the configured vertex memory size.

[0069] Similarly, for each resource, the maximum number of tasks used by the compilation instruction sequence can be calculated, and the number of tasks allowed to be launched when the compilation instruction sequence is allocated the resource according to the maximum number of tasks can be determined. The minimum number of tasks allowed to be launched for each resource is actually the number of tasks allowed to be launched for the current resource.

[0070] The number of active tasks required for task scheduling is used to hide the switching overhead or delay when switching tasks. The number of active tasks required for task scheduling corresponding to the processor core can be pre-set. When the number of tasks actually started is lower than the number of active tasks required for task scheduling, the task scheduling efficiency will decrease. Finally, the minimum number of tasks allowed to be started corresponding to each resource is compared with the number of active tasks required for task scheduling, and the resource usage of the compilation instruction sequence is judged to be reasonable based on the comparison result. When the minimum number of tasks allowed to be started corresponding to each resource is less than the number of active tasks required for task scheduling, the resource usage of the compilation instruction sequence is judged to be unreasonable; when the minimum number of tasks allowed to be started corresponding to each resource is greater than or equal to the number of active tasks required for task scheduling, the resource usage of the compilation instruction sequence is judged to be reasonable.

[0071] Accordingly, if the resource usage of the compiled instruction sequence is judged to be unreasonable based on the comparison result of the minimum number of tasks allowed to be started corresponding to each resource and the number of active tasks required for task scheduling, an optimization method can be further determined.

[0072] In one possible implementation, when a minimum number of tasks allowed to be started corresponding to each resource is less than a number of active tasks required for task scheduling, and the resource corresponding to the minimum number includes a vertex memory, the task includes a vertex task, and the optimization method includes reducing an amount of vertex memory required to be occupied by a single vertex task;

[0073] When the minimum number of tasks allowed to be started corresponding to each resource is less than the number of active tasks required for task scheduling, and the resources corresponding to the minimum value include general data registers, the optimization method includes removing invalid data in the general data registers.

[0074] For example, if the minimum number of tasks allowed to be started corresponding to each resource is less than the number of active tasks required for task scheduling, and the resource corresponding to the minimum value includes vertex memory, it can be considered that the number of tasks allowed to be started under the current resource usage is determined by the vertex memory resource. In this case, the task may include a vertex task. The determined optimization method may include reducing the amount of vertex memory required to be occupied by a single vertex task. For another example, if the minimum number of tasks allowed to be started corresponding to each resource is less than the number of active tasks required for task scheduling, and the resource corresponding to the minimum value includes a general data register, it can be considered that the number of tasks allowed to be started under the current resource usage is determined by the general data register resource, and the determined optimization method may include removing invalid data in the general data register. Determining whether the data is invalid can be implemented based on existing technology and will not be repeated here.

[0075] It is understandable that when it is judged that the resource usage of the compilation instruction sequence is unreasonable based on the number of tasks allowed to be started, the optimization methods that can be determined should be more than the above examples. As long as the optimization of the compilation instruction sequence can be achieved, the embodiments of the present disclosure do not limit the optimization methods that can be determined.

[0076] In this way, the rationality of resource usage of the compilation instruction sequence can be judged based on the number of tasks allowed to be started. Compared with manually calculating the number of tasks allowed to be started, work efficiency is greatly improved.

[0077] In a possible implementation, step S23 includes:

[0078] Determine the life cycle of resources used by the compiled instruction sequence based on the instruction type, source operand address, and destination operand address;

[0079] determining, based on a lifecycle of resources used by the compiled instruction sequence, an amount of resources used when executing each instruction;

[0080] Determining a minimum number of resources used to execute the compiled instruction sequence based on the number of resources used when executing each instruction;

[0081] When the minimum number is less than the actual number of resources used to execute the compiled instruction sequence, it is determined that the resource usage of the compiled instruction sequence is unreasonable.

[0082] For example, a compiled instruction sequence may involve multiple resources, but not every resource is necessarily used by every instruction. Therefore, it's possible that a resource used by one instruction may no longer be used by other instructions. This can lead to significant resource waste.

[0083] In this regard, when executing step S23, the lifecycle of resources used in compiling the instruction sequence can be determined based on the instruction type, source operand address, and destination operand address. The amount of resources used when executing each instruction can then be determined based on the resource lifecycle. An instruction sequence fragment information table can be constructed to store the determined information.

[0084] Table 1 shows an example of a compilation instruction sequence segment information table according to an embodiment of the present disclosure.

[0085] Assume that a compiled instruction sequence fragment contains instructions numbered 0-6, and the instructions are executed in ascending order. This instruction sequence uses 13 register resources: i0, r3-r7, r12-r15, r24, r25, and r39. Therefore, the actual number of register resources used to execute this compiled instruction sequence fragment is 13.

[0086] The type of instruction numbered 0 may be an addition instruction, and the two source operand addresses may be register resource r7 and register resource r39 respectively. When the instruction is executed, the two source operands are added together to obtain the destination operand, and the destination operand address may be register resource r7.

[0087] The type of instruction numbered 1 may be an addition instruction (represented by add in Table 1), and the two source operand addresses may be register resource r5 and register resource r25 respectively. Executing this instruction adds the two source operands to obtain a destination operand, and the destination operand address may be register resource r6.

[0088] The type of instruction numbered 2 may be an addition instruction, and the two source operand addresses may be relay register resource i0 and register resource r24 respectively. Executing this instruction adds the two source operands to obtain a destination operand, and the destination operand address may be register resource r5.

[0089] The type of instruction numbered 3 may be a multiply-accumulate instruction (represented by fma in Table 1), and the two source operand addresses may be register resources r12 and register resource r3, respectively. Executing this instruction multiplies the source operand obtained from register resource r12 by the floating-point number 2 (represented by 2f in Table 1), and the product is added to the source operand obtained from register resource r3 to obtain the destination operand, the destination operand address of which may be register resource i0.

[0090] The type of instruction numbered 4 may be a multiplication instruction (represented by mul in Table 1), and the two source operand addresses may be the relay register resource i0 and the register resource r6, respectively. Executing this instruction multiplies the two source operands to obtain the destination operand, and the destination operand address may be the register resource r13.

[0091] The type of instruction numbered 5 may be a multiplication instruction, and the two source operand addresses may be relay register resource i0 and register resource r5 respectively. Executing this instruction multiplies the two source operands to obtain a destination operand, and the destination operand address may be register resource r14.

[0092] The type of instruction numbered 6 may be a multiplication instruction, and the two source operand addresses may be relay register resource i0 and register resource r4 respectively. Executing this instruction multiplies the two source operands to obtain a destination operand, and the destination operand address may be register resource r15.

[0093] Table 1

[0094]

[0095] As shown in Table 1, the first column of the compiled instruction sequence fragment information table may be the instruction number. The second column may be information included in the compiled instruction sequence, such as the instruction type and the source and destination operand addresses. The third column may be the number of resources used when executing each instruction, that is, the number of register resources still in use when executing each instruction. Columns 4-16 may be the lifecycle of the resources used by the compiled instruction sequence. Each row corresponds to a single instruction.

[0096] The following first introduces a method for determining the life cycle of resources used by a compilation instruction sequence.

[0097] Relay register resource i0 is used by instructions numbered 2-6. When used by instruction numbered 2, it serves as the source operand address. Therefore, when instructions before instruction numbered 2 are executed, relay register resource i0 is also occupied. Therefore, in Table 1, the column corresponding to the lifetime of relay register resource i0 in the information table corresponding to instructions numbered 0-6 can be filled with 1s, indicating that the lifetime of relay register resource i0 is the execution time of instructions numbered 0-6.

[0098] The lifetime of other resources used as source operands is calculated in a similar manner to that of relay register resource i0 and will not be detailed here. For resources used only as destination operand addresses, such as register resources r13-r15, which are not occupied until the instruction using the resource is executed, the lifetime of the resource can be the execution time of the instruction using the resource.

[0099] The following describes how to determine the amount of resources used when executing each instruction.

[0100] The instruction numbered 0 corresponds to the lifecycle of 9 registers, namely, resources i0, r3-r5, r7, r12, r24, r25, and r39. Therefore, the number of resources used when executing the instruction numbered 0 can be 9. The instruction numbered 1 corresponds to the lifecycle of 8 registers, namely, register resources i0, r3-r6, r12, and r24. Therefore, the number of register resources used when executing the instruction numbered 1 can be 8. The method for determining the number of resources used to execute other instructions is similar to that for the instructions numbered 0 and 1, and will not be repeated here. It is finally determined that the number of register resources used to execute the instruction numbered 2 can be 7, the number of register resources used to execute the instruction numbered 3 can be 6, the number of register resources used to execute the instruction numbered 4 can be 5, the number of register resources used to execute the instruction numbered 5 can be 4, and the number of register resources used to execute the instruction numbered 6 can be 3.

[0101] In the example of Table 1, it can be seen that for this compilation instruction sequence fragment, only 9 register resources are required at least, that is, the minimum number of register resources used by this compilation instruction sequence fragment is 9. At this time, the minimum number of register resources used by this compilation instruction sequence fragment is less than the actual number of resources used to execute this compilation instruction sequence fragment. Therefore, it can be determined that the register resource usage of this compilation instruction sequence fragment is unreasonable.

[0102] Accordingly, if it is determined based on the minimum number of register resources used by the compiled instruction sequence fragment that the register resource usage of the compiled instruction sequence is unreasonable, an optimization approach may be further determined.

[0103] In a possible implementation, when the minimum number is less than the actual number of resources used to execute the compiled instruction sequence, the optimization method includes:

[0104] A resource having a life cycle smaller than a first threshold and being used only as the source operand address is selected to replace the resource used only as the destination operand address.

[0105] For example, when the minimum number is less than the actual number of resources used to execute the compiled instruction sequence, the resources can be replaced to reduce the actual number of resources used to execute the compiled instruction sequence to approach the minimum number. For example, the optimization method can be to select resources whose life cycle is less than the first threshold and are only used as source operand addresses to replace resources that are only used as destination operand addresses. For example, resource r39 can be used to replace resource r13, resource r25 can be used to replace resource r14, and resource r24 can be used to replace resource r15. In this case, resources r13-r15 do not need to be used, so that the actual number of resources used to execute the compiled instruction sequence is reduced from 13 to 10.

[0106] The first threshold can be set according to user needs, and the embodiment of the present disclosure does not limit the specific value of the first threshold.

[0107] When optimizing a compilation instruction sequence according to a determined optimization method, the optimized position can be marked with a compilation symbol and the number of the optimized resource can be filled in. In this way, when the optimized compilation instruction sequence is executed, the destination operand can be stored in the optimized resource.

[0108] It is understandable that when it is judged that the resource usage of the compilation instruction sequence is unreasonable based on the minimum number of resources used by the compilation instruction sequence, the optimization methods that can be determined should be more than the above examples. For example, the resources with the shortest life cycle and used only as source operand addresses can be selected to replace the resources used only as destination operand addresses. As long as the optimization of the compilation instruction sequence can be achieved, the embodiments of the present disclosure do not limit the optimization methods that can be determined.

[0109] It is understandable that the parsed information may also be stored in formats other than tables, and the embodiments of the present disclosure do not limit the storage format of the parsed information.

[0110] In this way, the resource usage rationality of the compiled instruction sequence can be judged based on the minimum number of resources used by the compiled instruction sequence, making the method of determining the resource usage rationality more flexible.

[0111] In a possible implementation, step S23 includes:

[0112] Determine the dependency relationship between instructions in the compiled instruction sequence based on the source operand address and the destination operand address;

[0113] Determine whether the instructions with the dependency relationship are compressible according to the source operand addresses and the destination operand addresses of the instructions with the dependency relationship;

[0114] When instructions with dependencies are compressible, it is determined that resource usage of the compiled instruction sequence is unreasonable.

[0115] For example, among multiple instructions in a compiled instruction sequence, there may be multiple instructions that are far apart, independently calculated, but have dependencies. Figure 3 An example of instructions having dependency relationships in a compilation instruction sequence according to an embodiment of the present disclosure is shown.

[0116] like Figure 3 As shown, the compilation instruction sequence includes instructions X, Y, and Z, where the type of instruction X can be a move instruction ( Figure 3 The source operand address may be register resource R0, and the destination operand address may be register resource R10. Executing this instruction moves the source operand to the destination operand.

[0117] The type of instruction Y can be a signed multiplication instruction ( Figure 3 The source operand addresses may be register resource R10 and register resource R4, respectively, and the destination operand address may be register resource R12. Executing this instruction multiplies the two source operands and stores the result in register resource R12.

[0118] The type of instruction Z can be a signed addition instruction ( Figure 3 The source operand addresses may be register resource R12 and register resource R0, respectively, and the destination operand address may be register resource R2. Executing this instruction adds the two source operands and stores the result in register resource R2.

[0119] It can be seen that the source operand address of instruction Y and the destination operand address of instruction X are the same and are resource R10, so instruction Y depends on instruction X. The source operand address of instruction Z and the destination operand address of instruction Y are the same and are resource R12, so instruction Z depends on instruction Y. Therefore, there is a dependency relationship between instructions X, Y, and Z.

[0120] According to the source operand address and destination operand address of the instructions with dependency relationship, it can be determined whether the instructions with dependency relationship can be compressed. Figure 3 For example, if there are no other instructions between instructions X and Y that use register resource R10 as the destination operand address, then instructions X and Y can be compressed. If there are no other instructions between instructions Y and Z that use resource R12 as the destination operand address, then instructions Y and Z can be compressed. If instructions X and Y are compressible, instructions X, Y, and Z can be compressed together. When dependent instructions are compressible, it can be determined that the resource usage of the compiled instruction sequence is unreasonable.

[0121] Accordingly, if it is determined that the resource usage of the compiled instruction sequence is unreasonable based on the compressibility of the instructions having the dependency relationship, an optimization method may be further determined.

[0122] In a possible implementation, when the instructions with dependencies are compressible, the optimization method includes:

[0123] Compress the instructions with dependencies, wherein:

[0124] Using the resources used only as source operand addresses in the instructions with dependency as the source operand addresses of the compressed instructions;

[0125] Using the resource that is only used as the destination operand address in the instructions with dependency as the destination operand address of the compressed instruction;

[0126] The type of the compressed instruction is determined according to the type of the dependency relationship.

[0127] For example, when instructions with dependencies can be compressed, the optimization method can be to compress the instructions with dependencies. Figure 3 Instructions X, Y, and Z in the instruction list can be compressed together to obtain a compressed instruction W. Resources that are used only as source operand addresses in instructions X, Y, and Z (register resource R4 and register resource R0) can be used as source operand addresses of the compressed instruction, and resources that are used only as destination operand addresses in instructions X, Y, and Z (register resource R2) can be used as destination operand addresses of the compressed instruction.

[0128] According to the type of instruction X, Y, Z, when executing instruction X, Y, Z, the source operand at register resource R4 is multiplied by the source operand at register resource R0, the product is added to the source operand at register resource R0, and the result is stored in register resource R2. Therefore, the type of instruction W can be a signed multiply-add instruction (in Figure 3 This optimization method can reduce the number of instruction issuances and the number of execution steps of the processor.

[0129] It is understandable that when it is determined that the resource usage of the compiled instruction sequence is unreasonable based on the compression of instructions with dependencies, the optimization methods that can be determined should be more than the above examples. As long as the optimization of the compiled instruction sequence can be achieved, the embodiments of the present disclosure do not limit the optimization methods that can be determined.

[0130] In this way, the resource usage rationality of the compiled instruction sequence can be judged based on whether the instructions with dependencies are compressible, making the method of determining the resource usage rationality more flexible.

[0131] In a possible implementation, step S23 includes:

[0132] For any instruction in the compiled instruction sequence, if it is determined based on the type of the instruction that the execution time of the instruction is greater than a second threshold, and if there are other instructions in the compiled instruction sequence that have no dependency on the instruction following the instruction, then it is determined that the resource usage of the compiled instruction sequence is unreasonable;

[0133] The optimization method includes moving the execution order of other instructions that have no dependency on this instruction forward.

[0134] For example, some instructions take a short time to execute, while others take a long time to execute. A second threshold can be preset, and instructions with execution times greater than the second threshold are considered "long-latency instructions." If a subsequent instruction is required to execute only after the previous instruction has completed, and the previous instruction is a long-latency instruction, then the backlog of instructions waiting to be executed will increase. If the subsequent instruction doesn't have a dependency on the previous instruction, then the subsequent instruction doesn't actually have to execute only after the previous instruction has completed.

[0135] Therefore, for any instruction in the compilation instruction sequence, when it is determined based on the type of the instruction that the execution time of the instruction is greater than the second threshold, and in the compilation instruction sequence, when there are other instructions that have no dependency relationship with the instruction after the instruction, it can be determined that the resource usage of the compilation instruction sequence is unreasonable. And the optimization method at this time may include moving the execution order of other instructions that have no dependency relationship with the instruction forward. The degree of forward movement may be to move forward to execute simultaneously with the instruction whose execution time is greater than the second threshold, or to move forward to execute after the instruction that has a dependency relationship with other instructions, and the present disclosure does not impose any restrictions on this.

[0136] In this way, unreasonable resource usage caused by unreasonable setting of instruction execution order can be detected, and an adaptive optimization method can be given for optimizing the execution order of instructions, making the method of determining the rationality of resource usage and the selection of optimization method more flexible.

[0137] The above-mentioned examples of methods for judging the rationality of resource usage of compilation instruction sequences are all applicable to compilation instruction sequences with a single-layer structure. In some scenarios, the compilation instruction sequence may have a multi-layer nested structure due to instructions such as loops and branches. The predefined data structure described above can also be set to include a hierarchical structure (single or multi-layer nested) of instruction sequences. In this case, the resource rationality of the instructions in each layer of the structure can be judged separately. The judgment method is similar to the method for judging the rationality of resource usage of the compilation instruction sequence. The compilation instruction sequence can be replaced with an instruction segment in a layer of structure. When giving an optimization method, an optimization method for the resources used by the instruction segments in a layer of structure can also be given.

[0138] In a possible implementation, when the compilation instruction sequence is a multi-layer nested structure, the method further includes:

[0139] Taking any instruction in the compiled instruction sequence as the current instruction, and tracing other instructions in the compiled instruction sequence that are executed before the current instruction and involve the source operand address of the current instruction according to the source operand address of the current instruction;

[0140] Determine whether a read / write behavior conflict occurs in the source operand address of the current instruction based on the traced instructions;

[0141] When a read / write behavior conflict occurs, the read / write behavior conflict is output in log form.

[0142] For example, the same resource may be used by multiple instructions simultaneously. Some instructions use the resource as a source operand address to read the resource, while other instructions use the resource as a destination operand address to write the resource. However, a resource cannot be read and written simultaneously, so a read / write conflict may occur.

[0143] To this end, any instruction in the compiled instruction sequence can be used as the current instruction. Based on the source operand address of the current instruction, other instructions in the compiled instruction sequence that were executed before the current instruction and involve the source operand address of the current instruction can be tracked. Based on the tracked instructions, it can be determined whether a read / write behavior conflict occurs with the source operand address of the current instruction. The method for determining a read / write behavior conflict can be implemented based on existing technologies and will not be further described here.

[0144] When a read / write conflict occurs, the conflict can be logged. In this case, after subsequent optimization, the conflict location recorded in the log can be used to verify whether the optimization has eliminated the conflict. This verification method can be implemented based on existing technologies and will not be detailed here.

[0145] In a possible implementation, the method further includes:

[0146] Determine a tag value of a nesting level corresponding to each instruction of the compiled instruction sequence;

[0147] According to the tag value, visualization data of the nested hierarchical structure of the compilation instruction sequence is determined, and the visualization data is output in the form of a log.

[0148] For example, the nesting level of a compilation instruction sequence is difficult to reflect in the code. In this regard, for a compilation instruction sequence with a multi-layer nested structure, the tag value of the nesting level corresponding to each instruction can be determined, and the tag value can also be stored in the compilation instruction sequence fragment information table. Visual data of the nested hierarchy structure of the compilation instruction sequence can be determined based on the tag value. The visual data can be output in the form of a log for easy observation by the user. When determining the optimization method, it can be determined based on the visual data that when the compilation instruction sequence has a large number of nested levels, an optimization method that can reduce the number of nested levels can be given, etc.

[0149] In one possible implementation, when the resources include temporary registers and relay registers, and the temporary registers store integer data and / or floating-point data used when executing a compiled instruction sequence, the optimization method includes:

[0150] Use relay registers instead of temporary registers to store integer and / or floating-point data.

[0151] For example, the optimization can be based on the hardware performance of the resource. For example, the hardware performance of the relay register is better than that of the temporary register. Therefore, when the temporary register stores integer data and / or floating-point data used when the compiled instruction sequence is executed, the optimization method can be to use the relay register instead of the temporary register to store integer data and / or floating-point data. It can be understood that the data types that can be replaced and stored should not only be integer data and / or floating-point data, and the objects that can be replaced can be more than temporary registers. Other resources can also be used to replace temporary registers. As long as the resource storage structure is optimized by replacing the resources, the embodiments of the present disclosure do not limit this.

[0152] In actual applications, one or more of the above-mentioned judgment methods for the rationality of resource utilization can be selected to judge the rationality of resource utilization. Accordingly, when outputting the optimization method, one or more of the above-mentioned optimization methods can also be output. The embodiments of the present disclosure do not limit the specific judgment method used and the specific output optimization method.

[0153] The present disclosure also provides an analysis device. Figure 4 A schematic diagram showing the structure of a parsing device according to an embodiment of the present disclosure.

[0154] like Figure 4 As shown, the parsing device is used to parse and determine whether the compiler's compilation instruction sequence is optimizable, and the device includes:

[0155] An acquisition module 41 is configured to acquire the compilation instruction sequence obtained by the compiler compiling the current program code, where the compilation instruction sequence includes a plurality of instructions;

[0156] a first parsing module 42 for parsing the compiled instruction sequence and determining fields included in each instruction, wherein the fields indicate one or more of the type, source operand address, and destination operand address of the instruction;

[0157] A second parsing module 43 is configured to parse the fields and determine the rationality of resource usage of the compilation instruction sequence, wherein the resource includes a module with a storage function;

[0158] The first output module 44 is configured to determine, when the resource usage of the compilation instruction sequence is unreasonable, that the compilation instruction sequence can be optimized and output an optimization method for the compilation instruction sequence.

[0159] In one possible implementation, parsing the field and determining the rationality of resource usage of the compilation instruction sequence include: for each resource, counting the maximum number of the resource used by the compilation instruction sequence based on the source operand address and the destination operand address; determining, based on preset resource configuration parameters, the number of tasks allowed to be started when the resource is allocated to the compilation instruction sequence according to the maximum number, and the tasks are used to execute the compilation instruction sequence; when the minimum number of tasks allowed to be started corresponding to each resource is less than the number of active tasks required for task scheduling, determining that the resource usage of the compilation instruction sequence is unreasonable.

[0160] In one possible implementation, when the minimum number of tasks allowed to be started corresponding to each resource is less than the number of active tasks required for task scheduling, and the resources corresponding to the minimum value include vertex memory, the tasks include vertex tasks, and the optimization method includes reducing the amount of vertex memory required to be occupied by a single vertex task; when the minimum number of tasks allowed to be started corresponding to each resource is less than the number of active tasks required for task scheduling, and the resources corresponding to the minimum value include general data registers, the optimization method includes moving out invalid data in the general data registers.

[0161] In one possible implementation, parsing the field and judging the rationality of resource usage of the compilation instruction sequence include: determining the lifecycle of resources used by the compilation instruction sequence based on the type of the instruction, the source operand address, and the destination operand address; determining the number of resources used when executing each instruction based on the lifecycle of the resources used by the compilation instruction sequence; determining the minimum number of resources used to execute the compilation instruction sequence based on the number of resources used when executing each instruction; and judging that the resource usage of the compilation instruction sequence is unreasonable when the minimum number is less than the actual number of resources used to execute the compilation instruction sequence.

[0162] In one possible implementation, when the minimum number is less than the actual number of resources used to execute the compiled instruction sequence, the optimization method includes: selecting a resource whose life cycle is less than a first threshold and is only used as the source operand address, and replacing the resource that is only used as the destination operand address.

[0163] In one possible implementation, parsing the field and determining the rationality of resource usage of the compilation instruction sequence include: determining the dependency relationship of each instruction in the compilation instruction sequence based on the source operand address and the destination operand address; determining whether the instructions with the dependency relationship are compressible based on the source operand address and the destination operand address of the instructions with the dependency relationship; and determining that the resource usage of the compilation instruction sequence is unreasonable when the instructions with the dependency relationship are compressible.

[0164] In one possible implementation, when the instructions with dependencies are compressible, the optimization method includes: compressing the instructions with dependencies, wherein the resources that are only used as source operand addresses in the instructions with dependencies are used as source operand addresses of the compressed instructions; the resources that are only used as destination operand addresses in the instructions with dependencies are used as destination operand addresses of the compressed instructions; and determining the type of the compressed instructions according to the type of the dependencies.

[0165] In one possible implementation, parsing the field and determining the rationality of resource usage of the compilation instruction sequence includes: for any instruction in the compilation instruction sequence, determining, based on the type of the instruction, that the execution time of the instruction is greater than a second threshold, and when, in the compilation instruction sequence, there are other instructions following the instruction that have no dependency on the instruction, determining that the resource usage of the compilation instruction sequence is unreasonable; and the optimization method includes moving the execution order of the other instructions that have no dependency on the instruction forward.

[0166] In a possible implementation, when the compilation instruction sequence is a multi-layer nested structure, the apparatus further includes:

[0167] a tracing module, configured to take any instruction in the compiled instruction sequence as a current instruction and, based on a source operand address of the current instruction, trace other instructions in the compiled instruction sequence that are executed before the current instruction and involve the source operand address of the current instruction;

[0168] A judgment module, configured to judge whether a read / write conflict occurs in a source operand address of the current instruction according to the tracked instruction;

[0169] The second output module is used to output the read / write behavior conflict in the form of a log when a read / write behavior conflict occurs.

[0170] In a possible implementation, the apparatus further includes:

[0171] A determination module, configured to determine a tag value of a nesting level corresponding to each instruction of the compilation instruction sequence;

[0172] The third output module is configured to determine visual data of the nested hierarchical structure of the compilation instruction sequence according to the tag value, and output the visual data in a log format.

[0173] In one possible implementation, the resources include temporary registers and relay registers, and when the temporary registers store integer data and / or floating-point data used when the compiled instruction sequence is executed, the optimization method includes: using the relay registers instead of the temporary registers to store the integer data and / or the floating-point data.

[0174] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments. For the sake of brevity, it will not be repeated here.

[0175] The present disclosure also provides a computer-readable storage medium having computer program instructions stored thereon, wherein the computer program instructions implement the above method when executed by a processor. The computer-readable storage medium may be a volatile or non-volatile computer-readable storage medium.

[0176] An embodiment of the present disclosure further proposes an electronic device, comprising: a processor; and a memory for storing instructions executable by the processor; wherein the processor is configured to implement the above method when executing the instructions stored in the memory.

[0177] An embodiment of the present disclosure also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

[0178] Figure 5 FIG1 shows a block diagram of an apparatus 1900 according to an embodiment of the present disclosure. For example, the apparatus 1900 may be provided as an electronic device. Figure 5 The apparatus 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions, such as an application, that can be executed by the processing component 1922. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute the instructions to perform the above-described method.

[0179] The device 1900 may also include a power supply component 1926 configured to perform power management of the device 1900, a wired or wireless network interface 1950 configured to connect the device 1900 to a network, and an input / output interface 1958 (I / O interface). The device 1900 may operate based on an operating system stored in the memory 1932, such as Windows Server 2003. TM , MacOS X TM, Unix TM ,Linux TM , FreeBSD TM or similar.

[0180] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by the processing component 1922 of the apparatus 1900 to perform the above-described method.

[0181] The present disclosure may be a system, method and / or computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0182] A computer-readable storage medium can be a tangible device that can hold and store instructions for use by an instruction execution device. A computer-readable storage medium can be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination thereof. As used herein, a computer-readable storage medium is not to be construed as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through an electrical wire.

[0183] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in the computer-readable storage medium in each computing / processing device.

[0184] The computer program instructions for performing the operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, and conventional procedural programming languages ​​such as "C" language or similar programming languages. Computer-readable program instructions may be executed entirely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., utilizing an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be personalized by utilizing the state information of the computer-readable program instructions. The electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0185] Various aspects of the present disclosure are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0186] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device is generated that implements the functions / actions specified in one or more blocks in the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, where these instructions cause the computer, programmable data processing device, and / or other device to operate in a specific manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing various aspects of the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0187] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0188] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the systems, methods and computer program products according to multiple embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and the part of the module, program segment or instruction contains one or more executable instructions for realizing the prescribed logical function. In some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the prescribed function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0189] While various embodiments of the present disclosure have been described above, the foregoing description is intended to be illustrative, non-exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or technological improvements in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A parsing method, characterized in that: The method for analyzing and determining whether a compilation instruction sequence of a compiler is optimizable includes: Obtaining the compilation instruction sequence obtained by the compiler compiling the current program code, the compilation instruction sequence including a plurality of instructions; Parsing the compiled instruction sequence to determine fields included in each instruction, where the fields indicate one or more of a type of the instruction, a source operand address, and a destination operand address; parsing the fields to determine rationality of resource usage of the compilation instruction sequence, wherein the resources include a module with a storage function; When resource usage of the compilation instruction sequence is unreasonable, determining that the compilation instruction sequence can be optimized, and outputting an optimization method for the compilation instruction sequence; The unreasonable resource usage of the compilation instruction sequence includes at least one of the following situations: The minimum number of tasks allowed to be started corresponding to each resource is less than the number of active tasks required for task scheduling, wherein each resource is a resource used to execute the compiled instruction sequence, the task is used to execute the compiled instruction sequence, and the number of active tasks required for task scheduling is a preset value used to hide switching overhead or delay when switching tasks; The minimum number of resources used to execute the compiled instruction sequence is less than the actual number of resources used to execute the compiled instruction sequence; the minimum number is determined based on the number of resources used when executing each instruction, and the number of resources used when executing each instruction is determined based on the life cycle of the resources used by the compiled instruction sequence; Each instruction in the compilation instruction sequence includes instructions with dependency relationships, and the instructions with dependency relationships are compressible; any instruction in the compiled instruction sequence, where the execution time of the instruction is determined to be greater than a second threshold based on the type of the instruction, and other instructions that have no dependency on the instruction exist after the instruction in the compiled instruction sequence; Among them, when the minimum number of resources used to execute the compiled instruction sequence is less than the actual number of resources used to execute the compiled instruction sequence, the optimization method of the compiled instruction sequence includes: selecting a resource with the shortest life cycle or a life cycle less than a first threshold and only used as the source operand address, replacing the resource used only as the destination operand address, when any resource is used as a source operand address by any instruction, the life cycle of the resource includes the execution time of the instruction and other instructions executed before the instruction; when any resource is used as a destination operand address by any instruction, the life cycle of the resource includes the execution time of the instruction.

2. The method according to claim 1, characterized in that The parsing of the fields to determine rationality of resource usage of the compilation instruction sequence includes: For each resource, counting the maximum number of the resource used by the compiled instruction sequence according to the source operand address and the destination operand address; Determining, based on preset resource configuration parameters, the number of tasks allowed to be started when allocating the resource to the compiled instruction sequence according to the maximum number; When the minimum number of tasks allowed to be started corresponding to each resource is less than the number of active tasks required for task scheduling, it is determined that the resource usage of the compilation instruction sequence is unreasonable.

3. The method according to claim 2, characterized in that When a minimum number of tasks allowed to be started corresponding to each resource is less than the number of active tasks required for task scheduling, and the resource corresponding to the minimum number includes a vertex memory, the task includes a vertex task, and the optimization method includes reducing the amount of vertex memory required to be occupied by a single vertex task; When the minimum number of tasks allowed to be started corresponding to each resource is less than the number of active tasks required for task scheduling, and the resources corresponding to the minimum value include general data registers, the optimization method includes removing invalid data in the general data registers.

4. The method according to claim 1, wherein The parsing of the fields to determine rationality of resource usage of the compilation instruction sequence includes: Determining a life cycle of resources used by the compiled instruction sequence according to the type of the instruction, the source operand address, and the destination operand address; determining, based on a lifecycle of resources used by the compiled instruction sequence, an amount of resources used when executing each instruction; Determining a minimum number of resources used to execute the compiled instruction sequence based on the number of resources used when executing each instruction; When the minimum number is less than the actual number of resources used to execute the compiled instruction sequence, it is determined that the resource usage of the compiled instruction sequence is unreasonable.

5. The method according to claim 1, wherein The parsing of the fields to determine rationality of resource usage of the compilation instruction sequence includes: Determining the dependency relationship of each instruction in the compiled instruction sequence according to the source operand address and the destination operand address; Determining whether the instructions with the dependency relationship are compressible according to the source operand addresses and the destination operand addresses of the instructions with the dependency relationship; When the instructions with the dependency relationship are compressible, it is determined that resource usage of the compiled instruction sequence is unreasonable.

6. The method according to claim 5, characterized in that When the instructions with dependencies are compressible, the optimization method includes: Compress the instructions with dependencies, wherein: Using the resources used only as source operand addresses in the instructions with dependency as the source operand addresses of the compressed instructions; Using the resource that is only used as the destination operand address in the instructions with dependency as the destination operand address of the compressed instruction; The type of the compressed instruction is determined according to the type of the dependency relationship.

7. The method according to claim 1, characterized in that The parsing of the fields to determine rationality of resource usage of the compilation instruction sequence includes: For any instruction in the compiled instruction sequence, if, based on the type of the instruction, the execution time of the instruction is greater than a second threshold, and if, in the compiled instruction sequence, there are other instructions following the instruction that have no dependency on the instruction, then determining that resource usage of the compiled instruction sequence is unreasonable; The optimization method includes moving the execution order of other instructions that have no dependency on the instruction forward.

8. The method according to claim 1, characterized in that When the compilation instruction sequence is a multi-layer nested structure, the method further includes: Taking any instruction in the compiled instruction sequence as a current instruction, and tracing other instructions in the compiled instruction sequence that are executed before the current instruction and involve the source operand address of the current instruction according to the source operand address of the current instruction; Determining whether a read / write behavior conflict occurs in a source operand address of the current instruction according to the traced instruction; When a read / write behavior conflict occurs, the read / write behavior conflict is output in log form.

9. The method according to claim 8, characterized in that The method further comprises: Determining a tag value of a nesting level corresponding to each instruction of the compilation instruction sequence; Visual data of the nested hierarchical structure of the compilation instruction sequence is determined according to the tag value, and the visual data is output in a log form.

10. The method according to claim 1, characterized in that When the resource includes a temporary register and a relay register, and the temporary register stores integer data and / or floating-point data used when the compiled instruction sequence is executed, the optimization method includes: The relay register is used instead of the temporary register to store the integer data and / or the floating-point data.

11. An analysis device, characterized in that: The apparatus is used to analyze and determine whether a compilation instruction sequence of a compiler is optimizable, and includes: an acquisition module, configured to acquire the compilation instruction sequence obtained by the compiler compiling the current program code, wherein the compilation instruction sequence includes a plurality of instructions; a first parsing module, configured to parse the compiled instruction sequence and determine fields included in each instruction, wherein the fields indicate one or more of a type of the instruction, a source operand address, and a destination operand address; a second parsing module, configured to parse the fields and determine rationality of resource usage of the compilation instruction sequence, wherein the resources include a module with a storage function; a first output module, configured to determine, when resource usage of the compilation instruction sequence is unreasonable, that the compilation instruction sequence can be optimized, and output an optimization method for the compilation instruction sequence; The unreasonable resource usage of the compilation instruction sequence includes at least one of the following situations: The minimum number of tasks allowed to be started corresponding to each resource is less than the number of active tasks required for task scheduling, wherein each resource is a resource used to execute the compiled instruction sequence, the task is used to execute the compiled instruction sequence, and the number of active tasks required for task scheduling is a preset value used to hide switching overhead or delay when switching tasks; The minimum number of resources used to execute the compiled instruction sequence is less than the actual number of resources used to execute the compiled instruction sequence; the minimum number is determined based on the number of resources used when executing each instruction, and the number of resources used when executing each instruction is determined based on the life cycle of the resources used by the compiled instruction sequence; Each instruction in the compilation instruction sequence includes instructions with dependency relationships, and the instructions with dependency relationships are compressible; any instruction in the compiled instruction sequence, where the execution time of the instruction is determined to be greater than a second threshold based on the type of the instruction, and other instructions that have no dependency on the instruction exist after the instruction in the compiled instruction sequence; Among them, when the minimum number of resources used to execute the compiled instruction sequence is less than the actual number of resources used to execute the compiled instruction sequence, the optimization method of the compiled instruction sequence includes: selecting a resource with the shortest life cycle or a life cycle less than a first threshold and only used as the source operand address, replacing the resource used only as the destination operand address, when any resource is used as a source operand address by any instruction, the life cycle of the resource includes the execution time of the instruction and other instructions executed before the instruction; when any resource is used as a destination operand address by any instruction, the life cycle of the resource includes the execution time of the instruction.

12. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to implement the method according to any one of claims 1 to 10 when executing the instructions stored in the memory.

13. A non-volatile computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 10 is implemented.

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