A quantum chip, a preparation method thereof and a quantum computer

Abstract

The application discloses a quantum chip, a preparation method thereof and a quantum computer, and belongs to the field of quantum information. The quantum chip comprises a first quantum bit and a second quantum bit, and a coupling structure which is not coplanar with the first quantum bit and the second quantum bit, the frequency of the coupling structure is tunable, one end of the coupling structure is coupled with the first quantum bit, and the other end of the coupling structure is coupled with the second quantum bit. The preparation method comprises the following steps: forming a first quantum bit and a second quantum bit; and forming a coupling structure which is not coplanar with the first quantum bit and the second quantum bit, the frequency of the coupling structure is tunable, one end of the coupling structure is coupled with the first quantum bit, and the other end of the coupling structure is coupled with the second quantum bit. Since the coupling structure does not occupy the space where the quantum bits are located, the integration and expansion of the quantum bits are facilitated, and the integration and expansion degree of the quantum bits is improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of quantum information, in particular, the field of quantum computing technology, and particularly relates to a quantum chip, a preparation method thereof and a quantum computer. BACKGROUND

[0002] A quantum computer is a physical device that performs high-speed mathematical and logical operations, stores and processes quantum information in accordance with the laws of quantum mechanics. The quantum computer has the characteristics of fast operation, strong information processing capacity, and wide application range. Compared with general computers, the more information processing, the more advantageous the quantum computer is in operation, and the more accurate the operation can be ensured.

[0003] Superconducting quantum computing can use micro-nano processing technology to prepare quantum bits on a substrate, and has superior performance such as integration and scalability. In recent years, superconducting quantum computing has developed rapidly, but the structure form conducive to the integration and expansion of quantum chips needs to be further optimized. CONTENT OF THE INVENTION

[0004] In order to facilitate the integration and expansion of quantum chips, the present application provides a quantum chip, a preparation method thereof and a quantum computer to solve the problems in the prior art.

[0005] One aspect of the present application provides a quantum chip, comprising: a first quantum bit and a second quantum bit; and a coupling structure not coplanar with the first quantum bit and the second quantum bit, the coupling structure being frequency tunable, one end of the coupling structure being coupled to the first quantum bit, and the other end of the coupling structure being coupled to the second quantum bit.

[0006] The quantum chip as described above, in an embodiment, the first quantum bit and the second quantum bit are located on a first surface, the coupling structure is located on a second surface, and the first surface and the second surface are located on opposite surfaces of the same substrate.

[0007] The quantum chip as described above, in an embodiment, the coupling structure comprises: a superconducting quantum interference device; a first capacitive element connected to one end of the superconducting quantum interference device, and the first capacitive element being capacitively coupled to the first quantum bit; and a second capacitive element connected to the other end of the superconducting quantum interference device, and the second capacitive element being capacitively coupled to the second quantum bit.

[0008] The quantum chip as described above, in an embodiment, the first quantum bit is located on a first substrate, the second quantum bit is located on a second substrate, and the coupling structure is located on a third substrate, and the first substrate and the second substrate are interconnected with the third substrate.

[0009] The quantum chip as claimed in the preceding article, in an embodiment, the first substrate and the second substrate are on the same side of the third substrate.

[0010] The quantum chip as claimed in the preceding article, in an embodiment, the first substrate and the second substrate are on opposite sides of the third substrate.

[0011] The quantum chip as claimed in the preceding article, in an embodiment, the coupling structure comprises: a superconducting quantum interference device; a first capacitive element connected to one end of the superconducting quantum interference device, and the first capacitive element is opposite to the first quantum bit to form a capacitive coupling; and a second capacitive element connected to the other end of the superconducting quantum interference device, the second capacitive element and the first capacitive element are formed on opposite sides of the third substrate, and the second capacitive element is opposite to the second quantum bit to form a capacitive coupling.

[0012] The quantum chip as claimed in the preceding article, in an embodiment, the first quantum bit and the second quantum bit each comprise a Josephson junction with a nonlinear inductance, the Josephson junction comprises a first superconductor, a barrier layer and a second superconductor which are stacked; and an equivalent capacitance formed between the first superconductor and the second superconductor forms a non-uniform energy level with the nonlinear inductance.

[0013] The quantum chip as claimed in the preceding article, in an embodiment, the second superconductor comprises a first part and a second part which are spaced apart on the barrier layer, and the first part and the second part are electrically connected.

[0014] The quantum chip as claimed in the preceding article, in an embodiment, the first part and the second part are electrically connected by an air bridge.

[0015] Another aspect of the present application provides a method for preparing a quantum chip, comprising the following steps: forming a first quantum bit and a second quantum bit; and forming a coupling structure which is not coplanar with the first quantum bit and the second quantum bit, the frequency of the coupling structure is tunable, one end of the coupling structure is coupled to the first quantum bit, and the other end is coupled to the second quantum bit.

[0016] The method for preparing a quantum chip as claimed in the preceding article, in an embodiment, the step of forming a first quantum bit and a second quantum bit comprises forming a first quantum bit on a first substrate and forming a second quantum bit on a second substrate; the step of forming a coupling structure which is not coplanar with the first quantum bit and the second quantum bit comprises forming a coupling structure on a third substrate, and the first substrate and the second substrate are interconnected with the third substrate.

[0017] The preparation method as described above, in an embodiment, the first substrate and the second substrate are on the same side of the third substrate.

[0018] The preparation method as described above, in an embodiment, the first substrate and the second substrate are on the opposite side of the third substrate.

[0019] The third aspect of the present application also provides a quantum computer comprising the quantum chip as described above.

[0020] Compared with the related art, the quantum chip involved in the scheme provided in the present application has a frequency-tunable coupling structure which is non-coplanar with the first quantum bit and the second quantum bit, and one end of the coupling structure is coupled to the first quantum bit and the other end is coupled to the second quantum bit, thereby realizing the regulation of the coupling strength between the first quantum bit and the second quantum bit. Since the coupling structure does not occupy the space where the quantum bits are located, it is conducive to the integration and expansion of the quantum bits, and improves the integration and expansion degree of the quantum bits. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 A structural diagram of quantum bits arranged on a quantum chip in the related art;

[0022] Figure 2 A structural diagram of a quantum chip provided in the first embodiment of the present application;

[0023] Figure 3 A structural diagram of a quantum chip provided in the second embodiment of the present application;

[0024] Figure 4 A structural diagram of a quantum chip provided in the third embodiment of the present application;

[0025] Figure 5 A structural diagram of a quantum bit provided in an embodiment of the present application;

[0026] Figure 6 A flowchart of a preparation method of a quantum chip provided in an embodiment of the present application.

[0027] REFERENCE SIGNS:

[0028] 1-substrate, 2-quantum bit, 3-coupling structure, 4-first interconnection element, 5-second interconnection element;

[0029] 11-first substrate, 12-second substrate, 13-third substrate;

[0030] 21-first quantum bit, 22-second quantum bit;

[0031] 31 - superconducting quantum interference device, 32 - first capacitive element, 33 - second capacitive element;

[0032] 201 - Josephson junction, 2011 - first superconductor, 2012 - barrier layer, 2013 - second superconductor, 20131 - first portion, 20132 - second portion, 2014 - air bridge. DETAILED DESCRIPTION

[0033] The embodiments described below are exemplary and are intended to be illustrative of the application, but are not to be construed as limiting the application.

[0034] So that the manner in which the above recited features, advantages and objects of the present application are attained and can be understood in detail, a more particular description of one or more embodiments of the application will be rendered by reference to the appended drawings. Understanding that the drawings depict only one or a preferred embodiment of the application and are not therefore to be considered to be limiting of its scope, the embodiments will be described and explained with additional specificity and detail through the use of the accompanying drawings.

[0035] It should be noted that the terms "first", "second", and the like, used in the description and in the claims of the present application are used to briefly and easily identify one element from another, and do not necessarily indicate a particular order or a particular order of succession. It should be understood that the terms as used herein can be interchanged, as appropriate, to refer to the same element in different embodiments of the application. In addition, the terms "comprise" and "have" and any variations thereof are intended to cover a non-exclusive inclusion, for example, a process, method, system, product or apparatus that includes a list of steps or units not necessarily limited to those clearly identified, but can include other not clearly identified steps or units that are inherent to such processes, methods, products or apparatus.

[0036] In addition, it should be understood that when a layer (or film), region, pattern or structure is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, and / or intervening layers can also be present. In addition, it should be understood that when a layer is referred to as being "under" another layer, it can be directly under the other layer, and / or one or more intervening layers can also be present. In addition, references to "on" and "under" can be made with respect to the drawings.

[0037] According to different physical systems for constructing qubits, qubits include superconducting quantum circuits, semiconductor quantum dots, ion traps, diamond vacancies, topological quantum, photons and the like in physical implementation. Superconducting quantum computing is currently the fastest and best solid quantum computing implementation method. Since the energy level structure of the superconducting quantum circuit can be regulated by an external electromagnetic signal, the controllability of the circuit design customization is strong. At the same time, benefiting from the existing mature integrated circuit process, the superconducting quantum circuit has scalability that is difficult to match by multiple quantum physical systems.

[0038] Figure 1 A schematic diagram of the structure of qubits arranged on a quantum chip in the related art.

[0039] The key component of a superconducting quantum chip is a Josephson junction. Transmons are a commonly used quantum bit structure of a superconducting quantum chip. The basic idea is to form an energy level system by connecting a Josephson junction in parallel with an extra constructed capacitor plate, combined with a superconducting quantum interference device (squid) connected to the capacitor plate. Figure 1 As shown in FIG. 1, the structure of a quantum bit often uses a single ground-connected capacitor, and a superconducting quantum interference device connected to the ground at one end and to the capacitor at the other end. The capacitor is often a cross-shaped parallel plate capacitor, as shown in FIG. 2. Figure 1 As shown in FIG. 2, the cross-shaped capacitor plate C q is surrounded by a ground plane (GND), and the cross-shaped capacitor plate C q has a gap between the ground plane (GND). One end of the superconducting quantum interference device squid is connected to the cross-shaped capacitor plate C q , and the other end is connected to the ground plane (GND). Since the first end of the cross-shaped capacitor plate C q is usually used to connect the superconducting quantum interference device squid, the second end is used to couple with the readout resonator, and a certain space is needed near the first and second ends for wiring, for example, space is needed near the first end to arrange the xy signal line and the z signal line, and the other two ends of the cross-shaped capacitor plate C q are used to couple with adjacent qubits. This structure has a great limitation for the expansion of the number of qubits. The capacitor plate connected in parallel with the Josephson junction occupies a large area, which to some extent limits the expansion of qubits.

[0040] In order to facilitate the integration and expansion of quantum chips, the present application provides a quantum chip, a preparation method thereof and a quantum computer to solve the problems in the prior art. The coupling structure for regulating the coupling strength between the first qubit and the second qubit is arranged in a form that is not coplanar with the first qubit and the second qubit. Since the coupling structure does not occupy the space of the qubits, it is beneficial to the integration and expansion of qubits, and improves the degree of integration and expansion of qubits.

[0041] Figure 2A structural schematic diagram of a quantum chip provided for a first embodiment of the present application.

[0042] Figure 3 A structural schematic diagram of a quantum chip provided for a second embodiment of the present application.

[0043] Figure 4 A structural schematic diagram of a quantum chip provided for a third embodiment of the present application.

[0044] Referring to Figure 2 , Figure 3 and Figure 4 , and in combination with Figure 1 , the embodiments of the present application provide a quantum chip on which a quantum bit 2 and a coupling structure 3 are formed, the coupling structure 3 is used to realize the coupling between the quantum bits 2, in order to facilitate the expansion of the number of quantum bits 2, the quantum chip comprises: a first quantum bit 21 and a second quantum bit 22; and the coupling structure 3 which is not coplanar with the first quantum bit 21 and the second quantum bit 22, the frequency of the coupling structure 3 is tunable, and one end of the coupling structure 3 is coupled to the first quantum bit 2122 and the other end is coupled to the second quantum bit. It can be understood that in the embodiments provided by the present application, since the coupling structure 3 does not occupy the space where the quantum bits 2 are located, it is beneficial to the integrated expansion of the quantum bits 2, and the integrated expansion degree of the quantum bits 2 is improved.

[0045] In some embodiments of the present application, the first qubit 21 and the second qubit 22 are located on a first surface, and the coupling structure 3 is located on a second surface, and the first surface and the second surface are located on opposite surfaces of the same substrate 1. The circuit for arranging qubits 2 and the circuit for coupling structure 3 are respectively constructed on the top surface and the bottom surface of the same substrate 1, so as to reduce the influence of the area occupation of the coupling structure 3 on the expansion of the number of qubits 2, and facilitate the expansion integration of a larger number of qubits 2. In some examples, the coupling structure 3 includes: a superconducting quantum interference device 31 (squid); a first capacitive element 32 connected to one end of the superconducting quantum interference device 31 (squid), and the first capacitive element 32 is capacitively coupled to the first qubit 21; and a second capacitive element 33 connected to the other end of the superconducting quantum interference device 31 (squid), and the second capacitive element 33 is capacitively coupled to the second qubit 22. Wherein, the first capacitive element 32 and the first qubit 21 can form a capacitive coupling through a first TSV structure, and the second capacitive element 33 and the second qubit 22 can form a capacitive coupling through a second TSV structure. For example, the first qubit 21 and the second qubit 22 are both located on the top surface of the substrate 1, and the first capacitive element 32, the second capacitive element 33 and the superconducting quantum interference device 31 (squid) are all located on the bottom surface. In addition, a first TSV structure is formed through the top surface and the bottom surface, one end of the first TSV structure is connected to the first capacitive element 32, and the other end is connected to a pad capacitor. The first capacitive element 32 forms a capacitive coupling with the first qubit 21 through the pad capacitor.

[0046] In some embodiments of the present application, the first quantum bit 21 is located on the first substrate 11, the second quantum bit 22 is located on the second substrate 12, and the coupling structure 3 is located on the third substrate 13. In some embodiments of the present application, the first substrate 11 is interconnected with the third substrate 13 through the first interconnection element 4, and the second substrate 12 is interconnected with the third substrate 13 through the second interconnection element 5. In some embodiments of the present application, the first substrate 11 and the second substrate 12 are located on the same side of the third substrate 13, i.e., the first substrate 11 and the second substrate 12 are extended in a tiled manner with respect to the third substrate 13. In some embodiments of the present application, the first substrate 11 and the second substrate 12 are located on opposite sides of the third substrate 13, i.e., the first substrate 11 and the second substrate 12 are extended in a stacked manner. In some embodiments of the present application, the coupling structure 3 located on the third substrate 13 includes a superconducting quantum interference device 31 (squid), a first capacitive element 32 connected to one end of the superconducting quantum interference device 31 (squid), and a second capacitive element 33 connected to the other end of the superconducting quantum interference device 31 (squid). The first capacitive element 32 is located on the opposite side of the second capacitive element 33 with respect to the superconducting quantum interference device 31 (squid). The first capacitive element 32 is opposite to the first quantum bit 21 to form a capacitive coupling. The second capacitive element 33 is opposite to the second quantum bit 22 to form a capacitive coupling. In some embodiments of the present application, the first capacitive element 32 and the superconducting quantum interference device 31 (squid) are located on the top surface of the third substrate 13, the second capacitive element 33 is located on the bottom surface of the third substrate 13, and the second capacitive element 33 and the superconducting quantum interference device 31 (squid) can be electrically connected through a TSV structure penetrating the top surface and the bottom surface of the third substrate 13. In some embodiments of the present application, the first quantum bit 21 on the first substrate 11 is opposite to the top surface of the third substrate 13, and the second quantum bit 22 on the second substrate 12 is opposite to the bottom surface of the third substrate 13, so as to realize the extension in a stacked manner and ensure that the first capacitive element 32 and the first quantum bit 21 form a capacitive coupling and the second capacitive element 33 and the second quantum bit 22 form a capacitive coupling.

[0047] Figure 5 A schematic diagram of a quantum bit structure is provided for an embodiment of the present application.

[0048] Referring to Figure 5 and combiningFigures 1 to 4 As shown, in some embodiments of the present application, the second quantum bit 2 comprises a Josephson junction 201 with a nonlinear inductance, the Josephson junction 201 comprises a first superconductor 2011, a barrier layer 2012 and a second superconductor 2013 which are stacked; and an equivalent capacitance formed between the first superconductor 2011 and the second superconductor 2013 forms a non-uniform energy level system with the nonlinear inductance. The quantum bit 2 provided by the present application is constructed by using the nonlinear inductance of the Josephson junction 201, and the non-uniform energy level system formed by the equivalent capacitance between the first superconductor 2011 and the second superconductor 2013 of the Josephson junction 201. It can be understood that, compared with the structure of the quantum bit in the related art which uses a Josephson junction and an extra constructed capacitor plate in parallel to form an energy level system, the capacitor formed by the structure of the Josephson junction 201 itself replaces the extra constructed capacitor plate in the related art, which can avoid the problem that the capacitor plate occupies a large area and limits the planar expansion of the quantum bit 2. In the non-uniform energy level system, the uneven distribution of each energy level ensures that the energy level difference between any energy level and its adjacent low energy level, and the energy level difference between the any energy level and its adjacent high energy level are not the same, and according to the requirements of the quantum bit related parameters, the nonlinear inductance and the equivalent capacitance can be designed to control the difference between the above two energy level differences to be between 170 MHZ and 200 MHZ, so as to increase the anharmonicity of the superconducting quantum bit, and then facilitate the manipulation of the quantum state. In order to make the area of the overall structure of the superconducting quantum bit small, the dielectric constant of the barrier layer 112 is greater than 10. It can be understood that, as the dielectric constant increases, the relative area required to reach the target capacitance value can be reduced. For example, the barrier layer 112 can be amorphous silicon, and the dielectric constant of amorphous silicon is greater than that of conventional crystalline silicon, which is easy to reach more than 10. In some examples, the area covered by the Josephson junction 11 is (2-5) μm x (2-5) μm, and the resistance of the Josephson junction 11 is (5-10) KΩ. The resistance of the Josephson junction 11 can be determined according to the target frequency, anharmonicity requirements and other requirements of the superconducting quantum bit 1.

[0049] In some embodiments of the present application, the second superconductor 2013 includes a first portion 20131 and a second portion 20132 arranged at intervals on the barrier layer 2012, and the first portion 20131 and the second portion 20132 are electrically connected. A Josephson junction 201 is formed between the first portion 20131, the barrier layer 2012, and the first superconductor 2011, another Josephson junction 201 is formed between the second portion 20132, the barrier layer 2012, and the first superconductor 2011, and the electrical connection between the first portion 20131 and the second portion 20132 ensures that the two Josephson junctions 201 are in a parallel structure, i.e., in the form of a superconducting quantum interference device 31 (squid). In some embodiments of the present application, the first portion 20131 and the second portion 20132 are electrically connected by an air bridge 2014.

[0050] It should be noted that the first superconductor 2011, the barrier layer 2012, and the second superconductor 2013 can be a medium layer with a specific pattern formed on a specified area of the surface of the substrate by a semiconductor process. In the embodiments provided in the present application, the first superconductor 2011, the barrier layer 2012, and the second superconductor 2013 are all long strips, the barrier layer 2012 is directly formed on the surface of the first superconductor 2011, and the second superconductor 113 can be directly formed on the surface of the barrier layer 2012 as a whole, or can be partially overlapped on the surface of the barrier layer 2012 in a staggered form with a different extension direction relative to the first superconductor 2011. The Josephson junction with nonlinear inductance can be obtained at the overlapping position of the first superconductor 2011, the barrier layer 2012, and the second superconductor 2013, and the equivalent capacitance formed between the first superconductor 2011 and the second superconductor 2013 is related to the shape and structure of the first superconductor 2011, the barrier layer 2012, and the second superconductor 2013 and the physical position relationship.

[0051] Figure 6 A flowchart of a preparation method of a quantum chip provided in an embodiment of the present application

[0052] Referring to Figure 6 and in combination with Figures 1 to 5 , the preparation method of a quantum chip provided in an embodiment of the present application includes the following steps S100 to S200, wherein:

[0053] Step S100, forming a first quantum bit 21 and a second quantum bit 22;

[0054] Step S200, a coupling structure 3 is formed which is not coplanar with the first quantum bit 21 and the second quantum bit 22, the frequency of the coupling structure 3 is tunable, and one end of the coupling structure 3 is coupled to the first quantum bit 21 and the other end is coupled to the second quantum bit 22.

[0055] In the embodiments provided in the present application, in the quantum chip prepared through steps S100 to S200, since the coupling structure 3 does not occupy the space where the quantum bit is located, it is beneficial to the integration and expansion of the quantum bit 2, and the integration and expansion degree of the quantum bit 2 is improved.

[0056] In some embodiments of the present application, the step of forming the first qubit 21 and the second qubit 22 includes forming the first qubit 21 on the first substrate 11 and forming the second qubit 22 on the second substrate 12, and the step of forming the coupling structure 3 non-coplanar with the first qubit 21 and the second qubit 22 includes forming the coupling structure 3 on the third substrate 13, and the first substrate 11 and the second substrate 12 are both interconnected with the third substrate 13, and the coupling structure 3 formed on the independent substrate establishes the coupling between the qubits 2 on different substrates, which can greatly expand the number of qubits 2, for example, a plurality of first substrates 11, a plurality of second substrates 12 and the same third substrate 13 are interconnected, and the first qubit 21 on the first substrate 11 and the second qubit 22 on the second substrate 12 are coupled by the coupling structure 3 on the third substrate 13. In an embodiment, the first substrate 11 and the second substrate 12 are on the same side of the third substrate 13, that is, relative to the third substrate 13, the first substrate 11 and the second substrate 12 are expanded in a tiled form. In another embodiment, the first substrate 11 and the second substrate 12 are on opposite sides of the third substrate 13, and are expanded in a stacked form. In some examples, the coupling structure 3 includes: a superconducting quantum interference device 31 (squid); a first capacitive element 32 connected to one end of the superconducting quantum interference device 31 (squid), and the first capacitive element 32 is opposite to the first qubit 21 to form a capacitive coupling; and a second capacitive element 33 connected to the other end of the superconducting quantum interference device 31 (squid), the second capacitive element 33 is formed on the opposite side of the first capacitive element 32 and the third substrate 13, and the second capacitive element 33 is opposite to the second qubit 22 to form a capacitive coupling, that is, the first capacitive element 32 and the superconducting quantum interference device 31 (squid) are located on the top surface of the third substrate 13, the second capacitive element 33 is located on the bottom surface of the third substrate 13, and the second capacitive element 33 and the superconducting quantum interference device 31 (squid) can be electrically connected through the TSV structure penetrating the top surface and the bottom surface of the third substrate 13, on this basis, the first qubit 21 on the first substrate 11 is opposite to the top surface of the third substrate 13, and the second qubit 22 on the second substrate 12 is opposite to the bottom surface of the third substrate 13, to realize the expansion in a stacked form while ensuring that the first capacitive element 32 and the first qubit 21 form a capacitive coupling, and the second capacitive element 22 and the second qubit 22 form a capacitive coupling.

[0057] The embodiment of the present application also provides a quantum computer, which comprises the quantum chip as described above. It can be understood that the quantum chip arranged in the quantum computer is similar to the structure of the quantum chip embodiment described above and has the same beneficial effects as the quantum chip embodiment described above, and thus is not described in detail. For technical details not disclosed in the quantum chip embodiment of the present application, those skilled in the art can refer to the description of the quantum chip described above for understanding, and for the sake of saving space, the description is not repeated here.

[0058] The above describes the structure, features and effects of the present application according to the embodiments shown in the drawings. The above description is only the preferred embodiment of the present application, but the present application is not limited to the embodiments shown in the drawings. Any change or modification made according to the concept of the present application or equivalent embodiment with equivalent changes within the scope of the description and drawings should be within the protection scope of the present application.

Claims

1. A quantum chip, characterized in that, include: First quantum bit and second quantum bit; The coupling structure is non-coplanar with both the first and second qubits, and the frequency of the coupling structure is tunable. The coupling structure includes: a superconducting quantum interference device; a first capacitor element connected to one end of the superconducting quantum interference device, and the first capacitor element is capacitively coupled to the first qubit; and a second capacitor element connected to the other end of the superconducting quantum interference device, and the second capacitor element is capacitively coupled to the second qubit.

2. The quantum chip according to claim 1, characterized in that, The first qubit and the second qubit are located on a first surface, the coupling structure is located on a second surface, and the first surface and the second surface are located on opposite sides of the same substrate.

3. The quantum chip according to claim 1, characterized in that, The first qubit is located on a first substrate, the second qubit is located on a second substrate, the coupling structure is located on a third substrate, and the first substrate, the second substrate, and the third substrate are all interconnected.

4. The quantum chip according to claim 3, characterized in that, The first substrate and the second substrate are on the same side of the third substrate.

5. The quantum chip according to claim 3, characterized in that, The first substrate and the second substrate are on opposite sides of the third substrate.

6. The quantum chip according to claim 5, characterized in that, The first capacitive element is capacitively coupled to the first quantum bit; The second capacitor element is formed on the opposite side of the first capacitor element on the third substrate, and the second capacitor element is capacitively coupled to the second quantum bit.

7. The quantum chip according to any one of claims 1 to 6, characterized in that, Both the first qubit and the second qubit include a Josephson junction with nonlinear inductance. The Josephson junction includes a first superconductor, a barrier layer, and a second superconductor stacked together. The equivalent capacitance formed between the first superconductor and the second superconductor forms a non-uniform energy level with the nonlinear inductance.

8. The quantum chip according to claim 7, characterized in that, The second superconductor includes a first portion and a second portion disposed at intervals on the barrier layer, and the first portion and the second portion are electrically connected.

9. The quantum chip according to claim 8, characterized in that, The first part and the second part are electrically connected by an air bridge.

10. A method for fabricating a quantum chip, characterized in that, Includes the following steps: Forming the first and second qubits; A coupling structure is formed that is not coplanar with either the first or the second qubit. The frequency of the coupling structure is tunable. The coupling structure includes: a superconducting quantum interference device; a first capacitor element connected to one end of the superconducting quantum interference device and capacitively coupled to the first qubit; and a second capacitor element connected to the other end of the superconducting quantum interference device and capacitively coupled to the second qubit.

11. The preparation method according to claim 10, characterized in that, The steps of forming the first qubit and the second qubit include: forming the first qubit on a first substrate and forming the second qubit on a second substrate; The step of forming a coupling structure that is not coplanar with the first qubit and the second qubit includes: forming a coupling structure located on a third substrate, wherein the first substrate and the second substrate are both interconnected with the third substrate.

12. The preparation method according to claim 11, characterized in that, The first substrate and the second substrate are on the same side of the third substrate.

13. The preparation method according to claim 11, characterized in that, The first substrate and the second substrate are on opposite sides of the third substrate.

14. A quantum computer, characterized in that, Includes the quantum chip as described in any one of claims 1 to 9.

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