A three-dimensional chip packaging structure and method

Abstract

The application provides a three-dimensional chip packaging structure and method, the packaging structure comprising: a wafer carrier used to carry a bare wafer; the bare wafer comprising a solder ball bare wafer and a non-solder ball bare wafer, the solder ball bare wafer being soldered and attached to the surface of the wafer carrier, and the non-solder ball bare wafer being adhered and attached to the surface of the solder ball bare wafer or the surface of the wafer carrier; the wafer carrier is provided with functional pads on both sides of the surface, the solder ball bare wafer has a first side and a second side, the first side of the solder ball bare wafer is provided with wafer solder balls, and the wafer solder balls are suitable for being soldered and attached to the functional pads; the non-solder ball bare wafer has a third side and a fourth side, the third side of the non-solder ball bare wafer is provided with first wafer pads, and the first wafer pads are suitable for being soldered and connected to the functional pads through metal leads; and the fourth side of the non-solder ball bare wafer is adhered and attached to the second side of the solder ball bare wafer or the surface of the wafer carrier. The application reduces the area occupied by the bare wafer and improves the chip integration.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and in particular to a three-dimensional chip packaging structure and method. Background Technology

[0002] With the rapid development of integrated circuit technology, device integration is increasing while linewidth is shrinking, posing greater challenges to chip packaging. In existing wafer-level chip packaging technologies, bare wafers are mounted on a carrier for packaging, with all bare wafers mounted on the carrier surface, occupying a large carrier area. The carrier only mounts the bare wafer on one side, while the other side is mounted on the PCB after packaging, resulting in lower integration. Furthermore, only one packaging method, such as wire bonding or flip-chip bonding, can be used for packaging bare wafers onto the carrier, making it difficult to achieve packaging on the same carrier using different processes, thus limiting the application of bare wafers from different processes.

[0003] Therefore, it is necessary to provide a three-dimensional chip packaging structure and method to effectively solve the above problems. Summary of the Invention

[0004] This invention provides a three-dimensional chip packaging structure and method. By changing the packaging method of non-solder ball bare wafers on the carrier, a three-dimensional stacked packaging of non-solder ball bare wafers and solder ball bare wafers is achieved, reducing the area occupied by bare wafers and improving chip integration.

[0005] This invention provides a three-dimensional chip packaging structure, comprising:

[0006] A wafer carrier for carrying a bare wafer;

[0007] A bare wafer includes solder ball bare wafers and non-solder ball bare wafers, wherein the solder ball bare wafers are soldered and mounted on the surface of the wafer carrier, and the non-solder ball bare wafers are bonded and mounted on the surface of the solder ball bare wafers or bonded and mounted on the surface of the wafer carrier;

[0008] An external carrier is disposed on both sides of the wafer carrier on which the bare wafer is held;

[0009] A metal support pillar is disposed between the wafer carrier and the external carrier to connect the wafer carrier and the external carrier;

[0010] Functional pads are provided on both sides of the wafer carrier.

[0011] The bare solder ball wafer has a first side and a second side. The first side of the bare solder ball wafer is provided with a wafer solder ball, which is suitable for soldering and mounting to the functional pad.

[0012] The non-solder ball bare wafer has a third side and a fourth side. The third side of the non-solder ball bare wafer is provided with a first wafer pad, which is adapted to be soldered to the functional pad via metal leads.

[0013] The fourth side of the non-solder ball bare wafer is bonded to the second side of the solder ball bare wafer or attached to the surface of the wafer carrier.

[0014] The wafer carrier is provided with a first conductive structure, and the external carrier is provided with a second conductive structure. The functional pads are electrically connected to the second conductive structure through the first conductive structure and the metal pillar.

[0015] Preferably, the first conductive structure includes a first through hole and a first metal line. The first through hole penetrates the wafer carrier. A first hole ring is formed on both sides of the first through hole on the wafer carrier. The inner walls of the first hole ring and the first through hole are plated with a metal layer. The first metal line is disposed on both sides of the wafer carrier and electrically connects the first hole ring to the functional pad.

[0016] Preferably, the first conductive structure further includes wafer carrier solder balls disposed on both sides of the wafer carrier, the wafer carrier solder balls being disposed at the first through hole, and the wafer carrier solder balls being adapted to be welded to the first hole ring and the metal pillar, electrically connecting the first hole ring and the metal pillar.

[0017] Preferably, the second conductive structure includes a second through hole and a second metal line. The second through hole penetrates the outer carrier and is provided with a second hole ring formed on both sides of the outer carrier. The inner walls of the second hole ring and the second through hole are plated with a metal layer. The second metal line is provided on the surface of the outer carrier and is electrically connected to the second hole ring.

[0018] Preferably, the second conductive structure further includes external carrier solder balls disposed on both sides of the external carrier. The external carrier solder balls disposed on the side of the external carrier closer to the wafer carrier are adapted to be soldered to the second metal line and the metal pillar, electrically connecting the second metal line and the metal pillar; the external carrier solder balls disposed on the side of the external carrier away from the wafer carrier are adapted to be soldered to the second hole ring and electrically connected.

[0019] Preferably, a second wafer pad is provided on the first side of the bare wafer of the solder ball, and a metal pillar is provided on the second wafer pad. The wafer solder ball covers the second wafer pad and the metal pillar.

[0020] Preferably, the wafer carrier is made of silicon, and the first metal line is sputtered on the surface of the wafer carrier; or, the wafer carrier is made of PI, FR4, PET or G10, and the first metal line is laid on the surface of the wafer carrier; the first metal line is made of copper, nickel, gold, copper alloy, nickel alloy or gold alloy.

[0021] The material of the external carrier is silicon, and the second metal line is sputtered on the surface of the external carrier; or, the material of the external carrier is PI, FR4, PET or G10, and the second metal line is laid on the surface of the external carrier; the material of the second metal line is copper, nickel, gold, copper alloy, nickel alloy or gold alloy.

[0022] Preferably, the wafer solder balls are made of tin, gold, silver, copper, nickel, tin alloy, gold alloy, silver alloy, copper alloy, or nickel alloy; the metal pillars are made of copper or copper alloy.

[0023] Based on the same concept, embodiments of the present invention also provide a three-dimensional chip packaging method. The packaging structure includes a wafer carrier, a bare wafer, an external carrier, and metal pillars. The wafer carrier is provided with functional pads and a first conductive structure, the first conductive structure being electrically connected to the functional pads. The bare wafer includes solder ball bare wafers and non-solder ball bare wafers. The solder ball bare wafers are provided with wafer solder balls, and the non-solder ball bare wafers are provided with first wafer pads. The external carrier is provided with a second conductive structure. The packaging method includes the following steps:

[0024] The wafer carrier is provided, as are the solder ball bare wafer and the non-solder ball bare wafer;

[0025] The wafer solder balls are soldered to the functional pads and electrically connected, so that the bare wafer of the solder balls is soldered and mounted on the surface of the wafer carrier.

[0026] The side of the non-solder ball bare wafer without the first wafer pad is bonded to the surface of the solder ball bare wafer or bonded to the surface of the wafer carrier using conductive adhesive;

[0027] The first wafer pad of the non-solder ball bare wafer is soldered to the functional pad via metal leads and electrically connected.

[0028] The external carrier is disposed on both sides of the wafer carrier, and the metal pillar is disposed between the wafer carrier and the external carrier;

[0029] One end of the metal pillar is welded to the first conductive structure and electrically connected, and the other end is welded to the second conductive structure and electrically connected, so that the functional pad is electrically connected to the second conductive structure.

[0030] Preferably, the first conductive structure includes a first via, a first metal line, and a wafer carrier solder ball. The first via penetrates the wafer carrier, and a first annular ring is formed on both sides of the first via. The inner walls of the first annular ring and the first via are plated with a metal layer. The first metal line is disposed on both sides of the wafer carrier and electrically connects the first annular ring to the functional pad. The wafer carrier solder ball is electrically connected to the first annular ring.

[0031] The second conductive structure includes a second via, a second metal line, and external carrier solder balls. The second via penetrates the external carrier. Second rings are formed on both sides of the second via. Both the second rings and the inner walls of the second via are plated with a metal layer. The second metal line is disposed on the surface of the external carrier and is electrically connected to the second rings. The external carrier solder balls are disposed on both sides of the external carrier. The external carrier solder balls disposed on the side of the external carrier closer to the wafer carrier are electrically connected to the second metal line. The external carrier solder balls disposed on the side of the external carrier away from the wafer carrier are electrically connected to the second rings. The packaging method further includes:

[0032] One end of the metal pillar is welded to the wafer carrier solder ball and electrically connected;

[0033] The other end of the metal pillar is welded to the external carrier solder ball located near the wafer carrier and electrically connected.

[0034] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0035] This invention provides a three-dimensional chip packaging structure and method that vertically stacks non-solder ball bare wafers onto solder ball bare wafers. Simultaneously, the bare wafers are mounted on both sides of a wafer carrier, reducing the area occupied by the bare wafers and improving integration density. Both wire bonding and flip-chip bonding are implemented on a single wafer carrier, allowing bare wafers of different processes to be integrated into one carrier, thus expanding the application range of bare wafers with different processes.

[0036] Furthermore, metal pillars are set to connect the wafer carrier and the external carrier to achieve support connection of the carrier. A first connecting structure is set in the wafer carrier and a second connecting structure is set in the external carrier, and they are connected by metal pillars to realize the electrical lead-out of the bare wafer. The process is simple and easy to implement.

[0037] Furthermore, by setting through holes on the carrier and plating a metal layer in the through holes to achieve the conduction of metal lines on both sides of the carrier, the process is simplified and efficiency is improved. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention, but not all embodiments. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 A schematic diagram of a three-dimensional chip packaging structure provided for one embodiment of the present invention;

[0040] Figure 2 A schematic cross-sectional view of the bare wafer for solder balls is provided for one embodiment of the present invention;

[0041] Figure 3 A schematic diagram of a cross-section of a bare wafer without solder balls is provided for one embodiment of the present invention;

[0042] Figure 4 A schematic diagram of a three-dimensional chip packaging structure provided for another embodiment of the present invention.

[0043] In the picture:

[0044] 1. Wafer carrier; 2. Bare wafer; 3. External carrier; 4. Metal pillar; 5. Metal lead; 6. Conductive adhesive;

[0045] 11. Functional pad; 12. First conductive structure; 121. First via; 122. Wafer carrier solder ball;

[0046] 21. Spare wafer with solder balls; 211. First side; 212. Second side; 213. Wafer solder ball; 214. Second wafer pad; 215. Metal pillar; 22. Non-solder bare wafer; 221. Third side; 222. Fourth side; 223. First wafer pad;

[0047] 31. Second conductive structure; 311. Second conductive hole; 312. External carrier solder ball. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0049] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0050] To address the problems existing in the prior art, this invention provides a three-dimensional chip packaging structure and method. By changing the packaging method of the non-solder ball bare wafer on the carrier, a three-dimensional stacked packaging of non-solder ball bare wafers and solder ball bare wafers is achieved, reducing the area occupied by the bare wafer and improving the chip integration.

[0051] Figure 1 A schematic diagram of a three-dimensional chip packaging structure provided for one embodiment of the present invention; Figure 2 A schematic cross-sectional view of the bare wafer for solder balls is provided for one embodiment of the present invention; Figure 3 A schematic diagram of a cross-section of a bare wafer without solder balls is provided for one embodiment of the present invention; Figure 4 A schematic diagram of a three-dimensional chip packaging structure provided for another embodiment of the present invention.

[0052] Now see Figures 1 to 4 This invention provides a three-dimensional chip packaging structure, comprising:

[0053] Wafer carrier 1, which is used to support bare wafer 2;

[0054] The bare wafer 2 includes a solder ball bare wafer 21 and a non-solder ball bare wafer 22. The solder ball bare wafer 21 is soldered and mounted on the surface of the wafer carrier 1, and the non-solder ball bare wafer 22 is bonded and mounted on the surface of the solder ball bare wafer 21 or bonded and mounted on the surface of the wafer carrier 1.

[0055] External carrier 3 is disposed on both sides of the wafer carrier 1 that carries the bare wafer 2;

[0056] Metal pillar 4 is disposed between wafer carrier 1 and external carrier 3 to connect wafer carrier 1 and external carrier 3;

[0057] Functional pads 11 are provided on both sides of the wafer carrier 1, and the bare wafer 2 can be mounted on both sides of the wafer carrier 1, increasing the mounting area of ​​the wafer carrier 1 and improving the integration.

[0058] The bare solder ball wafer 21 has a first side 211 and a second side 212. The first side 211 of the bare solder ball wafer 21 is provided with wafer solder balls 213. The wafer solder balls 213 are suitable for soldering and mounting with the functional pads 11 to achieve flip-chip bonding.

[0059] The non-ball bare wafer 22 has a third side 221 and a fourth side 222. The third side 221 of the non-ball bare wafer 22 is provided with a first wafer pad 223. The first wafer pad 223 is adapted to be soldered to the functional pad 11 through the metal lead 5 to realize wire bonding mounting.

[0060] The fourth side 222 of the non-solder ball bare wafer 22 is bonded and mounted to the second side 212 of the solder ball bare wafer 21 or mounted on the surface of the wafer carrier 1; the non-solder ball bare wafer 22 is bonded and mounted to the solder ball bare wafer 21 by vertical stacking, thereby reducing the area occupied by the bare wafer 2 and improving the integration density.

[0061] A first conductive structure 12 is provided on the wafer carrier 1, and a second conductive structure 31 is provided on the external carrier 3. The functional pad 11 is electrically connected to the second conductive structure 31 through the first conductive structure 12 and the metal pillar 4, so as to realize the electrical lead-out of the bare wafer 2.

[0062] In practical implementation, when the bare wafer 2 is double-sided mounted on the wafer carrier 1, the bare wafer 2 can be arranged symmetrically or asymmetrically. A solder ball bare wafer 21 can be individually soldered onto the wafer carrier 1, or a non-solder ball bare wafer 22 can be pasted onto the solder ball bare wafer 21 that has been soldered and mounted, or the non-solder ball bare wafer 22 can be pasted onto the wafer carrier 1. During soldering, areas where the bare wafer 2 has already been mounted or soldered must be avoided, and the wafer carrier 1 must have sufficient strength to support the stresses introduced during all manufacturing processes.

[0063] In a specific embodiment, a second wafer pad 214 is provided on the first side 211 of the bare wafer 21, and a metal pillar 215 is provided on the second wafer pad 214. The wafer solder ball 213 covers the second wafer pad 214 and the metal pillar 215.

[0064] In some embodiments, the first conductive structure 12 includes a first through hole 121 and a first metal line. The first through hole 121 is disposed through the wafer carrier 1. The first through hole 121 has a first hole ring formed on both sides of the wafer carrier 1. The inner walls of the first hole ring and the first through hole 121 are plated with a metal layer. The first metal line is disposed on both sides of the wafer carrier 1. The first metal line is electrically connected to the first hole ring and the functional pad 11.

[0065] In some embodiments, the diameter of the first via 121 is 20µm-200µm.

[0066] In some embodiments, the first conductive structure 12 further includes wafer carrier solder balls 122 disposed on both sides of the wafer carrier 1. The wafer carrier solder balls 122 are disposed at the first through hole 121 and are adapted to be welded to the first hole ring and the metal pillar 4, and electrically connected to the first hole ring and the metal pillar 4.

[0067] In some embodiments, the second conductive structure 31 includes a second conductive hole 311 and a second metal line. The second conductive hole 311 is disposed through the outer carrier 3. A second hole ring is formed on both sides of the second conductive hole 311. The inner walls of the second hole ring and the second conductive hole 311 are plated with a metal layer. The second metal line is disposed on the surface of the outer carrier 3 and is electrically connected to the second hole ring 311.

[0068] In some embodiments, the diameter of the second via 311 is 20µm-200µm.

[0069] In some embodiments, the second conductive structure 31 further includes external carrier solder balls 312 disposed on both sides of the external carrier 3. The external carrier solder balls 312 disposed on the side of the external carrier 3 near the wafer carrier 1 are adapted to be soldered to the second metal line and the metal pillar 4, and electrically connected to the second metal line and the metal pillar 4. The external carrier solder balls 312 disposed on the side of the external carrier 3 away from the wafer carrier 1 are adapted to be soldered to the second hole ring and electrically connected.

[0070] In some embodiments, external circuits are connected by external carrier solder balls 312 disposed on the side of the external carrier 3 away from the wafer carrier 1 and electrically connected to the PCB (Printed Circuit Board).

[0071] In some embodiments, the fourth side 222 of the non-solder ball bare wafer 22 is bonded to the second side 212 of the solder ball bare wafer 21 or attached to the surface of the wafer carrier 1 by conductive adhesive 6.

[0072] In some embodiments, the wafer carrier 1 is made of silicon, and a first metal line is sputtered onto the surface of the wafer carrier 1.

[0073] In some embodiments, the wafer carrier 1 is made of PI (Polyimide), FR4 (a code for the fire-retardant grade of glass fiber epoxy resin copper clad laminate, which means that the resin material must be able to extinguish itself after being burned), PET (Polyethylene terephthalate), or G10 (a glass fiber and resin rolled composite material; G represents glass fiber, and 10 means that the glass fiber content is 10%; G10 material has the characteristics of insulation, corrosion resistance, and wear resistance, and can withstand great force without being damaged or deformed); the first metal line is laid on the surface of the wafer carrier 1.

[0074] In some embodiments, the first metal line needs to be made of a metal material with very good conductivity, and the material of the first metal line is copper, nickel, gold, copper alloy, nickel alloy or gold alloy.

[0075] In some embodiments, the external carrier 3 is similar to the wafer carrier 1, and its material is silicon, with a second metal line sputtered onto the surface of the external carrier 3.

[0076] In some embodiments, the external carrier 3 is similar to the wafer carrier 1, and its material is PI, FR4, PET or G10, and the second metal line is laid on the surface of the external carrier 3.

[0077] In some embodiments, the second metal circuit needs to be made of a metal material with very good conductivity, and the material of the second metal circuit is copper, nickel, gold, copper alloy, nickel alloy or gold alloy.

[0078] In some embodiments, the wafer solder ball 213 is made of tin, gold, silver, copper, nickel, tin alloy, gold alloy, silver alloy, copper alloy, or nickel alloy; the metal support 4 is made of copper or copper alloy.

[0079] In some embodiments, the wafer carrier solder ball 122 and the external carrier solder ball 312 are similar to the wafer solder ball 213, and their materials are tin, gold, silver, copper, nickel, tin alloy, gold alloy, silver alloy, copper alloy or nickel alloy.

[0080] This invention also provides a method for a three-dimensional chip packaging structure. The packaging structure includes a wafer carrier 1, a bare wafer 2, an external carrier 3, and metal pillars 4. The wafer carrier 1 is provided with functional pads 11 and a first conductive structure 12, which is electrically connected to the functional pads 11. The bare wafer 2 includes a solder ball bare wafer 21 and a non-solder ball bare wafer 22. The solder ball bare wafer 21 is provided with wafer solder balls 213, and the non-solder ball bare wafer 22 is provided with first wafer pads 223. The external carrier 3 is provided with a second conductive structure 31. The packaging method includes the following steps:

[0081] S1: Provides a wafer carrier 1, and provides a solder ball bare wafer 21 and a non-solder ball bare wafer 22;

[0082] S2: Weld the wafer solder ball 213 to the functional pad 11 and make them electrically connected, so that the bare wafer 21 of the solder ball is soldered and mounted on the surface of the wafer carrier 1.

[0083] S3: The side of the non-solder ball bare wafer 22 without the first wafer pad 223 is bonded to the surface of the solder ball bare wafer 21 or bonded to the surface of the wafer carrier 1 using conductive adhesive 6.

[0084] S4: The first wafer pad 223 of the non-solder ball bare wafer 22 is soldered to the functional pad 11 through the metal lead 5 and electrically connected.

[0085] S5: The external carrier 3 is placed on both sides of the wafer carrier 1, and the metal pillar 4 is placed between the wafer carrier 1 and the external carrier 3.

[0086] S6: Weld one end of the metal pillar 4 to the first conductive structure 12 and make it electrically conductive, and weld the other end to the second conductive structure 31 and make it electrically conductive, so that the functional pad 11 is electrically conductive to the second conductive structure 31.

[0087] In some embodiments, the first conductive structure 12 includes a first via 121, a first metal line, and a wafer carrier solder ball 122. The first via 121 is disposed through the wafer carrier 1. A first hole ring is formed on both sides of the first via 121. The inner walls of the first hole ring and the first via 121 are plated with a metal layer. The first metal line is disposed on both sides of the wafer carrier 1 and is electrically connected to the first hole ring and the functional solder pad 11. The wafer carrier solder ball 122 is electrically connected to the first hole ring.

[0088] The second conductive structure 31 includes a second through-hole 311, a second metal line, and an external carrier solder ball 312. The second through-hole 311 penetrates the external carrier 3. A second hole ring is formed on both sides of the second through-hole 311. Both the second hole ring and the inner wall of the second through-hole 311 are plated with a metal layer. The second metal line is disposed on the surface of the external carrier 3 and is electrically connected to the second hole ring. The external carrier solder ball 312 is disposed on both sides of the external carrier 3. The external carrier solder ball 312 disposed on the side of the external carrier 3 closest to the wafer carrier 1 is electrically connected to the second metal line, and the external carrier solder ball 312 disposed on the side of the external carrier 3 furthest from the wafer carrier 1 is electrically connected to the second hole ring. The packaging method further includes:

[0089] One end of the metal pillar 4 is welded to the wafer carrier solder ball 122 and electrically connected;

[0090] The other end of the metal pillar 4 is welded to the external carrier solder ball 312 located near the wafer carrier 1 and electrically connected.

[0091] In practical implementation, during the fabrication of the bare solder ball wafer 21, it is necessary to ensure the precision of the metal pillars 215 and the wafer solder balls 213 implanted on the bare solder ball wafer 21 to guarantee the flatness of the bare solder ball wafer 21 when it is soldered and mounted onto the wafer carrier 1. This requires the use of a high-precision photolithography machine and photomask to implant the metal pillars 215 and the wafer solder balls 213. The fabrication process of the bare solder ball wafer 21 is as follows:

[0092] First, photoresist is applied to the surface of the wafer after metal sputtering. Then, a photomask is used to cover the surface of the wafer, and then it is irradiated with microwaves from a photolithography machine.

[0093] The process involves creating localized windows on the wafer surface in areas where photoresist does not need to be covered by developing, and then removing the photoresist to form the windowed area. Typically, the diameter of the windowed area is 100µm, and the alignment accuracy of the windowed area can reach ±1.0µm.

[0094] Metal plating is performed in the windowed area of ​​the photoresist using semiconductor electroplating equipment to generate metal pillars 215 and wafer solder balls 213. Typically, the overall height of the metal pillars 215 and wafer solder balls 213 is 45µm, and the flatness accuracy can reach ±1.5µm.

[0095] In practice, when the wafer solder balls 213 are soldered to the functional pads 11, the metal pillars 215 supporting the functional pads 11 after the wafer solder balls 213 have melted need to maintain a certain degree of flatness. When the bare wafers 21 are soldered and mounted, flux is printed on the wafer carrier 1, and then a special flip chip soldering device is used to mount the bare wafers 21 onto the wafer carrier 1. The mounting accuracy of the flip chip soldering device can reach ±1.0um. Finally, the wafer solder balls 213 on the bare wafers 21 are melted by a reflow soldering device, and the solder balls 213 are soldered together with the functional pads 11.

[0096] In summary, the three-dimensional chip packaging structure and method provided by the embodiments of the present invention bond and mount non-solder ball bare wafers 22 onto solder ball bare wafers 21 by vertical stacking. At the same time, the bare wafers 2 are mounted on both sides of the wafer carrier 1, reducing the area occupied by the bare wafers 2 and improving the integration density. Both wire bonding and flip-chip bonding mounting methods are realized on a single wafer carrier 1, which can integrate bare wafers 2 of different processes into a single carrier, expanding the application range of bare wafers 2 of different processes.

[0097] Furthermore, a metal pillar 4 is provided to connect the wafer carrier 1 and the external carrier 3 to achieve the support connection of the carrier. A first connecting structure 12 is provided on the wafer carrier 1, and a second connecting structure 31 is provided on the external carrier 3, and they are connected through the metal pillar 4 to realize the electrical lead-out of the bare wafer 2. The process is simple and easy to implement.

[0098] Furthermore, by setting through holes on the carrier and plating a metal layer in the through holes to achieve the conduction of metal lines on both sides of the carrier, the process is simplified and efficiency is improved.

[0099] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A three-dimensional chip packaging structure, characterized in that, include: A wafer carrier for carrying a bare wafer; A bare wafer includes solder ball bare wafers and non-solder ball bare wafers, wherein the solder ball bare wafers are soldered and mounted on the surface of the wafer carrier, and the non-solder ball bare wafers are bonded and mounted on the surface of the solder ball bare wafers or bonded and mounted on the surface of the wafer carrier; An external carrier is disposed on both sides of the wafer carrier on which the bare wafer is held; A metal support pillar is disposed between the wafer carrier and the external carrier to connect the wafer carrier and the external carrier; Functional pads are provided on both sides of the wafer carrier, and the bare wafer is mounted on both sides of the wafer carrier. The bare solder ball wafer has a first side and a second side. The first side of the bare solder ball wafer is provided with a wafer solder ball, which is suitable for soldering and mounting to the functional pad. The non-solder ball bare wafer has a third side and a fourth side. The third side of the non-solder ball bare wafer is provided with a first wafer pad, which is adapted to be soldered to the functional pad via metal leads. The fourth side of the non-solder ball bare wafer is bonded to the second side of the solder ball bare wafer or attached to the surface of the wafer carrier. The wafer carrier is provided with a first conductive structure, the external carrier is provided with a second conductive structure, and the functional pad is electrically connected to the second conductive structure through the first conductive structure and the metal pillar. The first conductive structure includes a first through hole and a first metal line. The first through hole penetrates the wafer carrier. A first hole ring is formed on both sides of the first through hole. The inner walls of the first hole ring and the first through hole are plated with a metal layer. The first metal line is disposed on both sides of the wafer carrier and electrically connects the first hole ring and the functional pad. The second conductive structure includes a second through hole and a second metal line. The second through hole penetrates the outer carrier and is provided with a second hole ring formed on both sides of the outer carrier. The inner walls of the second hole ring and the second through hole are plated with a metal layer. The second metal line is provided on the surface of the outer carrier and is electrically connected to the second hole ring.

2. The three-dimensional chip packaging structure according to claim 1, characterized in that, The first conductive structure further includes wafer carrier solder balls disposed on both sides of the wafer carrier. The wafer carrier solder balls are disposed at the first through hole and are adapted to be welded to the first hole ring and the metal pillar, electrically connecting the first hole ring and the metal pillar.

3. The three-dimensional chip packaging structure according to claim 1, characterized in that, The second conductive structure further includes external carrier solder balls disposed on both sides of the external carrier. The external carrier solder balls disposed on the side of the external carrier closer to the wafer carrier are adapted to be soldered to the second metal line and the metal pillar, and electrically connected to the second metal line and the metal pillar. The external carrier solder balls disposed on the side of the external carrier away from the wafer carrier are adapted to be soldered to the second hole ring and electrically connected.

4. The three-dimensional chip packaging structure according to claim 1, characterized in that, The first side of the bare wafer with the solder ball is provided with a second wafer pad, and a metal pillar is provided on the second wafer pad. The wafer solder ball covers the second wafer pad and the metal pillar.

5. The three-dimensional chip packaging structure according to claim 1, characterized in that, The wafer carrier is made of silicon, and the first metal line is sputtered on the surface of the wafer carrier; or, the wafer carrier is made of PI, FR4, PET or G10, and the first metal line is laid on the surface of the wafer carrier; the first metal line is made of copper, nickel, gold, copper alloy, nickel alloy or gold alloy. The material of the external carrier is silicon, and the second metal line is sputtered on the surface of the external carrier; or, the material of the external carrier is PI, FR4, PET or G10, and the second metal line is laid on the surface of the external carrier; the material of the second metal line is copper, nickel, gold, copper alloy, nickel alloy or gold alloy.

6. The three-dimensional chip packaging structure according to claim 1, characterized in that, The wafer solder balls are made of tin, gold, silver, copper, nickel, tin alloy, gold alloy, silver alloy, copper alloy, or nickel alloy; the metal pillars are made of copper or copper alloy.

7. A method for packaging a three-dimensional chip, characterized in that, The method is applied to the three-dimensional chip packaging structure as described in any one of claims 1-6; the packaging structure includes a wafer carrier, a bare wafer, an external carrier, and metal pillars; the wafer carrier is provided with functional pads and a first conductive structure, the first conductive structure being electrically connected to the functional pads; the bare wafer includes solder ball bare wafers and non-solder ball bare wafers; the solder ball bare wafers are provided with wafer solder balls, and the non-solder ball bare wafers are provided with first wafer pads; the external carrier is provided with a second conductive structure; the packaging method includes the following steps: The wafer carrier is provided, as are the solder ball bare wafer and the non-solder ball bare wafer; The wafer solder balls are soldered to the functional pads and electrically connected, so that the bare wafer of the solder balls is soldered and mounted on the surface of the wafer carrier. The side of the non-solder ball bare wafer without the first wafer pad is bonded to the surface of the solder ball bare wafer or bonded to the surface of the wafer carrier using conductive adhesive; The first wafer pad of the non-solder ball bare wafer is soldered to the functional pad via metal leads and electrically connected. The external carrier is disposed on both sides of the wafer carrier, and the metal pillar is disposed between the wafer carrier and the external carrier; One end of the metal pillar is welded to the first conductive structure and electrically connected, and the other end is welded to the second conductive structure and electrically connected, so that the functional pad is electrically connected to the second conductive structure.

8. The three-dimensional chip packaging method according to claim 7, characterized in that, The first conductive structure includes a first via, a first metal line, and a wafer carrier solder ball. The first via penetrates the wafer carrier. A first annular ring is formed on both sides of the first via. The inner walls of the first annular ring and the first via are plated with a metal layer. The first metal line is disposed on both sides of the wafer carrier and electrically connects the first annular ring to the functional pad. The wafer carrier solder ball is electrically connected to the first annular ring. The second conductive structure includes a second via, a second metal line, and external carrier solder balls. The second via penetrates the external carrier. Second rings are formed on both sides of the second via. Both the second rings and the inner walls of the second via are plated with a metal layer. The second metal line is disposed on the surface of the external carrier and is electrically connected to the second rings. The external carrier solder balls are disposed on both sides of the external carrier. The external carrier solder balls disposed on the side of the external carrier closer to the wafer carrier are electrically connected to the second metal line. The external carrier solder balls disposed on the side of the external carrier away from the wafer carrier are electrically connected to the second rings. The packaging method further includes: One end of the metal pillar is welded to the wafer carrier solder ball and electrically connected; The other end of the metal pillar is welded to the external carrier solder ball located near the wafer carrier and electrically connected.

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