Drive circuit, drive method and display device

Abstract

This disclosure provides a driving circuit, a driving method, and a display device. The driving circuit includes a first pull-down node, a first control circuit, and a pull-up node reset circuit. Under the control of a first control signal, the first control circuit controls the connection between the first pull-down node and a first voltage terminal, so that the potential of the first pull-down node is an effective voltage. When the potential of the first pull-down node is an effective voltage, the pull-up node reset circuit controls the connection between the pull-up node and a second voltage terminal to reset the potential of the pull-up node. This disclosure can improve the noise reduction capability of the transistor included in the pull-up node reset circuit, prevent the driving circuit from outputting incorrectly, and enable the driving circuit to correctly output driving signals.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a driving circuit, driving method and display device. Background Technology

[0002] In related technologies, the driving circuit may include only one pull-down node and one pull-down node control circuit to achieve a narrow bezel. However, since there is only one pull-down node to control the potential, the transistor characteristics will drift to a certain extent during high temperature and high humidity reliability processes. Under the negative bias, the threshold voltage of the transistor included in the input circuit drifts negatively, the leakage current increases, and the second input voltage terminal leaks to the pull-up node, generating noise. In addition, the characteristics of the transistor included in the pull-up node reset circuit and the characteristics of the transistor whose gate is electrically connected to the first pull-down control node in the first pull-down node control circuit drift positively, causing the potential of the first pull-down node to drop. The noise reduction capability of the transistor included in the pull-up node reset circuit decreases, and it is unable to pull down the potential of the pull-up node to a low voltage, thereby causing the driving circuit to output incorrectly and generate multiple driving signal outputs. Summary of the Invention

[0003] In one aspect, embodiments of this disclosure provide a driving circuit including a first pull-down node, a first control circuit, and a pull-up node reset circuit;

[0004] The first control circuit is electrically connected to the first pull-down node, the first control terminal, and the first voltage terminal respectively, and is used to control the connection between the first pull-down node and the first voltage terminal under the control of the first control signal provided by the first control terminal, so that the potential of the first pull-down node is an effective voltage.

[0005] The pull-up node reset circuit is electrically connected to the first pull-down node, the pull-up node, and the second voltage terminal, respectively, and is used to control the connection between the pull-up node and the second voltage terminal when the potential of the first pull-down node is an effective voltage, so as to reset the potential of the pull-up node.

[0006] Optionally, the first control terminal is a reset terminal, a first drop-down node, or a first drop-down control node.

[0007] Optionally, the first control circuit includes a first transistor;

[0008] The gate of the first transistor is electrically connected to the first control terminal, the first electrode of the first transistor is electrically connected to the first pull-down node, and the second electrode of the first transistor is electrically connected to the first voltage terminal.

[0009] The pull-up node reset circuit includes a second transistor;

[0010] The gate of the second transistor is electrically connected to the first pull-down node, the first terminal of the second transistor is electrically connected to the pull-up node, and the second terminal of the second transistor is electrically connected to the second voltage terminal.

[0011] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes a reset circuit;

[0012] The reset circuit is electrically connected to the reset terminal, the pull-up node, and the first input voltage, respectively, and is used to control the first input voltage provided by the first input voltage terminal to be written to the pull-up node under the control of the reset signal provided by the reset terminal.

[0013] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes a first pull-down node control circuit;

[0014] The first pull-down node control circuit is electrically connected to the first pull-down node, the first pull-down control node, the pull-up node, the first control voltage terminal, and the third voltage terminal, respectively. It is used to control the connection between the first control voltage terminal and the first pull-down control node under the control of the first control voltage provided by the first control voltage terminal, and to control the connection between the first pull-down control node and the third voltage terminal under the control of the potential of the pull-up node. It is also used to control the connection between the first pull-down node and the first control voltage terminal under the control of the potential of the first pull-down control node, and to control the connection between the first pull-down node and the third voltage terminal under the control of the potential of the pull-up node.

[0015] The first voltage terminal is the first control voltage terminal.

[0016] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes an output circuit;

[0017] The output circuit is electrically connected to the pull-up node, the first pull-down node, the output clock signal terminal, the fourth voltage terminal, and the drive signal output terminal, respectively. It is used to control the output clock signal provided by the output clock signal terminal to be written to the drive signal output terminal under the control of the potential of the pull-up node, and to control the connection between the drive signal output terminal and the fourth voltage terminal under the control of the potential of the first pull-down node.

[0018] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes a second pull-down node and a second control circuit;

[0019] The second control circuit is electrically connected to the second pull-down node, the second control terminal, and the fifth voltage terminal, respectively, and is used to control the connection between the second pull-down node and the fifth voltage terminal under the control of the second control signal provided by the second control terminal, so that the potential of the second pull-down node is an effective voltage;

[0020] The pull-up node reset circuit is also electrically connected to the second pull-down node, and is used to control the connection between the pull-up node and the second voltage terminal when the potential of the second pull-down node is an effective voltage, so as to reset the potential of the pull-up node.

[0021] Optionally, the second control terminal is a reset terminal, a second pull-down node, or a second pull-down control node.

[0022] Optionally, the second control circuit includes a third transistor; the pull-up node reset circuit further includes a fourth transistor.

[0023] The gate of the third transistor is electrically connected to the second control terminal, the first terminal of the third transistor is electrically connected to the second pull-down node, and the second terminal of the third transistor is electrically connected to the fifth voltage terminal.

[0024] The gate of the fourth transistor is electrically connected to the second pull-down node, the first terminal of the fourth transistor is electrically connected to the pull-up node, and the second terminal of the fourth transistor is electrically connected to the second voltage terminal.

[0025] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes a second pull-down node control circuit;

[0026] The second pull-down node control circuit is electrically connected to the second pull-down node, the second pull-down control node, the pull-up node, the second control voltage terminal, and the third voltage terminal, respectively. It is used to control the connection between the second control voltage terminal and the second pull-down control node under the control of the second control voltage provided by the second control voltage terminal, and to control the connection between the second pull-down control node and the third voltage terminal under the control of the potential of the pull-up node.

[0027] The fifth voltage terminal is the second control voltage terminal.

[0028] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes an input circuit, an output reset circuit, an initial reset circuit, and an energy storage circuit;

[0029] The input circuit is electrically connected to the input terminal, the second input voltage terminal and the pull-up node respectively, and is used to control the second input voltage provided by the second input voltage terminal to be written to the pull-up node under the control of the input signal provided by the input terminal;

[0030] The output reset circuit is electrically connected to the frame reset terminal, the drive signal output terminal and the fourth voltage terminal respectively, and is used to control the connection between the drive signal output terminal and the fourth voltage terminal under the control of the frame reset signal provided by the frame reset terminal;

[0031] The initial reset circuit is electrically connected to the initial reset terminal, the pull-up node, and the fourth voltage terminal, respectively, and is used to control the connection between the pull-up node and the fourth voltage terminal under the control of the initial reset signal provided by the initial reset terminal;

[0032] The first end of the energy storage circuit is electrically connected to the pull-up node, and the second end of the energy storage circuit is electrically connected to the drive signal output terminal. The energy storage circuit is used to store electrical energy.

[0033] Optionally, the reset circuit includes a fifth transistor;

[0034] The gate of the fifth transistor is electrically connected to the reset terminal, the first terminal of the fifth transistor is electrically connected to the pull-up node, and the second terminal of the fifth transistor is electrically connected to the first input voltage terminal.

[0035] Optionally, the first pull-down node control circuit includes a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor;

[0036] The gate and the first terminal of the sixth transistor are both electrically connected to the first control voltage terminal, and the second terminal of the sixth transistor is electrically connected to the first pull-down control node.

[0037] The gate of the seventh transistor is electrically connected to the pull-up node, the first terminal of the seventh transistor is electrically connected to the first pull-down control node, and the second terminal of the seventh transistor is electrically connected to the third voltage terminal.

[0038] The gate of the eighth transistor is electrically connected to the first pull-down control node, the first terminal of the eighth transistor is electrically connected to the first control voltage terminal, and the second terminal of the eighth transistor is electrically connected to the first pull-down node.

[0039] The gate of the ninth transistor is electrically connected to the pull-up node, the first terminal of the ninth transistor is electrically connected to the first pull-down node, and the second terminal of the ninth transistor is electrically connected to the third voltage terminal.

[0040] Optionally, the second pull-down node control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor;

[0041] The gate and the first terminal of the tenth transistor are both electrically connected to the second control voltage terminal, and the second terminal of the tenth transistor is electrically connected to the second pull-down control node.

[0042] The gate of the eleventh transistor is electrically connected to the pull-up node, the first terminal of the eleventh transistor is electrically connected to the second pull-down control node, and the second terminal of the eleventh transistor is electrically connected to the third voltage terminal.

[0043] The gate of the twelfth transistor is electrically connected to the second pull-down control node, the first terminal of the twelfth transistor is electrically connected to the second control voltage terminal, and the second terminal of the twelfth transistor is electrically connected to the second pull-down node.

[0044] The gate of the thirteenth transistor is electrically connected to the pull-up node, the first terminal of the thirteenth transistor is electrically connected to the second pull-down node, and the second terminal of the thirteenth transistor is electrically connected to the third voltage terminal.

[0045] Optionally, the input circuit includes a fourteenth transistor;

[0046] The gate of the fourteenth transistor is electrically connected to the input terminal, the first terminal of the fourteenth transistor is electrically connected to the second input voltage terminal, and the second terminal of the fourteenth transistor is electrically connected to the pull-up node.

[0047] The output circuit includes a fifteenth transistor and a sixteenth transistor;

[0048] The gate of the fifteenth transistor is electrically connected to the pull-up node, the first terminal of the fifteenth transistor is electrically connected to the output clock signal terminal, and the second terminal of the fifteenth transistor is electrically connected to the drive signal output terminal.

[0049] The gate of the sixteenth transistor is electrically connected to the first pull-down node, the first terminal of the sixteenth transistor is electrically connected to the drive signal output terminal, and the second terminal of the sixteenth transistor is electrically connected to the fourth voltage terminal.

[0050] The output reset circuit includes a seventeenth transistor;

[0051] The gate of the seventeenth transistor is electrically connected to the frame reset terminal, the first terminal of the seventeenth transistor is electrically connected to the drive signal output terminal, and the second terminal of the seventeenth transistor is electrically connected to the fourth voltage terminal.

[0052] The initial reset circuit includes an eighteenth transistor;

[0053] The gate of the eighteenth transistor is electrically connected to the initial reset terminal, the first terminal of the eighteenth transistor is electrically connected to the pull-up node, and the second terminal of the eighteenth transistor is electrically connected to the fourth voltage terminal.

[0054] The energy storage circuit includes a storage capacitor;

[0055] The first end of the storage capacitor is electrically connected to the pull-up node, and the second end of the storage capacitor is electrically connected to the drive signal output terminal.

[0056] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes a second pull-down node;

[0057] The output circuit is also electrically connected to the second pull-down node, and is used to control the connection between the drive signal output terminal and the fourth voltage terminal under the control of the potential of the second pull-down node.

[0058] Optionally, the output circuit may further include a nineteenth transistor;

[0059] The gate of the nineteenth transistor is electrically connected to the second pull-down node, the first terminal of the nineteenth transistor is electrically connected to the drive signal output terminal, and the second terminal of the nineteenth transistor is electrically connected to the fourth voltage terminal.

[0060] In a second aspect, embodiments of this disclosure provide a driving method applied to the aforementioned driving circuit, the driving method comprising:

[0061] Under the control of the first control signal, the first control circuit controls the connection between the first pull-down node and the first voltage terminal so that the potential of the first pull-down node is an effective voltage.

[0062] When the potential of the first pull-down node is an effective voltage, the pull-up node reset circuit controls the connection between the pull-up node and the second voltage terminal to reset the potential of the pull-up node.

[0063] Optionally, the driving circuit further includes a second pull-down node and a second control circuit; the driving method further includes:

[0064] Under the control of the second control signal, the second control circuit controls the connection between the second pull-down node and the fifth voltage terminal so that the potential of the second pull-down node is an effective voltage.

[0065] When the potential of the second pull-down node is an effective voltage, the pull-up node reset circuit controls the connection between the pull-up node and the second voltage terminal to reset the potential of the pull-up node.

[0066] In a third aspect, embodiments of this disclosure also provide a display device including the driving circuit described above.

[0067] Optionally, the display device includes a driving module;

[0068] The drive module includes multiple cascaded drive circuits;

[0069] The first input voltage terminal of the last stage drive circuit included in the drive module is not connected to the corresponding first input voltage, and the last stage drive circuit is a pseudo drive circuit.

[0070] The display device further includes a multi-row, multi-column pixel circuit disposed in the display area, wherein the last row of pixel circuits in the display device is a pseudo-pixel driving circuit.

[0071] The last-stage driving circuit is used to provide corresponding driving signals for the last row of pixel circuits, which do not emit light. Attached Figure Description

[0072] Figure 1 This is a structural diagram of the driving circuit described in the embodiments of this disclosure;

[0073] Figure 2 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0074] Figure 3 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0075] Figure 4 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0076] Figure 5 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0077] Figure 6 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0078] Figure 7 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0079] Figure 8 This is a circuit diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0080] Figure 9 This is a public announcement. Figure 8 The timing diagram of at least one embodiment of the driving circuit shown;

[0081] Figure 10This is the timing diagram of two adjacent drive circuit stages;

[0082] Figure 11A These are the simulation waveforms of the relevant drive circuit under reliability testing;

[0083] Figure 11B yes Figure 8 Comparison of simulation waveforms of at least one embodiment of the driving circuit shown under the same reliability conditions;

[0084] Figure 12A The waveforms of the currents I1 in M2 and I16 in M16 after the reliability test of the relevant drive circuits are shown.

[0085] Figure 12B This is a public announcement Figure 8 The waveforms of current I2 in M2 and current I16 in M16 after a reliability test for at least one embodiment of the drive circuit shown.

[0086] Figure 13A This is a waveform diagram of the potential of PU, the potential of PD1, and the drive signal output by O1 after the reliability test of the relevant drive circuit.

[0087] Figure 13B This is a public announcement Figure 8 The waveforms of the potential of PU, the potential of PD1, and the drive signal output by O1 after a reliability test are shown for at least one embodiment of the drive circuit.

[0088] Figure 14 This is a circuit diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0089] Figure 15A These are the simulation waveforms of the relevant drive circuit under reliability testing;

[0090] Figure 15B yes Figure 8 Comparison of simulation waveforms of at least one embodiment of the driving circuit shown under the same reliability conditions;

[0091] Figure 16A The waveforms of the currents I1 in M2 and I16 in M16 after the reliability test of the relevant drive circuits are shown.

[0092] Figure 16B This is a public announcement Figure 14 The waveforms of current I2 in M2 and current I16 in M16 after a reliability test for at least one embodiment of the drive circuit shown.

[0093] Figure 17A This is a waveform diagram of the potential of PU, the potential of PD1, and the drive signal output by O1 after the reliability test of the relevant drive circuit.

[0094] Figure 17B This is a public announcement Figure 14 The waveforms of the potential of PU, the potential of PD1, and the drive signal output by O1 after a reliability test are shown for at least one embodiment of the drive circuit.

[0095] Figure 18 This is a circuit diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0096] Figure 19 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0097] Figure 20 This is a circuit diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0098] Figure 21 This is a circuit diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0099] Figure 22 This is a circuit diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0100] Figure 23 This is a waveform diagram of the initial reset signal voltage provided by STV0, the first start signal STV1, the second start signal STV2, the third start signal STV3, the fourth start signal STV4, the first clock signal provided by the first clock signal terminal K11, the second clock signal provided by the second clock signal terminal K12, the third clock signal provided by the third clock signal terminal K13, the fourth clock signal provided by the fourth clock signal terminal K14, the fifth clock signal provided by the fifth clock signal terminal K15, the sixth clock signal provided by the sixth clock signal terminal K16, the seventh clock signal provided by the seventh clock signal terminal K17, the eighth clock signal provided by the eighth clock signal terminal K18, the first input voltage connected to the first input voltage terminal VSD, the second input voltage provided by the second input voltage terminal VDS, the control voltage provided by the first control voltage terminal GCH, the frame reset signal provided by the frame reset terminal GCL, and the low voltage signal provided by the low voltage terminal VGL. Detailed Implementation

[0101] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0102] like Figure 1As shown, the driving circuit described in this embodiment includes a first pull-down node PD1, a first control circuit 11, and a pull-up node reset circuit 12;

[0103] The first control circuit 11 is electrically connected to the first pull-down node PD1, the first control terminal Tr1 and the first voltage terminal V1 respectively, and is used to control the connection between the first pull-down node PD1 and the first voltage terminal V1 under the control of the first control signal provided by the first control terminal Tr1, so that the potential of the first pull-down node PD1 is an effective voltage.

[0104] The pull-up node reset circuit 12 is electrically connected to the first pull-down node PD1, the pull-up node PU, and the second voltage terminal V2, respectively. When the potential of the first pull-down node PD1 is an effective voltage, it controls the connection between the pull-up node PU and the second voltage terminal V2 to reset the potential of the pull-up node PU.

[0105] In at least one embodiment of this disclosure, when the transistor included in the pull-up node reset circuit 12 is an n-type transistor, the effective voltage can be a high voltage; when the transistor included in the pull-up node reset circuit 12 is a p-type transistor, the effective voltage can be a low voltage.

[0106] In at least one embodiment of this disclosure, the first voltage terminal may be a first control voltage terminal GCH, or the first voltage terminal may be a high voltage terminal, but is not limited thereto.

[0107] Optionally, the second voltage terminal V2 can be a low voltage terminal.

[0108] The driving circuit described in this embodiment adds a first control circuit 11. When the potential of the first control signal is an effective voltage, the first control circuit 11 controls the connection between the first pull-down node PD1 and the first voltage terminal V1, so that the potential of the first pull-down node PD1 is an effective voltage. Under the control of the potential of the first pull-down node PD1, the pull-up node reset circuit 12 controls the reset of the potential of the pull-up node PU, improves the noise reduction capability of the transistors included in the pull-up node reset circuit 12, prevents the driving circuit from outputting incorrectly, and enables the driving circuit to output the driving signal correctly.

[0109] In at least one embodiment of this disclosure, the first control terminal is a reset terminal, a first pull-down node, or a first pull-down control node.

[0110] like Figure 2 As shown, the driving circuit described in at least one embodiment of this disclosure includes a first pull-down node PD1, a first control circuit 11, and a pull-up node reset circuit 12;

[0111] The first control circuit 11 is electrically connected to the first pull-down node PD1, the reset terminal R1 and the first voltage terminal V1 respectively, and is used to control the connection between the first pull-down node PD1 and the first voltage terminal V1 under the control of the reset control signal provided by the reset terminal R1, so that the potential of the first pull-down node PD1 is an effective voltage.

[0112] The pull-up node reset circuit 12 is electrically connected to the first pull-down node PD1, the pull-up node PU, and the second voltage terminal V2, respectively. When the potential of the first pull-down node PD1 is an effective voltage, it controls the connection between the pull-up node PU and the second voltage terminal V2 to reset the potential of the pull-up node PU.

[0113] exist Figure 2 In at least one embodiment of the driving circuit shown, the first control terminal is the reset terminal R1; when the reset terminal R1 provides a high voltage signal, the potential of the first pull-down node PD1 is improved by the first voltage terminal V1, so that the current of the transistor included in the pull-up node reset circuit 12 increases, and the driving circuit will not have multiple outputs.

[0114] In at least one embodiment of this disclosure, the reset terminal may be a terminal that controls the writing of a first input voltage to the pull-up node to reset the potential of the pull-up node.

[0115] like Figure 3 As shown, the driving circuit described in at least one embodiment of this disclosure includes a first pull-down node PD1, a first control circuit 11, and a pull-up node reset circuit 12;

[0116] The first control circuit 11 is electrically connected to the first pull-down node PD1 and the first voltage terminal V1 respectively, and is used to control the connection between the first pull-down node PD1 and the first voltage terminal V1 under the control of the potential of the first pull-down node PD1, so that the potential of the first pull-down node PD1 is an effective voltage.

[0117] The pull-up node reset circuit 12 is electrically connected to the first pull-down node PD1, the pull-up node PU, and the second voltage terminal V2, respectively. When the potential of the first pull-down node PD1 is an effective voltage, it controls the connection between the pull-up node PU and the second voltage terminal V2 to reset the potential of the pull-up node PU.

[0118] exist Figure 3In at least one embodiment of the driving circuit shown, the first control terminal is the first pull-down node PD1; when the potential of the first pull-down node PD1 is high, the potential of the first pull-down node PD1 is improved by the first voltage terminal V1, which increases the current of the transistor included in the pull-up node reset circuit 12, enhances the noise reduction capability of the transistor included in the pull-up node reset circuit 12, and prevents the driving circuit from multi-output.

[0119] like Figure 4 As shown, the driving circuit described in at least one embodiment of this disclosure includes a first pull-down node PD1, a first control circuit 11, and a pull-up node reset circuit 12;

[0120] The first control circuit 11 is electrically connected to the first pull-down node PD1, the first pull-down control node PD_CN1 and the first voltage terminal V1 respectively, and is used to control the connection between the first pull-down node PD1 and the first voltage terminal V1 under the control of the potential of the first pull-down control node PD_CN1, so that the potential of the first pull-down node PD1 is an effective voltage.

[0121] The pull-up node reset circuit 12 is electrically connected to the first pull-down node PD1, the pull-up node PU, and the second voltage terminal V2, respectively. When the potential of the first pull-down node PD1 is an effective voltage, it controls the connection between the pull-up node PU and the second voltage terminal V2 to reset the potential of the pull-up node PU.

[0122] exist Figure 4 In at least one embodiment of the driving circuit shown, the first control terminal is the first pull-down control node PD_CN1; when the potential of the first pull-down control node PD_CN1 is high, the potential of the first pull-down node PD1 is improved by the first voltage terminal V1, which increases the current of the transistor included in the pull-up node reset circuit 12, enhances the noise reduction capability of the transistor included in the pull-up node reset circuit 12, and prevents the driving circuit from multi-output.

[0123] Optionally, the first control circuit includes a first transistor;

[0124] The gate of the first transistor is electrically connected to the first control terminal, the first electrode of the first transistor is electrically connected to the first pull-down node, and the second electrode of the first transistor is electrically connected to the first voltage terminal.

[0125] The pull-up node reset circuit includes a second transistor;

[0126] The gate of the second transistor is electrically connected to the first pull-down node, the first terminal of the second transistor is electrically connected to the pull-up node, and the second terminal of the second transistor is electrically connected to the second voltage terminal.

[0127] The driving circuit described in at least one embodiment of this disclosure may further include a reset circuit;

[0128] The reset circuit is electrically connected to the reset terminal, the pull-up node, and the first input voltage terminal, respectively, and is used to control the first input voltage provided by the first input voltage terminal to be written to the pull-up node under the control of the reset signal provided by the reset terminal.

[0129] In at least one embodiment of this disclosure, the driving circuit may further include a reset circuit, which, under the control of a reset signal, writes the first input voltage into the pull-up node.

[0130] The driving circuit described in at least one embodiment of this disclosure may further include a first pull-down node control circuit;

[0131] The first pull-down node control circuit is electrically connected to the first pull-down node, the first pull-down control node, the pull-up node, the first control voltage terminal, and the third voltage terminal, respectively. It is used to control the connection between the first control voltage terminal and the first pull-down control node under the control of the first control voltage provided by the first control voltage terminal, and to control the connection between the first pull-down control node and the third voltage terminal under the control of the potential of the pull-up node. It is also used to control the connection between the first pull-down node and the first control voltage terminal under the control of the potential of the first pull-down control node, and to control the connection between the first pull-down node and the third voltage terminal under the control of the potential of the pull-up node.

[0132] The first voltage terminal is the first control voltage terminal.

[0133] In a specific implementation, the driving circuit may further include a first pull-down node control circuit, which controls the potential of the first pull-down node and the potential of the first pull-down control node under the control of the potential of the pull-up node and the first control voltage.

[0134] In at least one embodiment of this disclosure, the third voltage terminal may be a low voltage terminal; the second voltage terminal and the third voltage terminal may be the same voltage terminal, but are not limited thereto.

[0135] The driving circuit described in at least one embodiment of this disclosure may further include an output circuit;

[0136] The output circuit is electrically connected to the pull-up node, the first pull-down node, the output clock signal terminal, the fourth voltage terminal, and the drive signal output terminal, respectively. It is used to control the output clock signal provided by the output clock signal terminal to be written to the drive signal output terminal under the control of the potential of the pull-up node, and to control the connection between the drive signal output terminal and the fourth voltage terminal under the control of the potential of the first pull-down node.

[0137] In at least one embodiment of this disclosure, the driving circuit may further include an output circuit. Under the control of the potential of the pull-up node, the output circuit writes the output clock signal to the driving signal output terminal and, under the control of the potential of the first pull-down node, controls the connection between the driving signal output terminal and the fourth voltage terminal to reduce noise at the driving signal output terminal.

[0138] Optionally, the fourth voltage terminal is a low voltage terminal, and the second voltage terminal, the third voltage terminal, and the fourth voltage terminal can be the same voltage terminal, but this is not a limitation.

[0139] The driving circuit described in at least one embodiment of this disclosure may further include a second pull-down node and a second control circuit;

[0140] The second control circuit is electrically connected to the second pull-down node, the second control terminal, and the fifth voltage terminal, respectively, and is used to control the connection between the second pull-down node and the fifth voltage terminal under the control of the second control signal provided by the second control terminal, so that the potential of the second pull-down node is an effective voltage;

[0141] The pull-up node reset circuit is also electrically connected to the second pull-down node, and is used to control the connection between the pull-up node and the second voltage terminal when the potential of the second pull-down node is an effective voltage, so as to reset the potential of the pull-up node.

[0142] Optionally, the fifth voltage terminal may be the second control voltage terminal or a high voltage terminal, but is not limited thereto.

[0143] At least one embodiment of the driving circuit disclosed herein adds a second control circuit. When the potential of the first control signal is an effective voltage, the second control circuit controls the connection between the second pull-down node and the fifth voltage terminal, so that the potential of the second pull-down node is an effective voltage. Under the control of the potential of the second pull-down node, the pull-up node reset circuit controls the reset of the potential of the pull-up node, improves the noise reduction capability of the transistor included in the pull-up node reset circuit, prevents the driving circuit from erroneously outputting, and enables the driving circuit to correctly output the driving signal.

[0144] Optionally, the second control terminal may be a reset terminal, a second pull-down node, or a second pull-down control node, but is not limited thereto.

[0145] like Figure 5 As shown, in Figure 1 Based on at least one embodiment of the driving circuit shown, the driving circuit described in at least one embodiment of this disclosure may further include a second pull-down node PD2 and a second control circuit 51;

[0146] The second control circuit 51 is electrically connected to the second pull-down node PD2, the second control terminal Tr2 and the fifth voltage terminal V5 respectively, and is used to control the connection between the second pull-down node PD2 and the fifth voltage terminal V5 under the control of the second control signal provided by the second control terminal Tr2, so that the potential of the second pull-down node PD2 is an effective voltage.

[0147] The pull-up node reset circuit 12 is also electrically connected to the second pull-down node PD2, and is used to control the connection between the pull-up node PU and the second voltage terminal V2 when the potential of the second pull-down node PD2 is an effective voltage, so as to reset the potential of the pull-up node PU.

[0148] Optionally, the second control circuit includes a third transistor; the pull-up node reset circuit further includes a fourth transistor.

[0149] The gate of the third transistor is electrically connected to the second control terminal, the first terminal of the third transistor is electrically connected to the second pull-down node, and the second terminal of the third transistor is electrically connected to the fifth voltage terminal.

[0150] The gate of the fourth transistor is electrically connected to the second pull-down node, the first terminal of the fourth transistor is electrically connected to the pull-up node, and the second terminal of the fourth transistor is electrically connected to the second voltage terminal.

[0151] like Figure 6 As shown, in Figure 5 Based on at least one embodiment of the driving circuit shown, the driving circuit described in at least one embodiment of this disclosure may further include a second pull-down node control circuit 61;

[0152] The second pull-down node control circuit 61 is electrically connected to the second pull-down node PD2, the second pull-down control node PD_CN2, the pull-up node PU, the second control voltage terminal GCH2, and the third voltage terminal V3, respectively. It is used to control the connection between the second control voltage terminal GCH2 and the second pull-down control node PD_CN2 under the control of the second control voltage provided by the second control voltage terminal GCH2, and to control the connection between the second pull-down control node PD_CN2 and the third voltage terminal V3 under the control of the potential of the pull-up node PU.

[0153] exist Figure 6 In at least one embodiment of the driving circuit shown, the fifth voltage terminal is the second control voltage terminal GCH2, but is not limited thereto.

[0154] This disclosure is as follows Figure 6 In at least one embodiment of the driving circuit, when in operation, the second pull-down node control circuit 61 controls the potential of the second pull-down node PD2 and the potential of the second pull-down control node PD_CN2 under the control of the potential of the pull-up node PU and the second control voltage.

[0155] The driving circuit described in at least one embodiment of this disclosure may further include an input circuit, an output reset circuit, an initial reset circuit, and an energy storage circuit;

[0156] The input circuit is electrically connected to the input terminal, the second input voltage terminal and the pull-up node respectively, and is used to control the second input voltage provided by the second input voltage terminal to be written to the pull-up node under the control of the input signal provided by the input terminal;

[0157] The output reset circuit is electrically connected to the frame reset terminal, the drive signal output terminal and the fourth voltage terminal respectively, and is used to control the connection between the drive signal output terminal and the fourth voltage terminal under the control of the frame reset signal provided by the frame reset terminal;

[0158] The initial reset circuit is electrically connected to the initial reset terminal, the pull-up node, and the fourth voltage terminal, respectively, and is used to control the connection between the pull-up node and the fourth voltage terminal under the control of the initial reset signal provided by the initial reset terminal;

[0159] The first end of the energy storage circuit is electrically connected to the pull-up node, and the second end of the energy storage circuit is electrically connected to the drive signal output terminal. The energy storage circuit is used to store electrical energy.

[0160] In at least one embodiment of this disclosure, the fourth voltage terminal may be a low voltage terminal, and the second voltage terminal, the third voltage terminal, and the fourth voltage terminal may be the same voltage terminal, but this is not a limitation.

[0161] When the driving circuit described in at least one embodiment of this disclosure is in operation, the input circuit writes the second input voltage into the pull-up node under the control of the input signal, the output reset circuit resets the driving signal provided by the driving signal output terminal under the control of the frame reset signal, and the initial reset circuit resets the potential of the pull-up node under the control of the initial reset signal.

[0162] like Figure 7 As shown, in Figure 1 Based on at least one embodiment of the driving circuit described herein, the driving circuit in at least one embodiment further includes a reset circuit 71, a first pull-down node control circuit 72, an output circuit 73, an input circuit 74, an output reset circuit 75, an initial reset circuit 76, and an energy storage circuit 70; the second voltage terminal is a low voltage terminal VGL, and the first voltage terminal is a first control voltage terminal GCH;

[0163] The reset circuit 71 is electrically connected to the reset terminal R1, the pull-up node PU, and the first input voltage terminal VSD, respectively, and is used to control the first input voltage provided by the first input voltage terminal VSD to be written to the pull-up node PU under the control of the reset signal provided by the reset terminal R1.

[0164] The first pull-down node control circuit 72 is electrically connected to the first pull-down node PD1, the first pull-down control node PD_CN1, the pull-up node PU, the first control voltage terminal GCH, and the low voltage terminal VGL, respectively. It is used to control the first control voltage terminal GCH to connect with the first pull-down control node PD_CN1 under the control of the first control voltage provided by the first control voltage terminal GCH, and to control the first pull-down control node PD_CN1 to connect with the low voltage terminal VGL1 under the control of the potential of the pull-up node PU. It is also used to control the first pull-down node PD1 to connect with the first control voltage terminal GCH under the control of the potential of the first pull-down control node PD_CN1, and to control the first pull-down node PD1 to connect with the low voltage terminal VGL under the control of the potential of the pull-up node PU.

[0165] The output circuit 73 is electrically connected to the pull-up node PU, the first pull-down node PD1, the output clock signal terminal K1, the low voltage terminal VGL, and the drive signal output terminal O1, respectively. It is used to control the output clock signal provided by the output clock signal terminal K1 to be written to the drive signal output terminal O1 under the control of the potential of the pull-up node PU, and to control the connection between the drive signal output terminal O1 and the low voltage terminal VGL under the control of the potential of the first pull-down node PD1.

[0166] The input circuit 74 is electrically connected to the input terminal I1, the second input voltage terminal VDS and the pull-up node PU respectively, and is used to control the second input voltage provided by the second input voltage terminal VDS to be written to the pull-up node PU under the control of the input signal provided by the input terminal I1;

[0167] The output reset circuit 75 is electrically connected to the frame reset terminal GCL, the drive signal output terminal O1 and the low voltage terminal VGL, respectively, and is used to control the connection between the drive signal output terminal O1 and the low voltage terminal VGL under the control of the frame reset signal provided by the frame reset terminal GCL.

[0168] The initial reset circuit 76 is electrically connected to the initial reset terminal STV0, the pull-up node PU, and the low voltage terminal VGL, respectively, and is used to control the connection between the pull-up node PU and the low voltage terminal VGL under the control of the initial reset signal provided by the initial reset terminal STV0.

[0169] The first end of the energy storage circuit 70 is electrically connected to the pull-up node PU, and the second end of the energy storage circuit 70 is electrically connected to the drive signal output terminal O1. The energy storage circuit 70 is used to store electrical energy.

[0170] Optionally, the reset circuit includes a fifth transistor;

[0171] The gate of the fifth transistor is electrically connected to the reset terminal, the first terminal of the fifth transistor is electrically connected to the pull-up node, and the second terminal of the fifth transistor is electrically connected to the first input voltage terminal.

[0172] Optionally, the first pull-down node control circuit includes a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor;

[0173] The gate and the first terminal of the sixth transistor are both electrically connected to the first control voltage terminal, and the second terminal of the sixth transistor is electrically connected to the first pull-down control node.

[0174] The gate of the seventh transistor is electrically connected to the pull-up node, the first terminal of the seventh transistor is electrically connected to the first pull-down control node, and the second terminal of the seventh transistor is electrically connected to the third voltage terminal.

[0175] The gate of the eighth transistor is electrically connected to the first pull-down control node, the first terminal of the eighth transistor is electrically connected to the first control voltage terminal, and the second terminal of the eighth transistor is electrically connected to the first pull-down node.

[0176] The gate of the ninth transistor is electrically connected to the pull-up node, the first terminal of the ninth transistor is electrically connected to the first pull-down node, and the second terminal of the ninth transistor is electrically connected to the third voltage terminal.

[0177] Optionally, the second pull-down node control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor;

[0178] The gate and the first terminal of the tenth transistor are both electrically connected to the second control voltage terminal, and the second terminal of the tenth transistor is electrically connected to the second pull-down control node.

[0179] The gate of the eleventh transistor is electrically connected to the pull-up node, the first terminal of the eleventh transistor is electrically connected to the second pull-down control node, and the second terminal of the eleventh transistor is electrically connected to the third voltage terminal.

[0180] The gate of the twelfth transistor is electrically connected to the second pull-down control node, the first terminal of the twelfth transistor is electrically connected to the second control voltage terminal, and the second terminal of the twelfth transistor is electrically connected to the second pull-down node.

[0181] The gate of the thirteenth transistor is electrically connected to the pull-up node, the first terminal of the thirteenth transistor is electrically connected to the second pull-down node, and the second terminal of the tenth transistor is electrically connected to the third voltage terminal.

[0182] Optionally, the input circuit includes a fourteenth transistor;

[0183] The gate of the fourteenth transistor is electrically connected to the input terminal, the first terminal of the fourteenth transistor is electrically connected to the second input voltage terminal, and the second terminal of the fourteenth transistor is electrically connected to the pull-up node.

[0184] The output circuit includes a fifteenth transistor and a sixteenth transistor;

[0185] The gate of the fifteenth transistor is electrically connected to the pull-up node, the first terminal of the fifteenth transistor is electrically connected to the output clock signal terminal, and the second terminal of the fifteenth transistor is electrically connected to the drive signal output terminal.

[0186] The gate of the sixteenth transistor is electrically connected to the first pull-down node, the first terminal of the sixteenth transistor is electrically connected to the drive signal output terminal, and the second terminal of the sixteenth transistor is electrically connected to the fourth voltage terminal.

[0187] The output reset circuit includes a seventeenth transistor;

[0188] The gate of the seventeenth transistor is electrically connected to the frame reset terminal, the first terminal of the seventeenth transistor is electrically connected to the drive signal output terminal, and the second terminal of the seventeenth transistor is electrically connected to the fourth voltage terminal.

[0189] The pull-down node reset circuit includes an eighteenth transistor;

[0190] The gate of the eighteenth transistor is electrically connected to the pull-up node, the first terminal of the eighteenth transistor is electrically connected to the first pull-down node, and the second terminal of the eighteenth transistor is electrically connected to the third voltage terminal.

[0191] The initial reset circuit includes a nineteenth transistor;

[0192] The gate of the nineteenth transistor is electrically connected to the initial reset terminal, the first terminal of the nineteenth transistor is electrically connected to the pull-up node, and the second terminal of the nineteenth transistor is electrically connected to the fourth voltage terminal.

[0193] The energy storage circuit includes a storage capacitor;

[0194] The first end of the storage capacitor is electrically connected to the pull-up node, and the second end of the storage capacitor is electrically connected to the drive signal output terminal.

[0195] like Figure 8 As shown, in Figure 7 Based on at least one embodiment of the driving circuit shown, the first control circuit 11 includes a first transistor M1; the first control terminal is electrically connected to the reset terminal R1. It should be noted that the reset terminal R1 here refers to: when multiple driving circuits are cascaded together, if the current driving circuit is the nth stage, for forward scanning, the reset terminal is connected to the output terminal of the n+i stage driving circuit, where i can be a positive integer greater than or equal to 1. Of course, for driving circuits in which the cascaded output terminal and the gate scan output terminal are output separately, the reset terminal can be a signal terminal connected to the cascaded output terminal.

[0196] The gate of the first transistor M1 is electrically connected to the reset terminal R1, the source of the first transistor M1 is electrically connected to the first pull-down node PD1, and the drain of the first transistor M1 is electrically connected to the first control voltage terminal GCH.

[0197] The pull-up node reset circuit 12 includes a second transistor M2;

[0198] The gate of the second transistor M2 is electrically connected to the first pull-down node PD1, the source of the second transistor M2 is electrically connected to the pull-up node PU, and the drain of the second transistor M2 is electrically connected to the low voltage terminal VGL.

[0199] The reset circuit 71 includes a fifth transistor M5;

[0200] The gate of the fifth transistor M5 is electrically connected to the reset terminal R1, the source of the fifth transistor M5 is electrically connected to the pull-up node PU, and the drain of the fifth transistor M5 is electrically connected to the first input voltage terminal VSD.

[0201] The first pull-down node control circuit 72 includes a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9;

[0202] The gate and source of the sixth transistor M6 are both electrically connected to the first control voltage terminal GCH, and the drain of the sixth transistor M6 is electrically connected to the first pull-down control node PD_CN1.

[0203] The gate of the seventh transistor M7 is electrically connected to the pull-up node PU, the source of the seventh transistor M7 is electrically connected to the first pull-down control node PD_CN1, and the drain of the seventh transistor M7 is electrically connected to the low voltage terminal VGL.

[0204] The gate of the eighth transistor M8 is electrically connected to the first pull-down control node PD_CN1, the source of the eighth transistor M8 is electrically connected to the first control voltage terminal GCH, and the drain of the eighth transistor M8 is electrically connected to the first pull-down node PD1.

[0205] The gate of the ninth transistor M9 is electrically connected to the pull-up node PU, the source of the ninth transistor M9 is electrically connected to the first pull-down node PD1, and the drain of the ninth transistor M9 is electrically connected to the low voltage terminal VGL.

[0206] The input circuit 74 includes a fourteenth transistor M14;

[0207] The gate of the fourteenth transistor M14 is electrically connected to the input terminal I1, the source of the fourteenth transistor M14 is electrically connected to the second input voltage terminal VDS, and the drain of the fourteenth transistor M14 is electrically connected to the pull-up node PU.

[0208] The output circuit 73 includes a fifteenth transistor M15 and a sixteenth transistor M16;

[0209] The gate of the fifteenth transistor M15 is electrically connected to the pull-up node PU, the source of the fifteenth transistor M15 is electrically connected to the output clock signal terminal K1, and the drain of the fifteenth transistor M15 is electrically connected to the drive signal output terminal O1.

[0210] The gate of the sixteenth transistor M16 is electrically connected to the first pull-down node PD1, the source of the sixteenth transistor M16 is electrically connected to the drive signal output terminal O1, and the drain of the sixteenth transistor M16 is electrically connected to the low voltage terminal VGL.

[0211] The output reset circuit 75 includes a seventeenth transistor M17;

[0212] The gate of the seventeenth transistor M17 is electrically connected to the frame reset terminal GCL, the source of the seventeenth transistor M17 is electrically connected to the drive signal output terminal O1, and the drain of the seventeenth transistor M17 is electrically connected to the low voltage terminal VGL.

[0213] The initial reset circuit 76 includes an eighteenth transistor M18;

[0214] The gate of the eighteenth transistor M18 is electrically connected to the initial reset terminal STV0, the source of the eighteenth transistor M18 is electrically connected to the pull-up node PU, and the drain of the eighteenth transistor M18 is electrically connected to the low voltage terminal VGL.

[0215] The energy storage circuit 70 includes a storage capacitor C1;

[0216] The first end of the storage capacitor C1 is electrically connected to the pull-up node PU, and the second end of the storage capacitor C1 is electrically connected to the drive signal output terminal O1.

[0217] exist Figure 8 Based on at least one embodiment of the driving circuit shown, all transistors are n-type thin-film transistors, but this is not a limitation.

[0218] This disclosure is as follows Figure 8 At least one embodiment of the driving circuit shown is capable of bidirectional scanning;

[0219] When VDS provides a high voltage signal and VSD provides a low voltage signal, the drive circuit can perform a forward scan;

[0220] When VDS provides a low voltage signal and VSD provides a high voltage signal, the drive circuit is capable of reverse scanning.

[0221] like Figure 9 As shown in this disclosure Figure 8 When at least one embodiment of the driving circuit shown is in operation, it is described using the example of VDS providing a high voltage signal and VSD providing a low voltage signal; the display cycle may include an input phase S1, an output phase S2, and a reset phase S3 set sequentially.

[0222] In the input phase S1, K1 provides a low voltage signal, I1 provides a high voltage signal, R1 provides a low voltage signal, GCH provides a high voltage signal, M1 is turned off, M14 is turned on, the high voltage signal provided by VDS is written to the pull-up node PU, causing the potential of PU to rise in one order, M15 is turned on, and O1 outputs a low voltage signal.

[0223] During the input phase S1, M6 and M7 are turned on to control the potential of PD_CN1 to a low voltage, M8 is turned off, and M9 is turned on to control the potential of PD1 to a low voltage.

[0224] In the output stage S2, K1 provides a high voltage signal, I1 provides a low voltage signal, R1 provides a high voltage signal, GCH provides a high voltage signal, the potential of PU is raised in a second order due to the coupling effect of C1, M15 continues to be turned on, O1 outputs a high voltage signal and provides an input signal for the adjacent next stage drive circuit;

[0225] During the reset phase S3, K1 provides a low voltage signal, I1 provides a low voltage signal, R1 provides a high voltage signal, GCH provides a high voltage signal, and M5 is turned on to reset the potential of PU and pull the potential of PU low.

[0226] During the reset phase S3, M6 is turned on, M7 is turned off, PD_CN1 is at a high voltage, M8 is turned on, M9 is turned off, PD1 is at a high voltage, and M2 and M16 are turned on, so that PU and VGL are connected and O1 outputs a low voltage signal.

[0227] exist Figure 9 In the diagram, S0 represents the output cutoff holding phase. During the output cutoff holding phase S0, O1 continuously outputs a low voltage signal.

[0228] This disclosure Figure 8In at least one embodiment of the driving circuit shown, during the reset phase S3, R1 provides a high voltage signal, GCH provides a high voltage signal, and M1 is turned on to pull the potential of PD1 high.

[0229] Figure 10 This is the timing diagram of two adjacent drive circuit stages. Figure 10 In the diagram, K11 is the clock signal connected to the first-stage driver circuit, K12 is the clock signal connected to the second-stage driver circuit, PU1 is the pull-up node in the first-stage driver circuit, I11 is the input signal connected to the input terminal in the first-stage driver circuit, and O11 is the dynamic signal output terminal of the first-stage driver circuit.

[0230] K12 is the clock signal connected to the second-stage driver circuit, PU2 is the pull-up node in the second-stage driver circuit, I12 is the input signal connected to the input terminal in the second-stage driver circuit, O12 is the drive signal output terminal of the second-stage driver circuit, and R11 is the reset signal connected to the reset terminal of the first-stage driver circuit.

[0231] This disclosure Figure 8 At least one embodiment of the driving circuit shown adds a first transistor M1, which can be turned on when a reset signal arrives, and further pull up the potential of PD1 by the high level provided by GCH. Figure 11A These are the simulation waveforms of the relevant drive circuit under reliability testing. Figure 11B yes Figure 8 Comparison of simulation waveforms of at least one embodiment of the driving circuit shown under the same reliability conditions.

[0232] This disclosure Figure 8 In at least one embodiment of the driving circuit shown, during operation, the high potential of PD1 is increased from 1V to 9V in the related art, and after the reset signal arrives, the potential of PU and the noise of the driving signal output by O1 are reduced.

[0233] Figure 12A The waveforms of the currents I1 in M2 and I16 in M16 after the reliability test of the relevant drive circuits are shown. Figure 12B This is a public announcement Figure 8 The waveforms of current I2 in M2 and current I16 in M16 after a reliability test for at least one embodiment of the drive circuit shown.

[0234] After reliability testing, the related driver circuit showed very small I2 and I16 values, as disclosed in this disclosure. Figure 8 In at least one embodiment of the driving circuit shown, during the period when the potential of PD1 is high after the arrival of the reset signal, M2 has a significantly large current, and the noise reduction capability of M2 is enhanced.

[0235] Figure 13AThis is a waveform diagram of the potential of PU, the potential of PD1, and the drive signal output by O1 after the reliability test of the relevant drive circuit. Figure 13B This is a public announcement Figure 8 The waveforms of the potential of PU, the potential of PD1, and the drive signal output by O1 after a reliability test are shown for at least one embodiment of the drive circuit.

[0236] In at least one embodiment of this disclosure, the reliability test can be a high temperature and high humidity reliability test; for example, the reliability test can be a high temperature reliability test at 60°C or higher; optionally, the reliability test can be a high temperature reliability test at 85°C; but it is not limited thereto.

[0237] After reliability testing, when the threshold voltage of M14 is increased by the same amount of negative bias, the drive signal output by the relevant drive circuit exhibits multi-output, while this disclosure... Figure 8 At least one embodiment of the driving circuit shown is able to output the driving signal correctly and maintain very little noise even after the reset signal is applied.

[0238] In at least one embodiment of this disclosure, when the associated driving circuit is outputting normally, within one display cycle (the display cycle may be, for example, one frame time), the driving signal output by the associated driving circuit has only one upward pulse; however, when the driving signal output by the associated driving circuit is multiplied, within one display cycle, the driving signal output by the associated driving circuit has multiple upward pulses. Figure 13A As shown, within one display cycle, the drive signal output by O1 has multiple upward pulses to produce a multi-output phenomenon.

[0239] Figure 14 At least one embodiment of the driving circuit shown is Figure 8 The only difference in at least one embodiment of the driving circuit shown is that the gate of M1 is electrically connected to the first pull-down node PD1.

[0240] Figure 14 In at least one embodiment of the driving circuit shown, when the potential of PU is low and the potential of PD1 is high, M1 is turned on, and the potential of PD1 is further pulled up by the first control voltage provided by GCH.

[0241] This disclosure Figure 14 At least one embodiment of the driving circuit shown adds a first transistor M1, which can turn on when the potential of PD1 is high, and further pull up the potential of PD1 through the high level provided by GCH.

[0242] Figure 15A These are the simulation waveforms of the relevant drive circuit under reliability testing. Figure 15B yes Figure 8 Comparison of simulation waveforms of at least one embodiment of the driving circuit shown under the same reliability conditions.

[0243] This disclosure Figure 14 In at least one embodiment of the driving circuit shown, the high potential of PD1 is increased from 1V in the related art to 11.5V during operation, and the potential of PU and the noise of the driving signal output by O1 are reduced after the reset signal arrives.

[0244] Figure 16A The waveforms of the currents I1 in M2 and I16 in M16 after the reliability test of the relevant drive circuits are shown. Figure 16B This is a public announcement Figure 14 The waveforms of current I2 in M2 and current I16 in M16 after a reliability test for at least one embodiment of the drive circuit shown.

[0245] After reliability testing, the related driver circuit showed very small I2 and I16 values, as disclosed in this disclosure. Figure 14 In at least one embodiment of the driving circuit shown, during the period when the potential of PD1 is high after the arrival of the reset signal, M2 has a significantly large current, and the noise reduction capability of M2 is enhanced.

[0246] Figure 17A This is a waveform diagram of the potential of PU, the potential of PD1, and the drive signal output by O1 after the reliability test of the relevant drive circuit. Figure 17B This is a public announcement Figure 14 The waveforms of the potential of PU, the potential of PD1, and the drive signal output by O1 after a reliability test are shown for at least one embodiment of the drive circuit.

[0247] After reliability testing, when the threshold voltage of M14 is increased by the same amount of negative bias, the drive signal output by the relevant drive circuit exhibits multi-output, while this disclosure... Figure 14 At least one embodiment of the driving circuit shown is able to output the driving signal correctly and maintain very little noise even after the reset signal is applied.

[0248] Figure 18 The difference between at least one embodiment of the driving circuit shown and at least one embodiment of the driving circuit shown in FIG11 is only that the gate of M1 is electrically connected to the first pull-down control node PD_CN1.

[0249] Figure 18 In at least one embodiment of the driving circuit shown, when the potential of PU is low and the potential of PD_CN1 is high, M1 is turned on, and the potential of PD1 is pulled up by the first control voltage provided by GCH.

[0250] Figure 18In at least one embodiment of the driving circuit shown, during operation, the potentials of PD1 and PD_CN1 are simultaneously high voltages, but the high voltage value of PD_CN1 is greater than the high voltage value of PD1. Therefore, compared to... Figure 14 In at least one embodiment of the driving circuit shown, the size of M1 can be set to be smaller. Since the tube size is smaller, the technical effect of a narrow bezel on the display panel can be further achieved.

[0251] In this public disclosure Figure 18 In at least one embodiment shown, only one pull-down node (first pull-down node PD1) is provided. This not only reduces the number of transistors used, facilitating the achievement of a narrow bezel on the display panel, but also allows the first control circuit to control the potential of the first pull-down node to be effective when the potential of the first control signal is effective. The pull-up node reset circuit, under the control of the potential of the first pull-down node, can reset the potential of the pull-up node, improving the noise reduction capability of the transistors included in the pull-up node reset circuit, preventing erroneous output from the driving circuit, and ensuring that the driving circuit can correctly output the driving signal. Figure 19 As shown, in Figure 6 Based on at least one embodiment of the driving circuit shown, the driving circuit described in at least one embodiment of this disclosure further includes a reset circuit 71, a first pull-down node control circuit 72, an output circuit 73, an input circuit 74, an output reset circuit 75, an initial reset circuit 76, and an energy storage circuit 70; the second voltage terminal is a low voltage terminal VGL, and the first voltage terminal is a first control voltage terminal GCH;

[0252] The reset circuit 71 is electrically connected to the reset terminal R1, the pull-up node PU, and the first input voltage terminal VSD, respectively, and is used to control the first input voltage provided by the first input voltage terminal VSD to be written to the pull-up node PU under the control of the reset signal provided by the reset terminal R1.

[0253] The first pull-down node control circuit 72 is electrically connected to the first pull-down node PD1, the first pull-down control node PD_CN1, the pull-up node PU, the first control voltage terminal GCH, and the low voltage terminal VGL, respectively. It is used to control the first control voltage terminal GCH to connect with the first pull-down control node PD_CN1 under the control of the first control voltage provided by the first control voltage terminal GCH, and to control the first pull-down control node PD_CN1 to connect with the low voltage terminal VGL1 under the control of the potential of the pull-up node PU. It is also used to control the first pull-down node PD1 to connect with the first control voltage terminal GCH under the control of the potential of the first pull-down control node PD_CN1, and to control the first pull-down node PD1 to connect with the low voltage terminal VGL under the control of the potential of the pull-up node PU.

[0254] The output circuit 73 is electrically connected to the pull-up node PU, the first pull-down node PD1, the second pull-down node PD2, the output clock signal terminal K1, the low voltage terminal VGL, and the drive signal output terminal O1, respectively. It is used to control the output clock signal provided by the output clock signal terminal K1 to be written to the drive signal output terminal O1 under the control of the potential of the pull-up node PU, control the connection between the drive signal output terminal O1 and the low voltage terminal VGL under the control of the potential of the first pull-down node PD1, and control the connection between the drive signal output terminal O1 and the low voltage terminal VGL under the control of the potential of the second pull-down node PD2.

[0255] The input circuit 74 is electrically connected to the input terminal I1, the second input voltage terminal VDS and the pull-up node PU respectively, and is used to control the second input voltage provided by the second input voltage terminal VDS to be written to the pull-up node PU under the control of the input signal provided by the input terminal I1;

[0256] The output reset circuit 75 is electrically connected to the frame reset terminal GCL, the drive signal output terminal O1 and the low voltage terminal VGL, respectively, and is used to control the connection between the drive signal output terminal O1 and the low voltage terminal VGL under the control of the frame reset signal provided by the frame reset terminal GCL.

[0257] The initial reset circuit 76 is electrically connected to the initial reset terminal STV0, the pull-up node PU, and the low voltage terminal VGL, respectively, and is used to control the connection between the pull-up node PU and the low voltage terminal VGL under the control of the initial reset signal provided by the initial reset terminal STV0.

[0258] The first end of the energy storage circuit 70 is electrically connected to the pull-up node PU, and the second end of the energy storage circuit 70 is electrically connected to the drive signal output terminal O1. The energy storage circuit 70 is used to store electrical energy.

[0259] like Figure 20 As shown in this disclosure Figure 8 Based on at least one embodiment of the driving circuit shown, the first control circuit 11 includes a first transistor M1; both the first control terminal and the second control terminal are reset terminals R1;

[0260] The gate of the first transistor M1 is electrically connected to the reset terminal R1, the source of the first transistor M1 is electrically connected to the first pull-down node PD1, and the drain of the first transistor M1 is electrically connected to the first control voltage terminal GCH.

[0261] The pull-up node reset circuit 12 includes a second transistor M2;

[0262] The gate of the second transistor M2 is electrically connected to the first pull-down node PD1, the source of the second transistor M2 is electrically connected to the pull-up node PU, and the drain of the second transistor M2 is electrically connected to the low voltage terminal VGL.

[0263] The second control circuit 51 includes a third transistor M3; the pull-up node reset circuit 12 also includes a fourth transistor M4;

[0264] The gate of the third transistor M3 is electrically connected to the reset terminal R1, the source of the third transistor M3 is electrically connected to the second pull-down node PD2, and the drain of the third transistor M3 is electrically connected to the second control voltage terminal GCH2.

[0265] The gate of the fourth transistor M4 is electrically connected to the second pull-down node PD2, the source of the fourth transistor M4 is electrically connected to the pull-up node PU, and the drain of the fourth transistor M4 is electrically connected to the low voltage terminal VGL.

[0266] The reset circuit 71 includes a fifth transistor M5;

[0267] The gate of the fifth transistor M5 is electrically connected to the reset terminal R1, the source of the fifth transistor M5 is electrically connected to the pull-up node PU, and the drain of the fifth transistor M5 is electrically connected to the first input voltage terminal VSD.

[0268] The first pull-down node control circuit 72 includes a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9;

[0269] The gate and source of the sixth transistor M6 are both electrically connected to the first control voltage terminal GCH, and the drain of the sixth transistor M6 is electrically connected to the first pull-down control node PD_CN1.

[0270] The gate of the seventh transistor M7 is electrically connected to the pull-up node PU, the source of the seventh transistor M7 is electrically connected to the first pull-down control node PD_CN1, and the drain of the seventh transistor M7 is electrically connected to the low voltage terminal VGL.

[0271] The gate of the eighth transistor M8 is electrically connected to the first pull-down control node PD_CN1, the source of the eighth transistor M8 is electrically connected to the first control voltage terminal GCH, and the drain of the eighth transistor M8 is electrically connected to the first pull-down node PD1.

[0272] The gate of the ninth transistor M9 is electrically connected to the pull-up node PU, the source of the ninth transistor M9 is electrically connected to the first pull-down node PD1, and the drain of the ninth transistor M9 is electrically connected to the low voltage terminal VGL.

[0273] The second pull-down node control circuit 61 includes a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13;

[0274] The gate and source of the tenth transistor M10 are both electrically connected to the second control voltage terminal GCH2, and the drain of the tenth transistor M10 is electrically connected to the second pull-down control node PD_CN2.

[0275] The gate of the eleventh transistor M11 is electrically connected to the pull-up node PU, the source of the eleventh transistor M11 is electrically connected to the second pull-down control node PD_CN2, and the drain of the eleventh transistor M11 is electrically connected to the low voltage terminal VGL.

[0276] The gate of the twelfth transistor M12 is electrically connected to the second pull-down control node PD_CN2, the source of the twelfth transistor M12 is electrically connected to the second control voltage terminal GCH2, and the drain of the twelfth transistor M12 is electrically connected to the second pull-down node PD2.

[0277] The gate of the thirteenth transistor M13 is electrically connected to the pull-up node PU, the source of the thirteenth transistor M13 is electrically connected to the second pull-down node PD2, and the second terminal of the tenth transistor is electrically connected to the third voltage terminal.

[0278] The input circuit 74 includes a fourteenth transistor M14;

[0279] The gate of the fourteenth transistor M14 is electrically connected to the input terminal I1, the source of the fourteenth transistor M14 is electrically connected to the second input voltage terminal VDS, and the drain of the fourteenth transistor M14 is electrically connected to the pull-up node PU.

[0280] The output circuit 73 includes a fifteenth transistor M15 and a sixteenth transistor M16;

[0281] The gate of the fifteenth transistor M15 is electrically connected to the pull-up node PU, the source of the fifteenth transistor M15 is electrically connected to the output clock signal terminal K1, and the drain of the fifteenth transistor M15 is electrically connected to the drive signal output terminal O1.

[0282] The gate of the sixteenth transistor M16 is electrically connected to the first pull-down node PD1, the source of the sixteenth transistor M16 is electrically connected to the drive signal output terminal O1, and the drain of the sixteenth transistor M16 is electrically connected to the low voltage terminal VGL.

[0283] The output reset circuit 75 includes a seventeenth transistor M17;

[0284] The gate of the seventeenth transistor M17 is electrically connected to the frame reset terminal GCL, the source of the seventeenth transistor M17 is electrically connected to the drive signal output terminal O1, and the drain of the seventeenth transistor M17 is electrically connected to the low voltage terminal VGL.

[0285] The initial reset circuit 76 includes an eighteenth transistor M18;

[0286] The gate of the eighteenth transistor M18 is electrically connected to the initial reset terminal STV0, the source of the eighteenth transistor M18 is electrically connected to the pull-up node PU, and the drain of the eighteenth transistor M18 is electrically connected to the low voltage terminal VGL.

[0287] The energy storage circuit 70 includes a storage capacitor C1;

[0288] The first end of the storage capacitor C1 is electrically connected to the pull-up node PU, and the second end of the storage capacitor C1 is electrically connected to the drive signal output terminal O1.

[0289] The output circuit 73 also includes a nineteenth transistor M19;

[0290] The gate of the nineteenth transistor M19 is electrically connected to the second pull-down node PD2, the source of the nineteenth transistor M19 is electrically connected to the drive signal output terminal O1, and the drain of the nineteenth transistor M19 is electrically connected to the low voltage terminal VGL.

[0291] exist Figure 20 In at least one embodiment of the driving circuit shown, all transistors may be n-type thin-film transistors, but are not limited thereto.

[0292] This disclosure is as follows Figure 20 At least one embodiment of the driving circuit shown is capable of bidirectional scanning;

[0293] When VDS provides a high voltage signal and VSD provides a low voltage signal, the drive circuit can perform a forward scan;

[0294] When VDS provides a low voltage signal and VSD provides a high voltage signal, the drive circuit is capable of reverse scanning.

[0295] This disclosure Figure 14 At least one embodiment of the driving circuit shown employs two pull-down nodes: a first pull-down node PD1 and a second pull-down node PD2;

[0296] Every few display cycles (e.g., every 2-3 seconds), the potential of the first control voltage provided by GCH2 and the potential of the second control voltage provided by GCH2 alternately become high voltage;

[0297] When the potential of the first control voltage is high, the potential of the second control voltage can be low; when the potential of the second control voltage is low, the potential of the first control voltage can be high; but this is not a limitation.

[0298] This disclosure Figure 20 In at least one embodiment of the driving circuit shown, when the potential of the first control voltage is high, the potential of PD1 is high during the output phase included in the display cycle, and during the output cutoff holding phase after the output phase.

[0299] When the potential of the second control voltage is high, during the reset phase included in the display cycle, and during the output cutoff holding phase set after the reset phase, the potential of PD2 is high.

[0300] The transistor controlled by PD1 and the transistor controlled by PD2 are turned on alternately, thereby improving the threshold voltage drift phenomenon of the transistor.

[0301] This disclosure Figure 20 In at least one embodiment of the driving circuit shown, when the potential of the first control voltage is high, during the reset phase included in the display cycle, R1 provides a high voltage signal, M1 is turned on, so as to pull up the potential of PD1.

[0302] When the potential of the second control voltage is high, during the reset phase included in the display cycle, R1 provides a high voltage signal, and M3 is turned on to pull up the potential of PD2.

[0303] Figure 21 At least one embodiment of the driving circuit shown is Figure 20 The only difference in at least one embodiment of the driving circuit shown is that the gate of M1 is electrically connected to the first pull-down node PD1, and the gate of M3 is electrically connected to the second pull-down node PD2.

[0304] Figure 21 In at least one embodiment of the driving circuit shown, when the first control voltage is high, the potential of PU is low and the potential of PD1 is high, M1 is turned on, and the potential of PD1 is further pulled up by the first control voltage provided by GCH.

[0305] When the second control voltage is high, and the potential of PU is low while the potential of PD2 is high, M3 is turned on, further raising the potential of PD1 by the second control voltage provided by GCH2.

[0306] Figure 22 At least one embodiment of the driving circuit shown is Figure 20 The only difference in at least one embodiment of the driving circuit shown is that the gate of M1 is electrically connected to the first pull-down control node PD_CN1, and the gate of M2 is electrically connected to the second pull-down control node PD_CN2.

[0307] Figure 22 In at least one embodiment of the driving circuit shown, when the first control voltage is high, the potential of PU is low, and the potential of PD_CN1 is high, M1 is turned on, and the potential of PD1 is pulled up by the first control voltage provided by GCH.

[0308] When the second control voltage is high, and the potential of PU is low while the potential of PD_CN2 is high, M3 is turned on, and the potential of PD2 is raised by the second control voltage provided by GCH2.

[0309] Figure 22 In at least one embodiment of the driving circuit shown, when the first control voltage is high, the potentials of PD1 and PD_CN1 are both high, but the high voltage value of PD_CN1 is greater than the high voltage value of PD1. Therefore, compared to... Figure 20 In at least one embodiment of the driving circuit shown, the size of M1 can be set to be relatively small;

[0310] When the second control voltage is high, the potentials of PD2 and PD_CN2 are both high, but the high voltage value of PD_CN2 is greater than that of PD2. Therefore, compared to... Figure 20 In at least one embodiment of the driving circuit shown, the size of M3 can be set to be relatively small.

[0311] In related technologies, during high-temperature and high-humidity reliability testing of drive circuits, jitter and horizontal stripe defects may occur. After the reliability test, the threshold voltage of M14 drifts negatively, the leakage current of M14 increases (direct factor), and the noise reduction capability of M2 and M16 decreases (indirect factor). These factors collectively lead to increased noise at the pull-up nodes and drive signal terminals of this stage of the drive circuit. The noise at the drive output signal terminal causes even greater noise at the pull-up nodes of the next stage of the drive circuit, resulting in more severe noise at the drive signal output terminal of the next stage. This noise accumulates at each stage, leading to severe multi-output at the drive signal output terminal of later-stage drive circuits. The more severe the negative drift of the threshold voltage of M14, the faster the noise accumulates, resulting in multi-output at the drive signal output terminal. For the 2.0-inch simulation results, multi-output occurs when the threshold voltage of M14 drifts to -0.6V, but not when the threshold voltage of M14 is greater than -0.5V. After reliability testing, a reverse scan was performed. At 85 degrees Celsius, the threshold voltage of M14 drifted significantly. During the reverse scan, the leakage current of M14, acting as a reset unit, increased, resulting in no second-order rise in the pull-up node potential and preventing the drive signal output from functioning correctly. At 70 degrees Celsius, the drift of M14 was smaller, and its leakage current was also smaller. Therefore, the pull-up node potential was able to achieve a second-order rise, and the drive signal output functioned correctly.

[0312] In related technologies, during forward scanning, the potential of the pull-up node is not reset via M5 due to the scan tail line (the drain of M5 is not connected to the corresponding first input voltage), and the drive signal output terminal outputs a complete clock signal until the frame is reset. However, in the middle line, due to the reset and leakage noise of M14, the Multi output period of the drive signal output terminal has no obvious regularity.

[0313] When improving the relevant technologies, the initial suspicion was that the decrease in PD1 potential and the drift in M2 characteristics after reliability testing reduced the noise reduction capability of the pull-up node PU, causing multi-waveform output and jittering. However, other models also showed that the PD1 potential dropped to 1V-2V after reliability testing. The measured threshold voltage of M2 after reliability testing for the 2.0-inch derivative was 14V, which is within the normal range after reliability testing. Simulations showed that the decrease in PD1 potential and the drift in the threshold voltage of M2 would not cause severe multi-output at the drive signal output.

[0314] In related technologies, after reliability testing, when the characteristics of the transistors drift normally (threshold voltage of M1 is 0.29V, threshold voltage of M8 is 6.92V, threshold voltage of M2 is 14.79V), the potentials of PU, PD1, and the waveforms of the drive signal output from the drive signal output terminal are as follows: the high voltage value of PD1 is 1.33V, the low voltage value of PU is -11V, and when the potential of PU is low, it will fluctuate upward by 1.7V multiple times, but the drive signal can be output normally.

[0315] After the reliability test, when the characteristic drift of M2 is aggravated (the threshold voltage of M2 is increased to 25V), the waveforms of the potential of PU, the potential of PD1, and the drive signal output at the drive signal output terminal are observed. The low voltage value of PU is -11V, and when the potential of PU is low, it will fluctuate upward by 2V multiple times, but the drive signal can be output normally.

[0316] After the reliability test, the drift of the threshold voltage of M2 caused the potential of PU to fluctuate to some extent, but the potential of PU was still low and would not cause the drive signal to be output incorrectly. The rise of the potential of PU had other reasons.

[0317] In related technologies, based on the analysis of high-temperature flickering issues, bidirectional scanning is prone to flickering due to the negative drift of the threshold voltage of M14 after reliability testing, leading to increased leakage current and increased noise in the power supply unit (PU). This, combined with a single pull-down node, results in increased flickering. After increasing the degree of negative drift of M14 during reliability testing (M14's threshold voltage was -3V, while the threshold voltages of other transistors were at normal levels after reliability testing), simulation results confirm that the PU's potential and drive signal terminals do indeed generate severe multi-output, causing display abnormalities.

[0318] Based on the above tests, this embodiment adds a first control circuit 11. When the potential of the first control signal is an effective voltage, the first control circuit 11 controls the connection between the first pull-down node PD1 and the first voltage terminal V1, so that the potential of the first pull-down node PD1 is an effective voltage. Under the control of the potential of the first pull-down node PD1, the pull-up node reset circuit 12 controls the reset of the potential of the pull-up node PU, improves the noise reduction capability of the transistors included in the pull-up node reset circuit 12, prevents the drive circuit from outputting incorrectly, and enables the drive circuit to output the drive signal correctly.

[0319] The driving method described in this embodiment is applied to the above-mentioned driving circuit, and the driving method includes:

[0320] Under the control of the first control signal, the first control circuit controls the connection between the first pull-down node and the first voltage terminal so that the potential of the first pull-down node is an effective voltage.

[0321] When the potential of the first pull-down node is an effective voltage, the pull-up node reset circuit controls the connection between the pull-up node and the second voltage terminal to reset the potential of the pull-up node.

[0322] In at least one embodiment of this disclosure, the driving circuit further includes a second pull-down node and a second control circuit; the driving method further includes:

[0323] Under the control of the second control signal, the second control circuit controls the connection between the second pull-down node and the fourth voltage terminal so that the potential of the second pull-down node is an effective voltage.

[0324] When the potential of the second pull-down node is an effective voltage, the pull-up node reset circuit controls the connection between the pull-up node and the second voltage terminal to reset the potential of the pull-up node.

[0325] The display device described in this embodiment includes the driving circuit described above.

[0326] The display device described in at least one embodiment of this disclosure includes a driving module;

[0327] The drive module includes multiple cascaded drive circuits;

[0328] The first input voltage terminal of the last stage drive circuit included in the drive module is not connected to the corresponding first input voltage, and the last stage drive circuit is a pseudo drive circuit.

[0329] The display device further includes a multi-row, multi-column pixel circuit disposed in the display area, and the last row of pixel circuits in the display device can be a pseudo-pixel driving circuit.

[0330] The last-stage driving circuit is used to provide corresponding driving signals for the last row of pixel circuits, which do not emit light.

[0331] In the display device described in at least one embodiment of this disclosure, a multi-stage driving circuit cascaded together forms a driving module;

[0332] When the driving module is scanned in the forward direction, the reset circuit included in the last stage driving circuit is not connected to the corresponding first input voltage. Therefore, during the reset phase, the transistors included in the reset circuit will not be turned on and will not reset the potential of the pull-up node in the last stage driving circuit. The last stage driving circuit can be a dummy driving circuit. The dummy driving circuit can provide driving signals to the dummy pixel circuit, which is not used for display.

[0333] In a specific implementation, the display device may include a first driving module located on the left side of the display panel and a second driving module located on the right side of the display panel;

[0334] The first drive module includes a multi-stage drive circuit that is cascaded together.

[0335] The second drive module includes a multi-stage drive circuit that is cascaded together.

[0336] The second drive module is electrically connected to the second clock signal terminal K12, the fourth clock signal terminal K14, the sixth clock signal terminal K16 and the eighth clock signal terminal K18 respectively;

[0337] The first drive module is electrically connected to the first clock signal terminal K11, the third clock signal terminal K13, the fifth clock signal terminal K15 and the seventh clock signal terminal K17 respectively;

[0338] Figure 23 This is a waveform diagram of the initial reset signal voltage provided by STV0, the first start signal STV1, the second start signal STV2, the third start signal STV3, the fourth start signal STV4, the first clock signal provided by the first clock signal terminal K11, the second clock signal provided by the second clock signal terminal K12, the third clock signal provided by the third clock signal terminal K13, the fourth clock signal provided by the fourth clock signal terminal K14, the fifth clock signal provided by the fifth clock signal terminal K15, the sixth clock signal provided by the sixth clock signal terminal K16, the seventh clock signal provided by the seventh clock signal terminal K17, the eighth clock signal provided by the eighth clock signal terminal K18, the first input voltage connected to the first input voltage terminal VSD, the second input voltage provided by the second input voltage terminal VDS, the control voltage provided by the first control voltage terminal GCH, the frame reset signal provided by the frame reset terminal GCL, and the low voltage signal provided by the low voltage terminal VGL.

[0339] exist Figure 23 In this context, SN represents the time of frame N, SN+1 represents the time of frame N+1, and B0 represents the blank time period between SN and SN+1.

[0340] The display device provided in this disclosure can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0341] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A driving circuit, characterized in that, It includes a first pull-down node, a first control circuit, and a pull-up node reset circuit; The first control circuit is electrically connected to the first pull-down node, the first control terminal, and the first voltage terminal respectively, and is used to control the connection between the first pull-down node and the first voltage terminal under the control of the first control signal provided by the first control terminal, so that the potential of the first pull-down node is an effective voltage. The pull-up node reset circuit is electrically connected to the first pull-down node, the pull-up node, and the second voltage terminal, respectively, and is used to control the connection between the pull-up node and the second voltage terminal when the potential of the first pull-down node is an effective voltage, so as to reset the potential of the pull-up node; The driving circuit also includes a second pull-down node and a second control circuit; The second control circuit is electrically connected to the second pull-down node, the second control terminal, and the fifth voltage terminal, respectively, and is used to control the connection between the second pull-down node and the fifth voltage terminal under the control of the second control signal provided by the second control terminal, so that the potential of the second pull-down node is an effective voltage; The pull-up node reset circuit is also electrically connected to the second pull-down node, and is used to control the connection between the pull-up node and the second voltage terminal when the potential of the second pull-down node is an effective voltage, so as to reset the potential of the pull-up node.

2. The driving circuit as described in claim 1, characterized in that, The first control terminal is a reset terminal, a first pull-down node, or a first pull-down control node.

3. The driving circuit as described in claim 1, characterized in that, The first control circuit includes a first transistor; The gate of the first transistor is electrically connected to the first control terminal, the first electrode of the first transistor is electrically connected to the first pull-down node, and the second electrode of the first transistor is electrically connected to the first voltage terminal. The pull-up node reset circuit includes a second transistor; The gate of the second transistor is electrically connected to the first pull-down node, the first terminal of the second transistor is electrically connected to the pull-up node, and the second terminal of the second transistor is electrically connected to the second voltage terminal.

4. The driving circuit as described in claim 2, characterized in that, It also includes a reset circuit; The reset circuit is electrically connected to the reset terminal, the pull-up node, and the first input voltage terminal, respectively, and is used to control the first input voltage provided by the first input voltage terminal to be written to the pull-up node under the control of the reset signal provided by the reset terminal.

5. The driving circuit as described in claim 2, characterized in that, It also includes the first drop-down node control circuit; The first pull-down node control circuit is electrically connected to the first pull-down node, the first pull-down control node, the pull-up node, the first control voltage terminal, and the third voltage terminal, respectively. It is used to control the connection between the first control voltage terminal and the first pull-down control node under the control of the first control voltage provided by the first control voltage terminal, and to control the connection between the first pull-down control node and the third voltage terminal under the control of the potential of the pull-up node. It is also used to control the connection between the first pull-down node and the first control voltage terminal under the control of the potential of the first pull-down control node, and to control the connection between the first pull-down node and the third voltage terminal under the control of the potential of the pull-up node. The first voltage terminal is the first control voltage terminal.

6. The driving circuit as described in claim 5, characterized in that, It also includes the output circuit; The output circuit is electrically connected to the pull-up node, the first pull-down node, the output clock signal terminal, the fourth voltage terminal, and the drive signal output terminal, respectively. It is used to control the output clock signal provided by the output clock signal terminal to be written to the drive signal output terminal under the control of the potential of the pull-up node, and to control the connection between the drive signal output terminal and the fourth voltage terminal under the control of the potential of the first pull-down node.

7. The driving circuit as described in claim 1, characterized in that, The second control terminal is a reset terminal, a second pull-down node, or a second pull-down control node.

8. The driving circuit as described in claim 1, characterized in that, The second control circuit includes a third transistor; the pull-up node reset circuit also includes a fourth transistor; The gate of the third transistor is electrically connected to the second control terminal, the first terminal of the third transistor is electrically connected to the second pull-down node, and the second terminal of the third transistor is electrically connected to the fifth voltage terminal. The gate of the fourth transistor is electrically connected to the second pull-down node, the first terminal of the fourth transistor is electrically connected to the pull-up node, and the second terminal of the fourth transistor is electrically connected to the second voltage terminal.

9. The driving circuit as described in claim 7, characterized in that, It also includes the second pull-down node control circuit; The second pull-down node control circuit is electrically connected to the second pull-down node, the second pull-down control node, the pull-up node, the second control voltage terminal, and the third voltage terminal, respectively. It is used to control the connection between the second control voltage terminal and the second pull-down control node under the control of the second control voltage provided by the second control voltage terminal, and to control the connection between the second pull-down control node and the third voltage terminal under the control of the potential of the pull-up node. The fifth voltage terminal is the second control voltage terminal.

10. The driving circuit as described in claim 6, characterized in that, It also includes an input circuit, an output reset circuit, an initial reset circuit, and an energy storage circuit; The input circuit is electrically connected to the input terminal, the second input voltage terminal and the pull-up node respectively, and is used to control the second input voltage provided by the second input voltage terminal to be written to the pull-up node under the control of the input signal provided by the input terminal; The output reset circuit is electrically connected to the frame reset terminal, the drive signal output terminal and the fourth voltage terminal respectively, and is used to control the connection between the drive signal output terminal and the fourth voltage terminal under the control of the frame reset signal provided by the frame reset terminal; The initial reset circuit is electrically connected to the initial reset terminal, the pull-up node, and the fourth voltage terminal, respectively, and is used to control the connection between the pull-up node and the fourth voltage terminal under the control of the initial reset signal provided by the initial reset terminal; The first end of the energy storage circuit is electrically connected to the pull-up node, and the second end of the energy storage circuit is electrically connected to the drive signal output terminal. The energy storage circuit is used to store electrical energy.

11. The driving circuit as described in claim 4, characterized in that, The reset circuit includes a fifth transistor; The gate of the fifth transistor is electrically connected to the reset terminal, the first terminal of the fifth transistor is electrically connected to the pull-up node, and the second terminal of the fifth transistor is electrically connected to the first input voltage terminal.

12. The driving circuit as described in claim 5, characterized in that, The first pull-down node control circuit includes a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor; The gate and the first terminal of the sixth transistor are both electrically connected to the first control voltage terminal, and the second terminal of the sixth transistor is electrically connected to the first pull-down control node. The gate of the seventh transistor is electrically connected to the pull-up node, the first terminal of the seventh transistor is electrically connected to the first pull-down control node, and the second terminal of the seventh transistor is electrically connected to the third voltage terminal. The gate of the eighth transistor is electrically connected to the first pull-down control node, the first terminal of the eighth transistor is electrically connected to the first control voltage terminal, and the second terminal of the eighth transistor is electrically connected to the first pull-down node. The gate of the ninth transistor is electrically connected to the pull-up node, the first terminal of the ninth transistor is electrically connected to the first pull-down node, and the second terminal of the ninth transistor is electrically connected to the third voltage terminal.

13. The driving circuit as described in claim 9, characterized in that, The second pull-down node control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor; The gate and the first terminal of the tenth transistor are both electrically connected to the second control voltage terminal, and the second terminal of the tenth transistor is electrically connected to the second pull-down control node; The gate of the eleventh transistor is electrically connected to the pull-up node, the first terminal of the eleventh transistor is electrically connected to the second pull-down control node, and the second terminal of the eleventh transistor is electrically connected to the third voltage terminal. The gate of the twelfth transistor is electrically connected to the second pull-down control node, the first terminal of the twelfth transistor is electrically connected to the second control voltage terminal, and the second terminal of the twelfth transistor is electrically connected to the second pull-down node. The gate of the thirteenth transistor is electrically connected to the pull-up node, the first terminal of the thirteenth transistor is electrically connected to the second pull-down node, and the second terminal of the thirteenth transistor is electrically connected to the third voltage terminal.

14. The driving circuit as described in claim 10, characterized in that, The input circuit includes a fourteenth transistor; The gate of the fourteenth transistor is electrically connected to the input terminal, the first terminal of the fourteenth transistor is electrically connected to the second input voltage terminal, and the second terminal of the fourteenth transistor is electrically connected to the pull-up node. The output circuit includes a fifteenth transistor and a sixteenth transistor; The gate of the fifteenth transistor is electrically connected to the pull-up node, the first terminal of the fifteenth transistor is electrically connected to the output clock signal terminal, and the second terminal of the fifteenth transistor is electrically connected to the drive signal output terminal. The gate of the sixteenth transistor is electrically connected to the first pull-down node, the first terminal of the sixteenth transistor is electrically connected to the drive signal output terminal, and the second terminal of the sixteenth transistor is electrically connected to the fourth voltage terminal. The output reset circuit includes a seventeenth transistor; The gate of the seventeenth transistor is electrically connected to the frame reset terminal, the first terminal of the seventeenth transistor is electrically connected to the drive signal output terminal, and the second terminal of the seventeenth transistor is electrically connected to the fourth voltage terminal. The initial reset circuit includes an eighteenth transistor; The gate of the eighteenth transistor is electrically connected to the initial reset terminal, the first terminal of the eighteenth transistor is electrically connected to the pull-up node, and the second terminal of the eighteenth transistor is electrically connected to the fourth voltage terminal. The energy storage circuit includes a storage capacitor; The first end of the storage capacitor is electrically connected to the pull-up node, and the second end of the storage capacitor is electrically connected to the drive signal output terminal.

15. The driving circuit as described in claim 14, characterized in that, It also includes a second dropdown node; The output circuit is also electrically connected to the second pull-down node, and is used to control the connection between the drive signal output terminal and the fourth voltage terminal under the control of the potential of the second pull-down node.

16. The driving circuit as described in claim 15, characterized in that, The output circuit also includes a nineteenth transistor; The gate of the nineteenth transistor is electrically connected to the second pull-down node, the first terminal of the nineteenth transistor is electrically connected to the drive signal output terminal, and the second terminal of the nineteenth transistor is electrically connected to the fourth voltage terminal.

17. A driving method applied to a driving circuit as described in any one of claims 1 to 16, characterized in that, The driving method includes: Under the control of the first control signal, the first control circuit controls the connection between the first pull-down node and the first voltage terminal so that the potential of the first pull-down node is an effective voltage. When the potential of the first pull-down node is an effective voltage, the pull-up node reset circuit controls the connection between the pull-up node and the second voltage terminal to reset the potential of the pull-up node; The driving circuit further includes a second pull-down node and a second control circuit; the driving method further includes: Under the control of the second control signal, the second control circuit controls the connection between the second pull-down node and the fifth voltage terminal so that the potential of the second pull-down node is an effective voltage. When the potential of the second pull-down node is an effective voltage, the pull-up node reset circuit controls the connection between the pull-up node and the second voltage terminal to reset the potential of the pull-up node.

18. A display device, characterized in that, Includes the driving circuit as described in any one of claims 1 to 16.

19. The display device as claimed in claim 18, characterized in that, The display device includes a driving module; The drive module includes multiple cascaded drive circuits; The first input voltage terminal of the last stage drive circuit included in the drive module is not connected to the corresponding first input voltage, and the last stage drive circuit is a pseudo drive circuit. The display device further includes a multi-row, multi-column pixel circuit disposed in the display area, wherein the last row of pixel circuits in the display device is a pseudo-pixel driving circuit. The last-stage driving circuit is used to provide corresponding driving signals for the last row of pixel circuits, which do not emit light.

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