FPGA-based space traveling wave tube amplifier power module and control method thereof

Abstract

The application discloses a space traveling wave tube amplifier power module based on FPGA and a control method thereof. Control logics of original sub-circuits are realized through FPGA software, the number of circuit components, the circuit area and weight are effectively reduced under the premise of realizing the same control circuit function, the production debugging difficulty and period are greatly reduced, the consistency of products in the production process is improved, meanwhile, the conversion efficiency and power density of the power module are improved by adopting the method, and the performance of the product is improved.

Description

Technical Field

[0001] This application relates to the technical field of space continuous wave traveling wave tube amplifiers, and in particular to an FPGA-based power supply module for a space traveling wave tube amplifier and its control method. Background Technology

[0002] A space continuous wave traveling wave tube amplifier typically consists of three parts: a traveling wave tube (TWT), a power supply (EPC), and a linearized channel amplifier (LCAMP), along with related accessories (HV cables, etc.). The EPC and TWT are integrated into a TWTA, and the LCAMP and TWTA are integrated into a continuous wave linearized traveling wave tube amplifier (LTWTA). Its block diagram is shown below. Figure 1 As shown.

[0003] The traveling wave tube (TWT) power supply is responsible for transforming the bus voltage into the voltage required for the TWT and LCAMP to operate. The TWT power supply (EPC) includes a low-voltage module, which is primarily responsible for setting the bus voltage and providing power input to the high-voltage transformer, while also enabling remote control, telemetry, and protection control functions for a single unit. Traditional TWT power supply low-voltage modules use digital logic gates and discrete components to construct the various sub-circuits of the control circuit. To achieve the above functions, these sub-circuits need to work together, requiring a large number of components, resulting in a large low-voltage module area and weight, increasing the workload of electrical assembly and debugging. Furthermore, the extensive use of digital logic gates and discrete components significantly impacts the efficiency, stability, and reliability of the low-voltage power supply. Summary of the Invention

[0004] This patent proposes an FPGA-based power module control method to replace the original discrete digital circuits. The control logic of each sub-circuit is implemented through FPGA software. Under the premise of achieving the same control circuit function, the number of circuit components, circuit area and weight are effectively reduced, which greatly reduces the difficulty and cycle of production and debugging, improves the consistency of products in the production process, and improves the conversion efficiency and power density of the power module, thus enhancing the performance of the product.

[0005] Firstly, an FPGA-based space traveling wave tube amplifier power supply module is provided, including a power conversion circuit and an FPGA;

[0006] The FPGA is used to receive the crystal oscillator clock signal as the FPGA's operating clock, and uses this to control the generation of the output clock signal CLOCK_FPGA to the power conversion circuit.

[0007] The FPGA is also used to receive dead time control signals and, according to the dead time control signals, change the dead time of the two carrier pulse control signals DRIVE_1_FPGA and DRIVE_2_FPGA output by the FPGA to the power conversion circuit.

[0008] In conjunction with the first aspect, in some implementations of the first aspect, the number of dead time control signals is two, namely dead time control signal DT_CON_A and dead time control signal DT_CON_B. Dead time control signal DT_CON_A and dead time control signal DT_CON_B jointly indicate four dead times. The value range of the four dead times is 200~2000ns, and the interval between adjacent dead times is 200~600ns.

[0009] In conjunction with the first aspect, in some implementations of the first aspect, the FPGA is further configured to receive an automatic restart threshold control signal to adjust the automatic restart threshold, wherein the FPGA is further configured to determine whether the monitored number of automatic restarts has reached the threshold based on the automatic restart threshold.

[0010] In conjunction with the first aspect, in some implementations of the first aspect, the FPGA is also used to receive a power-off command signal, a bus undervoltage signal, a bus overcurrent signal, and an overcurrent protection signal, to switch the operating state of the FPGA, thereby changing the state of the power conversion circuit.

[0011] The FPGA is also used to receive signals from the reset circuit to reset the power conversion circuit.

[0012] The FPGA is also used to receive filament preheating time control signals to adjust the filament preheating monitoring duration inside the FPGA.

[0013] Secondly, a control method for a space traveling wave tube amplifier power module based on an FPGA is provided, wherein the power module is the power module described in any of the implementations of the first aspect above, and the method includes:

[0014] The FPGA controls the power conversion circuit to operate in a soft-start state according to the dead-time control signal. In the first half cycle of the soft-start state, the first carrier pulse control signal DRIVE_1_FPGA outputs a high-level signal, and the second carrier pulse control signal DRIVE_2_FPGA outputs a low-level signal. In the second half cycle of the soft-start state, the first carrier pulse control signal DRIVE_1_FPGA outputs a low-level signal, and the second carrier pulse control signal DRIVE_2_FPGA outputs a high-level signal.

[0015] After the soft start is completed, the FPGA controls the power conversion circuit to operate in normal mode.

[0016] In conjunction with the second aspect, in some implementations of the second aspect, in two adjacent cycles of the soft-start state, the total pulse width of the high-level signal output by the first carrier pulse control signal DRIVE_1_FPGA in the previous cycle is less than the total pulse width of the high-level signal output by the first carrier pulse control signal DRIVE_1_FPGA in the subsequent cycle.

[0017] In conjunction with the second aspect, in some implementations of the second aspect, in the soft-start state, the number of high-level signals output by the first carrier pulse control signal DRIVE_1_FPGA is multiple. In the same cycle, the pulse width of each high-level signal output by the first carrier pulse control signal DRIVE_1_FPGA is the same. In the next cycle, the pulse width of each high-level signal output by the first carrier pulse control signal DRIVE_1_FPGA increases by the same amount.

[0018] In conjunction with the second aspect, in some implementations of the second aspect, the soft start ends when multiple high-level signals output by the first carrier pulse control signal DRIVE_1_FPGA overlap to form a single high-level signal.

[0019] In conjunction with the second aspect, in some implementations of the second aspect, the method further includes:

[0020] After the FPGA is powered on, it performs an "asynchronous reset, synchronous release" operation under the action of an external reset signal;

[0021] After the external reset is canceled, the FPGA-controlled power conversion circuit operates in the preheating state.

[0022] In conjunction with the second aspect, in some implementations of the second aspect, the method further includes:

[0023] The system monitors whether the bus overcurrent signal and the overcurrent protection signal are normal. When the bus overcurrent signal or the overcurrent protection signal changes from high to low, the automatic restart count counter increments by 1. When the automatic restart count counter is greater than or equal to the restart threshold, the power conversion circuit performs a protection shutdown operation. At this time, the first carrier pulse signal DRIVE_1_FPGA and the second DRIVE_2_FPGA signal output by the FPGA to the power conversion circuit are both set to low level, and CLOCK_FPGA maintains its original state. When the automatic restart count counter is less than the restart threshold, the FPGA controls the power conversion circuit to perform an automatic restart operation.

[0024] In conjunction with the second aspect, in some implementations of the second aspect, the FPGA controlling the power conversion circuit to perform an automatic restart operation includes:

[0025] The FPGA controls the internal timer to start counting for the first duration, with the automatic restart counter incrementing by 1 as D0. After D0 + the second duration, the power conversion circuit re-enters the soft-start state. If the automatic restart counter increments again within the first duration, the above process restarts, with this moment as D0, and after D0 + the second duration, it re-enters the soft-start state. If the automatic restart counter reaches the set threshold number of times within the first duration, the soft-start process is not repeated, and a protective shutdown operation is performed. If the automatic restart counter does not reach the set threshold number of times after the first duration ends, both the automatic restart counter and the internal timer are reset to zero.

[0026] Compared with the prior art, the solution provided in this application has at least the following beneficial technical effects:

[0027] This patented method enables reliable driving of a high-efficiency power supply for a traveling wave tube amplifier. The soft-start precise control timing provided by this patent, which divides the carrier signal into three segments and unfolds them simultaneously, ensures efficient synchronous / asynchronous operation of the switching transistors in the power conversion circuit. This reduces switching losses and noise, and improves power supply efficiency and power density. Actual measurements show that the power supply's rated power point output efficiency is increased to over 94%, representing an efficiency improvement of over 5%, and the power density is increased by over 10%, significantly enhancing product performance.

[0028] The method described in this patent can be adapted to multiple power conversion circuits. The control method provided by this patent simultaneously implements four dead-time drive controls, corresponding to four soft-start timing step parameters. By flexibly configuring the dead time using parameters based on the actual circuit debugging results, the power conversion circuit can be guaranteed to operate in its optimal state. The optimal operating point of different transformer types in the power conversion circuit can be matched without modifying the FPGA control program, improving the versatility and scalability of this patent.

[0029] The FPGA-based automatic restart control circuit eliminates the need for numerous digital and discrete components found in traditional designs, requiring only two digital I / O pins on the FPGA. Its control logic is implemented in software, significantly reducing the number of components and circuit area. A comprehensive comparison of the entire control circuit shows that using an FPGA effectively reduces the number of components by approximately 120, decreases circuit area by about 40%, and reduces module weight by 100g, while also offering higher reliability. Furthermore, since the internal logic is all software-defined, no secondary debugging is required, greatly shortening the production cycle and facilitating manufacturing. Overall, the FPGA-based control method demonstrates clear advantages over traditional products. Attached Figure Description

[0030] Figure 1This is a basic diagram of a continuous wave traveling wave tube amplifier.

[0031] Figure 2 This is a block diagram illustrating the composition and principle of a low-voltage module.

[0032] Figure 3 This is a circuit diagram of the FPGA hardware peripheral interface.

[0033] Figure 4 This is the output timing diagram for the preheating state of the power conversion circuit.

[0034] Figure 5 This is the timing logic diagram for the soft-start of the FPGA control switch.

[0035] Figure 6 Configure the interface circuit diagram for dead time.

[0036] Figure 7 This is the control timing diagram for a power conversion circuit with a dead time of 1.1µs.

[0037] Figure 8 This is a diagram showing the operating state of the power conversion circuit. Detailed Implementation

[0038] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0039] The components of the FPGA-based traveling wave tube power supply low-voltage module are as follows: Figure 2 As shown, the FPGA, as the core circuit of the low-voltage module, plays the role of the "brain" of the module and even the individual unit. Its main functions are: 1.) To implement the control timing output function of the power conversion circuit, controlling the internal power conversion circuit of the low-voltage module to operate under the same time base and predetermined timing, ensuring the alternating coordination of switching timing to realize the power conversion function; 2.) To implement automatic restart and protection control functions, when the unit experiences abnormalities such as overcurrent or overvoltage, the control circuit can quickly respond and execute corresponding protection actions to ensure that the unit is not damaged on the track; 3.) To implement remote control and telemetry functions, ensuring that the unit can be turned on and off and accurately execute corresponding actions on the track via commands. The FPGA and various functional circuits within the low-voltage module are directly connected, and the normal operation of each functional circuit depends on the normal and stable operation of the FPGA control program.

[0040] Figure 3The diagram shows the peripheral interface circuit of the FPGA hardware. The FPGA can receive power-off command signals, bus undervoltage / overvoltage signals, bus overcurrent signals, and overcurrent protection signals to switch the FPGA's operating state, thereby changing the state of the power conversion circuit. The FPGA can also receive signals from the reset circuit to reset the power conversion circuit. The FPGA can also receive filament preheating time control signals to adjust the FPGA's internal filament preheating monitoring duration. The FPGA can also receive the ZA715-40M clock signal as its operating clock and use it to control the generation of the output clock signal CLOCK_FPGA to the power conversion circuit. The FPGA can also receive two dead-time control signals, DT_CON_A and DT_CON_B, to change the dead time of the FPGA-controlled power conversion circuit to adapt to the transformer in the power conversion circuit. The FPGA can also receive an automatic restart threshold control signal to adjust whether the number of automatic restarts monitored by the FPGA has reached a threshold. Based on the above signals, the FPGA outputs DRIVE_1_FPGA, DRIVE_2_FPGA, and CLOCK_FPGA to the power conversion circuit through pre-configured control methods, controlling the operating state of the power conversion circuit.

[0041] The following combination Figure 8 This application provides a more detailed description of the FPGA-based traveling wave tube amplifier power module control method.

[0042] Step 1: After the FPGA is powered on, it performs an "asynchronous reset, synchronous release" operation under the action of an external reset signal.

[0043] When the reset signal is low, the FPGA-controlled power conversion circuit operates in a reset initialization state, setting the output control signal to low. This type of reset detection offers faster response and higher reliability compared to discrete circuits.

[0044] Step 2: After the external reset is canceled, the FPGA controls the power conversion circuit to operate in the preheating state.

[0045] Combination Figure 2 A filament can be installed on the busbar. The filament needs to be preheated by the current flowing through the busbar to ensure its normal operation. An internal FPGA filament preheating timer T1 tracks the preheating time. The timing of the filament preheating timer T1 can be set to two states via the input filament preheating time pin level. In one embodiment, a low level indicates a timing time of 10 seconds, and a high level indicates a timing time of 210 seconds. After the filament preheating timer T1 (210 seconds or 10 seconds) finishes timing, the FPGA controls the power conversion circuit to proceed to step 3.

[0046] During the preheating phase, subsequent soft-start phase, and normal operation phase, the FPGA can output a clock signal CLOCK_FPGA to the power conversion circuit. The output operating frequency and signal duty cycle are as follows: Figure 4 As shown: The CLOCK_FPGA output period is 8.3µs, and the high-level duration is 0.5µs. In other embodiments, the high-level duration can be 3.5‰ to 8.5‰ of the CLOCK_FPGA output period. The CLOCK_FPGA output period can be the period of the carrier pulse control signal when the FPGA is in normal operating condition / the number of carrier pulse control signals (e.g., ...). Figure 5 As shown, the period of the carrier pulse control signal is 16.6 μs, and the number is 2.

[0047] Step 3: The FPGA controls the power conversion circuit to operate in a soft-start state.

[0048] The main design objective of the soft-start state is to precisely control the startup time of each switch in the power conversion circuit through FPGA software, ensuring that the switches alternately conduct at a fixed frequency and dead time interval. This effectively reduces the switching losses of the switches. Simultaneously, the FPGA software controls the carrier signal to gradually expand its pulse width during the alternating conduction startup process of each switch. Figure 5 In the illustrated embodiment, a three-segment pulse width progressive expansion operating mode is used. This mode helps reduce the power supply's startup current surge and minimizes the impact of the startup stage on the power conversion circuit, especially when the soft-start time is relatively short. This requires precise nanosecond-level control of the startup timing of each switch in the circuit. For this application scenario, FPGA-based control methods have inherent advantages.

[0049] The soft-start control method provided in this patent can precisely control the switching transistor to alternately conduct at a fixed frequency and dead time interval with nanosecond-level accuracy. When the switching frequency of the transistor is fixed, the dead time affects the resonant efficiency of the load transformer in the power conversion circuit. The resonant parameters of the load transformer are... L S For the leakage inductance in the load transformer, C T This is a resonant capacitor. Due to the parasitic parameter L in the transformer circuit under different loads... S and C TDifferent dead times result in variations in dead time, thus affecting the transformer's conversion efficiency. To improve circuit conversion efficiency, this patent provides a control method that simultaneously implements four dead time drive controls (corresponding to states 00, 01, 10, and 11), corresponding to four soft-start timing step parameters. Through two dead time parameter configuration pins on the FPGA, an optimal soft-start control sequence can be selected to output to the load transformer based on the actual circuit debugging effect, ensuring the circuit operates in its best state. This method is compatible with various models and specifications of load transformers. The dead time range can be, for example, 200~2000ns. The interval between adjacent dead times can be, for example, 200~600ns.

[0050] In soft-start mode, the switching timing of the FPGA output power conversion circuit is as follows: Figure 4 As shown in Table 1, the relevant parameters are defined. The FPGA outputs two carrier pulse control signals, DRIVE_1_FPGA and DRIVE_2_FPGA, with a period of 16.6µs. The dead time between the two signals can be set to different values ​​by adjusting the input pins DT_CON_A and DT_CON_B.

[0051] When the dead time is 500ns, the initial high-level time is 100ns (4 clock cycles). During the soft-start process, the high-level time of the carrier pulse signals DRIVE_1_FPGA and DRIVE_2_FPGA gradually increases, with each step adding 2 basic clock cycles (50ns), for a total of 51 steps. Each step stays for 8 cycles (8... (16.6us), the pulse width is fully expanded in step 51, the high level is 7.8us at the end of the soft start, and the total time of the soft start process is 8. 16.6us 51 = 6.7728ms.

[0052] When the dead time is 800ns, the initial high-level time is 100ns (4 clock cycles). During the soft-start process, the high-level time of the carrier pulse signals DRIVE_1_FPGA and DRIVE_2_FPGA gradually increases, with each step adding two basic clock cycles (50ns), for a total of 49 steps. Each step stays for 8 cycles (8... (16.6us), the pulse width is fully expanded in step 49, the high level is 7.5us at the end of the soft start, and the total time of the soft start process is 8. 16.6us 49 = 6.5072ms.

[0053] When the dead time is 1100ns, the initial high-level time is 100ns (4 clock cycles). During the soft-start process, the high-level time of the carrier pulse signals DRIVE_1_FPGA and DRIVE_2_FPGA gradually increases, with each step adding 2 basic clock cycles (50ns), for a total of 47 steps. Each step stays for 8 cycles (8 cycles). (16.6us), the pulse width is fully expanded in step 47, the high level is 7.2us at the end of the soft start, and the total time of the soft start process is 8. 16.6us 47 = 6.2416ms.

[0054] When the dead time is 1400ns, the initial high-level time is 100ns (4 clock cycles). During the soft-start process, the high-level time of the carrier pulse signals DRIVE_1_FPGA and DRIVE_2_FPGA gradually increases, with each step adding 2 basic clock cycles (50ns), for a total of 45 steps. Each step stays for 8 cycles (8... (16.6us), the pulse width is fully expanded in step 45, the high level is 6.9us at the end of the soft start, and the total time of the soft start process is 8. 16.6us 45 = 5.9760ms.

[0055] Table 1. Parameter settings for different dead times in the power conversion circuit.

[0056]

[0057] The circuit diagram for implementing drive control with four dead times is as follows: Figure 6 As shown. DT_CON_A can be used to output a high or low level to the FPGA. DT_CON_B is used to output a high or low level to the FPGA. Among them, in Figure 6 In the illustrated embodiment, the high level comes from the +5V port, and the low level comes from the GND port.

[0058] A resistor R422 can be set between the low-level port and the high-level port. The port between the low-level port and the resistor R422 can be electrically connected to DT_CON_A. To make DT_CON_A output a high level (1), the resistor R422 and the low-level port can be disconnected, that is, the resistor R421 to be adjusted is not connected between DT_CON_A and the low-level port. To make DT_CON_A output a low level (0), the resistor R422 and the low-level port can be shorted, that is, the resistor R421 to be adjusted is connected between DT_CON_A and the low-level port. The resistance value of the resistor R421 to be adjusted is equivalent to a wire. In other words, the two-way connection is achieved by disconnecting and shorting the resistor R421 to be adjusted. Figure 6The circuit shown.

[0059] A resistor R424 can be set between the low-level port and the high-level port. The port between the low-level port and the resistor R424 can be electrically connected to DT_CON_B. To make DT_CON_B output a high level (1), the resistor R424 and the low-level port can be disconnected, that is, the resistor R423 to be adjusted is not connected between DT_CON_B and the low-level port. To make DT_CON_B output a low level (0), the resistor R424 and the low-level port can be shorted, that is, the resistor R423 to be adjusted is connected between DT_CON_B and the low-level port. The resistance value of the resistor R423 to be adjusted is equivalent to a wire. In other words, the two-way connection is achieved by disconnecting and shorting the resistor R423 to be adjusted. Figure 6 The circuit shown.

[0060] This method employs the technique of disconnecting or shorting the adjustable resistors during FPGA hardware interface design to achieve flexible configuration of the dead time. DT_CON_A and DT_CON_B are the parameterized configuration input pins for the FPGA dead time. Based on the actual circuit debugging results, by flexibly configuring the adjustable resistors R421 and R423 to disconnect or short-circuit, one optimal control timing sequence under the dead time can be selected to output to the load transformer, ensuring that the circuit operates in its best state.

[0061] Step 4: After the high-level time of the carrier pulse signals DRIVE_1_FPGA and DRIVE_2_FPGA is fully extended, the FPGA controls the power conversion circuit to work in normal operating condition.

[0062] In this operating state, the FPGA precisely controls the on-time and dead time of each switch, ensuring that all switches operate within a predetermined timing sequence and complete power conversion within a fixed pulse width, resulting in higher power supply efficiency. In this state, the phase relationship between the FPGA output carrier pulse signals DRIVE_1_FPGA and DRIVE_2_FPGA is as follows: Figure 7 As shown, the high-level time + dead time of the carrier pulse signal in one cycle equals one cycle time. 50%, and the rising edge of the carrier pulse signal must be aligned with the rising edge of the CLOCK_FPGA clock.

[0063] Step 5: When the FPGA controls the power conversion circuit to operate in soft-start or normal operation mode, it is necessary to monitor the bus overcurrent signal and the overcurrent protection signal in real time. When the bus overcurrent signal changes from high to low or the overcurrent protection signal changes from high to low, the automatic restart count counter T2 is incremented by 1. When the automatic restart count counter T2 is greater than or equal to the restart threshold, the power conversion circuit performs a protection shutdown operation. At this time, the carrier pulse signals DRIVE_1_FPGA and DRIVE_2_FPGA output by the FPGA to the power conversion circuit should be set to low level, and CLOCK_FPGA should maintain its original state. When the automatic restart count counter T2 is less than the restart threshold, the FPGA needs to control the power conversion circuit to perform an automatic restart operation.

[0064] The FPGA-controlled power conversion circuit performs an automatic restart operation as follows: Taking the increment of the automatic restart counter as D0, the FPGA controls the internal timer T3 to start timing for 210 seconds. After D0 + 250 ms, the power conversion circuit re-enters the soft-start state. If the automatic restart counter T2 increments again within the 210 seconds of timer T3, the above process restarts, taking this moment as D0, and re-enters the soft-start state after D0 + 250 ms. If the automatic restart counter T2 reaches the set threshold (e.g., 1, 2, 3, 4) counts within the 210 seconds of timer T3, the soft-start process is not repeated, and a protective shutdown operation is performed. At this time, the carrier pulse signals DRIVE_1_FPGA and DRIVE_2_FPGA are output at a low level, and CLOCK_FPGA remains in its original state. If, after the 210 seconds of timer T3, the automatic restart counter T2 has not reached the set threshold (1, 2, 3, 4) counts, both counters T2 and T3 are reset to zero. During the automatic restart process at time D0, the carrier pulse signals DRIVE_1_FPGA and DRIVE_2_FPGA are output at a low level, while CLOCK_FPGA maintains its original state.

[0065] After the FPGA is powered on and reset, the power-off command signal and the bus undervoltage / overvoltage signal need to be monitored in real time. If detected... Figure 2 The shutdown command signal transitions from high to low, or the bus undervoltage / overvoltage signal transitions from low to high, triggering a protective shutdown operation. Specifically, the carrier pulse signals DRIVE_1_FPGA and DRIVE_2_FPGA output by the FPGA to the power conversion circuit should be set to low, while CLOCK_FPGA remains in its original state. The shutdown command signal and the bus undervoltage / overvoltage signal have the highest priority; they will not respond if an automatic restart or other event occurs during the protective shutdown operation.

[0066] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope defined in the claims of the present invention.

Claims

1. A power supply module for a space traveling wave tube amplifier based on FPGA, characterized in that, Including power conversion circuits and FPGAs; The FPGA is used to receive the crystal oscillator clock signal as the FPGA's operating clock, and uses this to control the generation of the output clock signal CLOCK_FPGA to the power conversion circuit. The FPGA is also used to receive dead time control signals and, according to the dead time control signals, change the dead time of the two carrier pulse control signals DRIVE_1_FPGA and DRIVE_2_FPGA output by the FPGA to the power conversion circuit. A control method for a space traveling wave tube amplifier power module based on an FPGA includes: the FPGA controlling the power conversion circuit to operate in a soft-start state according to a dead-time control signal; during the first half-cycle of the soft-start state, the first carrier pulse control signal DRIVE_1_FPGA outputs a high-level signal, and the second carrier pulse control signal DRIVE_2_FPGA outputs a low-level signal; during the second half-cycle of the soft-start state, the first carrier pulse control signal DRIVE_1_FPGA outputs a low-level signal, and the second carrier pulse control signal DRIVE_2_FPGA outputs a high-level signal; after the soft-start ends, the FPGA controls the power conversion circuit to operate in a normal state. In two adjacent cycles of the soft-start state, the total pulse width of the high-level signal output by the first carrier pulse control signal DRIVE_1_FPGA in the previous cycle is smaller than the total pulse width of the high-level signal output by the first carrier pulse control signal DRIVE_1_FPGA in the next cycle. In the soft-start state, the number of high-level signals output by the first carrier pulse control signal DRIVE_1_FPGA is multiple. In the same cycle, the pulse width of each high-level signal output by the first carrier pulse control signal DRIVE_1_FPGA is the same. In the next cycle, the pulse width of each high-level signal output by the first carrier pulse control signal DRIVE_1_FPGA increases by the same amount. The soft start ends when multiple high-level signals output by the first carrier pulse control signal DRIVE_1_FPGA overlap to form a single high-level signal.

2. The power module according to claim 1, characterized in that, There are two dead time control signals: DT_CON_A and DT_CON_B. DT_CON_A and DT_CON_B together indicate four dead times, with the values ​​of the four dead times ranging from 200 to 2000 ns and the interval between adjacent dead times ranging from 200 to 600 ns.

3. The power module according to claim 1, characterized in that, The FPGA is also used to receive an automatic restart threshold control signal to adjust the automatic restart threshold, wherein the FPGA is also used to determine whether the monitored number of automatic restarts has reached the threshold based on the automatic restart threshold.

4. The power module according to claim 1, characterized in that, The FPGA is also used to receive power-off command signals, bus undervoltage signals, bus overcurrent signals, and overcurrent protection signals, switch the FPGA's operating state, and thus change the state of the power conversion circuit. The FPGA is also used to receive signals from the reset circuit to reset the power conversion circuit. The FPGA is also used to receive filament preheating time control signals to adjust the filament preheating monitoring duration inside the FPGA.

5. The power module according to claim 1, characterized in that, After the FPGA is powered on, it performs an "asynchronous reset, synchronous release" operation under the action of an external reset signal; after the external reset is removed, the FPGA controls the power conversion circuit to work in the preheating state.

6. The power module according to claim 1, characterized in that, The system monitors whether the bus overcurrent signal and the overcurrent protection signal are normal. When the bus overcurrent signal or the overcurrent protection signal changes from high to low, the automatic restart count counter increments by 1. When the automatic restart count counter is greater than or equal to the restart threshold, the power conversion circuit performs a protection shutdown operation. At this time, the first carrier pulse signal DRIVE_1_FPGA and the second DRIVE_2_FPGA signal output by the FPGA to the power conversion circuit are both set to low level, and CLOCK_FPGA maintains its original state. When the automatic restart count counter is less than the restart threshold, the FPGA controls the power conversion circuit to perform an automatic restart operation.

7. The power module according to claim 6, characterized in that, The FPGA-controlled power conversion circuit performs an automatic restart operation as follows: Taking the moment when the automatic restart count counter increments by 1 as D0, the FPGA controls the internal timer to start timing for a first duration. After D0 + a second duration, the power conversion circuit re-enters the soft-start state. If the automatic restart count counter increments again within the first duration, the above process restarts, taking that moment as D0, and re-enters the soft-start state after D0 + a second duration. If the automatic restart count counter reaches the set threshold number within the first duration, the soft-start process is not repeated, and a protective shutdown operation is performed. If the automatic restart count counter has not reached the set threshold number after the first duration ends, both the automatic restart count counter and the internal timer are reset to zero.

Images