Storage device, method, and electronic device

Abstract

The application relates to a storage device, a method and an electronic device, the storage device comprising a controller and a first memory, the first memory comprising a plurality of disks, the controller comprising a second memory for caching data, the controller being configured to: generate a virtual address corresponding to first address information of first data to be operated and a category of a target disk; generate an operation instruction according to the virtual address; send the operation instruction to the target disk to make the target disk generate an address reading instruction for the virtual address; and in the case that the address reading instruction sent by the target disk is received, interact with the target disk according to the first address information corresponding to the virtual address. The embodiment of the application can simplify address management inside the storage device through address virtualization, thereby improving processing efficiency.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more particularly to a storage device, method, and electronic device. Background Technology

[0002] A redundant array of independent disks (RAID) is a large-capacity disk group composed of multiple independent disks, which can provide better storage performance than a single hard drive. RAID arrays are typically managed through an array card (also known as a RAID card, disk array card, etc.).

[0003] Different disks in a disk array may support different data management protocols, and different data management protocols may support different address description methods. When disks in a disk array support multiple address description methods, there will be mixed and complex address management within the array card, which will affect the processing efficiency of the disk array, such as input / output (I / O) efficiency. Summary of the Invention

[0004] In view of this, a storage device, method and electronic device are proposed.

[0005] In a first aspect, embodiments of this application provide a storage device, the storage device including a controller and a first memory, the first memory including a plurality of disks, the controller including a second memory for caching data, the controller being configured to: generate a virtual address corresponding to the first address information based on first address information of first data to be operated and the type of the target disk, the first address information being used to indicate the physical address of the first data in the second memory, the target disk being at least one of the plurality of disks, the virtual address including an identifier of the first address information; generate an operation instruction based on the virtual address; send the operation instruction to the target disk to cause the target disk to generate an address read instruction for the virtual address; and upon receiving the address read instruction sent by the target disk, perform data interaction with the target disk based on the first address information corresponding to the virtual address.

[0006] The storage device in this embodiment includes a controller and a first memory. The controller can generate a virtual address corresponding to the first address information based on the first address information of the first data to be operated (which is part or all of the data in the second data) and the type of the target disk. Then, based on the virtual address, it generates and sends an operation instruction to the target disk in the first memory. When the target disk receives the operation instruction sent by the controller, it generates and sends an address read instruction for the virtual address to the controller. When the controller receives the address read instruction sent by the target disk, it performs data interaction with the target disk based on the first address information corresponding to the virtual address. This allows the address information of the data to be operated (i.e., the physical address of the data to be operated in the second memory) to be virtualized, obtaining the corresponding virtual address. The virtual address is used in the instruction (or command) interaction between the controller and the target disk, thereby virtualizing and normalizing the address information management inside the storage device, simplifying the address management inside the storage device, and improving the processing efficiency of the storage device.

[0007] According to the first aspect, in a first possible implementation of the storage device, the controller is connected to a host, and the controller is further configured to: upon receiving a data write instruction for second data sent by the host, cache the second data in the second memory according to the second address information of the second data in the data write instruction, wherein the data write instruction is used to instruct the controller to write the second data into the first memory; and determine the first address information of the first data to be operated on according to the third address information of the second data in the second memory, wherein the first data is part or all of the data in the second data.

[0008] In the embodiments of this application, when the controller of the storage device receives a data write instruction for the second data sent by the host, it caches the second data in the second memory according to the second address information of the second data in the data write instruction, and determines the first address information of the first data to be operated (which is part or all of the data in the second data) according to the third address information of the second data in the second memory. Thus, by caching the second data in the second memory of the controller during data writing, the spatial distribution of the second data in the second memory can not only be recombined to reduce the dispersion of the second data, but also the address information can be managed in a unified address description method within the controller, reducing the complexity of address management within the controller.

[0009] According to a first possible implementation of the first aspect, in a second possible implementation of the storage device, the controller is further configured to: upon receiving a data read instruction for third data sent by the host, allocate cache space for the third data in the second memory according to the length of the third data, wherein the data read instruction is used to instruct the controller to read the third data from the first memory, and the cache space is used to cache the third data in the controller; determine first address information of the first data to be operated on according to fourth address information of the cache space, wherein the first data is part or all of the data in the third data.

[0010] In the embodiments of this application, the controller of the storage device can, upon receiving a data read instruction for third data sent by the host, allocate cache space in the second memory for the third data to be read according to the length of the third data, and determine the first address information of the first data to be operated (which is part or all of the data in the third data) according to the fourth address information of the cache space. This enables the controller to pre-allocate cache space within the controller for the third data to be read, allowing the controller to uniformly manage the address information of the data read from the first memory and cached in the second memory, thereby reducing the complexity of address management within the controller.

[0011] According to the second possible implementation of the first aspect, in the third possible implementation of the storage device, the address description method of the second address information is any one of Physical Region Page (PRP), Distributed Aggregate Table (SGL), and Distributed Aggregate Element (SGE), the address description method of the first address information, the third address information, and the fourth address information is PRP, and the category of the target disk is any one of PRP category, SGL category, and SGE category.

[0012] In the embodiments of this application, the first, third, and fourth address information within the controller adopt a unified address description method (PRP), while the address description method of the second address information from the host can be any one of PRP, SGL, and SGE, and the target disk category can be any one of PRP, SGL, and SGE. In this way, the storage device controller can not only receive address information with different address description methods from the host and interact with target disks of different categories, but also manage its internal address information using a unified address description method (PRP). This allows the storage device controller to achieve unified management of internal address information without affecting external interactions.

[0013] According to the first possible implementation of the first aspect, in the fourth possible implementation of the storage device, determining the first address information of the first data based on the third address information of the second data in the second memory includes: when the first data is a part of the second data, determining the first address information of the first data based on the third address information, the length of the first data, and the starting position offset, wherein the starting position offset is used to indicate the offset of the starting position of the first data relative to the starting position of the second data.

[0014] In the embodiments of this application, when the first data to be operated on is a portion of the second data, it is necessary to extract the first data to be processed from the second data. The first address information of the first data can be determined based on the third address information of the second data in the second memory, the length of the first data, and the starting position offset. In this way, the first address information of the first data can be quickly and accurately determined when the first data is a portion of the second data, so that the second data can be written in blocks or written to disk.

[0015] According to the first possible implementation of the first aspect, in the fifth possible implementation of the storage device, determining the first address information of the first data based on the third address information of the second data in the second memory includes: when the first data is all the data in the second data, determining the third address information of the second data as the first address information of the first data.

[0016] In the embodiments of this application, when the first data to be operated is all the data in the second data, that is, when the second data is written to or removed from the disk as a whole, the third address information of the second data in the second memory can be directly determined as the first address information of the first data, which is simple, fast and can improve processing efficiency.

[0017] According to any one of the first to fifth possible implementations of the first aspect, in a sixth possible implementation of the storage device, the controller is further configured to: determine that the first data is all the data in the second data when the length of the first data is the same as the length of the second data and the starting position offset of the first data is equal to 0.

[0018] In the embodiments of this application, the length and starting position offset of the data are used to determine whether the first data is all or part of the second data. When the length of the first data is the same as the length of the second data and the starting position offset of the first data is equal to 0, the first data is determined to be all the data in the second data. This method is simple, fast and accurate, thereby improving processing efficiency.

[0019] According to any one of the first to sixth possible implementations of the first aspect, in a seventh possible implementation of the storage device, the controller is further configured to: determine that the first data is a portion of the second data when the length of the first data is different from the length of the second data or the offset of the starting position of the first data is not equal to 0.

[0020] In the embodiments of this application, the length and starting position offset of the data are used to determine whether the first data is all or part of the second data. If the length of the first data is different from the length of the second data, or if the starting position offset of the first data is not equal to 0, the first data is determined to be part of the second data. This method is simple, fast and accurate, thereby improving processing efficiency.

[0021] According to the first aspect or any one of the first to seventh possible implementations of the first aspect, in the eighth possible implementation of the storage device, the step of interacting with the target disk based on the first address information corresponding to the virtual address includes: if the address description method of the first address information does not match the category of the target disk, converting the first address information according to the category of the target disk to obtain target address information; and interacting with the target disk based on the target address information.

[0022] In the embodiments of this application, when the address description method of the first address information corresponding to the virtual address does not match the category of the target disk, the controller converts the first address information according to the category of the target disk to obtain the target address information, and performs data interaction with the target disk according to the target address information, so that the controller and the target disk can perform data interaction when the target address information matches the category of the target disk.

[0023] According to any one of the first aspect or the first to seventh possible implementations of the first aspect, in the ninth possible implementation of the storage device, the step of interacting with the target disk based on the first address information corresponding to the virtual address includes: when the address description method of the first address information matches the category of the target disk, interacting with the target disk using the first address information as target address information.

[0024] In the embodiments of this application, when the address description method of the first address information corresponding to the virtual address matches the category of the target disk, the first address information is directly used as the target address information to interact with the target disk, without the need for address conversion, thereby improving processing efficiency.

[0025] Secondly, embodiments of this application provide a storage method applied to a controller in a storage device, the storage device further including a first memory comprising a plurality of disks, and the controller including a second memory for caching data. The method includes: generating a virtual address corresponding to the first address information based on first address information of first data to be operated and the type of the target disk, the first address information indicating the physical address of the first data in the second memory, the target disk being at least one of the plurality of disks, and the virtual address including an identifier of the first address information; generating an operation instruction based on the virtual address; sending the operation instruction to the target disk to cause the target disk to generate an address read instruction for the virtual address; and upon receiving the address read instruction sent by the target disk, performing data interaction with the target disk based on the first address information corresponding to the virtual address.

[0026] The embodiments of this application can generate a virtual address corresponding to the first address information based on the first address information of the first data to be operated (which is part or all of the data in the second data) and the type of the target disk. Then, based on the virtual address, an operation instruction is generated and sent to the target disk in the first memory. When the target disk receives the operation instruction sent by the controller, it generates and sends an address read instruction for the virtual address to the controller. When the controller receives the address read instruction sent by the target disk, it performs data interaction with the target disk based on the first address information corresponding to the virtual address. This allows the address information of the data to be operated (i.e., the physical address of the data to be operated in the second memory) to be virtualized, obtaining the corresponding virtual address. The virtual address is used in the instruction (or command) interaction between the controller and the target disk, thereby virtualizing and normalizing the address information management inside the storage device, simplifying the address management inside the storage device, and improving the processing efficiency of the storage device.

[0027] According to the second aspect, in a first possible implementation of the storage method, the controller is connected to a host, and the method further includes: upon receiving a data write instruction for second data sent by the host, caching the second data in the second memory according to the second address information of the second data in the data write instruction, wherein the data write instruction is used to instruct the controller to write the second data into the first memory; determining the first address information of the first data to be operated on according to the third address information of the second data in the second memory, wherein the first data is part or all of the data in the second data.

[0028] In the embodiments of this application, when a data write instruction for the second data is received from the host, the second data can be cached in the second memory according to the second address information of the second data in the data write instruction, and the first address information of the first data to be operated (which may be part or all of the data in the second data) can be determined according to the third address information of the second data in the second memory. Thus, by caching the second data in the second memory of the controller during data writing, the spatial distribution of the second data in the second memory can be recombined to reduce the dispersion of the second data, and the address information can be managed in a unified address description method within the controller, thereby reducing the complexity of address management within the controller.

[0029] According to the first possible implementation of the second aspect, in the second possible implementation of the storage method, the method further includes: upon receiving a data read instruction for third data sent by the host, allocating cache space for the third data in the second memory according to the length of the third data, the data read instruction being used to instruct the controller to read the third data from the first memory, the cache space being used to cache the third data in the controller; determining first address information of the first data to be operated on according to fourth address information of the cache space, wherein the first data is part or all of the data in the third data.

[0030] In the embodiments of this application, when a data read instruction for third data is received from the host, a cache space can be allocated in the second memory for the third data to be read according to the length of the third data, and the first address information of the first data to be operated (which is part or all of the data in the third data) can be determined according to the fourth address information of the cache space. This allows the cache space to be allocated in the controller in advance for the third data to be read, enabling the controller to uniformly manage the address information of the data read from the first memory and cached in the second memory, thereby reducing the complexity of address management within the controller.

[0031] According to the second possible implementation of the second aspect, in the third possible implementation of the storage method, the address description method of the second address information is any one of Physical Region Page (PRP), Distributed Aggregate Table (SGL), and Distributed Aggregate Element (SGE), the address description method of the first address information, the third address information, and the fourth address information is PRP, and the category of the target disk is any one of PRP category, SGL category, and SGE category.

[0032] In the embodiments of this application, the first, third, and fourth address information within the controller adopt a unified address description method (PRP), while the address description method of the second address information from the host can be any one of PRP, SGL, and SGE, and the target disk category can be any one of PRP, SGL, and SGE. In this way, the storage device controller can not only receive address information with different address description methods from the host and interact with target disks of different categories, but also manage its internal address information using a unified address description method (PRP). This allows the storage device controller to achieve unified management of internal address information without affecting external interactions.

[0033] According to the first possible implementation of the second aspect, in the fourth possible implementation of the storage method, determining the first address information of the first data based on the third address information of the second data in the second memory includes: when the first data is a part of the second data, determining the first address information of the first data based on the third address information, the length of the first data, and the starting position offset, wherein the starting position offset is used to indicate the offset of the starting position of the first data relative to the starting position of the second data.

[0034] In the embodiments of this application, when the first data to be operated on is a portion of the second data, it is necessary to extract the first data to be processed from the second data. The first address information of the first data can be determined based on the third address information of the second data in the second memory, the length of the first data, and the starting position offset. In this way, the first address information of the first data can be quickly and accurately determined when the first data is a portion of the second data, so that the second data can be written in blocks or written to disk.

[0035] According to the first possible implementation of the second aspect, in the fifth possible implementation of the storage method, determining the first address information of the first data based on the third address information of the second data in the second memory includes: when the first data is all the data in the second data, determining the third address information of the second data as the first address information of the first data.

[0036] In the embodiments of this application, when the first data to be operated is all the data in the second data, that is, when the second data is written to or removed from the disk as a whole, the third address information of the second data in the second memory can be directly determined as the first address information of the first data, which is simple, fast and can improve processing efficiency.

[0037] According to any one of the first to fifth possible implementations of the second aspect, in the sixth possible implementation of the storage method, the method further includes: determining that the first data is all the data in the second data when the length of the first data is the same as the length of the second data and the starting position offset of the first data is equal to 0.

[0038] In the embodiments of this application, the length and starting position offset of the data are used to determine whether the first data is all or part of the second data. When the length of the first data is the same as the length of the second data and the starting position offset of the first data is equal to 0, the first data is determined to be all the data in the second data. This method is simple, fast and accurate, thereby improving processing efficiency.

[0039] According to any one of the first to sixth possible implementations of the second aspect, in the seventh possible implementation of the storage method, the method further includes: determining that the first data is a portion of the second data when the length of the first data is different from the length of the second data, or when the offset of the starting position of the first data is not equal to 0.

[0040] In the embodiments of this application, the length and starting position offset of the data are used to determine whether the first data is all or part of the second data. If the length of the first data is different from the length of the second data, or if the starting position offset of the first data is not equal to 0, the first data is determined to be part of the second data. This method is simple, fast and accurate, thereby improving processing efficiency.

[0041] According to the second aspect or any one of the first to seventh possible implementations of the second aspect, in the eighth possible implementation of the storage method, the step of interacting with the target disk based on the first address information corresponding to the virtual address includes: if the address description method of the first address information does not match the category of the target disk, converting the first address information according to the category of the target disk to obtain target address information; and interacting with the target disk based on the target address information.

[0042] In the embodiments of this application, when the address description method of the first address information corresponding to the virtual address does not match the category of the target disk, the controller converts the first address information according to the category of the target disk to obtain the target address information, and performs data interaction with the target disk according to the target address information, so that the controller and the target disk can perform data interaction when the target address information matches the category of the target disk.

[0043] According to the second aspect or any one of the first to seventh possible implementations of the second aspect, in the ninth possible implementation of the storage method, the step of interacting with the target disk based on the first address information corresponding to the virtual address includes: when the address description method of the first address information matches the category of the target disk, interacting with the target disk using the first address information as target address information.

[0044] In the embodiments of this application, when the address description method of the first address information corresponding to the virtual address matches the category of the target disk, the first address information is directly used as the target address information to interact with the target disk, without the need for address conversion, thereby improving processing efficiency.

[0045] Thirdly, embodiments of this application provide an electronic device including a processor and a storage device connected to the processor, wherein the storage device is one or more of the storage devices described in the first aspect or various possible implementations of the first aspect.

[0046] In the embodiments of this application, the controller of the storage device can generate a virtual address corresponding to the first address information based on the first address information of the first data to be operated (which may be part or all of the data in the second data) and the type of the target disk. Then, based on the virtual address, it generates and sends an operation instruction to the target disk in the first memory. Upon receiving the operation instruction from the controller, the target disk generates and sends an address read instruction for the virtual address to the controller. Upon receiving the address read instruction from the target disk, the controller interacts with the target disk based on the first address information corresponding to the virtual address. This virtualization of the address information of the data to be operated (i.e., the physical address of the data to be operated in the second memory) to obtain the corresponding virtual address, and its use in the instruction (or command) interaction between the controller and the target disk, virtualizes and normalizes the address information management within the storage device, thereby simplifying address management within the storage device and improving its processing efficiency.

[0047] These and other aspects of this application will become more apparent in the description of the following embodiments(s). Attached Figure Description

[0048] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this application together with the specification and serve to explain the principles of this application.

[0049] Figure 1A schematic diagram illustrating an application scenario of a storage device according to an embodiment of this application is shown.

[0050] Figure 2 A block diagram of a storage device according to an embodiment of this application is shown.

[0051] Figure 3 A schematic diagram illustrating the data writing process of a storage device according to an embodiment of this application is shown.

[0052] Figure 4 This diagram illustrates a controller caching data according to an embodiment of the present application.

[0053] Figure 5 This diagram illustrates a controller caching data according to an embodiment of the present application.

[0054] Figure 6 A schematic diagram of a virtual address space according to an embodiment of this application is shown.

[0055] Figure 7 A schematic diagram illustrating a virtual address according to an embodiment of this application is shown.

[0056] Figure 8 A schematic diagram illustrating a data reading process of a storage device according to an embodiment of this application is shown.

[0057] Figure 9 A flowchart illustrating a storage method according to an embodiment of this application is shown. Detailed Implementation

[0058] Various exemplary embodiments, features, and aspects of this application will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0059] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0060] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed embodiments. Those skilled in the art should understand that this application can be implemented without certain specific details. In some instances, methods, means, components, and circuits well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.

[0061] In related technologies, the interaction of service data between the host and the disk array is typically carried out through a RAID card (i.e., array card). The process by which the RAID card interacts with the host's service data and the individual disks (also called platters) in the disk array can be seen as the back-end of the RAID card.

[0062] Data management at the back end of a RAID card is typically related to the data management protocols supported by the individual disks in the disk array. Data management protocols instruct the data interaction process between the RAID card and the disks, address description methods, etc. Common data management protocols include Non-volatile Memory Express (NVMe) and Serial Attached Small Computer System Interface (SAS). NVMe supports address description methods such as Physical Region Page (PRP) and Scatter / Gather List (SGL); SAS supports address description methods such as Scatter / Gather Element (SGE).

[0063] When PRP is used as the address descriptor, the address information used by the RAID card during interaction with the disk is represented by PRP descriptors. Each PRP descriptor corresponds to a fixed-size (e.g., 4KB) physical page. The PRP descriptor can be used to indicate the starting address of the physical page, the offset within the page, etc., and its size is usually 8 bytes.

[0064] When the address description method is SGL, the address information used by the RAID card during interaction with the disk is represented by SGL. An SGL includes at least one SGL segment, and each SGL segment includes at least one SGL descriptor. The SGL descriptor can be used to indicate the starting address, size, etc., of a contiguous physical space, and its size is typically 16 bytes. The SGL address description method supports linked lists (i.e., multi-level linked lists).

[0065] When the address description mode is SGE, the address information used by the RAID card during interaction with the disk is represented by SGE descriptors. An SGE descriptor can indicate the starting address, size, etc., of a contiguous physical space; its size is typically 24 bytes. Multiple SGE descriptors can be linked together using pointers to form a linked list. The SGE address description mode also supports chained lists (i.e., multi-level linked lists).

[0066] When disks in a disk array support multiple address description methods, the RAID card itself also employs various complex address management methods. For example, suppose the disk array includes five disks: one supports PRP, three support SGL, and the remaining disk supports SGE. Correspondingly, the RAID card uses three complex address management methods corresponding to PRP, SGL, and SGE. This complex address management within the RAID card affects its processing efficiency, and consequently, the overall processing efficiency of the disk array, such as I / O efficiency.

[0067] To address the aforementioned technical problems, this application provides a storage device. The storage device of this application includes a controller and a first memory. The first memory includes multiple disks, and the controller includes a second memory for caching data. The controller of the storage device of this application can cache data to be operated on through the second memory, and can also virtualize the address information of the data to be operated on (i.e., the physical address of the data to be operated on in the second memory) to obtain a corresponding virtual address. This virtual address is used during instruction (or command) interaction between the controller and the first memory, thereby virtualizing and normalizing address management within the storage device, thus simplifying address management within the storage device and improving the processing efficiency of the storage device.

[0068] Figure 1 A schematic diagram illustrating an application scenario of a storage device according to an embodiment of this application is shown. For example... Figure 1 As shown, the storage device 200 includes a controller 210 and a first memory 220, with the controller 210 connected to the host 100. The host 100 can perform data operations on the storage device 200, such as data writing and data reading.

[0069] In some embodiments, the host 100 can be any type of electronic device, such as a server, desktop computer, mainframe computer, and any other type of computing device. In this embodiment, the storage device 200 is located outside the host 100.

[0070] In some embodiments, the host 100 may be a processor in an electronic device. The processor may include one or more processing units, such as an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural network processing unit (NPU). Different processing units may be independent devices or integrated into one or more processors. In this embodiment, the storage device 200 may be located inside or outside the electronic device to which the processor belongs; this application does not impose any limitations on this.

[0071] In some embodiments, the storage device 200 may be a disk array, the controller 210 in the storage device 200 may be a RAID card in the disk array, and the first memory 220 may be a storage medium in the disk array, including multiple disks or platters.

[0072] The controller 210 can be implemented by a central processing unit (CPU), an integrated circuit, or any other module capable of data processing, and this application does not limit this.

[0073] When the host 100 interacts with the storage device 200, the host 100 can send a data write command or a data read command to the controller 210 in the storage device 200. After receiving the data write command or data read command sent by the host 100, the controller 210 can perform relevant processing. For example, when receiving a data write command sent by the host 100, the controller 210 can write the data indicated by the data write command into the first memory 210 of the storage device 200; when receiving a data read command sent by the host 100, the controller 210 can read the data indicated by the data read command from the first memory 220 of the storage device 200 and send the read data to the host 100.

[0074] Figure 2 A block diagram of a storage device according to an embodiment of this application is shown. Figure 2As shown, the storage device 200 includes a controller 210 and a first memory 220 connected to the controller 210. The controller 210 includes a second memory 211, which can be regarded as the cache / memory of the controller 210 for caching data; the first memory 220 includes multiple disks 221.

[0075] In one possible implementation, the category of each disk in the first memory 220 can be determined based on the address description method used during the interaction between disk 221 and controller 210. For example, if the address description method used during the interaction between disk 221 and controller 210 is PRP, the category of disk 221 can be determined as PRP category; if the address description method used during the interaction between disk 221 and controller 210 is SGL, the category of disk 221 can be determined as SGL category; and if the address description method used during the interaction between disk 221 and controller 210 is SGE, the category of disk 221 can be determined as SGE category.

[0076] The following examples illustrate the processing procedure of the controller of the storage device using the data writing and reading processes of the storage device as examples.

[0077] Figure 3 This diagram illustrates a data writing process of a storage device according to an embodiment of the present application. Data to be written from the host to the storage device can be considered as second data. When writing the second data, the host can send a data write command to the storage device, instructing the controller of the storage device to write the second data to the first memory.

[0078] like Figure 3 As shown, when the controller of the storage device receives a data write command for the second data sent by the host, it can perform the following processing:

[0079] Step S310: Upon receiving a data write instruction for the second data sent by the host, the second data is cached in the second memory according to the second address information of the second data in the data write instruction.

[0080] The data write instruction sent by the host to the controller may include second address information instructing the controller to write second data to the first memory. This second address information may include at least one of the following: the start address, base address, address offset, data length, and address description method of the second data. The address description method of the second address information can be PRP or SGL, meaning that the address description method used during the interaction between the host and the controller can be PRP or SGL. In some embodiments, the second address information may also be represented by SGE or other address description methods; this application does not impose any limitations on this.

[0081] Upon receiving a data write instruction for the second data from the host, the controller can cache the second data in the second memory according to the second address information of the second data in the data write instruction. In other words, upon receiving a data write instruction for the second data from the host, the controller can first cache the second data, that is, store the second data in the second memory (i.e., the controller's local cache).

[0082] In one possible implementation, the address description mode supported internally by the controller is PRP. After the second data is cached in the second memory, its address description mode is converted to PRP. For example, in a data write instruction sent by the host to the controller, the address description mode of the second address information of the second data is SGL. Since the address description mode supported internally by the controller is PRP, after the controller caches the second data in the second memory, the address description mode of the second data is converted to PRP. It should be noted that the address description mode supported internally by the controller can also be SGL or other address description modes, and this application does not limit this.

[0083] Figure 4 This diagram illustrates a controller caching data according to an embodiment of the present application. Figure 4 As shown, cache 410 is located in the host and includes three cache regions: 411, 412, and 413, each with a size of 4KB. Cache 420 is located in the controller's second memory and includes three cache regions: 421, 422, and 423, each with a size of 4KB. The controller internally supports PRP as the address description method.

[0084] The data Data1 stored in cache 410 has a length of 7KB, including data block A1 (length 2KB), data block A2 (length 4KB) and data block A3 (length 1KB).

[0085] When the host needs to write data Data1 to the storage device, it can send a data write command to the controller in the storage device. The second address information of data Data1 in the data write command is represented by a PRP descriptor, as shown in Table 1 below:

[0086] Table 1

[0087] PRP1 Offset! = 0 PRP2 Offset=0 PRP3 Offset=0

[0088] As shown in Table 1, the second address information of data Data1 in the data write instruction is represented by PRP descriptors PRP1, PRP2 and PRP3, and Offset represents the address offset.

[0089] When the controller receives a data write instruction for data Data1 sent by the host, it can read data Data1 from the host's cache 410 according to the second address information of data Data1 shown in Table 1, and store the read data Data1 in the controller's cache 420.

[0090] like Figure 4 As shown, the data Data1 in cache 420 consists of two data blocks: data block A1′ and data block A2′, which are stored in cache areas 421 and 422 respectively. The address information of data Data1 in cache 420 can be represented by a PRP descriptor, as shown in Table 2 below:

[0091] Table 2

[0092] PRP4 Offset = LBA Offset1 PRP5 Offset=0

[0093] As shown in Table 2, the address information of data Data1 in cache 420 is represented by PRP descriptors PRP4 and PRP5. Among them, Offset represents the address offset, and LBA Offset1 represents the logical block address (LBA) offset of data block A1′ in cache area 421.

[0094] Figure 5 This diagram illustrates a controller caching data according to an embodiment of the present application. Figure 5 As shown, cache 510 is located in the host and includes three cache regions: 511, 512, and 513, each with a size of 4KB. Cache 520 is located in the controller's second memory and includes three cache regions: 521, 522, and 523, each with a size of 4KB. The controller internally supports PRP as the address description method.

[0095] The data Data2 stored in cache 510 is 7KB in length, including data block B1 (3KB in length), data block B2 (2.5KB in length) and data block B3 (1.5KB in length).

[0096] When the host needs to write data Data2 to the storage device, it can send a data write command to the controller in the storage device. The second address information of data Data2 in the data write command is represented by SGL, as shown in Table 3 below:

[0097] Table 3

[0098]

[0099] As shown in Table 3, the second address information of the data Data2 in the data write instruction is represented by SGL1, SGL2 and SGL3, where Offset represents the address offset and Length represents the data block length.

[0100] When the controller receives a data write instruction for data Data2 sent by the host, it can read data Data2 from the host's cache 510 according to the second address information of data Data2 shown in Table 3, and store the read data Data2 in the controller's cache 520.

[0101] like Figure 5 As shown, the data Data2 in cache 520 consists of two data blocks: data block B1′ and data block B2′, which are stored in cache areas 521 and 522 respectively. The address information of data Data2 in cache 520 can be represented by a PRP descriptor, as shown in Table 4 below:

[0102] Table 4

[0103] PRP6 Offset = LBA Offset2 PRP7 Offset=0

[0104] As shown in Table 4, the address information of data Data2 in cache 520 is represented by PRP descriptors PRP6 and PRP7. Among them, Offset represents the address offset, and LBA Offset2 represents the logical block address (LBA) offset of data block B1′ in cache area 521.

[0105] It should be noted that the above is based on only one perspective. Figure 4 and Figure 5 As an example, the caching process of the second data (Data1, Data2) in the controller is illustrated. The address description methods, size, storage location, and address description methods supported by the controller are all examples. In practical applications, those skilled in the art can configure the address description methods, size, storage location, and address description methods supported by the controller according to actual conditions; this application does not impose any limitations on this.

[0106] Step S320: Determine the first address information of the first data to be operated based on the third address information of the second data in the second memory.

[0107] In this context, the first data can be a portion or all of the second data. A scenario where the first data is all of the second data can be: the controller treats the second data as a whole and writes it, meaning the controller can complete the write operation (also known as a disk partitioning operation) to the second memory. A scenario where the first data is a portion of the second data can be: the controller splits the second data into multiple data blocks and writes each block separately, meaning the controller completes the write operation to the second memory through multiple write operations.

[0108] During data writing, the controller can determine the first data to be operated on based on preset data operation rules of the storage device (such as data block rules). The controller can preset a data block flag to indicate whether the second data is block-based, and then determine whether the first data is part or all of the second data based on the data block flag. The controller can also determine whether the first data is part or all of the second data in real time by judging the length of the data, the starting position offset, etc. during the data writing process.

[0109] In one possible implementation, the controller can determine whether the first data is all or part of the second data based on the length of the data. For example, it can determine whether the length of the first data is the same as the length of the second data. If the lengths of the first data and the second data are the same, the first data can be considered to be all the data in the second data; if the length of the first data is less than the length of the second data, the first data can be considered to be part of the second data.

[0110] In one possible implementation, the controller can also determine whether the first data is all or part of the second data based on the length of the data and the starting position offset of the data. Here, the starting position offset indicates the offset of the starting position of the first data relative to the starting position of the second data.

[0111] For example, we can determine if the length of the first data is the same as the length of the second data. If they are the same, we can determine if the starting position offset of the first data is equal to 0. If the starting position offset of the first data is equal to 0, we consider the first data to be all the data in the second data. Alternatively, we can determine if the starting position offset of the first data is equal to 0. If the starting position offset of the first data is equal to 0, we can determine if the length of the first data is the same as the length of the second data. If they are the same, we consider the first data to be all the data in the second data.

[0112] In other words, if the length of the first data is the same as the length of the second data and the starting position offset of the first data is equal to 0, then the first data is determined to be all the data in the second data. If the length of the first data is different from the length of the second data, or if the starting position offset of the first data is not equal to 0, then the first data can be considered to be part of the second data.

[0113] By determining whether the first data is all or part of the second data by analyzing the length and starting position offset of the data, this method is simple, fast, and highly accurate, thus improving processing efficiency.

[0114] After determining the first data to be operated on, the controller can determine the first address information of the first data based on the third address information of the second data in the second memory. The third address information can be used to indicate the physical address of the second data in the second memory. The first address information can be used to indicate the physical address of the first data to be operated on in the second memory.

[0115] When the first data to be operated is all the data in the second data, that is, when the second data is written to or removed from the disk as a whole, the third address information of the second data in the second memory can be directly determined as the first address information of the first data. This is simple, fast and can improve processing efficiency.

[0116] When the first data to be processed is a portion of the second data, it is necessary to extract the first data from the second data. The first address information of the first data can be determined based on the third address information of the second data in the second memory, the length of the first data, and its starting offset. In this way, even when the first data is a portion of the second data, the first address information of the first data can be quickly and accurately determined, facilitating the block writing or disk removal of the second data.

[0117] In one possible implementation, the first address information can be similar to the third address information, representing the physical address of the first data. When the first data to be operated on is a portion of the second data, the first address information can also be represented by a conversion table, data information table (DIT), etc., showing the conversion relationship between the physical address of the first data and the third address information. The controller can obtain the physical address of the first data by real-time parsing of the conversion table or data information table.

[0118] In one possible implementation, the address description method of the third address information is the address description method supported internally by the controller, and the address description method of the first address information is the same as that of the third address information. For example, assuming that the address description method supported internally by the controller is PRP, then the address description methods of both the third address information and the first address information are PRP.

[0119] When the controller of the storage device receives a data write instruction for the second data sent by the host, it caches the second data in the second memory according to the second address information of the second data in the data write instruction, and determines the first address information of the first data to be operated (which may be part or all of the data in the second data) according to the third address information of the second data in the second memory. Thus, by caching the second data in the second memory of the controller during data writing, it is possible not only to recombine the spatial distribution of the second data in the second memory and reduce the dispersion of the second data, but also to manage the address information in the controller with a unified address description method, thereby reducing the complexity of address management within the controller.

[0120] In one possible implementation, the controller can preset an address storage space for storing address information, which is a real physical storage space. The controller can store the third address information of the second data in the second memory into the address storage space. After determining the first address information of the first data to be operated, the controller can also store the first address information of the first data in the address storage space. The size of the storage area occupied by each address information in the address storage space can be a preset fixed size (e.g., 64B, 128B, etc.), or it can be set according to the actual situation, and this application does not limit it. The address storage space can be located in the second memory of the controller or in other locations of the controller. Those skilled in the art can set the specific location of the address storage space according to the actual situation, and this application does not limit it.

[0121] In one possible implementation, the first storage space can be managed in a manner similar to that of a memory management unit (MMU). For example, an address lookup table (ALT) can be created in the address storage space for the first address information of the first data, and the first address information of the first data can be stored in this address lookup table ALT. The size of the address lookup table ALT can be a preset size, such as 64B, 128B, etc. Optionally, if a single-level ALT is insufficient, multiple levels of ALT can be set according to the length of the first data, for example, a three-level ALT including a first-level ALT, a second-level ALT, and a third-level ALT.

[0122] It should be noted that those skilled in the art can determine the number of levels in a multi-level ALT based on actual conditions such as addressing efficiency and cache consumption, and this application does not impose any restrictions on this.

[0123] In one possible implementation, the controller can assign an identifier (key) as a unique identifier to each piece of address information stored in the address storage space. That is, in the address storage space, the storage area storing the first address information (i.e., the address lookup table ALT) is associated with the first address information through the identifier key. For example, the starting address of the address lookup table ALT storing the first address information can be associated with the key of the first address information.

[0124] When the address lookup table ALT has multiple levels, the starting address of the first-level ALT can be used as the index entry and associated with the key of the first address information. By calculating the offset of each level ALT, the corresponding table entry can be accessed directly without needing to chain according to the data management protocol (such as NVMe), thereby improving addressing efficiency.

[0125] By pre-setting an address storage space for storing address information in the controller's cache (i.e., the second memory), and allocating a corresponding storage area for each address information in the address storage space according to the preset size, and then storing each address information in the corresponding storage area in the address storage space, not only can addressing efficiency be improved, but cache resource consumption can also be reduced and cache utilization can be improved.

[0126] Step S330: Generate a virtual address corresponding to the first address information based on the first address information of the first data to be operated and the type of the target disk.

[0127] The target disk is at least one of the multiple disks of the first storage, which can be used to store the first data to be written (i.e., as the destination when writing data) or the first data to be read (i.e., as the data source when reading data).

[0128] During data writing, the controller can select at least one disk from multiple disks in the first memory as the target disk based on the address description method, available storage space, etc. For example, when the controller caches the second data, the target disk can be determined according to the address description method supported by the controller: assuming the controller supports PRP address description method, a disk of type PRP, SGL, or SGE can be selected as the target disk; assuming the controller supports SGL address description method, a disk of type SGL or SGE can be selected as the target disk. Furthermore, other information such as the available storage space of the disk can also be considered when determining the target disk. Those skilled in the art can set the target disk selection method according to actual conditions, and this application does not impose any restrictions on this.

[0129] A virtual address corresponding to the first address information can be generated based on the first address information of the first data to be operated on and the type of the target disk. The virtual address corresponding to the first address information may include the identifier of the first address information. For example, a virtual address corresponding to the first address information can be generated based on the identifier key0 of the first address information of the first data, the type of the target disk, and other information required by the data management protocol (such as the base address, address offset, etc. in the first address description information). This virtual address is associated with the first address information through the identifier key0.

[0130] In one possible implementation, the virtual address resides in a preset virtual address space. The virtual address corresponding to the first address information may include the base address of the preset virtual address space, the type of the target disk, the identifier key of the first address information, and the address offset of the first address information. The virtual address may also include other relevant information, which can be set by those skilled in the art according to actual conditions, and this application does not impose any restrictions on this.

[0131] Although a virtual address occupies a certain address space (i.e., an address segment) within a preset virtual address range, this address space does not correspond to the actual physical storage space in the controller. In other words, the controller's secondary memory cannot be accessed using this virtual address. The controller can operate on the virtual address and convert it into corresponding primary address information before data access can be performed.

[0132] Figure 6 A schematic diagram of a virtual address space according to an embodiment of this application is shown. Figure 6 As shown, the preset virtual address space includes 4 sub-regions, corresponding to the address spaces of 4 virtual addresses:

[0133] Subregion 1 corresponds to the first address information identified as key1, that is, the address space occupied by the virtual address corresponding to the first address information identified as key1 in the virtual address space is subregion 1;

[0134] Subregion 2 corresponds to the first address information identified as key2, that is, the address space occupied by the virtual address corresponding to the first address information identified as key2 in the virtual address space is subregion 2;

[0135] Subregion 3 corresponds to the first address information identified as key3, that is, the address space occupied by the virtual address corresponding to the first address information identified as key3 in the virtual address space is subregion 3;

[0136] Subregion 4 corresponds to the first address information identified as key4, that is, the address space occupied by the virtual address corresponding to the first address information identified as key4 in the virtual address space is subregion 4.

[0137] It should be noted that, Figure 6 The virtual address space is illustrated using only an example comprising four sub-regions. Those skilled in the art should understand that the number of sub-regions and the size of each sub-region can be set according to actual circumstances, and this application does not impose any restrictions on this.

[0138] In one possible implementation, a virtual address space S can be preset. Virtual addresses of target disk type PRP can occupy the address space of virtual address space S, and virtual addresses of target disk type SGL or SGE can also occupy the address space of virtual address space S.

[0139] In one possible implementation, different virtual address spaces can be preset according to the type of the target disk. For example, two virtual address spaces, S1 and S2, can be preset. The virtual address of the target disk of type PRP can occupy the address space in virtual address space S1, while the virtual address of the target disk of type SGL or SGE can occupy the address space in virtual address space S2.

[0140] Figure 7 A schematic diagram illustrating a virtual address according to an embodiment of this application is shown. Figure 7 As shown, virtual address 700 includes the base address of the virtual address space (base_address), the type of the target disk (disk_information), the identifier (key) of the first address information corresponding to virtual address 700, and the address offset (entry_offset) in the first address information corresponding to virtual address 700.

[0141] The virtual address 700 is 48 bits long, the base address is 12 bits long, the disk information is 2 bits long, the key is 16 bits long, and the entry offset is 18 bits long.

[0142] Step S340: Generate operation instructions based on the virtual address.

[0143] The controller can generate operation instructions based on the virtual address corresponding to the first address information and the data management protocol between the controller and the target disk. These operation instructions include the virtual address. When the instruction sent by the host to the controller is a data write instruction, i.e., during the data write process, the operation instruction generated by the controller is a data write instruction sent to the target disk.

[0144] In this way, not only does the address description in the operation instructions conform to the data management protocol requirements, but the first address information of the first data in the operation instructions is replaced by the corresponding virtual address, thereby realizing address virtualization in the interaction process between the controller and the target disk.

[0145] Step S350: Send the operation instruction to the target disk so that the target disk generates an address read instruction for the virtual address.

[0146] After generating an operation command, the controller can send the operation command to the target disk. Upon receiving the operation command sent by the controller, the target disk in the first memory can generate an address read command for the virtual address in the operation command according to the operation command and the data management protocol between the controller and the target disk, and send the address read command to the controller.

[0147] Step S360: Upon receiving the address read instruction sent by the target disk, perform data interaction with the target disk based on the first address information corresponding to the virtual address.

[0148] In one possible implementation, when the controller receives an address read instruction from the target disk, it can determine the type of the target disk from the virtual address in the address read instruction, and determine the first address information corresponding to the virtual address (i.e., the physical address corresponding to the virtual address) through the key, and determine whether the address description method of the first address information corresponding to the virtual address matches the type of the target disk.

[0149] For example, if the address description method of the first address information corresponding to the virtual address is PRP and the target disk category is PRP, then the address description method of the first address information corresponding to the virtual address is considered to match the category of the target disk; if the address description method of the first address information corresponding to the virtual address is PRP and the target disk category is SGL or SGE, then the address description method of the first address information corresponding to the virtual address is considered to not match the category of the target disk.

[0150] When the address description method of the first address information corresponding to the virtual address matches the type of the target disk, the first address information can be used as the target address information to interact with the target disk. For example, assuming the data management protocol between the controller and the target disk is NVMe, when the controller uses the first address information as the target address information to interact with the target disk, it can send the first address information to the target disk; upon receiving the first address information sent by the controller, the target disk can read the first data from the controller's second memory according to the first address information and write the read first data locally (i.e., the target disk).

[0151] By matching the address description method of the first address information corresponding to the virtual address with the category of the target disk, the first address information can be directly used as the target address information to interact with the target disk, without the need for address translation, thereby improving processing efficiency.

[0152] If the address description method of the first address information corresponding to the virtual address does not match the category of the target disk, the controller can convert the first address information according to the category of the target disk to obtain the target address information. For example, assuming the category of the target disk is SGL and the address description method of the first address information corresponding to the virtual address is PRP, the controller can convert the first address information, changing its address description method from PRP to SGL, so that the address description method of the converted address information matches the category of the target disk, and treat the converted address information as the target address information; then, data interaction is performed with the target disk according to the target address information.

[0153] If the address description method of the first address information corresponding to the virtual address does not match the type of the target disk, the controller converts the first address information according to the type of the target disk to obtain the target address information, and interacts with the target disk according to the target address information, so that the controller and the target disk can interact with each other when the target address information matches the type of the target disk.

[0154] The storage device of this application embodiment has a controller that, upon receiving a data write instruction for second data sent by a host, caches the second data in a second memory. It also generates a virtual address corresponding to the first address information based on the first address information of the first data to be operated on (which may be part or all of the data in the second data) and the type of the target disk. Then, based on the virtual address, it generates and sends an operation instruction to the target disk. Upon receiving the operation instruction from the controller, the target disk generates and sends an address read instruction for the virtual address to the controller. Upon receiving the address read instruction from the target disk, the controller interacts with the target disk based on the first address information corresponding to the virtual address. This virtualization of the address information of the data to be operated on (i.e., the physical address of the data to be operated on in the second memory) allows the controller to obtain the corresponding virtual address. The virtual address is then used during the instruction (or command) interaction between the controller and the target disk. This virtualization and normalization of address information management within the storage device simplifies address management and improves the processing efficiency of the storage device.

[0155] Figure 3 In the illustrated embodiment, steps S340 and S350 represent the instruction interaction process between the controller of the storage device and the target disk. In the prior art, the addresses used during the instruction interaction between the controller and the target disk are the physical addresses of the data to be operated on. That is, in the prior art, steps S340 and S350 use the physical address of the data to be operated on in the second memory, resulting in complex address management. However, in the storage device of this embodiment, steps S340 and S350 (i.e., the instruction interaction between the controller and the target disk) use virtual addresses generated based on the first address information (physical address) of the data to be operated on. This virtualizes and normalizes the address information management within the storage device, thereby improving the processing efficiency of the storage device.

[0156] Figure 8 This diagram illustrates a data reading process of a storage device according to an embodiment of the present application. Data that the host needs to read from the first memory of the storage device can be considered as third data. When reading the third data, the host can send a data read instruction for the third data to the storage device, instructing the controller of the storage device to read the third data from the first memory.

[0157] like Figure 8 As shown, when the controller of the storage device receives a data read instruction for third-party data sent by the host, it can perform the following processing:

[0158] Step S810: Upon receiving a data read instruction for the third data sent by the host, allocate cache space for the third data in the second memory according to the length of the third data.

[0159] The data read instruction sent by the host to the controller may include information such as the storage address and length of the third data stored in the first memory, which the host instructs the controller to read. Upon receiving the data read instruction for the third data from the host, the controller can determine the length of the third data from the data read instruction and allocate buffer space for the third data in the second memory according to the length of the third data.

[0160] The cache space is used to cache the third data in the controller. That is, after the controller reads the third data from the first memory, it can store the third data in the cache space, and then send the third data in the cache space to the host, thereby completing the host's reading of the third data.

[0161] Step S820: Determine the first address information of the first data to be operated on based on the fourth address information of the cache space.

[0162] Wherein, the first data may be a portion or all of the data in the third data. A scenario where the first data is all of the third data can be that the controller reads the third data as a whole, meaning the controller can read the third data from the first memory in a single read operation. A scenario where the first data is a portion of the third data can be that the controller splits the third data into multiple data blocks and reads each data block separately, meaning the controller can read the third data from the first memory in multiple read operations.

[0163] During data reading, the controller can determine the first data to be operated on based on preset data operation rules of the storage device (such as data segmentation rules). The controller can preset a data segmentation flag to indicate whether the third data is segmented, and then determine whether the first data is part or all of the third data based on the data segmentation flag.

[0164] The controller can also determine in real time whether the first data is part or all of the third data by judging the data length, starting position offset, etc. during the data reading process. It should be noted that this judgment process is similar to... Figure 3 The judgment process in step S320 of the illustrated embodiment is similar and will not be repeated here.

[0165] After determining the first data to be operated on, the controller can determine the first address information of the first data to be operated on based on the fourth address information of the cache space. The first address information can be used to indicate the physical address of the first data to be operated on in the second memory. During data reading, the first address information can be regarded as the address information of the cache space pre-allocated in the second memory for the first data to be read.

[0166] If the first data to be operated on is all the data in the third data, the fourth address information (physical address) of the cache space can be directly determined as the first address information of the first data.

[0167] When the first data to be operated on is a portion of the third data, the cache space needs to be divided to determine the cache region corresponding to the first data. Based on the fourth address information of the cache space, the length of the first data, and the starting offset, the cache region corresponding to the first data can be determined from the cache space, and the address information of this cache region can be used as the first address information of the first data.

[0168] In one possible implementation, the first address information can be similar to the fourth address information, representing the physical address of the cache space / cache region. When the first data to be operated on is a portion of the third data, the first address information can also be represented by a translation table, data information table (DIT), etc., as the conversion relationship between the cache region corresponding to the first data and the fourth address information. The controller can obtain the physical address of the cache region corresponding to the first data through real-time parsing of the translation table or data information table.

[0169] In one possible implementation, the address description method for the fourth address information is the same as the address description method supported internally by the controller, and the address description method for the first address information is the same as that for the fourth address information. For example, assuming that the address description method supported internally by the controller is PRP, then both the fourth address information and the first address information are described using PRP.

[0170] When the controller of the storage device receives a data read instruction for the third data sent by the host, it can allocate cache space for the third data in the second memory according to the length of the third data, and determine the first address information of the first data to be operated (which may be part or all of the data in the third data) according to the fourth address information of the cache space. Thus, the third data read can be cached in the second memory of the controller during data reading, so that the controller can manage the address information in a unified address description method, thereby reducing the complexity of address management inside the controller.

[0171] During data reading, the fourth address information and the first address information are also stored in the address storage space preset by the controller for storing address information, and are associated with an identifier key. The specific method is similar to... Figure 3 The embodiments shown are similar and will not be described again here.

[0172] Step S830: Generate a virtual address corresponding to the first address information based on the first address information of the first data to be operated and the type of the target disk.

[0173] The target disk is at least one of multiple disks in the first storage device. During data reading, the target disk is the disk in the first storage device that stores the first data to be read. The virtual address corresponding to the first address information includes the identifier of the first address information.

[0174] A virtual address corresponding to the first address information can be generated based on the first address information of the first data to be operated on and the type of the target disk. The specific method is similar to... Figure 3 The embodiments shown are similar and will not be described again here.

[0175] Step S840: Generate operation instructions based on the virtual address.

[0176] The controller can generate operation instructions based on the virtual address corresponding to the first address information and the data management protocol between the controller and the target disk. These operation instructions include the virtual address. When the instruction sent by the host to the controller is a data read instruction, that is, during the data read process, the operation instruction generated by the controller is a data read instruction sent to the target disk.

[0177] In this way, not only does the address description in the operation instructions conform to the data management protocol requirements, but the first address information of the first data in the operation instructions is replaced by the corresponding virtual address, thereby realizing address virtualization in the interaction process between the controller and the target disk.

[0178] Step S850: Send the operation instruction to the target disk so that the target disk generates an address read instruction for the virtual address.

[0179] After generating an operation command, the controller can send the operation command to the target disk. Upon receiving the operation command sent by the controller, the target disk in the first memory can generate an address read command for the virtual address in the operation command according to the operation command and the data management protocol between the controller and the target disk, and send the address read command to the controller.

[0180] Step S860: Upon receiving the address read instruction sent by the target disk, perform data interaction with the target disk based on the first address information corresponding to the virtual address.

[0181] In one possible implementation, when the controller receives an address read instruction from the target disk, it can determine the type of the target disk from the virtual address in the address read instruction, and determine the first address information corresponding to the virtual address (i.e., the physical address corresponding to the virtual address) through the key, and determine whether the address description method of the first address information corresponding to the virtual address matches the type of the target disk.

[0182] For example, if the address description method of the first address information corresponding to the virtual address is PRP and the target disk category is PRP, then the address description method of the first address information corresponding to the virtual address is considered to match the category of the target disk; if the address description method of the first address information corresponding to the virtual address is PRP and the target disk category is SGL or SGE, then the address description method of the first address information corresponding to the virtual address is considered to not match the category of the target disk.

[0183] When the address description method of the first address information corresponding to the virtual address matches the type of the target disk, the first address information can be used as the target address information to interact with the target disk. For example, assuming the data management protocol between the controller and the target disk is NVMe, when the controller uses the first address information as the target address information to interact with the target disk, it can send the first address information to the target disk; upon receiving the first address information sent by the controller, the target disk can read the first data from its local storage and write the read first data into the cache space indicated by the first address information (located in the controller's second memory).

[0184] If the address description method of the first address information corresponding to the virtual address does not match the category of the target disk, the controller can convert the first address information according to the category of the target disk to obtain the target address information. For example, assuming the category of the target disk is SGL and the address description method of the first address information corresponding to the virtual address is PRP, the controller can convert the first address information, changing its address description method from PRP to SGL, so that the address description method of the converted address information matches the category of the target disk, and treat the converted address information as the target address information; then, data interaction is performed with the target disk according to the target address information.

[0185] The storage device of this application embodiment has a controller that, upon receiving a data read instruction for third data sent by a host, can pre-allocate cache space in a second memory for the third data to be read, and determine the first address information of the first data to be operated (which may be part or all of the third data) based on the fourth address information of the cache space. It can also generate a virtual address corresponding to the first address information based on the first address information of the first data to be operated and the type of the target disk, and then generate and send an operation instruction to the target disk based on the virtual address. Upon receiving the operation instruction from the controller, the target disk generates and sends an address read instruction for the virtual address to the controller. Upon receiving the address read instruction from the target disk, the controller interacts with the target disk based on the first address information corresponding to the virtual address. This virtualization of the address information of the data to be operated (i.e., the physical address of the data to be operated in the second memory) to obtain the corresponding virtual address, and the use of the virtual address during the instruction (or command) interaction between the controller and the target disk, virtualizes and normalizes the address information management within the storage device, thereby simplifying address management within the storage device and improving the processing efficiency of the storage device.

[0186] Figure 8 In the illustrated embodiment, steps S840 and S850 represent the instruction interaction process between the controller of the storage device and the target disk. In the prior art, the addresses used during the instruction interaction between the controller and the target disk are the physical addresses of the data to be operated on. That is, in the prior art, steps S840 and S850 use the physical address of the data to be operated on in the second memory, resulting in complex address management. However, in the storage device of this embodiment, steps S840 and S850 (i.e., the instruction interaction between the controller and the target disk) use virtual addresses generated based on the first address information (physical address) of the data to be operated on. This virtualizes and normalizes the address information management within the storage device, thereby improving the processing efficiency of the storage device.

[0187] The storage device of this application embodiment can cache the data being operated on through the second memory in the controller, and use virtual addresses during the instruction interaction between the controller and the target disk, thereby virtualizing and normalizing the address information management within the storage device. During the instruction interaction between the controller and the target disk in the first memory, the virtual addresses in the operation instructions sent by the controller to the target disk exhibit different patterns depending on the type of the target disk.

[0188] Figure 9A flowchart illustrating a storage method according to an embodiment of this application is shown. The storage method described in this application embodiment is applied to a controller in a storage device, the storage device further including a first memory comprising a plurality of disks, and the controller including a second memory for caching data.

[0189] like Figure 9 As shown, the storage method includes:

[0190] Step S910: Based on the first address information of the first data to be operated and the type of the target disk, generate a virtual address corresponding to the first address information. The first address information is used to indicate the physical address of the first data in the second memory. The target disk is at least one of the plurality of disks. The virtual address includes the identifier of the first address information.

[0191] Step S920: Generate operation instructions based on the virtual address;

[0192] Step S930: Send the operation instruction to the target disk so that the target disk generates an address read instruction for the virtual address;

[0193] Step S940: Upon receiving the address read instruction sent by the target disk, perform data interaction with the target disk based on the first address information corresponding to the virtual address.

[0194] In one possible implementation, the controller is connected to a host, and the method may further include: upon receiving a data write instruction for second data sent by the host, caching the second data in the second memory according to the second address information of the second data in the data write instruction, wherein the data write instruction is used to instruct the controller to write the second data into the first memory; and determining the first address information of the first data to be operated on according to the third address information of the second data in the second memory, wherein the first data is part or all of the second data.

[0195] In one possible implementation, the method may further include: upon receiving a data read instruction for third data sent by the host, allocating cache space for the third data in the second memory according to the length of the third data, wherein the data read instruction is used to instruct the controller to read the third data from the first memory, and the cache space is used to cache the third data in the controller; determining the first address information of the first data to be operated on according to the fourth address information of the cache space, wherein the first data is part or all of the data in the third data.

[0196] In one possible implementation, the address description method of the second address information is any one of Physical Region Page (PRP), Distributed Aggregate Table (SGL), and Distributed Aggregate Element (SGE); the address description method of the first address information, the third address information, and the fourth address information is PRP; and the category of the target disk is any one of PRP category, SGL category, and SGE category.

[0197] In one possible implementation, determining the first address information of the first data based on the third address information of the second data in the second memory may include: when the first data is a portion of the second data, determining the first address information of the first data based on the third address information, the length of the first data, and the starting position offset, wherein the starting position offset is used to indicate the offset of the starting position of the first data relative to the starting position of the second data.

[0198] In one possible implementation, determining the first address information of the first data based on the third address information of the second data in the second memory may include: when the first data is all the data in the second data, determining the third address information of the second data as the first address information of the first data.

[0199] In one possible implementation, the method may further include: determining that the first data is all the data in the second data when the length of the first data is the same as the length of the second data and the starting position offset of the first data is equal to 0.

[0200] In one possible implementation, the method may further include: determining that the first data is a portion of the second data when the length of the first data is different from the length of the second data, or when the starting position offset of the first data is not equal to 0.

[0201] In one possible implementation, step S940 may include: if the address description method of the first address information does not match the category of the target disk, converting the first address information according to the category of the target disk to obtain target address information; and performing data interaction with the target disk according to the target address information.

[0202] In one possible implementation, step S940 may include: if the address description method of the first address information matches the category of the target disk, using the first address information as target address information to perform data interaction with the target disk.

[0203] Embodiments of this application also provide an electronic device, including: a processor, and a storage device connected to the processor, wherein the storage device is any of the storage devices described above.

[0204] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and electronic devices according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved.

[0205] It should also be noted that each block in the block diagram and / or flowchart, as well as combinations of blocks in the block diagram and / or flowchart, can be implemented using hardware (such as circuits or ASICs (Application Specific Integrated Circuits)) that performs the corresponding function or action, or using a combination of hardware and software, such as firmware.

[0206] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, disclosure, and appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0207] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A storage device, characterized in that, The storage device includes a controller and a first memory, the first memory including multiple disks, and the controller including a second memory for caching data. The controller is configured to: Based on the first address information of the first data to be operated and the type of the target disk, a virtual address corresponding to the first address information is generated. The first address information is used to indicate the physical address of the first data in the second memory. The target disk is at least one of the plurality of disks. The virtual address includes the identifier of the first address information. Based on the virtual address, generate operation instructions; The operation instruction is sent to the target disk to cause the target disk to generate an address read instruction for the virtual address; Upon receiving the address read instruction sent by the target disk, data interaction is performed with the target disk based on the first address information corresponding to the virtual address.

2. The storage device according to claim 1, characterized in that, The controller is connected to the host computer. The controller is also configured to: Upon receiving a data write instruction for the second data sent by the host, the second data is cached in the second memory according to the second address information of the second data in the data write instruction. The data write instruction is used to instruct the controller to write the second data into the first memory. Based on the third address information of the second data in the second memory, the first address information of the first data to be operated is determined, wherein the first data is part or all of the data in the second data.

3. The storage device according to claim 2, characterized in that, The controller is also configured to: Upon receiving a data read instruction for third data sent by the host, a cache space is allocated in the second memory for the third data according to the length of the third data. The data read instruction is used to instruct the controller to read the third data from the first memory, and the cache space is used to cache the third data in the controller. Based on the fourth address information of the cache space, the first address information of the first data to be operated is determined, wherein the first data is part or all of the data in the third data.

4. The storage device according to claim 3, characterized in that, The address description method of the second address information is any one of Physical Region Page (PRP), Distributed Aggregate Table (SGL), and Distributed Aggregate Element (SGE). The address description method of the first address information, the third address information, and the fourth address information is PRP. The category of the target disk is any one of PRP category, SGL category, and SGE category.

5. The storage device according to claim 2, characterized in that, Determining the first address information of the first data based on the third address information of the second data in the second memory includes: When the first data is a portion of the second data, the first address information of the first data is determined based on the third address information, the length of the first data, and the starting position offset. The starting position offset is used to indicate the offset of the starting position of the first data relative to the starting position of the second data.

6. The storage device according to claim 2, characterized in that, Determining the first address information of the first data based on the third address information of the second data in the second memory includes: If the first data is all the data in the second data, the third address information of the second data is determined as the first address information of the first data.

7. The storage device according to any one of claims 2-6, characterized in that, The controller is also configured to: If the length of the first data is the same as the length of the second data, and the starting position offset of the first data is equal to 0, then the first data is determined to be all the data in the second data.

8. The storage device according to claim 2, characterized in that, The controller is also configured to: If the length of the first data is different from the length of the second data, or if the starting position offset of the first data is not equal to 0, the first data is determined to be a part of the second data.

9. The storage device according to claim 1, characterized in that, The step of interacting with the target disk based on the first address information corresponding to the virtual address includes: If the address description method of the first address information does not match the category of the target disk, the first address information is converted according to the category of the target disk to obtain the target address information; Data interaction is performed with the target disk based on the target address information.

10. The storage device according to claim 1, characterized in that, The step of interacting with the target disk based on the first address information corresponding to the virtual address includes: If the address description method of the first address information matches the category of the target disk, the first address information is used as the target address information to interact with the target disk.

11. A storage method, characterized in that, The method is applied to a controller in a storage device, the storage device further including a first memory comprising a plurality of disks, and the controller including a second memory for caching data. The method includes: Based on the first address information of the first data to be operated and the type of the target disk, a virtual address corresponding to the first address information is generated. The first address information is used to indicate the physical address of the first data in the second memory. The target disk is at least one of the plurality of disks. The virtual address includes the identifier of the first address information. Based on the virtual address, generate operation instructions; The operation instruction is sent to the target disk to cause the target disk to generate an address read instruction for the virtual address; Upon receiving the address read instruction sent by the target disk, data interaction is performed with the target disk based on the first address information corresponding to the virtual address.

12. The storage method according to claim 11, characterized in that, The controller is connected to the host computer. The method further includes: Upon receiving a data write instruction for the second data sent by the host, the second data is cached in the second memory according to the second address information of the second data in the data write instruction. The data write instruction is used to instruct the controller to write the second data into the first memory. Based on the third address information of the second data in the second memory, the first address information of the first data to be operated is determined, wherein the first data is part or all of the data in the second data.

13. The storage method according to claim 12, characterized in that, The method further includes: Upon receiving a data read instruction for third data sent by the host, a cache space is allocated in the second memory for the third data according to the length of the third data. The data read instruction is used to instruct the controller to read the third data from the first memory, and the cache space is used to cache the third data in the controller. Based on the fourth address information of the cache space, the first address information of the first data to be operated is determined, wherein the first data is part or all of the data in the third data.

14. The storage method according to claim 13, characterized in that, The address description method of the second address information is any one of Physical Region Page (PRP), Distributed Aggregate Table (SGL), and Distributed Aggregate Element (SGE). The address description method of the first address information, the third address information, and the fourth address information is PRP. The category of the target disk is any one of PRP category, SGL category, and SGE category.

15. The storage method according to claim 12, characterized in that, Determining the first address information of the first data based on the third address information of the second data in the second memory includes: When the first data is a portion of the second data, the first address information of the first data is determined based on the third address information, the length of the first data, and the starting position offset. The starting position offset is used to indicate the offset of the starting position of the first data relative to the starting position of the second data.

16. The storage method according to claim 12, characterized in that, Determining the first address information of the first data based on the third address information of the second data in the second memory includes: If the first data is all the data in the second data, the third address information of the second data is determined as the first address information of the first data.

17. The storage method according to any one of claims 12-16, characterized in that, The method further includes: If the length of the first data is the same as the length of the second data, and the starting position offset of the first data is equal to 0, then the first data is determined to be all the data in the second data.

18. The storage method according to claim 12, characterized in that, The method further includes: If the length of the first data is different from the length of the second data, or if the starting position offset of the first data is not equal to 0, the first data is determined to be a part of the second data.

19. The storage method according to claim 11, characterized in that, The step of interacting with the target disk based on the first address information corresponding to the virtual address includes: If the address description method of the first address information does not match the category of the target disk, the first address information is converted according to the category of the target disk to obtain the target address information; Data interaction is performed with the target disk based on the target address information.

20. The storage method according to claim 11, characterized in that, The step of interacting with the target disk based on the first address information corresponding to the virtual address includes: If the address description method of the first address information matches the category of the target disk, the first address information is used as the target address information to interact with the target disk.

21. An electronic device, characterized in that, include: processor; A storage device connected to the processor, wherein the storage device is the storage device according to any one of claims 1-10.

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