Signal processing method, display device, electronic equipment and readable storage medium

Abstract

A signal processing method, a display device, an electronic device and a computer readable storage medium (600). The signal processing method is used for a display device, the display device includes a display substrate (110), the display substrate (110) includes M rows and N columns of pixel units arranged in an array, and the signal processing method includes: obtaining display data of a frame of to-be-displayed image, wherein the display data includes P rows and Q columns of pixel data arranged in an array; generating P rows of gate scanning signals corresponding to the P rows of pixel data; in the case that P is less than M, generating M-P rows of supplementary gate scanning signals based on the P rows of gate scanning signals, wherein the P rows of gate scanning signals and the M-P rows of supplementary gate scanning signals form M rows of gate scanning signals; and driving the M rows of pixel units by using the M rows of gate scanning signals respectively, wherein P, Q, M and N are all positive integers.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a signal processing method, a display device, an electronic device and a computer readable storage medium. BACKGROUND

[0002] With the development of display industry, display devices with display panels as display ports have been increasingly integrated into people's work and life. Common display devices include liquid crystal display devices and OLED (Organic Light-Emitting Diode) display devices, etc. SUMMARY

[0003] At least one embodiment of the present disclosure provides a signal processing method for a display device, the display device comprising a display substrate, the display substrate comprising M rows and N columns of pixel units arranged in an array, the signal processing method comprising: obtaining display data of a frame of to-be-displayed image, wherein the display data comprises P rows and Q columns of pixel data arranged in an array; generating P rows of gate scanning signals corresponding to the P rows of pixel data; in a case where P is less than M, generating M-P rows of supplementary gate scanning signals based on the P rows of gate scanning signals, wherein the P rows of gate scanning signals and the M-P rows of supplementary gate scanning signals form M rows of gate scanning signals; and driving the M rows of pixel units by using the M rows of gate scanning signals respectively; wherein P, Q, M and N are all positive integers.

[0004] For example, in the signal processing method provided by at least one embodiment of the present disclosure, in a case where M=A*P, generating M-P rows of supplementary gate scanning signals based on the P rows of gate scanning signals comprises: generating A-1 rows of supplementary gate scanning signals between every two adjacent rows of gate scanning signals in the P rows of gate scanning signals; and generating A-1 rows of gate scanning signals on at least one side of the P rows of gate scanning signals; wherein A is an integer greater than 1.

[0005] For example, in the signal processing method provided by at least one embodiment of the present disclosure, the P rows of gate scanning signals include an i-th row of gate scanning signal and an (i+1)-th row of gate scanning signal; and the M-P rows of supplementary gate scanning signals are generated based on the P rows of gate scanning signals, including: generating B rows of supplementary gate scanning signals between the i-th row of gate scanning signal and the (i+1)-th row of gate scanning signal based on the time sequence of the i-th row of gate scanning signal and the (i+1)-th row of gate scanning signal; wherein the rising edges of the B rows of supplementary gate scanning signals are all located between the rising edge of the i-th row of gate scanning signal and the rising edge of the (i+1)-th row of gate scanning signal in the time sequence, and the falling edges of the B rows of supplementary gate scanning signals are all located between the falling edge of the i-th row of gate scanning signal and the falling edge of the (i+1)-th row of gate scanning signal in the time sequence, wherein i is a positive integer less than P, and B is a positive integer less than or equal to M-P.

[0006] For example, in the signal processing method provided by at least one embodiment of the present disclosure, the rising edges of the i-th row of gate scanning signal, the B rows of supplementary gate scanning signals and the (i+1)-th row of gate scanning signal are sequentially and sequentially delayed in the time sequence; and the falling edges of the i-th row of gate scanning signal, the B rows of supplementary gate scanning signals and the (i+1)-th row of gate scanning signal are sequentially and sequentially delayed in the time sequence.

[0007] For example, in the signal processing method provided by at least one embodiment of the present disclosure, the B rows of supplementary gate scanning signals between the i-th row of gate scanning signal and the (i+1)-th row of gate scanning signal are generated based on the time sequence of the i-th row of gate scanning signal and the (i+1)-th row of gate scanning signal, including: performing an interpolation operation on the phase of the i-th row of gate scanning signal and the phase of the (i+1)-th row of gate scanning signal to obtain the phase of the B rows of supplementary gate scanning signals.

[0008] For example, in the signal processing method provided by at least one embodiment of the present disclosure, the time difference between the rising edge and the falling edge of each of the B rows of supplementary gate scanning signals is the same as the time difference between the rising edge and the falling edge of the i-th row of gate scanning signal.

[0009] For example, in the signal processing method provided by at least one embodiment of the present disclosure, each pixel unit includes S sub-pixels, and the S sub-pixels in the same pixel unit are arranged along a row direction, and the N columns of pixel units include N*S columns of sub-pixels; and the sub-pixels in the same column have the same polarity in the display time of a frame of to-be-displayed image, wherein S is a positive integer.

[0010] For example, the signal processing method provided in at least one embodiment of this disclosure further includes: driving the M row pixel units using the P row gate scan signal when P equals M.

[0011] For example, in at least one embodiment of the signal processing method provided in this disclosure, the display device further includes N data signal lines respectively connected to the N columns of pixel units; the signal processing method further includes: generating P rows of analog data signals based on the P rows of pixel data, wherein the P rows of analog data signals include an i-th row of analog data signals, and the i-th row of analog data signals includes Q analog data signals; from the time period from the start of driving the data write switch of the corresponding row of pixel units to open using the i-th row of gate scan signals to the time period before driving the data write switch of the corresponding row of pixel units to open using the (i+1)-th row of gate scan signals, inputting the Q analog data signals of the i-th row of analog data signals into the Q data signal lines of the N data signal lines respectively.

[0012] For example, in the signal processing method provided in at least one embodiment of this disclosure, each pixel unit includes S sub-pixels, the N column pixel unit includes N*S column sub-pixels, and the N data signal lines include N*S sub-data signal lines respectively connected to the N*S column sub-pixels; each analog data signal includes S sub-analog data signals, and the Q analog data signals include Q*S sub-analog data signals; inputting the Q analog data signals of the i-th row analog data signal into the Q data signal lines of the N data signal lines includes: inputting the Q*S sub-analog data signals into the Q*S data signal lines of the N*S sub-data signal lines.

[0013] For example, the signal processing method provided in at least one embodiment of this disclosure further includes: performing a data supplementation operation when Q is less than N, wherein the data supplementation operation includes: generating NQ columns of supplementary pixel data based on the Q columns of pixel data, the Q columns of pixel data and the NQ columns of supplementary pixel data forming N columns of pixel data; generating N columns of analog data signals based on the N columns of pixel data; and inputting the N columns of analog data signals into the N columns of pixel units respectively.

[0014] For example, in a signal processing method provided in at least one embodiment of this disclosure, when N = C * Q, generating NQ columns of supplementary pixel data based on the Q columns of pixel data includes: generating C-1 columns of supplementary pixel data between every two adjacent columns of pixel data in the Q columns of pixel data; generating C-1 columns of supplementary pixel data on at least one side of the Q columns of pixel data; wherein C is an integer greater than 1.

[0015] For example, in the signal processing method provided in at least one embodiment of this disclosure, the Q column pixel data includes adjacent j-th column pixel data and j+1-th column pixel data; generating NQ column supplementary pixel data based on the Q column pixel data includes: performing interpolation operations on the j-th column pixel data and the j+1-th column pixel data to generate D column supplementary pixel data located between the j-th column pixel data and the j+1-th column pixel data; wherein, j is a positive integer less than Q, and D is a positive integer less than or equal to NQ.

[0016] For example, at least one embodiment of the signal processing method provided in this disclosure further includes: when Q equals N, generating Q columns of analog data signals based on the Q columns of pixel data, wherein the Q columns of analog data signals are respectively used to input the N columns of pixel units.

[0017] For example, at least one embodiment of the signal processing method provided in this disclosure further includes: determining whether the display data of multiple consecutive frames of images to be displayed conforms to an alternating display pattern, wherein the Q column pixel data of the display data conforming to the alternating display pattern cycles among g pixel values, and the g pixel values ​​correspond to g brightness features respectively; if so, dividing the multiple frames of images to be displayed into multiple image groups, each image group including adjacent g frames of images to be displayed, and performing the following operations for each image group: if the current frame of images to be displayed is the kth frame of images to be displayed in the image group, transforming all the Q column pixel data of the kth frame of images to be displayed into the kth pixel value among the g pixel values; and performing the data supplementation for the transformed Q column pixel data. The operation involves generating analog data signals based on the (k+n*g)th column pixel data after the data supplementation operation and inputting them into the (k+n*g)th column pixel units respectively, so that the (k+n*g)th column pixel units are displayed as the kth brightness feature among the g brightness features. Specifically, when k is a positive integer greater than 1, the remaining column pixel units (excluding the (k+n*g)th column pixel units) are displayed as the brightness features corresponding to the previous frame of the image to be displayed in the kth frame. When k equals 1, the remaining column pixel units (excluding the (k+n*g)th column pixel units) are not displayed. Here, n takes all integers from 0 to [Q / g-1], g is an integer greater than 1 and less than Q, and k is an integer less than or equal to g.

[0018] At least one embodiment of this disclosure also provides a display device, including a display substrate and a timing controller. The display substrate includes M rows and N columns of pixel units arranged in an array. The timing controller includes a data receiving module and a gate signal generation module. The data receiving module is configured to acquire display data of a frame of image to be displayed, wherein the display data includes P rows and Q columns of pixel data arranged in an array. The gate signal generation module is configured to: generate P rows of gate scan signals corresponding to the P rows of pixel data; and perform a gate signal supplementation operation when P is less than M, wherein the gate signal supplementation operation includes: generating MP rows of supplementary gate scan signals based on the P rows of gate scan signals, wherein the P rows of gate scan signals and the MP rows of supplementary gate scan signals form M rows of gate scan signals to drive M rows of pixel units respectively using the M rows of gate scan signals; P, Q, M, and N are all positive integers.

[0019] For example, in at least one embodiment of the display device provided in this disclosure, the display device further includes a source driver chip. The source driver chip is connected to the M-row N-column pixel unit through multiple data signal lines extending along a second direction intersecting the first direction to provide analog data signals to the M-row N-column pixel unit. The source driver chip is configured to perform a data supplementation operation when Q is less than N. The data supplementation operation includes: generating NQ-column supplementary pixel data based on Q-column pixel data, and forming N-column pixel data from the Q-column pixel data and the NQ-column supplementary pixel data; generating N-column analog data signals based on the formed N-column pixel data; and inputting the N-column analog data signals into the N-column pixel unit respectively.

[0020] For example, in a display device provided in at least one embodiment of this disclosure, the source driver chip includes a cache module, multiple arithmetic modules, and multiple digital-to-analog conversion modules. The cache module is configured to cache display data; the multiple arithmetic modules are configured to perform data supplementation operations to obtain NQ columns of supplementary pixel data; and the multiple digital-to-analog conversion modules are configured to convert the N columns of pixel data into N columns of analog data signals.

[0021] For example, in the display device provided in at least one embodiment of this disclosure, the timing controller further includes a mode control module. The mode control module is configured to receive a mode instruction and send a control signal to the gate signal generation module and / or the source driver chip based on the mode instruction, so as to control whether the gate signal generation module performs a gate signal supplementation operation and / or control whether the source driver chip performs a data supplementation operation.

[0022] For example, in the display device provided in at least one embodiment of this disclosure, the source driver chip further includes a plurality of dual-pass switches and a mode switching module. Each dual-pass switch includes an input terminal and two output terminals. The input terminal is connected to a buffer module for receiving a series of pixel data. One of the output terminals is connected to at least one of a plurality of digital-to-analog conversion modules, and the other output terminal is connected to at least one of a plurality of arithmetic modules. The mode switching module is configured to control the dual-pass switches to output a series of pixel data to one of the two output terminals based on the control signal sent by the mode control module.

[0023] For example, in the display device provided in at least one embodiment of this disclosure, the timing controller further includes an image recognition module. The image recognition module is configured to: identify whether the display data of multiple consecutive frames of images to be displayed conforms to an alternating display pattern, wherein the Q column pixel data of the display data conforming to the alternating display pattern cycles among g pixel values, and the g pixel values ​​correspond to g brightness features respectively; if so, divide the multiple frames of images to be displayed into multiple image groups, each image group including adjacent g frames of images to be displayed, and perform the following for each image group: if the current frame of images to be displayed is the kth frame of images to be displayed in the image group, transform all the Q column pixel data of the kth frame of images to be displayed into the kth pixel value among the g pixel values; output the transformed Q column pixel data to the source driver chip; the source driver chip also... The configuration is as follows: For the transformed Q column pixel data, perform a data supplementation operation; generate an analog data signal based on the k+n*g column pixel data after the data supplementation operation and input it into the k+n*g column pixel units respectively, so that the k+n*g column pixel units are displayed as the kth brightness feature among the g brightness features. Wherein, when k is a positive integer greater than 1, the remaining column pixel units except the k+n*g column pixel units are displayed as the brightness features corresponding to the previous frame image to be displayed in the k frame image to be displayed; when k equals 1, the remaining column pixel units except the k+n*g column pixel units are not displayed. Here, n takes all integers from 0 to [Q / g-1], g is an integer greater than 1 and less than Q, and k is an integer less than or equal to g.

[0024] At least one embodiment of this disclosure provides an electronic device, including a display device provided in any embodiment of this disclosure.

[0025] At least one embodiment of this disclosure provides an electronic device, including a processor; a memory including one or more computer program modules; wherein the one or more computer program modules are stored in the memory and configured to be executed by the processor, and the one or more computer program modules include instructions for implementing the signal processing method provided in any embodiment of this disclosure.

[0026] At least one embodiment of this disclosure provides a computer-readable storage medium for storing non-transitory computer-readable instructions that, when executed by a computer, can implement the signal processing method provided in any embodiment of this disclosure. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of the present invention and are not intended to limit the present invention.

[0028] Figure 1 A schematic diagram of a display device provided in at least one embodiment of this disclosure;

[0029] Figure 2 This is a schematic diagram of the arrangement of sub-pixels provided for at least one embodiment of the present disclosure;

[0030] Figure 3 A schematic diagram of a timing controller provided for at least one embodiment of this disclosure;

[0031] Figure 4 A schematic diagram of another display device provided in at least one embodiment of the present disclosure;

[0032] Figure 5 A schematic diagram illustrating a signal processing method provided in at least one embodiment of this disclosure;

[0033] Figure 6 A timing diagram of a gate scan signal provided in at least one embodiment of this disclosure;

[0034] Figure 7 A schematic diagram illustrating a display process provided for at least one embodiment of this disclosure;

[0035] Figure 8 A schematic diagram illustrating another display process provided for at least one embodiment of this disclosure;

[0036] Figure 9 A schematic diagram illustrating a grayscale variation provided for at least one embodiment of this disclosure;

[0037] Figure 10 A schematic diagram illustrating another display process provided for at least one embodiment of this disclosure;

[0038] Figure 11 A schematic diagram of a source driver provided for at least one embodiment of this disclosure;

[0039] Figure 12 A schematic diagram of input pixel data and output pixel data in a source driver provided in at least one embodiment of the present disclosure;

[0040] Figure 13 A schematic diagram of a resolution control module provided for at least one embodiment of this disclosure;

[0041] Figure 14 A schematic diagram illustrating a grayscale variation provided for at least one embodiment of this disclosure;

[0042] Figure 15 A schematic diagram of input pixel data and output pixel data in another source driver provided in at least one embodiment of the present disclosure;

[0043] Figure 16 A schematic diagram of input pixel data and output pixel data in another source driver provided in at least one embodiment of the present disclosure;

[0044] Figure 17 A schematic diagram of another timing controller provided for at least one embodiment of this disclosure;

[0045] Figure 18 A schematic diagram of another source driver chip provided for at least one embodiment of this disclosure;

[0046] Figure 19 A schematic diagram of another resolution conversion module provided for at least one embodiment of this disclosure;

[0047] Figure 20 A schematic diagram of an image to be displayed that conforms to an alternating display pattern, provided for at least one embodiment of this disclosure;

[0048] Figure 21 A schematic diagram of another display device provided in at least one embodiment of the present disclosure;

[0049] Figure 22 A schematic diagram of another resolution conversion module provided for at least one embodiment of this disclosure;

[0050] Figure 23 This is a schematic diagram of a display screen provided for at least one embodiment of the present disclosure;

[0051] Figure 24 This is a schematic diagram illustrating another display screen provided in at least one embodiment of the present disclosure;

[0052] Figure 25 A schematic block diagram of an electronic device provided for some embodiments of this disclosure;

[0053] Figure 26 A schematic block diagram of another electronic device provided for some embodiments of this disclosure;

[0054] Figure 27 This is a schematic diagram of a storage medium provided for some embodiments of this disclosure. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0056] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising,” “including,” or “including,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0057] Figure 1 This is a schematic diagram of a display device provided for at least one embodiment of the present disclosure. Figure 1 As shown, the display device includes a display panel 110, a timing controller 120, a gate driver 130, and a source driver 140.

[0058] The display panel 110 includes multiple rows and columns of sub-pixels Pxij arranged in an array. For example, the display substrate 110 includes M rows and N columns of pixel units arranged in an array. A pixel unit is the smallest complete display unit of the display panel and can be composed of several sub-pixels Pxij. For example, each pixel unit includes S sub-pixels (S is a positive integer). The S sub-pixels located in the same pixel unit can be arranged along the row direction. In this case, the N column pixel unit includes N*S columns of sub-pixels.

[0059] Figure 2 This is a schematic diagram illustrating the arrangement of sub-pixels according to at least one embodiment of the present disclosure. Figure 2As shown, each pixel unit includes, for example, three sub-pixels arranged along the row direction, namely sub-pixel 1, sub-pixel 2, and sub-pixel 3. These three types of sub-pixels are, for example, R (red), G (green), and B (blue), respectively. Then the display panel includes M rows and 3N columns of sub-pixels. Three consecutive sub-pixels in each row form a pixel unit. For example, three sub-pixels connected to DL1 to DL3 in the first row form pixel unit 1, three sub-pixels connected to DL4 to DL6 in the first row form pixel unit 2, ..., three sub-pixels connected to DL(3x-2) to DL3x in the first row form pixel unit x, where 1 <= x <= N, ..., three sub-pixels connected to DL(3N-2) to DL3N in the first row form pixel unit N. In addition, the number and arrangement of sub-pixels contained in a pixel unit can also be adopted in other ways. This embodiment of the disclosure takes a pixel unit containing 3 sub-pixels and the 3 sub-pixels in the same pixel unit arranged along the row direction as an example for explanation.

[0060] like Figure 1 and Figure 2 As shown, the display panel also includes multiple gate scan signal lines (GL1~GLM) extending along a first direction and multiple data signal lines (DL1~DLN*S) extending along a second direction intersecting the first direction. For example, the first direction is the row direction, the second direction is the column direction, and the first direction is perpendicular to the second direction. The multiple gate scan signal lines (GL1~GLM) are respectively connected to M rows of pixel units. One gate scan signal line can be connected to each sub-pixel in a row. The gate scan signal transmitted by the gate scan signal line is used to drive the switching devices of all sub-pixels in the corresponding row to turn on. The multiple data signal lines (DL1~DLN*S) are respectively connected to N*S columns of sub-pixels. One data signal line is connected to each sub-pixel in a column. When the switching devices of a sub-pixel are turned on, the data signal transmitted by the data signal line can be written into the sub-pixel. The data signal is a signal for adjusting the grayscale of the sub-pixel display, causing each sub-pixel of the display panel to display different grayscale levels. In the following embodiments, GL1 to GLM are used to represent both gate scan signal lines and gate scan signals transmitted on the corresponding gate scan signal lines, and DL1 to DLN*S are used to represent both data signal lines and data signals transmitted on the corresponding data signal lines.

[0061] Each sub-pixel is connected to a gate scan signal line and a data signal line, and grayscale changes are achieved through control of these lines. During the presentation of the image to be displayed, one row of sub-pixels in the display panel can be turned on at a time, and the data driver 140 writes the corresponding row's data signal into the turned-on sub-pixels, causing those sub-pixels to display the corresponding brightness. By turning on and writing data row by row in this manner, the display panel can present the image to be displayed according to the corresponding display brightness.

[0062] The timing controller 120 is a board that implements timing conversion functions. It can be a standalone component or included in a front-end video and other signal processing system. Figure 3 This is a schematic diagram of a timing controller provided for at least one embodiment of the present disclosure. Figure 3 As shown, the timing controller 120 includes a data receiving module 121, a gate signal generation module 122, and a data signal transmitting module 123. The data receiving module 121 receives display data of the image to be displayed. The gate signal generation module 122 generates a one-to-one gate scan signal based on the vertical resolution of the display data (i.e., the number of rows of display data) and sends it to the gate driver 130, so that the gate scan signal is sent to the display panel through multiple shift register units cascaded in the gate driver 130. The data signal transmitting module 123 sends the display data to the source driver. The received and transmitted pixel data are one-to-one, referred to as Point-to-Point (P to P), meaning the number of columns of received data is the same as the number of columns of transmitted data, and the number of rows of received data is the same as the number of rows of transmitted data. The source driver processes the data signal and sends it to the display panel. In some embodiments, the timing controller is also referred to as a timing control board. In some embodiments, the gate signal generation module is also referred to as a gate line signal generation module, and the gate scan signal is also referred to as a gate line signal.

[0063] The source driver 140 may include a source driver IC (Integrated Circuit Chip), which is responsible for converting the received digital data signals into analog data signals that can drive the pixel display. Its output channels correspond one-to-one with the columns of the display panel. The digital data signal refers to the data signal in which the timing control board equally divides the pixel data signal of each row and sends it to the source driver IC through the data signal transmission module. It is a binary digital signal. The analog data signal is the analog voltage signal converted by the source driver IC from the digital data signal and sent to each data line of the display panel. In some embodiments below, the source driver 140 is also referred to as the source driver IC or source driver chip.

[0064] Figure 4 This is a schematic diagram of another display device provided for at least one embodiment of the present disclosure. (See diagram below.) Figure 4 As shown, the gate driver can be integrated into the display panel. The gate scan signal from the timing controller can be sent to the display panel through the source driver. The sub-pixels are driven row by row through the gate driver and gate scan signal line integrated into the display panel. The display data signal from the timing controller is sent to the source driver, which processes the display data signal and sends it to each column of sub-pixels through the data signal line.

[0065] To meet people's demand for high definition and high smoothness, ultra-high resolution and ultra-high refresh rate panels have been developed and introduced, leading to a significant increase in the demand for display signal data. For example, 4K2K 240Hz has twice the data volume of 4K2K 120Hz, and 8K4K 120Hz has four times the data volume of 4K2K 120Hz. The significantly increased data volume places higher demands on the processing speed of the system chips that generate display signals. Higher-speed signal transmission requires more optimized transmission paths (design, process, materials, etc.). At the same time, the timing control chip and source driver chip of the display system itself must also be matched, which greatly increases the cost and seriously affects the popularization of ultra-high resolution and ultra-high refresh rate panels, becoming a stumbling block to people's pursuit of a better life.

[0066] The display panel consists of M rows and N columns of display units, so its physical resolution is N*M. Each row has N pixels, called the horizontal resolution; each column has M pixels, called the vertical resolution. The resolution of the image to be displayed must match the physical resolution of the display panel, meaning the number of rows and columns must correspond one-to-one. When the display signal resolution does not match the physical resolution of the display panel, for example, if the horizontal resolution is only half the panel resolution, the display panel will be unable to display anything or the display quality will be poor.

[0067] This disclosure provides at least one embodiment of a signal processing method, a display device, an electronic device, and a computer-readable storage medium. The signal processing method is used in a display device, which includes a display substrate and an array of M rows and N columns of pixel units. The signal processing method includes: acquiring display data of a frame of an image to be displayed, wherein the display data includes P rows and Q columns of pixel data; generating a P-row gate scan signal corresponding to the P-row pixel data; generating an MP-row supplementary gate scan signal based on the P-row gate scan signal when P is less than M, wherein the P-row gate scan signal and the MP-row supplementary gate scan signal form an M-row gate scan signal; and driving the M-row pixel units using the generated M-row gate scan signal, where P, Q, M, and N are all positive integers.

[0068] The signal processing method of this disclosure generates a gate scan signal corresponding to the number of rows of display data and a supplementary gate scan signal based on the gate scan signal, thereby expanding the total number of rows of the gate scan signal to be the same as the number of rows of pixel units in the display panel. Based on this method, even when the vertical resolution of the image to be displayed is less than the vertical resolution of the display panel, all rows of pixel units in the display panel can be displayed, achieving an expansion of the vertical resolution and improving the display effect.

[0069] The embodiments and some examples of this disclosure will now be described in detail with reference to the accompanying drawings.

[0070] Figure 5 This diagram illustrates a signal processing method provided in at least one embodiment of the present disclosure. This signal processing method is used, for example, in the aforementioned display device, such as... Figure 5 As shown, the signal processing method includes steps S210-S240.

[0071] Step S210: Obtain display data for a frame of image to be displayed. The display data includes pixel data arranged in P rows and Q columns of the array.

[0072] Step S220: Generate P-row gate scan signals corresponding to the P-row pixel data.

[0073] Step S230: When P is less than M, generate MP row supplementary gate scan signals based on the P row gate scan signals, and the P row gate scan signals and MP row supplementary gate scan signals form M row gate scan signals.

[0074] Step S240: Drive the M rows of pixel units using the generated M row gate scan signals respectively.

[0075] For example, P, Q, M, and N are all positive integers, P is less than or equal to M, and Q is less than or equal to N.

[0076] For example, with Figure 1 Taking the display device shown as an example, the display panel includes M rows and N columns of pixel units. Each pixel unit includes S sub-pixels arranged along the row direction (S is a positive integer). The N column pixel units include N*S columns of sub-pixels, that is, the display panel includes M rows and N*S columns of sub-pixels. The M row pixel unit in the following content can also be understood as M row sub-pixels.

[0077] For example, subpixels located in the same column may have the same polarity during the display time of a single frame of an image, either both positive or both negative. For instance, the polarity of a subpixel here refers to the polarity of the data signal applied to that subpixel.

[0078] For example, in step S220, the gate signal generation module generates a gate scan signal corresponding to the number of rows P of the image to be displayed.

[0079] For example, in step S230, it can be determined whether the number of rows P of the image to be displayed is less than the number of rows M of pixel units in the display panel (i.e., the number of rows M of sub-pixels). If the number of rows P of the image to be displayed is less than the number of rows M of pixel units, then MP rows of supplementary gate scan signals are generated based on the generated P rows of gate scan signals to supplement the M rows of gate scan signals. For example, the physical resolution of the display panel is 1920×1200, that is, the number of rows of pixel units contained in the display panel is M=1200. And the image resolution of the image to be displayed is 1440×900, that is, the number of rows of display data is P=900. In this case, 900 rows of gate scan signals are first generated based on 900 rows of pixel data, and then 300 rows of supplementary gate scan signals are generated based on the 900 rows of gate scan signals to supplement the 1200 rows of gate scan signals. For example, at least some rows in the MP rows of supplementary gate scan signals can be interspersed between the P rows of gate scan signals, that is, at least one row of supplementary gate scan signals can be interspersed between two adjacent rows in the P rows of gate scan signals. In the MP row supplementary gate scan signal, some rows can also be located on both sides of the P row gate scan signal. For example, in one approach, supplementary gate scan signals can be generated between only some rows in the P row gate scan signal; in another approach, supplementary gate scan signals can be generated between every two adjacent rows in the P row gate scan signal; in yet another approach, supplementary gate scan signals can be generated on one or both sides of the P row gate scan signal; or a combination of the above three approaches can be used.

[0080] The signal processing method of this disclosure generates a gate scan signal corresponding to the number of rows of display data and a supplementary gate scan signal based on the gate scan signal, thereby expanding the total number of rows of the gate scan signal to be the same as the number of rows of pixel units in the display panel. Based on this method, even when the vertical resolution of the image to be displayed is less than the vertical resolution of the display panel, all rows of pixel units in the display panel can be displayed, achieving an expansion of the vertical resolution and improving the display effect.

[0081] For example, the enable period in the timing of each row of supplementary gate scan signals overlaps with the enable period in the timing of at least one row of gate scan signals in the P rows of gate scan signals. For example, the enable period of each row of supplementary gate scan signals may overlap with the enable period of the nearest row of gate scan signals in the P rows of gate scan signals.

[0082] Figure 6 This is a timing diagram of the gate scan signal provided in at least one embodiment of the present disclosure. Figure 6As shown, for example, the P-row gate scan signal includes two adjacent row gate scan signals GL1' and GL2'. For instance, the on-level of GL1' and GL2' is high, and their on-times are T10 and T20, respectively. During these on-times, the gate scan signal can drive the switching devices of the corresponding row's pixel units to be in the on state. For example, a supplementary gate scan signal GL2 (i.e., B=1) is generated between GL1' and GL2'. The on-time of the supplementary gate scan signal GL2 overlaps with the on-time of at least one of GL1 and GL3. For ease of description, after the gate scan signal is supplemented, the row numbers are adjusted (e.g., renumbered sequentially), and GL1' and GL2' can be considered as the adjusted GL1 and GL3.

[0083] For example, during the display process, because M rows of gate scan signals are generated, M rows of pixel units can be opened row by row. While the P rows of gate scan signals drive the corresponding P rows of pixel units (i.e., P row sub-pixels) to open, the source driver sends the corresponding data signal to the display panel, causing the P rows of pixel units to be displayed. During this process, because the opening periods of the MP row supplementary gate scan signals and the P row gate scan signals overlap, during the time period when the P row gate scan signals drive the corresponding P row of pixel units to open, the MP row supplementary gate scan signals will drive the remaining MP row of pixel units (i.e., MP row sub-pixels) to open for a period of time. Therefore, data signals are also written into these MP row of pixel units, causing them to be displayed. Thus, after scanning all M rows of pixel units row by row, all M rows of pixel units can be displayed.

[0084] For example, the P-row gate scan signal includes the adjacent i-th row gate scan signal and the (i+1)-th row gate scan signal. Taking the i-th row gate scan signal and the (i+1)-th row gate scan signal as an example, step S230 includes: generating a B-row supplementary gate scan signal located between the i-th row gate scan signal and the (i+1)-th row gate scan signal based on the timing of the i-th row gate scan signal and the (i+1)-th row gate scan signal; the rising edges of the B-row supplementary gate scan signal are all located between the rising edges of the i-th row gate scan signal and the (i+1)-th row gate scan signal in timing, and the falling edges of the B-row supplementary gate scan signal are all located between the falling edges of the i-th row gate scan signal and the (i+1)-th row gate scan signal in timing, where i is a positive integer less than P, and B is a positive integer less than or equal to MP.

[0085] It should be noted that the i-th row and i+1-th row refer to signal rows, i.e., gate scan signal rows, which are different from the physical pixel rows of the display panel. The gate scan signal of the i-th row can also be called the i-th gate scan signal row, and the gate scan signal of the i+1-th row can also be called the i+1-th gate scan signal row. Similarly, the "rows" in P-row, M-row, and B-row all refer to gate scan signal rows. The gate scan signal of P-row can also be called P gate scan signal rows, the gate scan signal of M-row can also be called M gate scan signal rows, and the supplementary gate scan signal of B-row can also be called B supplementary gate scan signals.

[0086] For example, in some embodiments, B is less than or equal to 4, meaning that the number of supplementary gate scan signal lines generated between any two adjacent gate scan signal lines in the P-row gate scan signal is less than or equal to 4. Based on this approach, for display panels with a resolution of 4K or 8K, no obvious image abnormalities will occur to the human eye during image display based on the supplementary gate scan signals, achieving a good visual effect.

[0087] For example, such as Figure 6 As shown, the gate scan signal for the i-th row is, for example, GL1, and the gate scan signal for the (i+1)-th row is, for example, GL3. In terms of timing, the rising edge of the supplementary gate scan signal GL2, generated between GL1 and GL3, is located between the rising edges of GL1 and GL3, and the falling edge of GL2 is located between the rising edges of GL1 and GL3. That is, the on-time of GL2 is located between the on-times of GL1 and GL3 on either side of it. During the latter half of time T11 when the first row of pixel units corresponding to GL1 is in the on-state, the second row of pixel units corresponding to GL2 is also in the on-state. Therefore, during time T11, the display data corresponding to the first row of pixel units is also written to the second row of pixel units, displaying the brightness characteristics corresponding to the first row of pixel units. Furthermore, during the first half of time T21 when the third row of pixel units corresponding to GL3 is in the on-state, the second row of pixel units corresponding to GL2 is also in the on-state. Therefore, during this time T21, the display data corresponding to the third row of pixel units is also written to the second row of pixel units, displaying the brightness characteristics corresponding to the third row of pixel units. Therefore, the second row of pixel units corresponding to GL2 combines the brightness characteristics of the first row of pixel units and the third row of pixel units, which can make the second row of pixel units a color transition between the first row of pixel units and the third row of pixel units.

[0088] For example, the rising edges of the gate scan signal in row i, the supplementary gate scan signal in row B, and the gate scan signal in row i+1 are sequentially delayed in timing. Similarly, the falling edges of the gate scan signal in row i, the supplementary gate scan signal in row B, and the gate scan signal in row i+1 are sequentially delayed in timing. For instance, the rising edges of GL1, GL2, and GL3 are sequentially delayed; and the falling edges of GL1, GL2, and GL3 are sequentially delayed. This approach allows for a more natural transition and ensures uniform pixel color transition.

[0089] For example, in some embodiments, the phase of the i-th row gate scan signal and the phase of the (i+1)-th row gate scan signal can be interpolated to obtain the phase of the B-row supplementary gate scan signal. For example, the phase of GL2 can be obtained by interpolating the phases of GL1 and GL3, such that the on-time of GL2 is located in the middle of the on-times of GL1 and GL3, with time period T11 being half of T10 and time period T21 being half of T20. This makes the transition between the first row of pixel units, the second row of pixel units, and the third row of pixel units more natural. For example, the above description only takes the generation of one supplementary gate scan signal between the i-th row gate scan signal and the (i+1)-th row gate scan signal as an example. However, this disclosure is not limited to this. When multiple rows of supplementary gate scan signals are formed between the i-th row gate scan signal and the (i+1)-th row gate scan signal, the phase of the supplementary gate scan signal can also be obtained by interpolation.

[0090] For example, the time difference between the rising and falling edges of each row of supplementary gate scan signals in row B is the same as the time difference between the rising and falling edges of the i-th row of gate scan signals. For example, the time difference T10 between the rising and falling edges of GL1, the time difference T11+T21 between the rising and falling edges of GL2, and the time difference T20 between the rising and falling edges of GL3 are all the same.

[0091] Figure 7 This is a schematic diagram of a display process provided for at least one embodiment of the present disclosure. Figure 8 This is a schematic diagram illustrating another display process provided for at least one embodiment of the present disclosure. Figure 7 The diagram shows the case where the vertical resolution M of the display panel is the same as the vertical resolution P of the display data of the image to be displayed. Figure 8 This refers to the case where the vertical resolution M of the display panel is twice the vertical resolution P of the display data of the image to be displayed. The following is combined with... Figure 7 and Figure 8 The embodiments of this disclosure will be described in further detail.

[0092] like Figure 7As shown, when M=P, the P rows of gate scan signals can be used to drive the M rows of pixel units. For example, GL1' to GLP' are the P rows of gate scan signals generated based on the P rows of display data, and GL1 to GLM are the gate scan signals output by the timing controller to the display panel. Since M=P, the multiple rows of gate scan signals generated based on the display data can be output one-to-one. Analog data signals 1 to M are used to write to each row of pixel units, representing the brightness characteristics (e.g., grayscale) displayed by each row of data units. For example, the first row of pixel units corresponds to analog data signal 1. During the time period when the first row of gate scan signal GL1 opens the first row of pixel units, analog data signal 1 is written to the first row of pixel units, giving the first row of pixel units brightness characteristic 1. Similarly, during the process of GL2 to GLM opening the second row of pixel units to the Mth row of pixel units row by row, analog data signals 2 to M are written to the second row of pixel units to the Mth row of pixel units row by row, giving the second row of pixel units to the Mth row of pixel units brightness characteristics 2 to M, respectively.

[0093] For example, when M = A * P, step S230 includes: generating A-1 rows of supplementary gate scan signals between every two adjacent rows of gate scan signals in the P rows of gate scan signals; generating A-1 rows of gate scan signals on at least one side of the P rows of gate scan signals, where A is an integer greater than 1. For example, if the number of rows M of pixel units is twice the number of rows P of display data, then a supplementary gate scan signal is generated between every two adjacent rows of the P rows of gate scan signals, and a supplementary gate scan signal is generated on one side of the P rows of gate scan signals, for example, a supplementary gate scan signal row is generated on the upper or lower side. For example, the supplementary gate scan signals can be generated using the interpolation operation method described above.

[0094] like Figure 8 As shown, P = M / 2, GL1' to GL(M / 2)' are the M / 2 row gate scan signals generated based on the M / 2 row display data, and GL1 to GLM are the gate scan signals output by the timing controller to the display panel. GL1 to GLM includes GL1' to GL(M / 2)' and supplementary gate scan signals generated based on GL1' to GL(M / 2)'. For example, GL1' to GL(M / 2)' can be used as odd-numbered rows GL1, GL3, GL5, ..., GL(M-1) in the output signal, and then supplementary gate scan signals GL2, GL4, GL6, ..., GL(M-2) are generated between every two adjacent odd-numbered rows for the middle even-numbered rows, and a supplementary gate scan signal GLM is generated for the last even-numbered row.

[0095] For example, if the number of rows M of the pixel unit is 3 times the number of rows P of the display data, then two supplementary gate scan signal rows are generated between each two adjacent rows of the P row gate scan signal, and two supplementary gate scan signal rows are generated on one side (upper side or lower side) of the P row gate scan signal, or one supplementary gate scan signal row can be generated on each side of the P row gate scan signal.

[0096] For example, the display device also includes N data signal lines connected to N columns of pixel units respectively. Figure 8 As shown, P rows of analog data signals can be generated based on P rows of pixel data. Analog data signals 1 to P are used to write pixel units in rows 1 to M. For ease of description, analog data signals 1 to P are arranged in the row direction in the figure, but this does not mean that analog data signals 1 to P are located in one row; analog data signals 1 to P correspond to pixel units in different rows.

[0097] For example, P rows of analog data signals include the i-th row of analog data signals (e.g., the first row of analog data signals), and the i-th row of analog data signals includes Q analog data signals (each row of analog data signals can include multiple signals to correspond to multiple columns respectively). Figure 8 In the example shown, the first row of analog signals contains multiple analog data signals, all of which are analog data signal 1. From the time the data write switch of the corresponding row of pixel units is turned on using the gate scan signal of the i-th row until the data write switch of the corresponding row of pixel units is turned on using the gate scan signal of the (i+1)-th row, the Q analog data signals of the i-th row are input to Q of the N data signal lines. For example, the Q signals of the first row of analog data signals are input to the Q pixel units in the first row, where Q is a positive integer less than or equal to N.

[0098] For example, each analog data signal includes S sub-analog data signals, and Q analog data signals include Q*S sub-analog data signals. These Q*S sub-analog data signals can be input into the Q*S sub-data signal lines of the N*S sub-data signal lines. For example, the Q pixel units in the first row include Q*S sub-pixels. Similarly, the Q signals in the first row of analog data signals also include Q*S sub-signals. Therefore, the Q*S sub-signals in the first row of analog data signals can be written into the Q*S sub-pixels of the first row.

[0099] For example, such as Figure 8As shown, during the time period when the first row of pixel units is turned on by the first row of gate scan signal GL1, analog data signal 1 is written to the first row of pixel units, giving them brightness feature 1. Furthermore, during the latter half of the time period when the first row of pixel units is turned on, the second row of pixel units is also turned on, so analog data signal 1 can also be written to the second row of pixel units. During the time period when the third row of pixel units is turned on by the third row of gate scan signal GL3, analog data signal 2 is written to the third row of pixel units, giving them brightness feature 1. Furthermore, during the first half of the time period when the third row of pixel units is turned on, the second row of pixel units is also turned on, so analog data signal 2 can also be written to the second row of pixel units. Therefore, the second row of pixel units can be displayed as an alternation of brightness feature 1 and brightness feature 2, exhibiting a uniform transition.

[0100] The analog data signals corresponding to the odd-numbered rows of the display panel are the data output by the source driver IC for each row. The analog data signals corresponding to the even-numbered rows (except for the Mth row) are the superposition of the data from the rows above and below for a certain period of time. That is, the actual charging process of the pixel unit in this row is to first charge the pixel data of the previous row for a period of time, and then charge the pixel data of the next row for a period of time. Therefore, the display shows a transition between the pixel data of the upper and lower rows, and the display effect is as follows. Figure 9 As shown. Furthermore, the actual charging time for each row of pixel units is the time of two rows, thus improving the charging rate and reducing image quality defects caused by insufficient charging. The analog data signal corresponding to the Mth row is the analog data signal of the (M-1)th row for a certain period of time, displayed as approximately the (M-1)th row. Vertical resolution expansion is achieved through doubling the interpolation of the grid line signals.

[0101] Figure 9 This is a schematic diagram illustrating a grayscale variation provided for at least one embodiment of this disclosure. For example... Figure 9As shown, the example above, which uses P rows of gate scan signals (e.g., GL1' to GL8') as odd-numbered row gate scan signals (e.g., GL1, GL3, ..., GL15) to generate even-numbered row supplementary gate scan signals (e.g., GL2, GL4, ..., GL16), is repeated. The left column of grayscale represents, for example, the brightness characteristics of the 8 rows of pixel units corresponding to GL1' to GL8' before the gate scan signals are expanded, and the right column of grayscale represents, for example, the brightness characteristics of the 16 rows of pixel units corresponding to GL1 to GL16 after the gate scan signals are expanded. The phase of the even-numbered row gate scan signals is the interpolation of the phases of the two adjacent odd-numbered row gate scan signals, ensuring that the grayscale of the even-numbered row pixel units transitions to the grayscale of the adjacent odd-numbered row pixel units without causing color confusion. For example, the phase of GL2 is the interpolation of the phases of GL1' (i.e., GL1) and GL2' (i.e., GL3), and the grayscale of the row of pixel units corresponding to GL2 is the interpolation of the grayscale of the two rows of pixel units above and below, thus creating a natural and uniform transition. The same principle applies to other rows, resulting in a better overall display effect after expansion.

[0102] Figure 10 This is a schematic diagram illustrating another display process provided for at least one embodiment of the present disclosure. For example... Figure 10 As shown, P = M / 2, GL1' to GL(M / 2)' can be used as even-numbered rows GL2, GL4, GL6, ..., GLM in the output signal, respectively. A supplementary gate scan signal GL1 is generated in the first odd-numbered row, and supplementary gate scan signals GL3, GL5, ..., GL(M-1) are generated in the middle odd-numbered row between every two adjacent even-numbered rows.

[0103] For example, the above Figure 8 and Figure 10 The description is based on the example of A-1 equal to 1. In other embodiments, if A-1 is greater than 1, A-1 is, for example, 2. In addition to generating two rows of supplementary gate scan signals between each pair of adjacent rows, A-1 rows of supplementary gate scan signals can also be generated on both sides of the P row gate scan signal, for example, one row of supplementary gate scan signals can be generated on each side.

[0104] For example, the above describes how to handle a situation where the vertical resolution of the image to be displayed is less than the vertical resolution of the display panel. The following describes how to handle a situation where the horizontal resolution of the image to be displayed is less than the horizontal resolution of the display panel.

[0105] For example, when the number of columns Q of the displayed data is less than the number of columns N of the pixel units, a data supplementation operation is performed. This operation includes: generating NQ columns of supplementary pixel data based on the Q columns of pixel data; the Q columns of pixel data and the NQ columns of supplementary pixel data forming N columns of pixel data; generating N columns of analog data signals based on the formed N columns of pixel data; and inputting the N columns of analog data signals into the N columns of pixel units respectively. This method can supplement the data signals, ensuring that each column of pixel units has a data signal written to it, thus improving horizontal resolution. In some of the following embodiments, pixel signal, data signal, and pixel data signal all refer to the signal of pixel data.

[0106] For example, each pixel unit includes S sub-pixel units arranged along the row direction. Each pixel data can also be understood as a set of S sub-pixel data. The process of writing pixel data into a pixel unit can be understood as writing S sub-pixel data into S sub-pixels. In the process of generating supplementary pixel data, interpolation operations can also be performed on the S sub-pixel data contained in two adjacent columns of pixel data to obtain the S sub-pixel data of the supplementary pixel data.

[0107] For example, at least some columns of the supplementary pixel data in the NQ columns can be interspersed between the pixel data in the Q columns; that is, at least one column of supplementary pixel data can be interspersed between any two adjacent columns of the pixel data in the Q columns. Some columns of the supplementary pixel data in the NQ columns can also be located on either side of the pixel data in the Q columns. For example, in one approach, supplementary pixel data can be generated between only some columns of the pixel data in the Q columns; in another approach, supplementary pixel data can be generated between every two adjacent columns of the pixel data in the Q columns; in yet another approach, supplementary pixel data can be generated on one or both sides of the pixel data in the Q columns; or a combination of the above three approaches may be used.

[0108] Data supplementation operations can be performed by the source driver, for example. Figure 11 This is a schematic diagram of a source driver provided for at least one embodiment of the present disclosure. Figure 11As shown, the source driver includes a serial-to-parallel conversion module 141, a buffer module 142, a power amplifier module 143, a digital-to-analog conversion module 144, an analog voltage module 145, and a power amplifier module 146. For example, the serial-to-parallel conversion module 141 converts the serial digital data signal sent by the timing control board into a parallel digital data signal and sends it to the buffer module 142. The buffer module 142 stores the parallel digital data signal sent by the serial-to-parallel converter and outputs it to the resolution conversion module 143, with each sub-pixel data corresponding to one output channel. The resolution conversion module 143 is located between the buffer module 142 and the digital-to-analog conversion module 144. Its function is to adjust the ratio of the number of input and output signals, for example, generating supplementary sub-pixel data based on existing sub-pixel data. The conversion is completed before the signal enters the digital-to-analog conversion module 144. The resolution conversion module 143 includes, for example, multiple arithmetic modules (arithmetic units) and related connection traces. The resolution conversion module 143 sends the supplemented pixel data to the digital-to-analog conversion module 144. The signal sent from the resolution conversion module 143 to the digital-to-analog conversion module 144 is a digital data signal. The digital-to-analog conversion module 144 is responsible for converting the digital data signal into an analog data signal by combining it with the analog voltage sent by the analog voltage module, and then outputting the analog data signal to the power amplifier module 146. The source driver may include multiple digital-to-analog conversion modules, with each sub-pixel data corresponding to one digital-to-analog conversion module. Its input and output channels correspond one-to-one with the output channel of the buffer module and the input channel of the power amplifier module, respectively.

[0109] For example, the power amplifier module 146 is responsible for amplifying the output capability of each channel, and its output channels are connected one by one to the data signal lines of the display panel. The polarity of the analog data signal output by the digital-to-analog converter module 144 is controlled by a polarity control signal (i.e., the polarity control signal shown in the figure). For example, for a certain frame of the image to be displayed, a polarity control signal is provided so that the output voltage of the odd-numbered channels of the digital-to-analog converter module is positive and the output voltage of the even-numbered channels is negative. Then, the odd-numbered columns of sub-pixels on the display panel are driven by positive line voltage and the even-numbered columns are driven by negative line voltage. In the next frame, the positive and negative polarity of the odd and even columns is switched.

[0110] For example, the Q column of pixel data includes adjacent j-th column and (j+1)-th column pixel data. Interpolation can be performed on the j-th column and (j+1)-th column pixel data to generate D columns of supplementary pixel data located between the j-th column and (j+1)-th column pixel data, where j is a positive integer less than Q and D is a positive integer less than or equal to NQ.

[0111] Figure 12 This is a schematic diagram of the input and output signals of a resolution conversion module provided in at least one embodiment of this disclosure. Figure 12As shown, for example, the pixel data in column j and the pixel data in column j+1 are, for example, the first column of pixel data (e.g., represented by identifier P_1') and the second column of pixel data (e.g., represented by identifier P_2') in column Q, respectively. An interpolation operation is performed between P_1' and P_2' to form a supplementary pixel data column (e.g., represented by identifier P_2). After readjusting the column numbers, P_1' becomes, for example, P_1, and P_2' becomes, for example, P_3. The supplementary pixel data column P_2 is located between P_1 and P_3. Since the pixel data of P_2 is obtained by interpolation of P_1 and P_3, the brightness characteristic of the second column of pixel units corresponding to P_2 is a transition between the adjacent first and third column of pixel units, making the image transition more natural.

[0112] It should be noted that the j-th and (j+1)-th columns refer to signal columns, i.e., pixel data signal columns, which are different from the physical pixel columns of the display panel. The pixel data in the j-th column can also be called the j-th pixel data signal column (or the j-th pixel data column), and the pixel data in the (j+1)-th column can also be called the (j+1)-th pixel data signal column (or the (j+1)-th pixel data column). Similarly, the "columns" in columns Q, N, and D are all pixel data signal columns. The pixel data in column Q can also be called the Q-th pixel data column, the pixel data in column N can also be called the N-th pixel data column, and the supplementary pixel data in column D can also be called the D-th supplementary pixel data column.

[0113] For example, in some embodiments, D is less than or equal to 4, meaning that the number of supplementary pixel data columns generated between any two adjacent pixel data columns in column Q is less than or equal to 4. Based on this approach, for display panels with a resolution of 4K or 8K, no obvious image abnormalities will occur to the human eye during image display based on the supplemented pixel data, achieving a good visual effect.

[0114] For example, when N = C * Q (i.e., the horizontal resolution of the display panel is an integer multiple of the horizontal resolution of the image to be displayed), C-1 columns of supplementary pixel data can be generated between every two adjacent columns of pixel data in column Q, and C-1 columns of supplementary pixel data can be generated on one or both sides of column Q to make up N columns of pixel data, where C is an integer greater than 1. For example, if the number of columns N of pixel units is twice the number of columns Q of display data, then one column of supplementary pixel data can be generated between every two adjacent columns of pixel data in column Q, and one column of supplementary pixel data can be generated on one side (e.g., the left or right side) of column Q.

[0115] like Figure 12As shown, taking N=2Q as an example, P_1', P_2', ..., P_3Y' represent the pixel data of column Q, respectively. ln1, ln2, and ln3 contained in P_1' represent the three sub-pixel data contained in P_1', and the same applies to other pixel data. P_1, P_2, ..., P_6Y represent the supplemented N columns of pixel data, serving as the output signal of the resolution conversion module. For example, P_1' to P_3Y' can be used as the odd-numbered columns P_1, P_3, P_5, ..., P_(6Y-1) in the output signal, respectively. Supplementary data signals P_2, P_4, P_6, ..., P_(6Y-2) are generated between every two adjacent odd-numbered columns, and supplementary data signal P_6Y can be generated in the last even-numbered column.

[0116] For example, if the number of columns N of the pixel unit is three times the number of columns Q of the display data, then two supplementary pixel data columns are generated between every two adjacent columns of the Q column of pixel data, and two supplementary pixel data columns are generated on one side (left or right) of the Q column of pixel data, or one supplementary pixel data column can be generated on each side of the Q column of pixel data.

[0117] Figure 13 This is a schematic diagram of a resolution conversion module provided for at least one embodiment of this disclosure. Figure 13 As shown, the resolution conversion module includes multiple arithmetic units. These units can perform interpolation operations. Each column of pixel signal at the input end can be used sequentially as the odd-numbered column at the output end. The even-numbered column at the output end is obtained by processing the pixel data of two adjacent odd-numbered columns through the arithmetic units. The last even-numbered column of pixel data can be copied from the preceding odd-numbered column of pixel data. Taking P_1 to P_3 as an example, during the generation of P_2, the sub-pixel data of the corresponding color sub-pixels in P_1 to P_3 can be interpolated to obtain the sub-pixel data of the corresponding color sub-pixels in P_2. For example, ln1, ln2, and ln3 represent the sub-pixel data of pixel R, pixel G, and pixel B, respectively; ln4, ln5, and ln6 represent the sub-pixel data of pixel R, pixel G, and pixel B, respectively. Interpolation is performed on ln1 and ln4 to obtain the sub-pixel data O_4 of the R sub-pixel in P_2; interpolation is performed on ln2 and ln5 to obtain the sub-pixel data O_5 of the G sub-pixel in P_2; and interpolation is performed on ln3 and ln6 to obtain the sub-pixel data O_6 of the B sub-pixel in P_2. The arithmetic unit could, for example, be a mean arithmetic unit.

[0118] Figure 14 This is a schematic diagram illustrating a grayscale variation provided for at least one embodiment of this disclosure. For example... Figure 14As shown, the example above uses Q column pixel data (e.g., P_1' to P_6') as odd-numbered column pixel data signals (e.g., P_1, P_3, ..., P_11) to generate even-numbered column supplementary pixel data signals (e.g., P_2, P_4, ..., GL12). The upper row of grayscale represents, for example, the brightness characteristics of the 6 pixel units corresponding to P_1' to P_6' before pixel data expansion, and the lower row of grayscale represents, for example, the brightness characteristics of the 12 pixel units corresponding to P_1 to P_12 after pixel data expansion. The values ​​of the even-numbered column pixel data are interpolated (e.g., the mean) between two adjacent odd-numbered column pixel data, ensuring that the grayscale of the even-numbered column pixel units transitions to the grayscale of the adjacent odd-numbered column pixel units, preventing color confusion and resulting in a better display effect for the expanded screen.

[0119] Figure 15 This is a schematic diagram of the input and output signals of another resolution conversion module provided in at least one embodiment of this disclosure. Figure 15 As shown, taking N=2Q as an example, P_1'~P_3Y' can be used as even-numbered columns P_2, P_4, P_6, ..., P_6Y in the output signal, respectively. Supplementary pixel data is generated in the first column P_1. The first column P_1 can copy the pixel data of the second column P_2, and supplementary data signals P_1, P_3, P_5, ..., P_(6Y-1) are generated between every two adjacent even-numbered columns.

[0120] Figure 16 This is a schematic diagram of input pixel data and output pixel data in another source driver provided in at least one embodiment of the present disclosure. (See diagram below.) Figure 16 As shown, for example, when Q equals N, Q columns of analog data signals can be generated based on the Q columns of pixel data, and these Q columns of analog data signals are used as inputs to the N columns of pixel units. In this case, no interpolation calculation is required.

[0121] Figure 17 This is a schematic diagram of another timing controller provided for at least one embodiment of the present disclosure. (See diagram for example.) Figure 17 As shown, for example, the timing controller may also include a mode control module. The mode control module is configured to receive mode instructions and, based on the mode instructions, send control signals to the gate signal generation module and / or the source driver chip to control whether the gate signal generation module performs a gate signal supplementation operation and / or whether the source driver chip performs a data supplementation operation. The mode instructions can be obtained by automatically detecting the resolution of the image to be displayed and comparing it with the physical resolution of the display panel, or by user input.

[0122] Figure 18 This is a schematic diagram of another source driver chip provided in at least one embodiment of this disclosure. (See diagram below.)Figure 18 As shown, for example, the control signal (mode control signal) sent by the timing controller to the source driver chip can act on the resolution conversion module to control the resolution conversion module to perform or not perform data supplementation operations.

[0123] For example, a mode control module can be added to the timing control board to handle the reception and transmission of mode commands. On one hand, it can send mode switching commands to the gate line signal generation module to select whether to use the interpolation function; on the other hand, it can send mode switching commands to the source driver IC to adjust the ratio of the number of input and output signals of the source driver IC. Enabling and disabling the interpolation function can be achieved by adding a switching device at its front end.

[0124] Figure 19 This is a schematic diagram of another resolution conversion module provided for at least one embodiment of this disclosure. (See diagram below.) Figure 19 As shown, the resolution conversion module also includes multiple dual-pass switches and a mode switching module (not shown in the figure). Each dual-pass switch includes one input terminal and two output terminals. The input terminal of the dual-pass switch is connected to a buffer module to receive a series of pixel data. One output terminal is connected to at least one of the multiple digital-to-analog conversion modules, and the other output terminal is connected to at least one of the multiple arithmetic modules. The mode switching module is configured to control the dual-pass switches to output a series of pixel data to one of the two output terminals based on control signals sent by the mode control module. For example, the display device has two operating modes: a normal mode and a resolution extended mode. In the normal mode, the dual-pass switches output the signal directly to the digital-to-analog conversion module without interpolation calculation. In the resolution extended mode, the dual-pass switches output the signal to the arithmetic unit, perform interpolation calculation, and then input it to the digital-to-analog conversion module.

[0125] For example, when the display signal resolution matches the physical resolution of the display panel, the mode command is set to normal mode. In normal mode, the timing control board sends a normal mode control command to the gate signal generator, the interpolation function of the gate signal generator is disabled, and the output gate scan signal corresponds one-to-one with the gate lines of the display panel, such as... Figure 7 As shown. On the other hand, the timing control board sends a normal mode control command to the source driver IC. The input and output paths of the double-pass switch in the resolution conversion module have the same input and output numbers. The output signal does not pass through the arithmetic unit, and the arithmetic unit of the source driver IC does not function, such as... Figure 16 As shown.

[0126] For example, when the resolution of the display signal received by the timing control board does not match the physical resolution of the display panel, the mode command is to use the resolution extension mode.

[0127] For example, in some embodiments, when the vertical resolution of the display signal is half the vertical resolution of the display panel and the horizontal resolution is the same, the timing control board sends a vertical resolution extension mode control command to the gate line signal generator to initiate the interpolation operation function, such as... Figure 12 or Figure 15 As shown, the timing control board sends normal mode control commands to the source driver IC, ensuring a one-to-one correspondence between its inputs and outputs.

[0128] For example, in other embodiments, when the horizontal resolution of the display signal is half the horizontal resolution of the display panel and the vertical resolution is the same, the timing control board sends a normal mode control command to the gate line signal generator, the interpolation operation function is turned off, and the output gate line signal corresponds one-to-one with the gate line of the display panel. The timing control board sends a horizontal resolution extended mode control command to the source driver IC. At this time, the dual-pass switch in the source driver IC directs the input signal to the arithmetic unit. For example, input channels In_1, In_2, and In_3 correspond to the first three output channels O_1, O_2, and O_3. Arithmetic unit 1 outputs the interpolation results of In_1 and In_4, corresponding to output channel O_4; Arithmetic unit 2 outputs the interpolation results of In_2 and In_5, corresponding to output channel O_5; Arithmetic unit 3 outputs the interpolation results of In_3 and In_6, corresponding to output channel O_6; Selector switch 1 outputs In_4, corresponding to output channel O_7; Selector switch 2 outputs In_5, corresponding to output channel O_8; Selector switch 3 outputs In_6, corresponding to output channel O_9; and so on. The input columns are successively used as the odd columns of the output, and the even columns are the operation results of the adjacent odd columns, changing the ratio of the digital data signal received by the source driver IC to the analog data signal output.

[0129] For example, in some other embodiments, when the horizontal resolution of the display signal is half the horizontal resolution of the display panel and the vertical resolution of the display signal is also half the vertical resolution of the display panel, the timing control board sends a vertical resolution extension mode control command to the gate line signal generator, the interpolation operation function is enabled, and the ratio of the output gate line signal to the panel gate line is 1:1. The timing control board sends a horizontal resolution extension mode control command to the source driver IC, and the input to output ratio is 1:2.

[0130] Figure 20 This is a schematic diagram of an image to be displayed, provided for at least one embodiment of this disclosure. For example... Figure 20As shown, in some cases, multiple consecutive images to be displayed exhibit two brightness features that alternately appear in different columns. For example, the brightest feature 301 and the darkest feature 302 may alternately appear in different columns. Alternatively, more than two brightness features may alternately appear in different columns, such as three or four brightness features. For this type of image, if supplementary pixel data is obtained by interpolating pixel data from adjacent columns, brightness features that were not originally present in the image will appear. For example, interpolating the brightest feature 301 and the darkest feature 302 will result in a grayscale feature located between the brightest and darkest, causing image distortion. To avoid this problem, the following processing method can be used.

[0131] For example, it can be determined whether the display data of multiple consecutive frames of images to be displayed conforms to the alternating display pattern. If the display data conforms to the alternating display pattern, the Q column pixel data cycles between g pixel values, and the g pixel values ​​correspond to g kinds of brightness features (e.g., two or more brightness features). If so, divide the multiple frames of images to be displayed into multiple image groups. Each image group includes g adjacent frames of images to be displayed. Perform the following operations for each image group: If the current frame of images to be displayed is the kth frame of images to be displayed in the image group, transform the Q column pixel data of the kth frame of images to the kth pixel value among the g pixel values; perform data supplementation operation on the transformed Q column pixel data; generate analog data signals based on the (k+n*g)th column pixel data after the data supplementation operation and input them into the (k+n*g)th column pixel units respectively, so that the (k+n*g)th column pixel units are displayed as the kth brightness feature among the g brightness features. Where, when k is a positive integer greater than 1, the remaining column pixel units except the (k+n*g)th column pixel units are displayed as the brightness features corresponding to the previous frame of images to be displayed of the kth frame of images to be displayed; when k equals 1, the remaining column pixel units except the (k+n*g)th column pixel units are not displayed. n takes all integers from 0 to [Q / g-1], g is an integer greater than 1 and less than Q, and k is an integer less than or equal to g.

[0132] For example, the timing control board can be equipped with image recognition functionality to identify special display screens that have at least two brightness characteristics and are displayed in alternating columns.

[0133] like Figure 20 As shown, taking the alternation of two brightness features in each column as an example, i.e., cyclically displaying between two pixel values, such as alternating between the brightest and darkest values. Figure 21 A schematic diagram of another display device provided in at least one embodiment of this disclosure, such as... Figure 21 As shown, the timing control board outputs control signals to the source driver IC to control the opening and closing of the output channel, thereby controlling whether the corresponding column sub-pixels are displayed. Figure 22This is a schematic diagram of another resolution conversion module provided for at least one embodiment of this disclosure. (See diagram below.) Figure 22 As shown, the resolution conversion module adds a switch module, which can turn the digital-to-analog conversion function of the corresponding column on or off.

[0134] For example, if no matching display is detected, the timing control board outputs the normal image, and the output control signal controls all output channels of the source driver IC to be turned on for normal output. Interpolation can be performed when the horizontal resolution is insufficient. If the timing control board detects a special display (e.g., an image with two brightness features alternating in different columns) and the horizontal resolution is insufficient, the timing control board can split the image according to the brightness features and form a full-area image for each feature, outputting them alternately. Simultaneously, when displaying any one feature, the output control signal turns off the output channels of the source driver IC corresponding to other features. Taking the case of alternating display of two brightness features as an example... Figure 23 As shown, for frame E (E is a positive integer), the timing control board outputs the brightest (first feature) display image across the entire area to the source driver IC. This means the odd-numbered columns are the brightest, and the even-numbered columns are also the brightest. Simultaneously, it sends an output control signal to the source driver IC to disable the digital-to-analog conversion module for the even-numbered pixel columns corresponding to the darkest (second feature), i.e., 4 / 5 / 6, 10 / 11 / 12… are disabled. At this time, the odd-numbered columns display the brightest image as indicated by the input signal, while the even-numbered columns display the image from the previous frame (frame E-1), assuming it's a certain grayscale level. Figure 24 As shown, in frame E+1, the darkest (feature two) display image of the entire area is output to the source driver IC, that is, each column is the darkest. At the same time, an output control signal is sent to the source driver IC to turn off the digital-to-analog conversion module of the odd-numbered pixel column corresponding to the brightest (feature one), that is, 1 / 2 / 3, 7 / 8 / 9... are turned off. At this time, the even-numbered columns are also the darkest because the input of the odd-numbered columns is the darkest, that is, the output display is the darkest. At this time, the odd-numbered columns display the image of the previous frame, which is the brightest.

[0135] Repeat the actions in frames E and E+1, keeping the image constant. Figure 24 This means that special images can be displayed.

[0136] For example, the same principle applies to the case of alternating display of two or more brightness features. For ease of description, multiple frames of images to be displayed can be grouped according to the number of brightness features, with each group containing an equal number of images to be displayed as the number of brightness features. Taking 12 consecutive frames of images all displaying three color features (first feature, second feature, and third feature) alternating in different columns as an example, the 12 frames can be divided into 4 groups, each containing 3 frames. For the first frame in each group, this first frame is transformed to display the first feature across the entire area. After interpolation, columns 1, 4 (i.e., 1+3), 7 (i.e., 1+2*3), and 10 (i.e., 1+3*3) undergo digital-to-analog conversion so that the pixel units in these columns display the first feature. The remaining columns (2-3, 5-6, 8-9, and 11-12) display the features of the corresponding columns from the previous frame; if there is no previous frame, these columns are not displayed. For the second frame image in each group, the second frame image is transformed to display the second feature across the entire area. After interpolation, columns 2, 5 (i.e., 2+3), 8 (i.e., 2+2*3), and 11 (i.e., 2+3*3) undergo digital-to-analog conversion so that the pixel units in these columns present the second feature. The remaining columns retain the features of the corresponding columns from the previous frame, i.e., columns 1, 4, 7, and 10 still present the first feature. For the third frame image in each group, the third frame image is transformed to display the third feature across the entire area. After interpolation, columns 3, 6 (i.e., 3+3), 9 (i.e., 3+2*3), and 12 (i.e., 3+3*3) undergo digital-to-analog conversion so that the pixel units in these columns present the third feature. The remaining columns retain the features from the previous frame, i.e., columns 1, 4, 7, and 10 still present the first feature, and columns 2, 5, 8, and 11 still present the second feature. Thus, every three columns of pixel units sequentially present the first, second, and third features. For the next set of images, the same method is used to achieve a display where the first feature, the second feature, and the third feature are displayed alternately in each frame, thus realizing the display of this special image.

[0137] Based on the above methods, for images with insufficient horizontal resolution and alternating display of a specific number of brightness features, not only can the horizontal resolution be increased, but unwanted brightness features can also be avoided through interpolation, thus ensuring the image display effect.

[0138] For example, in some embodiments, when the vertical resolution of the display signal is half of the physical resolution of the display panel, vertical resolution expansion is performed: the timing control board interpolates the gate line signal, the row signal frequency is doubled, and the data line signal output remains unchanged, that is, the data time of the row before the interpolation operation corresponds to the time of the two rows after the interpolation; if there are no adjacent rows in the first or last row, the phase difference after interpolation of other rows is used to advance or delay the insertion.

[0139] For example, in some embodiments, when the horizontal resolution of the display signal is half the physical resolution of the display panel, horizontal resolution expansion is performed: the resolution conversion module of the source driver IC sequentially uses the pixel data signal of each column of the input terminal as the odd column or even column of the output, and the other half of the output is calculated from its two adjacent columns; if the first or last column of the output terminal has no two adjacent columns, then the first or last column following the input terminal data is used; the resolution conversion module is located between the buffer and the digital-to-analog conversion module, and the conversion action is completed before the signal enters the digital-to-analog conversion module; the conversion action of the resolution conversion module is performed by the corresponding sub-pixels respectively, and no conversion or calculation is performed between different sub-pixels; the arithmetic unit between adjacent columns is an analog circuit arithmetic device.

[0140] For example, in some embodiments, vertical resolution scaling and horizontal resolution scaling are two relatively independent functions that do not interfere with each other.

[0141] For example, in some embodiments, the display panel architecture matching the signal processing method of the present disclosure is as follows: the gate lines are arranged horizontally and the data lines are arranged vertically; a pixel unit contains several sub-pixels and is arranged along the gate line direction; the sub-pixels in the same column are all the same sub-pixel and have the same polarity within one frame.

[0142] For example, in some embodiments, a mode control function is provided to handle the following cases respectively: the vertical resolution of the display signal is half of the physical resolution of the display panel and the horizontal resolution is the same; the horizontal resolution of the display signal is half of the physical resolution of the display panel and the vertical resolution is the same; the vertical and horizontal resolutions of the display signal are both half of the physical resolution of the display panel; and the vertical and horizontal resolutions of the display signal are both the same as the physical resolution of the display panel.

[0143] For example, in some embodiments, the timing control board receives a mode instruction; the timing control board sends a mode instruction to the gate line signal generation module to adjust the number of output row signals; the timing control board sends a mode instruction to the source driver IC to switch the ratio of input signal to output, for example, between 1:1 and 1:2.

[0144] For example, in some embodiments, the grid line signal generation module adjusts the number of output row signals by adding a control switch before the interpolation operation function. When the vertical resolution is half of the panel, the switch is turned on to enable the interpolation operation function, and the interpolated row grid line signal is output after the operation. Otherwise, the switch is turned off, and the number of output signals remains unchanged.

[0145] For example, in some embodiments, the number of input channels and output channels of the source driver IC are the same. The channel connection method for switching the input and output signals of the source driver IC is as follows: For the first half of the input channels of the source driver IC, after connecting the switching device, they are sequentially connected to the first half of the output channels one by one; after connecting the switching device, they are sequentially connected to the odd or even columns of the output terminal one by one; and after connecting the switching device, they perform mutual operations between each other, with the output port of the arithmetic unit sequentially connected to the even or odd channels of the output terminal. For the second half of the input channels, after connecting the switching device, they are sequentially connected to the second half of the output channels one by one. The switching device is controlled by mode commands. When the horizontal resolution of the display signal is half of the display panel, the second half of the input channel is closed by the switch, and the first half of the input channel is opened by the switch, and the output is sent to the odd or even columns of the output terminal, and to the arithmetic unit. When the horizontal resolution of the display signal is the same as that of the display panel, the second half of the input channel is opened by the switch; the first half of the input channel is opened by the switch, and the output is sent to the first half of the output channel.

[0146] For example, in some embodiments, the timing control board has a screen recognition function, which can identify special screens and adjust the output graphics according to the characteristics of the special screens. It then sends corresponding output control commands to the source driver IC for time-division display, and finally superimposes the results to form the desired screen. The special screen has at least two brightness features, which are displayed alternately in columns. The timing control board splits the identified special screens according to the number of features and forms a full-area screen for each feature, which is then output alternately. When the timing control board outputs a full-area screen for a certain feature, it outputs a control signal to the source driver IC to shut down the output channels corresponding to other features. The output control signal controls the output mode of each channel of the source driver IC; it can control the on / off state of each digital-to-analog converter module or the power amplifier module channels.

[0147] The signal processing methods of some embodiments of this disclosure enable the display system to perform normal display when the vertical and / or horizontal resolution of the display signal does not match the physical resolution of the display panel (e.g., the vertical and / or horizontal resolution of the display signal is half of the physical resolution of the display panel).

[0148] The signal processing methods of some embodiments of this disclosure achieve a display effect that is close to the display effect corresponding to the physical resolution of the display panel, where the physical resolution of the display panel is greater than the resolution of the display signal.

[0149] The signal processing method of some embodiments of this disclosure can greatly reduce costs by reducing the requirements for display signal resolution, reducing the requirements for the system chip outputting the display signal, reducing the data transmission rate requirements between the system board and the timing control board, reducing the data transmission rate requirements between the timing control board and the source driver chip, and reducing the requirements for the timing control chip and the source driver chip. This makes it easier to implement and lowers costs when facing the requirements of ultra-high resolution and ultra-high refresh rate panels.

[0150] The signal processing methods of some embodiments of this disclosure can also output normally when the display signal resolution is the same as the display panel resolution, thus improving flexibility.

[0151] The signal processing methods of some embodiments disclosed herein have universal applicability to the source driver IC, thus avoiding increased usage costs.

[0152] The signal processing methods of some embodiments disclosed herein solve the problem that special screens such as vertically spaced columns cannot be displayed normally, thereby improving the display quality.

[0153] The signal processing method of some embodiments of this disclosure improves the charging rate by doubling the pixel charging time, reduces image quality problems caused by insufficient charging, and improves image quality.

[0154] This disclosure also provides a display device. For example... Figure 1 or Figure 4 As shown, the display device includes a display substrate and a timing controller. The display substrate includes M rows and N columns of pixel units arranged in an array. The timing controller includes a data receiving module and a gate signal generating module.

[0155] The data receiving module is configured to acquire display data for one frame of an image to be displayed, wherein the display data includes pixel data arranged in an array of P rows and Q columns. The gate signal generation module is configured to: generate P rows of gate scan signals corresponding to the P rows of pixel data; and perform a gate signal supplementation operation when P is less than M, wherein the gate signal supplementation operation includes: generating MP rows of supplementary gate scan signals based on the P rows of gate scan signals, wherein the P rows of gate scan signals and the MP rows of supplementary gate scan signals form M rows of gate scan signals, which are used to drive M rows of pixel units respectively; P, Q, M, and N are all positive integers.

[0156] For example, the display device further includes a source driver chip, which is connected to the M-row N-column pixel unit via multiple data signal lines extending along a second direction intersecting the first direction to provide analog data signals to the M-row N-column pixel unit. The source driver chip is configured to perform a data supplementation operation when Q is less than N. The data supplementation operation includes: generating NQ-column supplementary pixel data based on Q-column pixel data, and the Q-column pixel data and NQ-column supplementary pixel data forming N-column pixel data; generating N-column analog data signals based on the N-column pixel data; and inputting the N-column analog data signals into the N-column pixel unit respectively.

[0157] For example, the source driver chip includes a cache module, multiple arithmetic modules, and multiple digital-to-analog conversion modules. The cache module is configured to cache display data; the multiple arithmetic modules are configured to perform data supplementation operations to obtain NQ columns of supplementary pixel data; and the multiple digital-to-analog conversion modules are configured to convert the N columns of pixel data into N columns of analog data signals.

[0158] For example, the timing controller also includes a mode control module, which is configured to receive mode instructions and send control signals to the gate signal generation module and / or the source driver chip based on the mode instructions, so as to control whether the gate signal generation module performs a gate signal supplementation operation and / or control whether the source driver chip performs a data supplementation operation.

[0159] For example, the source driver chip also includes multiple dual-pass switches and a mode switching module. Each dual-pass switch includes an input terminal and two output terminals. The input terminal is connected to a buffer module for receiving a series of pixel data. One of the output terminals is connected to at least one of multiple digital-to-analog conversion modules, and the other output terminal is connected to at least one of multiple arithmetic modules. The mode switching module is configured to control the dual-pass switch to output a series of pixel data to one of the two output terminals based on the control signal sent by the mode control module.

[0160] For example, the timing controller also includes an image recognition module, which is configured to: identify whether the display data of multiple consecutive frames of images to be displayed conforms to an alternating display pattern, wherein the Q column pixel data of the display data conforming to the alternating display pattern cycles among g pixel values, and the g pixel values ​​correspond to g brightness features respectively; if so, divide the multiple frames of images to be displayed into multiple image groups, each image group including adjacent g frames of images to be displayed, and perform the following for each image group: if the current frame of images to be displayed is the kth frame of images to be displayed in the image group, transform all the Q column pixel data of the kth frame of images to be displayed into the kth pixel value among the g pixel values; and output the transformed Q column pixel data to the source driver chip;

[0161] The source driver chip is also configured to: perform a data supplementation operation on the transformed Q column pixel data; generate an analog data signal based on the k+n*g column pixel data after the data supplementation operation and input it into the k+n*g column pixel units respectively, so that the k+n*g column pixel units are displayed as the kth brightness feature among the g brightness features, wherein, when k is a positive integer greater than 1, the remaining column pixel units except the k+n*g column pixel units are displayed as the brightness features corresponding to the previous frame of the image to be displayed in the k frame; when k equals 1, the remaining column pixel units except the k+n*g column pixel units are not displayed, where n takes all integers from 0 to [Q / g-1], g is an integer greater than 1 and less than Q, and k is an integer less than or equal to g.

[0162] At least one embodiment of this disclosure provides an electronic device, including the display device provided in any embodiment of this disclosure. For example, the electronic device may include any electronic product with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0163] Figure 25 This is a schematic block diagram of another electronic device provided for some embodiments of this disclosure. For example... Figure 25 As shown, the electronic device 400 includes a processor 410 and a memory 420. The memory 420 stores non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor 410 executes the non-transitory computer-readable instructions, which, when executed by the processor 410, can perform one or more steps of the signal processing method described above. The memory 420 and the processor 410 can be interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0164] For example, processor 410 may be a central processing unit (CPU), a graphics processing unit (GPU), or other form of processing unit with data processing and / or program execution capabilities. For example, the central processing unit (CPU) may be an x86 or ARM architecture. Processor 410 may be a general-purpose processor or a special-purpose processor, capable of controlling other components in electronic device 400 to perform desired functions.

[0165] For example, memory 420 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and processor 410 may run one or more computer program modules to implement various functions of electronic device 400. Various application programs and various data, as well as various data used and / or generated by the application programs, may also be stored in the computer-readable storage medium.

[0166] It should be noted that, in the embodiments of this disclosure, the specific functions and technical effects of the electronic device 400 can be referred to the description of the signal processing method above, and will not be repeated here.

[0167] Figure 26 This is a schematic block diagram of another electronic device provided in some embodiments of the present disclosure. The electronic device 500 is, for example, suitable for implementing the signal processing method provided in the embodiments of the present disclosure. The electronic device 500 may be a terminal device, etc. It should be noted that... Figure 26 The illustrated electronic device 500 is merely an example and does not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.

[0168] like Figure 26 As shown, electronic device 500 may include a processing device (e.g., a central processing unit, a graphics processor, etc.) 510, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 520 or a program loaded from storage device 580 into random access memory (RAM) 530. RAM 530 also stores various programs and data required for the operation of electronic device 500. The processing device 510, ROM 520, and RAM 530 are interconnected via bus 540. Input / output (I / O) interface 550 is also connected to bus 540.

[0169] Typically, the following devices can be connected to I / O interface 550: input devices 560 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 570 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 580 including, for example, magnetic tapes, hard disks, etc.; and communication devices 590. Communication device 590 allows electronic device 500 to communicate wirelessly or wiredly with other electronic devices to exchange data. Although Figure 26 An electronic device 500 with various devices is shown, but it should be understood that it is not required to implement or have all of the devices shown, and the electronic device 500 may alternatively implement or have more or fewer devices.

[0170] For example, according to embodiments of this disclosure, the signal processing method described above can be implemented as a computer software program. For instance, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program including program code for performing the signal processing method described above. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 590, or installed from a storage device 580, or installed from a ROM 520. When the computer program is executed by the processing device 510, the functions defined in the signal processing method provided by embodiments of this disclosure can be implemented.

[0171] At least one embodiment of this disclosure also provides a computer-readable storage medium for storing non-transitory computer-readable instructions that, when executed by a computer, can implement the signal processing method described above.

[0172] Figure 27 This is a schematic diagram of a storage medium provided for some embodiments of this disclosure. For example... Figure 27 As shown, storage medium 600 is used to store non-transitory computer-readable instructions 610. For example, when the non-transitory computer-readable instructions 610 are executed by a computer, one or more steps in the signal processing method described above can be performed.

[0173] For example, the storage medium 600 can be used in the aforementioned electronic device 400. For example, the storage medium 600 can be... Figure 25 The memory 420 in the illustrated electronic device 400. For example, a description of the storage medium 600 can be found here. Figure 25 The corresponding description of the memory 420 in the illustrated electronic device 400 will not be repeated here.

[0174] The following points need to be explained:

[0175] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0176] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0177] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A signal processing method for a display device, the display device comprising a display substrate, the display substrate comprising M rows and N columns of pixel units arranged in an array, the signal processing method comprising: Obtain display data for a frame of an image to be displayed, wherein the display data includes pixel data arranged in an array of P rows and Q columns; A P-row gate scan signal is generated corresponding to the P-row pixel data; When P is less than M, MP row supplementary gate scan signals are generated based on the P row gate scan signals, wherein the P row gate scan signals and the MP row supplementary gate scan signals form M row gate scan signals; The M rows of pixel units are driven respectively using the M rows of gate scan signals; Where P, Q, M, and N are all positive integers. The signal processing method further includes: performing a data supplementation operation when Q is less than N, wherein the data supplementation operation includes: Based on the Q column pixel data, NQ column supplementary pixel data is generated, and the Q column pixel data and the NQ column supplementary pixel data form N column pixel data; Based on the N columns of pixel data, generate N columns of analog data signals; The N columns of analog data signals are respectively input into the N columns of pixel units.

2. The signal processing method according to claim 1, wherein, When M=A*P, based on the P-row gate scan signals, MP-row supplementary gate scan signals are generated, including: Between each two adjacent rows of gate scan signals in the P-row gate scan signals, an A-1 row of supplementary gate scan signals is generated; A-1 row gate scan signal is generated on at least one side of the P row gate scan signal; Where A is an integer greater than 1.

3. The signal processing method according to claim 1, wherein, The P-row gate scan signal includes the adjacent i-th row gate scan signal and the (i+1)-th row gate scan signal; Based on the P-row gate scan signal, an MP-row supplementary gate scan signal is generated, including: Based on the timing of the i-th row gate scan signal and the (i+1)-th row gate scan signal, a B-row supplementary gate scan signal is generated between the i-th row gate scan signal and the (i+1)-th row gate scan signal. Specifically, the rising edges of the supplementary gate scan signals for row B are all located between the rising edges of the gate scan signals for row i and row i+1, and the falling edges of the supplementary gate scan signals for row B are all located between the falling edges of the gate scan signals for row i and row i+1. Where i is a positive integer less than P, and B is a positive integer less than or equal to MP.

4. The signal processing method according to claim 3, wherein, The rising edge of the i-th row gate scan signal, the rising edge of the B-row supplementary gate scan signal, and the rising edge of the (i+1)-th row gate scan signal are sequentially delayed in timing. The falling edge of the i-th row gate scan signal, the falling edge of the B-th row supplementary gate scan signal, and the falling edge of the (i+1)-th row gate scan signal are sequentially delayed in timing.

5. The signal processing method according to claim 3, wherein, Based on the timing of the i-th row gate scan signal and the (i+1)-th row gate scan signal, a B-row supplementary gate scan signal located between the i-th row gate scan signal and the (i+1)-th row gate scan signal is generated, including: The phase of the gate scan signal in the i-th row and the phase of the gate scan signal in the (i+1)-th row are interpolated to obtain the phase of the supplementary gate scan signal in row B.

6. The signal processing method according to claim 3, wherein, The time difference between the rising and falling edges of each row of supplementary gate scan signals in the B row is the same as the time difference between the rising and falling edges of the i-th row gate scan signal.

7. The signal processing method according to claim 1, wherein, Each pixel unit includes S sub-pixels, and the S sub-pixels located in the same pixel unit are arranged along the row direction. The N column pixel unit includes N*S column sub-pixels. Subpixels located in the same column have the same polarity during the display time of a frame of image to be displayed. Where S is a positive integer.

8. The signal processing method according to claim 1, further comprising: When P equals M, the M row pixel units are driven by the P row gate scan signal respectively.

9. The signal processing method according to claim 3, wherein, The display device further includes N data signal lines respectively connected to the N columns of pixel units; The signal processing method further includes: Based on the P rows of pixel data, P rows of analog data signals are generated, wherein the P rows of analog data signals include the i-th row of analog data signals, and the i-th row of analog data signals includes Q analog data signals; From the time period from when the data write switch of the corresponding row pixel unit is turned on using the gate scan signal of the i-th row until the time period before the data write switch of the corresponding row pixel unit is turned on using the gate scan signal of the (i+1)-th row, the Q analog data signals of the i-th row analog data signal are respectively input into the Q data signal lines of the N data signal lines.

10. The signal processing method according to claim 9, wherein, Each pixel unit includes S sub-pixels, the N column pixel unit includes N*S column sub-pixels, and the N data signal lines include N*S sub-data signal lines respectively connected to the N*S column sub-pixels; Each of the analog data signals includes S sub-analog data signals, and the Q analog data signals include Q*S sub-analog data signals; The Q analog data signals of the i-th row of analog data signals are respectively input into Q of the N data signal lines, including: The Q*S sub-analog data signals are respectively input into the Q*S sub-data signal lines of the N*S sub-data signal lines.

11. The signal processing method according to claim 1, wherein, When N=C*Q, based on the Q column pixel data, NQ column supplementary pixel data is generated, including: Between every two adjacent columns of pixel data in column Q, column C-1 of supplementary pixel data is generated; A supplementary pixel data column C-1 is generated on at least one side of the Q column pixel data; Where C is an integer greater than 1.

12. The signal processing method according to claim 1, wherein, The Q column pixel data includes adjacent j-th column pixel data and j+1-th column pixel data; Based on the Q column pixel data, NQ column supplementary pixel data is generated, including: Interpolation is performed on the pixel data in column j and the pixel data in column j+1 to generate supplementary pixel data in column D located between the pixel data in column j and the pixel data in column j+1. Where j is a positive integer less than Q, and D is a positive integer less than or equal to NQ.

13. The signal processing method according to claim 1, further comprising: When Q equals N, Q columns of analog data signals are generated based on the Q columns of pixel data, and the Q columns of analog data signals are used to input the N columns of pixel units.

14. The signal processing method according to claim 12, further comprising: Determine whether the display data of multiple consecutive frames of images to be displayed conforms to an alternating display pattern, wherein the Q column pixel data of the display data conforming to the alternating display pattern cycles between g pixel values, and the g pixel values ​​correspond to g brightness features respectively; If so, divide the multi-frame images to be displayed into multiple image groups, each image group including adjacent g-frame images to be displayed, and perform the following operations for each image group: If the image to be displayed in the current frame is the kth frame image to be displayed in the image group, then all the pixel data in column Q of the kth frame image to be displayed are transformed into the kth pixel value among the g pixel values; For the transformed Q column pixel data, perform the data supplementation operation; Based on the pixel data of the (k+n*g)th column after the data supplementation operation, an analog data signal is generated and input to the (k+n*g)th column pixel unit, so that the (k+n*g)th column pixel unit is displayed as the kth brightness feature among the g brightness features. Specifically, when k is a positive integer greater than 1, the pixel units in all columns except the (k+n*g)th column are displayed as the brightness features corresponding to the previous frame of the image to be displayed in the k-th frame; when k equals 1, the pixel units in all columns except the (k+n*g)th column are not displayed. Where n takes any integer from 0 to [Q / g-1], g is an integer greater than 1 and less than Q, and k is an integer less than or equal to g.

15. A display device, comprising: The display substrate includes M rows and N columns of pixel units arranged in an array; The timing controller includes a data receiving module and a gate signal generation module; The data receiving module is configured to acquire display data of a frame of image to be displayed, wherein the display data includes pixel data arranged in an array of P rows and Q columns; The gate signal generation module is configured as follows: A P-row gate scan signal is generated corresponding to the P-row pixel data; When P is less than M, a gate signal supplementation operation is performed, wherein the gate signal supplementation operation includes: generating an MP row supplementary gate scan signal based on the P row gate scan signal, wherein the P row gate scan signal and the MP row supplementary gate scan signal form an M row gate scan signal, so as to drive the M row pixel units respectively using the M row gate scan signal; Where P, Q, M, and N are all positive integers. The gate signal generation module is further configured to perform a data supplementation operation when Q is less than N, wherein the data supplementation operation includes: Based on the Q column pixel data, NQ column supplementary pixel data is generated, and the Q column pixel data and the NQ column supplementary pixel data form N column pixel data; Based on the N columns of pixel data, generate N columns of analog data signals; The N columns of analog data signals are respectively input into the N columns of pixel units.

16. The display device according to claim 15, further comprising: The source driver chip is connected to the M row N column pixel unit via multiple data signal lines extending along a second direction intersecting the first direction, to provide analog data signals to the M row N column pixel unit. The source driver chip is configured as follows: When Q is less than N, a data supplementation operation is performed, wherein the data supplementation operation includes: generating NQ columns of supplementary pixel data based on the Q column pixel data, and the Q column pixel data and the NQ column supplementary pixel data form N columns of pixel data; Based on the N columns of pixel data, generate N columns of analog data signals; The N columns of analog data signals are respectively input into the N columns of pixel units.

17. The display device according to claim 16, wherein, The source driver chip includes: The caching module is configured to cache the displayed data. Multiple processing modules are configured to perform the data supplementation operation to obtain the supplemented pixel data of the NQ column; Multiple digital-to-analog conversion modules are configured to convert the N columns of pixel data into the N columns of analog data signals.

18. The display device according to claim 17, wherein, The timing controller further includes: The mode control module is configured to receive a mode instruction and send a control signal to the gate signal generation module and / or the source driver chip based on the mode instruction, so as to control whether the gate signal generation module performs the gate signal supplementation operation and / or control whether the source driver chip performs the data supplementation operation.

19. The display device according to claim 18, wherein, The source driver chip also includes: Multiple dual-pass switches, wherein each dual-pass switch includes an input terminal and two output terminals, the input terminal is connected to the buffer module for receiving a column of pixel data, one output terminal is connected to at least one of the multiple digital-to-analog conversion modules, and the other output terminal is connected to at least one of the multiple arithmetic modules; The mode switching module is configured to control the dual-pass switch to output the pixel data of the column to one of the two output terminals based on the control signal sent by the mode control module.

20. The display device according to claim 16, wherein, The timing controller further includes an image recognition module, which is configured as follows: The system identifies whether the display data of multiple consecutive frames of images to be displayed conforms to an alternating display pattern. The Q column pixel data of the display data that conforms to the alternating display pattern cycles between g pixel values, and the g pixel values ​​correspond to g brightness features respectively. If so, the multiple frames of images to be displayed are divided into multiple image groups, each image group including g adjacent frames of images to be displayed, and for each image group, the following is performed: if the current frame of images to be displayed is the kth frame of images to be displayed in the image group, the Q column pixel data of the kth frame of images to be displayed are all transformed into the kth pixel value among the g pixel values; the transformed Q column pixel data is output to the source driver chip; The source driver chip is further configured as follows: For the transformed Q column pixel data, perform the data supplementation operation; Based on the pixel data of the (k+n*g)th column after the data supplementation operation, an analog data signal is generated and input to the (k+n*g)th column pixel unit, so that the (k+n*g)th column pixel unit is displayed as the kth brightness feature among the g brightness features. Specifically, when k is a positive integer greater than 1, the pixel units in all columns except the (k+n*g)th column are displayed as the brightness features corresponding to the previous frame of the image to be displayed in the k-th frame; when k equals 1, the pixel units in all columns except the (k+n*g)th column are not displayed. Where n takes any integer from 0 to [Q / g-1], g is an integer greater than 1 and less than Q, and k is an integer less than or equal to g.

21. An electronic device, comprising: The display device as claimed in any one of claims 15-20.

22. An electronic device, comprising: processor; Memory, including one or more computer program modules; The one or more computer program modules are stored in the memory and configured to be executed by the processor, and the one or more computer program modules include instructions for implementing the signal processing method according to any one of claims 1-14.

23. A computer-readable storage medium storing non-transitory computer-readable instructions that, when executed by a computer, implement the signal processing method according to any one of claims 1-14.

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