Display panel and display device

Abstract

The application provides a first substrate, a second substrate, a display panel and a display device. The first substrate comprises: a first substrate; a color resistance layer arranged on the first substrate, the color resistance layer comprising a plurality of color resistance blocks; a first electrode layer arranged on the color resistance layer and the substrate, the first electrode layer comprising a plurality of first electrode patterns, and each of the plurality of first electrode patterns is arranged on each of the plurality of color resistance blocks; and a plurality of first spacers, each of which is arranged on each of the plurality of first electrode patterns, and the orthographic projection of the first spacer on the first substrate in a non-display area covers the orthographic projection of the corresponding first electrode pattern on the first substrate. The first spacer wraps the first electrode pattern, thereby avoiding short circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a first substrate, a second substrate, a display panel and a display device. BACKGROUND

[0002] Liquid Crystal Display (LCD) and other flat panel display devices have been widely applied to mobile phones, televisions, personal digital assistants, notebook computers and other consumer electronic products due to their high image quality, power saving, thin body, no radiation and other advantages, and have become the mainstream of display devices.

[0003] In order to improve the support strength of the liquid crystal display panel, a spacer is usually arranged in the display panel to increase the support height in the display panel, but this may cause pressing short circuit or corrosion short circuit problems, resulting in display defects. SUMMARY

[0004] Therefore, the present application aims to provide a first substrate, a second substrate, a display panel and a display device.

[0005] To achieve the above purpose, the present application provides a first substrate in the first aspect, having a display area and a non-display area, comprising:

[0006] a first substrate;

[0007] a color resistance layer arranged on the first substrate, the color resistance layer comprising a plurality of color resistance blocks;

[0008] a first electrode layer arranged on the color resistance layer and the first substrate, the first electrode layer comprising a plurality of first electrode patterns, each of the plurality of first electrode patterns being arranged on one of the plurality of color resistance blocks;

[0009] a plurality of first spacers, each of the plurality of first spacers being arranged on one of the plurality of first electrode patterns, the first spacer in the non-display area covering the normal projection of the corresponding first electrode pattern on the first substrate.

[0010] Optionally, the first electrode pattern covers the corresponding color resistance block, the first electrode pattern comprising a first side edge, a horizontal edge and a second side edge connected in sequence, the horizontal edge being arranged close to the first spacer, and the first spacer covering the horizontal edge in whole or in part.

[0011] Optionally, the first spacer covers the first side edge and / or the second side edge in whole or in part.

[0012] Optionally, the first spacer covers the end of the first side edge and / or the second side edge close to the first spacer.

[0013] Optionally, the first electrode layer further comprises a second electrode pattern; and the first substrate further comprises a second spacer, the second spacer being disposed on the second electrode pattern in the non-display area.

[0014] Optionally, the first spacer in the non-display area has a thickness greater than that of the second spacer, the thickness direction being perpendicular to the first substrate.

[0015] Optionally, the difference between the thickness of the first spacer and the second spacer in the non-display area is 0.4-0.6 um.

[0016] Optionally, the thickness of the second spacer is the same as that of the first spacer in the display area.

[0017] The second aspect of the present application provides a second substrate having a display area and a non-display area, comprising: a second substrate, the non-display area of the second substrate being provided with a via line changing area, the orthographic projection of the via line changing area on the second substrate at least partially overlaps with the orthographic projection of the first spacer of the first substrate on the second substrate.

[0018] Optionally, the via line changing area comprises:

[0019] a first metal layer disposed on the second substrate and comprising a first metal trace;

[0020] a first insulating layer disposed on the first metal layer;

[0021] a second metal layer disposed on the first insulating layer and comprising a second metal trace;

[0022] a second insulating layer disposed on the second metal layer;

[0023] a second electrode layer disposed on the second insulating layer, the first metal trace and the second metal trace being connected through a via hole of the second electrode layer.

[0024] Optionally, the first insulating layer is provided with a first via hole, the second insulating layer is provided with a second via hole, the second electrode layer is connected with the first metal trace through the first via hole and the second via hole, and the second insulating layer is further provided with a third via hole, the second electrode layer being connected with the second metal trace through the third via hole.

[0025] The third aspect of the present application provides a display panel, comprising: the first substrate according to any one of the first aspect, the second substrate according to any one of the second aspect, and a liquid crystal molecule layer clamped between the first substrate and the second substrate.

[0026] The fourth aspect of the present application provides a display device comprising the display panel according to the third aspect.

[0027] From the above, it can be seen that the first substrate, the second substrate, the display panel and the display device provided by the present application, the substrate of the first spacer in the non-display area is the first electrode pattern and the color resistance block, and the substrate of the first spacer in the display area is also the first electrode layer and the color resistance block, so that the support height of the display area and the non-display area is almost free of step difference, the support height matching of the display area and the peripheral non-display area is optimized, and the picture quality is improved. At the same time, the orthographic projection of the first spacer in the non-display area on the first substrate covers the orthographic projection of the corresponding first electrode pattern on the first substrate, so that the first electrode pattern is wrapped by the first spacer. In actual application, even if the distance between the first electrode pattern and the second electrode on the second substrate is too close due to the addition of the color resistance block, the wrapped first electrode pattern will not directly contact the second electrode, so that short circuit will not occur. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the present application or the related art, the following will briefly introduce the drawings needed to be used in the embodiments or the related art descriptions. Obviously, the drawings in the following description are only embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0029] Figure 1 An exemplary schematic diagram of an existing liquid crystal display panel;

[0030] Figure 2 A schematic diagram of an existing display panel with color resistance blocks arranged under the spacers in the non-display area;

[0031] Figure 3 A schematic diagram of the spacers being offset after being extruded;

[0032] Figure 4 A physical diagram of short circuit burn of a vertical alignment low cell gap product;

[0033] Figure 5 A physical diagram of no short circuit burn of a vertical alignment low cell gap product;

[0034] Figure 6 A first structure schematic diagram of the first substrate of the embodiment of the present application;

[0035] Figure 7 A second structure schematic view of the first substrate of the embodiment of the present application;

[0036] Figure 8 A third structure schematic view of the first substrate of the embodiment of the present application;

[0037] Figure 9 A fourth structure schematic view of the first substrate of the embodiment of the present application;

[0038] Figure 10 A fifth structure schematic view of the first substrate of the embodiment of the present application;

[0039] Figure 11 A sixth structure schematic view of the first substrate of the embodiment of the present application;

[0040] Figure 12 A top view of AA' in the accompanying drawings of the description; Figure 10

[0041] Figure 13 A seventh structure schematic view of the first substrate of the embodiment of the present application;

[0042] Figure 14 An eighth structure schematic view of the first substrate of the embodiment of the present application;

[0043] Figure 15 A ninth structure schematic view of the first substrate of the embodiment of the present application;

[0044] Figure 16 A tenth structure schematic view of the first substrate of the embodiment of the present application;

[0045] Figure 17 A first structure schematic view of the second substrate of the embodiment of the present application;

[0046] Figure 18 A second structure schematic view of the second substrate of the embodiment of the present application;

[0047] Figure 19 A structure schematic view of the display panel of the embodiment of the present application.

[0048] ​In the figure, 01, color filter substrate; 02, common electrode; 03, black matrix; 04, color blocking block; 05, array substrate; 06, pixel electrode; 07, metal trace switching area; 08, spacer block; 1, first substrate; 11, first substrate; 12, color resist layer; 121, color resist block; 13, first electrode layer; 131, first electrode pattern; 1311, first side edge; 1312, horizontal edge; 1313, second side edge; 132, second electrode pattern; 14, first spacer; 15, second spacer; 16, shielding layer; 2, second substrate; 21, second substrate; 22, via switching area; 221, first metal layer; 222, first insulating layer; 223, second metal layer; 224, second insulating layer; 225, second electrode layer; 23, active layer; 24, gate; 25, source; 26, drain. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0050] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0051] A liquid crystal display panel typically consists of an array substrate, a color filter substrate, and a layer of liquid crystal molecules sandwiched between them, all arranged opposite each other. By applying a driving voltage between the array substrate and the color filter substrate, the rotation of the liquid crystal molecules can be controlled, causing the light from the backlight module to be refracted to produce an image. The display area of ​​the color filter substrate has red, green, and blue blocking units to achieve color display.

[0052] See Figure 1 As shown, Figure 1For the existing liquid crystal display panel, the existing vertical alignment liquid crystal display panel, including array substrate 05 and color film substrate 01, array substrate 05 is sequentially provided with thin film transistor and pixel electrode 06 layer and the like; color film substrate 01 is provided with black shielding matrix (hereinafter referred to as "black matrix 03"), then color resistance block 04 is arranged in the pixel area formed by black matrix 03, common electrode 02 layer is continuously arranged on color resistance block 04, spacer 08 is arranged on pixel electrode 06 layer, then frame glue material is coated on the outer edge of array substrate 05 or color film substrate 01, the sealing and lamination of color film substrate 01 and array substrate 05 is carried out, at the same time, array substrate 05 and color film substrate 01 are supported by spacer 08, the space in the box is formed, and the filling of liquid crystal is facilitated.

[0053] However, since color resistance block 04 is arranged in the display area of color film substrate 01, and color resistance block 04 is not arranged in the non-display area of color film substrate 01, it leads to that the substrate of spacer 08 located in the display area of the panel is black matrix 03 plus color resistance block 04 plus common electrode 02 layer, and the substrate of spacer 08 in the peripheral non-display area is only common electrode 02 layer plus black matrix 03, so that the support height of the display area and the peripheral non-display area is not matched, and the phenomenon of uneven display brightness of the periphery is easily generated, various traces are also easily generated, and the product image quality is affected.

[0054] In the related art, as shown in Figure 2 The color resistance block 04 is arranged directly below the spacer 08 in the non-display area to increase the support height, so as to reduce the difference between the support height of the display area and the peripheral non-display area. However, since the color resistance block 04 is introduced in the non-display area, the distance between the common electrode 02 and the pixel electrode 06 is further reduced, and there are many metal wiring exchange areas 07 in the non-display area. The metal wires of different layers are connected through the pixel electrode 06 in the area to realize signal transmission between different metal wires, so the pixel electrode 06 in the area is used for conduction and signal transmission, also known as conductive electrode.

[0055] However, since there is no insulating protective layer above the pixel electrode 06, when the distance between the common electrode 02 and the pixel electrode 06 is too small, short circuit caused by the contact between the pixel electrode 06 and the common electrode 02 is easily generated, and then display failure is caused. Especially in the vertical alignment low box thickness product or long-term reliability verification, since the distance between the common electrode 02 on the color film substrate 01 side and the pixel electrode 06 on the array substrate 05 side is reduced, the electric field effect between the two is enhanced, and press short circuit or corrosion short circuit is easily generated. For example, see Figure 3Since the end of the spacer 08 close to the pixel electrode 06 is free and not fixed, after being pressed, the distance between the common electrode 02 and the pixel electrode 06 is further reduced, and the free end of the spacer 08 also slides and shifts, finally causing the common electrode 02 and the pixel electrode 06 to be easily short-circuited by pressing, affecting the product image quality.

[0056] Referring to Figure 4 , Figure 4 The actual photo of the short-circuit burn of the through hole on the array substrate 05 side (i.e. the metal trace exchange area 07) caused by the too small distance between the pixel electrode 06 and the common electrode 02 of the vertical alignment low box thickness product, Figure 5 The actual photo of the normal through hole on the array substrate 05 side, Figure 4 and Figure 5 It can be obviously seen from the comparison that the short circuit is easy to occur due to the reduced distance between the common electrode 02 on the color film substrate 01 side and the pixel electrode 06 on the array substrate 05 side, thereby affecting the product performance.

[0057] Therefore, how to increase the support height of the non-display area without causing short circuit is an urgent problem to be solved.

[0058] Based on this, the application provides a first substrate, a second substrate, a display panel and a display device, which can optimize the support height matching of the display area and the peripheral non-display area, improve the image quality, and avoid the pressing short circuit by wrapping the first electrode pattern with the first spacer.

[0059] The application will be further described in detail below in combination with specific embodiments and with reference to the drawings.

[0060] Referring to Figure 6 The application provides a first substrate 1 having a display area (i.e. AA area) and a non-display area (i.e. BB area), which comprises:

[0061] A first substrate 11;

[0062] A color resistance layer 12 is arranged on the first substrate 11, and the color resistance layer 12 comprises a plurality of color resistance blocks 121;

[0063] A first electrode layer 13 is arranged on the color resistance layer 12 and the first substrate 11, and the first electrode layer 13 comprises a plurality of first electrode patterns 131, and the plurality of first electrode patterns 131 are arranged one by one on the plurality of color resistance blocks 121;

[0064] A plurality of first spacers 14 are arranged one by one on the plurality of first electrode patterns 131, and the orthographic projection of the first spacers 14 in the non-display area on the first substrate 11 covers the orthographic projection of the corresponding first electrode pattern 131 on the first substrate 11.

[0065] Specifically, the material of the first substrate 11 can include inorganic materials, for example, the inorganic material can be glass, quartz or metal, etc., and can also include organic materials, for example, the organic material can be polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate and polyethylene naphthalate resin material, etc. The first substrate 11 can be formed by a plurality of material layers, for example, the first substrate 11 can include a plurality of base layers, and the material of the base layer can be any of the above materials. Of course, the first substrate 11 can also be provided as a single layer, which can be any of the above materials.

[0066] The first substrate 11 is provided with a shielding layer 16, and the shielding layer 16 can be made of a shielding material. Exemplarily, the shielding layer 16 can be a black shielding matrix, also known as a black matrix layer.

[0067] The color resistance layer 12 is arranged on the first substrate 11, and the color resistance layer 12 includes a plurality of color resistance blocks 121 arranged at intervals, and the color resistance blocks 121 are arranged in the display area and the non-display area of the first substrate 11.

[0068] In the display area of the first substrate 11, the first substrate 11 includes a plurality of sub-pixel regions arranged in an array, the shielding layer 16 is provided with a plurality of openings corresponding to the sub-pixel regions, and a plurality of color resistance blocks 121 are arranged in the plurality of openings. The color resistance block 121 can be a green color resistance block, a blue color resistance block or a red color resistance block, and of course can also be a color resistance block 121 of other colors, such as a white color resistance block, a yellow color resistance block, etc. For example, in each row of sub-pixel regions, the color resistance blocks 121 of three colors can be periodically arranged with a cycle of blue color resistance blocks, red color resistance blocks and green color resistance blocks. In the row direction, the color resistance blocks 121 of different colors on both sides of each shielding layer 16 respectively have an extension part extending to the center position of the shielding layer 16 in the row direction and extending to the center position of the shielding layer 16 in the row direction, forming a state similar to abutment, thereby ensuring uniform and stable arrangement of red, green and blue sub-pixels.

[0069] In the non-display area of the first substrate 11, the shielding layer 16 is also provided with a plurality of openings, and a plurality of color resist blocks 121 are arranged in the plurality of openings. The color resist blocks 121 can be green color resist blocks, blue color resist blocks, or red color resist blocks, and can also be color resist blocks 121 of other colors, such as white color resist blocks, yellow color resist blocks, etc.

[0070] In the present application, the color resist blocks 121 are arranged in the display area and the non-display area of the first substrate 11, which can reduce the difference in support height between the display area and the surrounding non-display area, and improve the image quality.

[0071] The first electrode layer 13 is arranged on the color resist layer 12 and the first substrate 11. When the first substrate 1 is a color film substrate, the first electrode layer 13 can be a common electrode layer. The first electrode layer 13 includes a plurality of first electrode patterns 131, and the plurality of first electrode patterns 131 are arranged in a spaced manner. The plurality of first electrode patterns 131 are arranged one by one on the plurality of color resist blocks 121. Corresponding to the color resist blocks 121, the plurality of first electrode patterns 131 are also arranged in the display area and the non-display area of the first substrate 11.

[0072] The plurality of first spacers 14 are arranged one by one on the plurality of first electrode patterns 131. Corresponding to the first electrode patterns 131 and the color resist blocks 121, the first spacers 14 are also arranged in the display area and the non-display area of the first substrate 11. In this way, the substrate of the first spacers 14 in the non-display area is the first electrode patterns 131 and the color resist blocks 121, and the substrate of the first spacers 14 in the display area is also the first electrode layer 13 and the color resist blocks 121. In this way, there is almost no difference in support height between the display area and the non-display area, the matching of the support height between the display area and the surrounding non-display area is optimized, and the image quality is improved.

[0073] The arrangement density of the first spacers 14 in the display area and the arrangement density of the first spacers 14 in the non-display area can be the same or different. The arrangement density refers to the density of the arrangement of the first spacers 14. In the display area, the arrangement positions of the first spacers 14 correspond to the sub-pixel areas on the first substrate 11 one by one, so the first spacers 14 are arranged relatively densely in the display area, and the distance between two adjacent first spacers 14 is relatively small. In the non-display area, the specific arrangement positions of the first spacers 14 correspond to the arrangement positions of the via exchange areas 22 on the second substrate 2 arranged correspondingly. Since the via exchange areas 22 are not strictly arranged in an array and the number is not large, the first spacers 14 are arranged relatively sparsely in the non-display area, and the distance between two adjacent first spacers 14 is relatively large.

[0074] Meanwhile, the orthographic projection of the first spacers 14 on the first substrate 11 covers the orthographic projection of the corresponding first electrode patterns 131 on the first substrate 11, so that the first spacers 14 can wrap the first electrode patterns 131, and the first electrode patterns 131 will not leak out, even if the free end of the first spacers 14 is offset due to pressing, the wrapped first electrode patterns 131 will not be in direct contact with other conductive components (such as conductive electrodes, or conductive parts of the second electrodes on the second substrate 2 opposite to the first substrate 1), and pressing short circuit will not occur.

[0075] In particular implementation, the display panel includes the first substrate 1 and the second substrate 2 opposite to each other, and in this application, the orthographic projection of the first spacers 14 on the first substrate 11 covers the orthographic projection of the corresponding first electrode patterns 131 on the first substrate 11, so that the first spacers 14 can wrap the first electrode patterns 131, and even if the first electrode patterns 131 are too close to the second electrodes on the second substrate 2 due to the increase of the color resistance blocks 121, the wrapped first electrode patterns 131 will not be in direct contact with the second electrodes, so that short circuit will not occur, and product performance is improved.

[0076] In this application, by simultaneously arranging the color resistance blocks 121, the first electrode patterns 131 and the first spacers 14 on the display area and the non-display area of the first substrate 11, the support height of the display area and the non-display area can be almost continuous, the support height matching of the display area and the surrounding non-display area is optimized, and the picture quality is improved; meanwhile, since the first spacers 14 in the non-display area wrap the corresponding first electrode patterns 131, the first electrode patterns 131 can be protected from leaking out, short circuit is avoided, and product performance is improved.

[0077] In some embodiments, referring to Figure 7 , Figure 8 and Figure 9 , the first electrode patterns 131 all cover the corresponding color resistance blocks 121, the first electrode patterns 131 include a first side edge 1311, a horizontal edge 1312 and a second side edge 1313 connected in sequence, the horizontal edge 1312 is arranged close to the first spacers 14, and the first spacers 14 all or partially cover the horizontal edge 1312.

[0078] Specifically, since the lateral edge 1312 is arranged close to the first partition 14, when the first substrate 1 and the second substrate 2 are arranged opposite to each other in a specific implementation, the lateral edge 1312 is closer to the second substrate 2 than the first side edge 1311 and the second side edge 1313, so that the lateral edge 1312 is more likely to contact the second electrode on the second substrate 2 and cause short circuit. Therefore, in the present application, the first partition 14 can cover the lateral edge 1312 entirely or partially, so as to avoid short circuit of the lateral edge 1312, and thus short circuit of the first electrode layer 13 can be avoided to a great extent. Meanwhile, the first partition 14 can not cover the first side edge 1311 and the second side edge 1313, so as to reduce the manufacturing cost.

[0079] The first partition 14 covers the lateral edge 1312 entirely or partially, i.e., the orthogonal projection of the first partition 14 on the first substrate 11 can completely coincide with the orthogonal projection of the lateral edge 1312 on the first substrate 11 (as shown in FIG. 13A), partially coincide with the orthogonal projection of the lateral edge 1312 on the first substrate 11 (as shown in FIG. 13B), or the orthogonal projection of the lateral edge 1312 on the first substrate 11 is located in the orthogonal projection of the first partition 14 on the first substrate 11 (as shown in FIG. 13C). Figure 8 Figure 9 The first partition 14 covers the lateral edge 1312 entirely or partially, i.e., the orthogonal projection of the first partition 14 on the first substrate 11 can completely coincide with the orthogonal projection of the lateral edge 1312 on the first substrate 11 (as shown in FIG. 13A), partially coincide with the orthogonal projection of the lateral edge 1312 on the first substrate 11 (as shown in FIG. 13B), or the orthogonal projection of the lateral edge 1312 on the first substrate 11 is located in the orthogonal projection of the first partition 14 on the first substrate 11 (as shown in FIG. 13C). Figure 7

[0080] As shown in FIG. 13A, when the orthogonal projection of the first partition 14 on the first substrate 11 completely coincides with the orthogonal projection of the lateral edge 1312 on the first substrate 11, the first partition 14 can completely cover the lateral edge 1312, so as to avoid contact between the lateral edge 1312 and other conductive electrodes and thus short circuit. Figure 7 As shown in FIG. 13B, when the orthogonal projection of the first partition 14 on the first substrate 11 partially coincides with the orthogonal projection of the lateral edge 1312 on the first substrate 11, the first partition 14 covers the part of the lateral edge 1312 that is more likely to cause short circuit. For example, referring to FIG. 13B, the first partition 14 covers the part of the lateral edge 1312 that is more likely to cause short circuit.

[0081] Figure 8 As shown in FIG. 13C, when the orthogonal projection of the first partition 14 on the first substrate 11 is located in the orthogonal projection of the lateral edge 1312 on the first substrate 11, the first partition 14 not only completely covers the first lateral edge 1312, but also covers the positions on both sides of the lateral edge 1312, so that all positions of the lateral edge 1312 (including the positions on both sides) are covered by the first partition 14, so that the lateral edge 1312 cannot directly contact other conductive electrodes, and thus short circuit of the lateral edge 1312 can be avoided.

[0082] As shown in FIG. 13C, when the orthogonal projection of the first partition 14 on the first substrate 11 is located in the orthogonal projection of the lateral edge 1312 on the first substrate 11, the first partition 14 not only completely covers the first lateral edge 1312, but also covers the positions on both sides of the lateral edge 1312, so that all positions of the lateral edge 1312 (including the positions on both sides) are covered by the first partition 14, so that the lateral edge 1312 cannot directly contact other conductive electrodes, and thus short circuit of the lateral edge 1312 can be avoided. Figure 9 Figure 9 ​​​​As shown, through multiple tests, it is found that the right part of the horizontal edge 1312 of the first electrode pattern 131 located in the BB area is prone to short circuit, therefore, in the embodiment, the first spacer 14 is arranged at the right part of the horizontal edge 1312 to avoid short circuit of the horizontal edge 1312.

[0083] In some embodiments, referring to Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 and Figure 14 , the first spacer 14 covers the first side edge 1311 and / or the second side edge 1313 wholly or partially.

[0084] Specifically, on the basis of the first spacer 14 covering the horizontal edge 1312 wholly or partially to reduce the probability of short circuit of the first electrode layer 13, in order to further reduce the probability of short circuit of the first electrode layer 13, or even completely avoid short circuit of the first electrode layer 13, in the present application, the first spacer 14 covers the first side edge 1311 and / or the second side edge 1313 wholly or partially.

[0085] The first spacer 14 can cover the first side edge 1311 and the second side edge 1313 wholly (as shown in Figure 10 、 Figure 11 and Figure 12 ), can cover the first side edge 1311 and the second side edge 1313 partially (as shown in Figure 13 ), can cover the first side edge 1311 or the second side edge 1313 wholly (as shown in Figure 14 ), or can cover the first side edge 1311 or the second side edge 1313 partially (as shown in Figure 15 ).

[0086] As shown in Figure 10 、 Figure 11 and Figure 12 , when the first spacer 14 covers the first side edge 1311 and the second side edge 1313 wholly, the first spacer 14 also covers the horizontal edge 1312 wholly, at this time, the whole position of the first electrode pattern 131 is wrapped by the first spacer 14, so that the whole position of the first electrode pattern 131 will not be exposed, and there will be no chance of any part of the first electrode pattern 131 directly contacting other conductive electrodes, thus the short circuit of the first electrode layer 13 can be completely avoided.

[0087] The first spacers 14 can be a cubic structure, a trapezoidal structure, an inverted trapezoidal structure, a hemispherical structure, etc., which is not limited here and is selected according to actual conditions. In this embodiment, the first spacers 14 are in an inverted trapezoidal structure, and the first spacers 14 include a first end surface and a second end surface. The first end surface is arranged close to the first substrate 11, and the orthographic projection of the second end surface on the first substrate 11 is located in the orthographic projection of the first end surface on the first substrate 11. This is beneficial to the actual manufacturing process and facilitates actual operation.

[0088] As shown in Figure 13 , when the first spacers 14 partially cover the first side edge 1311 and the second side edge 1313, the first spacers 14 can optionally cover the end of the first side edge 1311 and / or the second side edge 1313 close to the first spacers 14. This is because, for the first side edge 1311 and the second side edge 1313, the end close to the first spacers 14 is more likely to cause a short circuit than the end away from the first spacers 14. Therefore, the first spacers 14 covering the end of the first side edge 1311 and / or the second side edge 1313 close to the first spacers 14 can further prevent the first electrode pattern 131 from causing a short circuit.

[0089] When the first spacers 14 only fully or partially cover the first side edge 1311 or the second side edge 1313, the side edge covered by the first spacers 14 is the side edge of the first electrode pattern 131 that is most likely to cause a short circuit. For example, as shown in Figure 14 and Figure 15 , it has been verified through multiple tests that the second side edge 1313 of the first electrode pattern 131 is more likely to cause a short circuit than the first side edge 1311. Therefore, the first spacers 14 only fully or partially cover the first side edge 1311 to reduce the manufacturing cost of the first substrate 1 while further reducing the probability of the first electrode pattern 131 causing a short circuit.

[0090] In some embodiments, referring to Figure 16 , the first electrode layer 13 further includes a second electrode pattern 132, and the first substrate 1 further includes a second spacer 15 arranged on the second electrode pattern 132 located in the non-display area.

[0091] Specifically, the second electrode pattern 132 is the first electrode layer 13 between two adjacent first electrode patterns 131. The second electrode pattern 132 can be located in the display area or the non-display area.

[0092] Since the first spacers 14 are arranged closely in the display area, the distance between two adjacent first spacers 14 is short, so that the support strength of the display area is strong, while in the non-display area, the first spacers 14 are arranged sparsely, the distance between two adjacent first spacers 14 is long, so that the support strength of the non-display area is weak. Therefore, in order to further improve the support strength of the non-display area of the liquid crystal display panel, the second spacers 15 are arranged on the second electrode pattern 132 located in the non-display area.

[0093] Since the second spacers 15 correspond to the non-via area on the second substrate 2, short circuit caused by the contact between the second electrode pattern 132 and the second substrate 2 will not occur, therefore, the arrangement of the second spacers 15 is only for further improving the support strength on the basis of the arrangement of the first spacers 14, and the projection size of the second spacers 15 on the first substrate 11 is not limited.

[0094] Optionally, the thickness of the first spacers 14 located in the non-display area is greater than the thickness of the second spacers 15, and the thickness of the second spacers 15 is the same as the thickness of the first spacers 14 located in the display area, and the thickness direction is perpendicular to the first substrate 11. In this way, the first spacers 14 located in the display area, the first spacers 14 located in the non-display area and the second spacers 15 can be made in the same layer by using the same half tone mask process, thereby saving the manufacturing cost. The width of the first spacers 14 and the second spacers 15 is determined by the size of the light transmission area of the mask, and the height (i.e. thickness) of the first spacers 14 and the second spacers 15 is determined by the light transmission rate of the light transmission area of the mask.

[0095] Specifically, the semi-transparent part of the light transmission area of the mask can be selected to be arranged between 20% and 40% of the light transmission rate, so that the thickness difference between the first spacers 14 located in the non-display area and the second spacers 15 is 0.4-0.6 um, which can ensure that the display area and the non-display area both have good support, without obvious height difference, and is also beneficial to the actual manufacturing process and easy to operate.

[0096] Referring to Figure 17 The application also provides a second substrate 2 having a display area and a non-display area, comprising: a second substrate 21, and a via area 22 arranged in the non-display area of the second substrate 21, wherein the orthographic projection of the via area 22 on the second substrate 21 at least partially overlaps with the orthographic projection of the first spacers 14 of the first substrate 1 on the second substrate 21.

[0097] Specifically, the material of the second substrate 21 can include inorganic materials, for example, the inorganic materials can be glass, quartz or metal, etc., and can also include organic materials, for example, the organic materials can be polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate and polyethylene naphthalate, etc. resin materials. The second substrate 21 can be formed by multiple layers of materials, for example, the second substrate 21 can include multiple base layers, and the material of the base layer can be any of the above materials. Of course, the second substrate 21 can also be provided as a single layer, which can be any of the above materials.

[0098] The via line changing area 22 is an area for connecting different layers of metal traces to realize signal transmission between different metal traces. Therefore, the side of the via line changing area 22 away from the second substrate 21 is conductive, which belongs to the conductive area.

[0099] The orthographic projection of the via line changing area 22 on the second substrate 21 at least partially overlaps the orthographic projection of the first spacer 14 of the first substrate 1 on the second substrate 21, so that the first electrode pattern 131 wrapped by the first spacer 14 will not directly contact the via line changing area 22 and will not cause contact short circuit.

[0100] Specifically, the orthographic projection of the via line changing area 22 on the second substrate 21 can completely overlap or partially overlap the orthographic projection of the first spacer 14 on the second substrate 21, or the orthographic projection of the via line changing area 22 on the second substrate 21 is located in the orthographic projection of the first spacer 14 on the second substrate 21, so as to avoid short circuit of the first electrode pattern 131.

[0101] In specific implementation, the display panel includes the first substrate 1 and the second substrate 2 arranged oppositely. Since the first electrode pattern 131 is wrapped by the first spacer 14, even if the distance between the first substrate 1 and the second substrate 2 is further reduced after being pressed, and the free end of the first spacer 14 also slides and shifts, the first electrode pattern 131 will not directly contact the via line changing area 22, and thus short circuit will not occur.

[0102] In some embodiments, continuing to refer to Figure 17 , the via line changing area 22 includes:

[0103] The first metal layer 221 is arranged on the second substrate 21 and includes a first metal trace.

[0104] The first insulating layer 222 is arranged on the first metal layer 221.

[0105] The second metal layer 223 is arranged on the first insulating layer 222 and includes a second metal trace;

[0106] The second insulating layer 224 is arranged on the second metal layer 223.

[0107] The second electrode layer 225 is arranged on the second insulating layer 224, and the first metal trace and the second metal trace are connected through a via hole of the second electrode layer 225.

[0108] Specifically, when the second substrate 2 is an array substrate, the second electrode layer 225 can be a conductive electrode (the conductive electrode and the pixel electrode are made in the same layer, have the same material, and are only different in that they are located in different areas and have different functions) made in the same layer as the pixel electrode on the array substrate, or can be a conductive layer not made in the same layer as the pixel electrode.

[0109] The second electrode layer 225 is used to realize the via hole connection of the first metal trace and the second metal trace, so that the signals between the first metal trace and the second metal trace can be transmitted.

[0110] The first insulating layer 222 is provided with a first via hole, the second insulating layer 224 is provided with a second via hole, the first via hole and the second via hole are through, the second electrode layer 225 is connected with the first metal trace through the first via hole and the second via hole, and the second insulating layer 224 is further provided with a third via hole. The second electrode layer 225 is connected with the second metal trace through the third via hole. In this way, the first metal trace and the second metal trace are connected through the second electrode layer 225 to realize the signal transmission between the first metal trace and the second metal trace.

[0111] In specific implementation, the display panel includes the first substrate 1 and the second substrate 2 arranged oppositely. Since the first electrode pattern 131 is wrapped by the first spacers 14, even if the distance between the first substrate 1 and the second substrate 2 is further reduced after being pressed, and the free end of the first spacers 14 also slides and shifts, the first electrode pattern 131 will not directly contact the second electrode layer 225, and thus short circuit will not occur.

[0112] In some embodiments, referring to Figure 18The second substrate 21 is provided with a buffer layer (not shown in the figure), a source layer 23 provided on the side of the buffer layer away from the second substrate 21, the source layer 23 can include a channel portion and a conductor portion provided at both ends of the channel portion, a gate insulating layer provided on the side of the source layer 23 away from the second substrate 21, a gate electrode 24 provided on the side of the gate insulating layer, an interlayer dielectric layer provided on the side of the gate electrode 24 away from the second substrate 21, a first via provided on the interlayer dielectric layer, the first via being communicated to the conductor portion; a source electrode 25 and a drain electrode 26 provided on the side of the interlayer dielectric layer away from the second substrate 21, the source electrode 25 and the drain electrode 26 being respectively connected to the two conductor portions through the two first vias. A passivation layer is provided on the side of the source electrode 25 and the drain electrode 26 away from the substrate. The source layer 23, the gate electrode 24, the source electrode 25 and the drain electrode 26 form a thin film transistor.

[0113] A pixel electrode is provided on the side of the passivation layer away from the second substrate 21.

[0114] The gate insulating layer can be made of the same material as the first insulating layer 222 and be manufactured by the same process; the second insulating layer 224 can be made of the same material as the interlayer dielectric layer and / or the passivation layer and be manufactured by the same process; the pixel electrode can also be made of the same material as the second electrode layer 225 and be manufactured by the same process, so that the manufacturing process of the second substrate 2 can be simplified, which is beneficial to the actual manufacturing process.

[0115] Referring to Figure 19 The application further provides a display panel, which comprises the first substrate 1 according to any one of the embodiments, the second substrate 2 according to any one of the embodiments and a liquid crystal molecule layer clamped between the first substrate 1 and the second substrate 2.

[0116] Specifically, the first substrate 1 can be a color film substrate, and the first electrode layer 13 can be a common electrode layer; the second substrate 2 can be an array substrate, and the second electrode layer 225 can be a pixel electrode layer. Of course, the first substrate 1 can also be an array substrate, and the second substrate 2 can also be a color film substrate, which is not limited herein.

[0117] The display area and the non-display area of the display panel described in the present application have almost no step difference in support height, which optimizes the support height matching of the display area and the peripheral non-display area, and improves the picture quality. At the same time, since the first spacers 14 located in the non-display area wrap the corresponding first electrode pattern 131, the first electrode pattern 131 can be protected from leaking out. Therefore, even after being pressed, the distance between the first substrate 1 and the second substrate 2 is further reduced, and at the same time, the free end of the first spacer 14 also slides and shifts, and the first electrode pattern 131 will not be in direct contact with the second electrode layer 225, so as to avoid short circuit, thereby improving the product performance.

[0118] The present application also provides a display device comprising the display panel described in the above embodiments.

[0119] The display device can be a product with image display function, for example, can be: a display, a television, a billboard, a digital photo frame, a laser printer with display function, a telephone, a mobile phone, a personal digital assistant (PDA), a digital camera, a camcorder, a viewfinder, a navigator, a vehicle, a large-area wall, a household appliance, an information query device (such as a business query device of an electronic government, a bank, a hospital, a power department, a monitor, etc.).

[0120] The display device has the technical effects described in any of the above embodiments, which will not be repeated here.

[0121] It should be noted that the above describes some embodiments of the present disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in an order different than that described in the above embodiments and still achieve the desired result. In addition, the processes depicted in the figures do not necessarily require the particular order shown or sequential order to achieve the desired results. In certain implementations, multitasking and parallel processing can be advantageous or possible.

[0122] Those skilled in the art will understand that the discussion of any of the above embodiments is merely exemplary and is not intended to suggest that the scope of the present disclosure (including the claims) is limited to these examples; under the idea of the present disclosure, the above embodiments or technical features among different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of the present disclosure as described above, which are not provided in detail for the sake of brevity.

[0123] Embodiments of the present disclosure are intended to cover all such alternatives, modifications, and variations as fall within the broad scope of the appended claims. Accordingly, any one or more of the omitted, modified, equivalently replaced, improved, and the like, as long as within the spirit and principle of the embodiments of the present disclosure, should be included in the scope of protection of the present disclosure.

Claims

1. A display panel, characterized in that, include: A first substrate, a second substrate, and a liquid crystal molecule layer sandwiched between the first substrate and the second substrate are disposed opposite to each other; The first substrate has a display area and a non-display area, including: First substrate; A shielding layer is disposed on a first substrate. Within the display area of ​​the first substrate, the shielding layer has multiple openings corresponding to sub-pixel areas. A color resist layer is disposed on the first substrate. The color resist layer includes a plurality of color resist blocks, which are respectively disposed in a plurality of openings. The color resist blocks are simultaneously disposed in the display area and non-display area of ​​the first substrate. A first electrode layer is disposed on the color resist layer and the first substrate. The first electrode layer includes a plurality of first electrode patterns, which are disposed one-to-one on the plurality of color resist blocks. Multiple first spacers are disposed one-to-one on multiple first electrode patterns. The orthographic projection of the first spacer located in the non-display area on the first substrate covers the orthographic projection of the corresponding first electrode pattern on the first substrate. The first electrode pattern includes a first side, a horizontal side, and a second side connected in sequence. The horizontal side is disposed close to the first spacer. The first spacer completely covers the horizontal side. The first spacer completely or partially covers the first side and the second side. The second substrate has a display area and a non-display area, including a second substrate. The non-display area of ​​the second substrate is provided with a via switching area. The orthographic projection of the via switching area on the second substrate at least partially overlaps with the orthographic projection of the first spacer of the first substrate on the second substrate.

2. The display panel according to claim 1, characterized in that, The first electrode pattern completely covers the corresponding color resist block.

3. The display panel according to claim 1, characterized in that, The first spacer covers the first side and / or the second side near the end of the first spacer.

4. The display panel according to claim 1, characterized in that, The first electrode layer further includes a second electrode pattern; the first substrate further includes a second spacer disposed on the second electrode pattern located in the non-display area.

5. The display panel according to claim 4, characterized in that, The thickness of the first spacer located in the non-display area is greater than the thickness of the second spacer, and the thickness direction is perpendicular to the first substrate.

6. The display panel according to claim 5, characterized in that, The thickness difference between the first spacer and the second spacer located in the non-display area is 0.4~0.6um.

7. The display panel according to claim 4, characterized in that, The thickness of the second spacer is the same as the thickness of the first spacer located in the display area.

8. The display panel according to claim 1, characterized in that, The via switching area includes: A first metal layer is disposed on the second substrate, including a first metal trace; A first insulating layer is disposed on the first metal layer; A second metal layer is disposed on the first insulating layer, including a second metal trace; A second insulating layer is disposed on the second metal layer; The second electrode layer is disposed on the second insulating layer, and the first metal trace and the second metal trace are connected through vias in the second electrode layer.

9. The display panel according to claim 8, characterized in that, The first insulating layer has a first via, the second insulating layer has a second via, the second electrode layer is connected to the first metal trace through the first via and the second via, the second insulating layer also has a third via, and the second electrode layer is connected to the second metal trace through the third via.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 9.

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