A control system hardware resource optimization method and apparatus

Abstract

The application discloses a control system hardware resource optimization method and device, and the method comprises the following steps: dividing a system to be simulated into an electrical system and a control system, constructing a control system solving hardware resource optimization model with a control system solving calculation resource, storage resource and time resource weighted sum minimum as an objective function according to the topological structure of the control system and the calculation type; solving the control system solving hardware resource optimization model, and outputting a hardware resource optimization result; and downloading the hardware resource optimization result to an FPGA real-time simulator for simulation, so that the technical problems of long hardware debugging time and low efficiency caused by the manual hardware design method in the simulation preparation process of the prior art are solved.

Description

Technical Field

[0001] This application relates to the field of simulation system technology, and in particular to a method and apparatus for optimizing hardware resources of a control system. Background Technology

[0002] With the introduction of the "dual carbon" target and in line with new trends in economic and technological development, electricity has become the "main force" in the energy "battlefield," with new energy power generation serving as the "vanguard." However, the randomness and volatility of wind and solar power generation have altered the structure and operation of power systems connected in the form of renewable energy sources, posing significant challenges to the grid's adequacy, security, economy, and institutional mechanisms. The large-scale integration of renewable energy sources has resulted in power systems exhibiting a high proportion of power electronics characteristics. In this context, electromagnetic transient simulation technology provides a powerful tool for studying the dynamic characteristics and underlying mechanisms of systems, becoming a crucial research tool in the development of new power systems. Due to the large size of the power electronic converters and the complexity of the controllers, the electromagnetic transient models of renewable energy sources are typically extremely large. Electromagnetic transient models generally consist of two parts: an electrical system model and a control system model. Transient modeling of renewable energy sources primarily focuses on modeling the controller, resulting in a renewable energy source with a tens-dimensional electrical system model often having a hundreds-dimensional control system model. To meet practical engineering needs, high-precision transient real-time simulation of the fast dynamic response characteristics of high-frequency power electronic converter equipment typically requires simulation steps in the microsecond range, completing the simulation task in the shortest possible time. This necessitates high-efficiency simulation technology. Since the room for improvement in simulation algorithms is limited, and constrained by limited CPU resources and CPU frequency, practical engineering often requires heterogeneous, high-efficiency parallel computing resources such as GPUs and FPGAs to work in conjunction with a CPU-based host computer to complete the simulation task, thereby improving simulation efficiency.

[0003] Due to the large-scale control systems of renewable energy sources, and the fact that control system models typically employ sequential solution methods, the computation of renewable energy control systems generally consumes 60%-80% of computational resources, with low resource utilization efficiency. This represents an unbearable computational burden for mechanistic modeling simulations of renewable energy clusters. Given the limited parallel computing resources in engineering projects, an efficient computing hardware design approach is needed to fully improve the utilization rate of computing resources to meet the simulation speed requirements of microsecond-level simulation steps for large-scale renewable energy sources. Time-division multiplexing (TDM) is a hardware design technique that ensures efficient hardware resource utilization and is commonly used in digital communications. TDM interweaves different data at different time intervals, allowing multiple data streams that would otherwise utilize multiple hardware resources to utilize the same hardware resource at different times, thereby significantly improving hardware resource utilization efficiency. For transient simulation control systems with fewer simulation calculation types but a large computational load in parallel computing scenarios, TDM can effectively improve computational efficiency.

[0004] For large-scale simulations of renewable energy power plants, system design for highly flexible parallel computing resources is extremely complex. During simulation preparation, control system simulation design typically employs a "building block" approach, involving manual hardware design. This often requires a significant amount of time for hardware debugging to achieve the desired simulation results, especially when dealing with complex controllers such as renewable energy sources. Furthermore, manually designing time-division multiplexing for existing pipelined control system solution structures is undoubtedly more difficult. Moreover, if the number of pipeline subsystems changes, the original time-division multiplexing design can cause data flow conflicts, necessitating a complete redesign of the time-division multiplexing mechanism. Summary of the Invention

[0005] This application provides a method and apparatus for optimizing hardware resources in a control system, which addresses the technical problems of long hardware debugging time and low efficiency in the existing technology that uses manual hardware design during simulation preparation.

[0006] In view of this, the first aspect of this application provides a method for optimizing hardware resources of a control system, comprising:

[0007] The system to be simulated is divided into an electrical system and a control system. Based on the topology and computation type of the control system, a hardware resource optimization model for the control system is constructed with the objective function of minimizing the weighted sum of computational resources, storage resources and time resources for the control system solution.

[0008] Solve the hardware resource optimization model of the control system and output the hardware resource optimization results;

[0009] The hardware resource optimization results are downloaded to the FPGA real-time simulator for simulation.

[0010] Optionally, the step of constructing a hardware resource optimization model for the control system, based on the topology and computation type of the control system and with the objective function of minimizing the weighted sum of computational, storage, and time resources for solving the control system problem, includes:

[0011] Based on the topology of the control system, the number of the first intermediate node encountered on the way from the i-th computing node to the j-th computing node is defined as follows: Define the distance from the i-th computing node to the j-th computing node as D. ij The control system is defined to have performed M types of calculations, and the calculation of the m-th type of the control system has performed N calculations. m Next, define a flag indicating whether the result of the j-th computation of the m-th type of computation is used as the input of the i-th computation of the l-th type of computation.

[0012] Node R is initialized based on the dependencies and computation types of each computing node in the topology of the control system. ij Distance D ij and flags

[0013] A hardware resource optimization model for solving the control system is obtained by constructing a model with the objective function of minimizing the weighted sum of computational, storage, and time resources for solving the control system, and setting time series constraints on the computational data flow of the control system and constraints on the use of computational resources for solving the control system.

[0014] Optionally, the objective function is:

[0015] minf = w1A ctr +w2B ctr +pT p

[0016]

[0017]

[0018]

[0019]

[0020]

[0021]

[0022] In the formula, f represents the objective function, w1 and w2 are the weighted coefficients of the computational and storage resource overhead caused by the control system's solution, p is the penalty coefficient for the additional solution time overhead of the control system, and Tp This represents the additional computation time overhead of the control system. A represents the computational and storage resource overhead incurred by the control system solution. ctr B represents the computational resource overhead incurred in solving the control system. ctr This represents the storage resource overhead incurred by the control system's computation. This represents the computational resource overhead incurred by the multiplexers used in the time-division multiplexing solution of the control system. This represents the computational resource overhead caused by data buffering in the solution of the control system, and M represents the total number of computational types during the solution of the control system. This indicates that the control system solution used a total of The m-th type of computational unit This represents the computational resource overhead incurred by the computational unit used for the m-th type of computation. This represents the storage resource overhead caused by data buffering in the control system solution. A represents the storage resource overhead incurred by the computing unit used for the m-th type of computation. db,ALM B represents the computational resource overhead caused by a single data latency. db,BMB N represents the storage resource overhead caused by a single data latency. m N represents the number of times the m-th calculation type is used in the control system solution. l This indicates the number of times the l-th type of calculation is used in the control system solution. A is a flag indicating whether there is a data stream delay between the j-th computation of the m-th computation and the i-th computation of the l-th computation. ms,ini A represents the computational resource overhead of a multiplexer with zero inputs. ms,com This parameter represents the computational resource overhead of the multiplexer as the number of inputs increases. This indicates that the control system solution used a total of The first type of computational unit.

[0023] Optionally, the time-series constraints for the data stream calculated by the control system include:

[0024]

[0025]

[0026]

[0027]

[0028]

[0029]

[0030] In the formula, This represents the starting clock cycle of the i-th computation of the l-th type of computation. This is a flag indicating whether the result of the j-th computation in the m-th type of computation is used as the input to the i-th computation in the l-th type of computation. This is a flag indicating whether the result of the i-th computation in the l-th type of computation is used as the input to the k-th computation in the o-th type of computation. This indicates the end clock cycle of the j-th computation of the m-th computation, where the output result serves as the i-th computational input for the l-th computation. This represents the computation output delay for the l-th type of computation. This indicates that the input to the o-th computation is the starting clock cycle of the k-th computation output result. For the time overhead of the control system solution, T min T represents the shortest time cost of solving a control system based on its topology. p v represents the additional solution time overhead incurred by the control system solution, excluding the shortest solution time. c This represents the actual time elapsed in a single clock cycle. The delay in the data stream is represented by the output of the j-th computation of the m-th computation being used as the input of the i-th computation of the l-th computation, and C is a large number introduced to make the constraints linearize;

[0031] The constraints on the use of computational resources by the control system include:

[0032]

[0033]

[0034]

[0035]

[0036]

[0037]

[0038]

[0039] In the formula, A flag indicating whether the i-th computation of type l computation begins in clock cycle v. A flag indicating whether the i-th computation of type l ended in the v-th clock cycle. A flag indicating whether the i-th computation of type l is performed in the v-th clock cycle, n sThis indicates the number of subsystems that the control system is solving.

[0040] Optionally, the specific process for obtaining the shortest solution time cost of the control system based on its topology is as follows:

[0041] A distance matrix is ​​generated based on the distance between computing nodes in the topology of the control system, wherein the distance between two computing nodes is the time cost of obtaining the computing result of one computing node from another computing node.

[0042] Generate a routing matrix based on the topology and the number of the first intermediate node of the two computing nodes;

[0043] Determine the distance D between computation node i and computation node j. ij The sum of the distances D from computation node i to intermediate node k and from intermediate node k to computation node j ik +D kj The size of D, if ik +D kj Greater than D ij Then update D ij =D ik +D kj The updated distance matrix is ​​obtained, and the first intermediate node between computation node i and computation node j is updated to R. ij =R ik Continue until all intermediate nodes have been traversed;

[0044] Obtain the maximum distance in the final distance matrix, calculate the product of this maximum distance and the actual time elapsed in a single clock cycle, and obtain the shortest solution time T of the control system. min .

[0045] A second aspect of this application provides a control system hardware resource optimization device, comprising:

[0046] The model building unit is used to divide the system to be simulated into an electrical system and a control system. Based on the topology and computing type of the control system, it constructs a hardware resource optimization model for the control system with the objective function of minimizing the weighted sum of computing resources, storage resources and time resources for the control system solution.

[0047] The model solving unit is used to solve the hardware resource optimization model of the control system and output the hardware resource optimization results.

[0048] The simulation unit is used to download the hardware resource optimization results to the FPGA real-time simulator for simulation.

[0049] Optionally, the model building unit is specifically used for:

[0050] The system to be simulated is divided into an electrical system and a control system;

[0051] Based on the topology of the control system, the number of the first intermediate node encountered on the way from the i-th computing node to the j-th computing node is defined as follows: Define the distance from the i-th computing node to the j-th computing node as D. ij The control system is defined to have performed M types of calculations, and the calculation of the m-th type of the control system has performed N calculations. m Next, define a flag indicating whether the result of the j-th computation of the m-th type of computation is used as the input of the i-th computation of the l-th type of computation.

[0052] Node R is initialized based on the dependencies and computation types of each computing node in the topology of the control system. ij Distance D ij and flags

[0053] A hardware resource optimization model for solving the control system is obtained by constructing a model with the objective function of minimizing the weighted sum of computational, storage, and time resources for solving the control system, and setting time series constraints on the computational data flow of the control system and constraints on the use of computational resources for solving the control system.

[0054] Optionally, the objective function is:

[0055] minf = w1A ctr +w2B ctr +pT p

[0056]

[0057]

[0058]

[0059]

[0060]

[0061]

[0062] In the formula, f represents the objective function, w1 and w2 are the weighted coefficients of the computational and storage resource overhead caused by the control system's solution, p is the penalty coefficient for the additional solution time overhead of the control system, and T p This represents the additional computation time overhead of the control system. A represents the computational and storage resource overhead incurred by the control system solution. ctrB represents the computational resource overhead incurred in solving the control system. ctr This represents the storage resource overhead incurred by the control system's computation. This represents the computational resource overhead incurred by the multiplexers used in the time-division multiplexing solution of the control system. This represents the computational resource overhead caused by data buffering in the solution of the control system, and M represents the total number of computational types during the solution of the control system. This indicates that the control system solution used a total of The m-th type of computational unit This represents the computational resource overhead incurred by the computational unit used for the m-th type of computation. This represents the storage resource overhead caused by data buffering in the control system solution. A represents the storage resource overhead incurred by the computing unit used for the m-th type of computation. db,ALM B represents the computational resource overhead caused by a single data latency. db,BMB N represents the storage resource overhead caused by a single data latency. m N represents the number of times the m-th calculation type is used in the control system solution. l This indicates the number of times the l-th type of calculation is used in the control system solution. A is a flag indicating whether there is a data stream delay between the j-th computation of the m-th computation and the i-th computation of the l-th computation. ms,ini A represents the computational resource overhead of a multiplexer with zero inputs. ms,com This parameter represents the computational resource overhead of the multiplexer as the number of inputs increases. This indicates that the control system solution used a total of The first type of computational unit.

[0063] Optionally, the time-series constraints for the data stream calculated by the control system include:

[0064]

[0065]

[0066]

[0067]

[0068]

[0069]

[0070] In the formula, This represents the starting clock cycle of the i-th computation of the l-th type of computation. This is a flag indicating whether the result of the j-th computation in the m-th type of computation is used as the input to the i-th computation in the l-th type of computation. This is a flag indicating whether the result of the i-th computation in the l-th type of computation is used as the input to the k-th computation in the o-th type of computation. This indicates the end clock cycle of the j-th computation of the m-th computation, where the output result serves as the i-th computational input for the l-th computation. This represents the computation output delay for the l-th type of computation. This indicates that the input to the o-th computation is the starting clock cycle of the k-th computation output result. For the time overhead of the control system solution, T min T represents the shortest time cost of solving a control system based on its topology. p v represents the additional solution time overhead incurred by the control system solution, excluding the shortest solution time. c This represents the actual time elapsed in a single clock cycle. The delay in the data stream is represented by the output of the j-th computation of the m-th computation being used as the input of the i-th computation of the l-th computation, and C is a large number introduced to make the constraints linearize;

[0071] The constraints on the use of computational resources by the control system include:

[0072]

[0073]

[0074]

[0075]

[0076]

[0077]

[0078]

[0079] In the formula, A flag indicating whether the i-th computation of type l computation begins in clock cycle v. A flag indicating whether the i-th computation of type l ended in the v-th clock cycle. A flag indicating whether the i-th computation of type l is performed in the v-th clock cycle, n s This indicates the number of subsystems that the control system is solving.

[0080] Optionally, the specific process for obtaining the shortest solution time cost of the control system based on its topology is as follows:

[0081] A distance matrix is ​​generated based on the distance between computing nodes in the topology of the control system, wherein the distance between two computing nodes is the time cost of obtaining the computing result of one computing node from another computing node.

[0082] Generate a routing matrix based on the topology and the number of the first intermediate node of the two computing nodes;

[0083] Determine the distance D between computation node i and computation node j. ij The sum of the distances D from computation node i to intermediate node k and from intermediate node k to computation node j ik +D kj The size of D, if ik +D kj Greater than D ij Then update D ij =D ik +D kj The updated distance matrix is ​​obtained, and the first intermediate node between computation node i and computation node j is updated to R. ij =R ik Continue until all intermediate nodes have been traversed;

[0084] Obtain the maximum distance in the final distance matrix, calculate the product of this maximum distance and the actual time elapsed in a single clock cycle, and obtain the shortest solution time T of the control system. min .

[0085] As can be seen from the above technical solutions, this application has the following advantages:

[0086] This application provides a method for optimizing hardware resources in a control system, comprising: dividing the system to be simulated into an electrical system and a control system; constructing a hardware resource optimization model for the control system based on the topology and computation type of the control system, with the objective function being the minimum weighted sum of computational resources, storage resources, and time resources for solving the control system; solving the hardware resource optimization model for the control system and outputting the hardware resource optimization results; and downloading the hardware resource optimization results to an FPGA real-time simulator for simulation.

[0087] In this application, a hardware resource optimization model for solving the control system is constructed based on the topology and computation type of the control system. The objective function is to minimize the weighted sum of computational resources, storage resources and time resources for solving the control system. The hardware resource optimization results obtained by the optimization model are used to plan the hardware design of the entire control system, thereby obtaining a hardware design scheme with the minimum resource overhead. This improves the technical problems of long hardware debugging time and low efficiency in the existing technology that uses manual hardware design during simulation preparation. Attached Figure Description

[0088] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0089] Figure 1 A flowchart illustrating a method for optimizing hardware resources in a control system, as provided in this application embodiment;

[0090] Figure 2 This is a schematic diagram of the permanent magnet direct drive fan cluster computational example provided in the embodiments of this application;

[0091] Figure 3 This is a schematic diagram of the permanent magnet direct-drive fan control system provided in an embodiment of this application;

[0092] Figure 4 A flowchart illustrating the process of obtaining the shortest solution time of the control system provided in this application embodiment;

[0093] Figure 5 This is a schematic diagram of the overall architecture of the FPGA real-time emulator provided in the embodiments of this application;

[0094] Figure 6 This is a schematic diagram of a control system hardware resource optimization device provided in an embodiment of this application. Detailed Implementation

[0095] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0096] For easier understanding, please refer to Figure 1This application provides a method for optimizing hardware resources in a control system, including:

[0097] Step 101: Divide the system to be simulated into an electrical system and a control system. Based on the topology of the control system and the type of computation, construct a hardware resource optimization model for the control system with the objective function of minimizing the weighted sum of computational resources, storage resources and time resources for solving the control system.

[0098] Based on function and structure, the system to be simulated is divided into an electrical system and a control system. According to the topology and computation type of the control system, a hardware resource optimization model for the control system is constructed with the objective function of minimizing the weighted sum of computational, storage, and time resources. The specific construction process of the hardware resource optimization model for the control system can be as follows:

[0099] S1. Based on the topology of the control system, define the number of the first intermediate node encountered on the way from the i-th computing node to the j-th computing node as follows: Define the distance from the i-th computing node to the j-th computing node as D. ij The control system is defined to have performed M types of calculations, and the calculation of the m-th type of the control system has performed N calculations. m Next, define a flag indicating whether the result of the j-th computation of the m-th type of computation is used as the input of the i-th computation of the l-th type of computation.

[0100] When the method in the embodiments of this application is applied to an electromagnetic transient simulation FPGA accelerator, for example, permanent magnet direct-drive wind power cluster computing... Figure 2 As shown, the structure of the direct-drive permanent magnet synchronous wind turbine control system is as follows: Figure 3 As shown, the system consists of an aerodynamic system, a permanent magnet synchronous generator, a back-to-back converter, and related controllers. The aerodynamic system's mathematical model describes the process of converting wind energy into wind turbine power output, employing variable pitch control to ensure operation at maximum wind energy conversion efficiency. The permanent magnet synchronous generator converts the generator model into a transfer function to express the mathematical relationships of the model, and finally connects to other electrical components of the system as a controlled current source, completing the modeling within the control system. The back-to-back converter is modeled using a power electronic switch converter switching function model, and its controller consists of a machine-side converter controller and a grid-side converter controller.

[0101] S2. Initialize node R based on the dependencies and computation types of each computing node in the topology of the control system. ij Distance D ij and flags

[0102] S3. Construct a hardware resource optimization model for the control system with the objective function of minimizing the weighted sum of computational resources, storage resources, and time resources for solving the control system, and set time series constraints on the data flow of the control system computation and constraints on the use of computational resources for the control system solution.

[0103] The objective function is:

[0104] minf = w1A ctr +w2B ctr +pT p

[0105]

[0106]

[0107]

[0108]

[0109]

[0110]

[0111] In the formula, f represents the objective function, w1 and w2 are the weighted coefficients of the computational and storage resource overhead caused by the control system's solution, p is the penalty coefficient for the additional solution time overhead of the control system, and T p This represents the additional computation time overhead of the control system. A represents the computational and storage resource overhead incurred by the control system solution. ctr B represents the computational resource overhead incurred in solving the control system. ctr This represents the storage resource overhead incurred by the control system's computation. This represents the computational resource overhead incurred by the multiplexers used in the time-division multiplexing solution of the control system. This represents the computational resource overhead caused by data buffering in the solution of the control system, and M represents the total number of computational types during the solution of the control system. This indicates that the control system solution used a total of The m-th type of computational unit This represents the computational resource overhead incurred by the computational unit used for the m-th type of computation. This represents the storage resource overhead caused by data buffering in the control system solution. A represents the storage resource overhead incurred by the computing unit used for the m-th type of computation. db,ALM B represents the computational resource overhead caused by a single data latency. db,BMB N represents the storage resource overhead caused by a single data latency.m N represents the number of times the m-th calculation type is used in the control system solution. l This indicates the number of times the l-th type of calculation is used in the control system solution. A is a flag indicating whether there is a data stream delay between the j-th computation of the m-th computation and the i-th computation of the l-th computation. ms,ini A represents the computational resource overhead of a multiplexer with zero inputs. ms,com This parameter represents the computational resource overhead of the multiplexer as the number of inputs increases. This indicates that the control system solution used a total of The first type of computational unit.

[0112] The time-series constraints on the data stream computation of the control system include:

[0113]

[0114]

[0115]

[0116]

[0117]

[0118]

[0119] In the formula, This represents the starting clock cycle of the i-th computation of the l-th type of computation. This is a flag indicating whether the result of the j-th computation in the m-th type of computation is used as the input to the i-th computation in the l-th type of computation. This is a flag indicating whether the result of the i-th computation in the l-th type of computation is used as the input to the k-th computation in the o-th type of computation. This indicates the end clock cycle of the j-th computation of the m-th computation, where the output result serves as the i-th computational input for the l-th computation. This represents the computation output delay for the l-th type of computation. This indicates that the input to the o-th computation is the starting clock cycle of the k-th computation output result. For the time overhead of the control system solution, T min T represents the shortest time cost of solving a control system based on its topology, which can be obtained using the Floyd algorithm based on the control system topology; p v represents the additional solution time overhead incurred by the control system solution, excluding the shortest solution time. c This represents the actual time elapsed in a single clock cycle. The delay in the data stream is represented by the output of the j-th computation of the m-th computation being used as the input of the i-th computation of the l-th computation, and C is a large number introduced to make the constraints linearize;

[0120] The constraints on the use of computational resources for solving the control system include:

[0121]

[0122]

[0123]

[0124]

[0125]

[0126]

[0127]

[0128] In the formula, A flag indicating whether the i-th computation of type l computation begins in clock cycle v. A flag indicating whether the i-th computation of type l ended in the v-th clock cycle. A flag indicating whether the i-th computation of type l is performed in the v-th clock cycle, n s This indicates the number of subsystems that the control system is solving.

[0129] Furthermore, the specific process of obtaining the shortest solution time cost of the control system based on its topology is as follows:

[0130] (1) Construct the distance matrix D of the control system topology: Generate the distance matrix based on the distance between the computing nodes in the topology of the control system, where the distance between two computing nodes is the time cost of obtaining the computing result of one computing node from another computing node.

[0131] Assuming the control system topology has H computing nodes, the time cost of obtaining the computation result from one computing node to another is considered as the directed distance between the two computing nodes. Then, the directed distance between every two computing nodes in the topology can form a distance matrix D of order H:

[0132]

[0133] Among them, D ij The initial value is the time from computing node i to computing node j directly, where i,j = 1,2,...,H. If a direct journey is not possible, it is denoted as negative infinity.

[0134] (2) Construct the routing matrix R of the control system topology: Generate the routing matrix based on the topology and the number of the first intermediate node of the two computing nodes;

[0135] In the topology of a control system, the numbering of the first intermediate node traversed to reach another computing node from one computing node can form a routing matrix R of order H:

[0136]

[0137] (3) Traverse all intermediate nodes, update the distance matrix D and the routing matrix R, and complete the search for the shortest solution time:

[0138] Determine the distance D between computation node i and computation node j. ij The sum of the distances D from computation node i to intermediate node k and from intermediate node k to computation node j ik +D kj The size of D, if ik +D kj Greater than D ij Then update D ij =D ik +D kj The updated distance matrix is ​​obtained, and the first intermediate node between computation node i and computation node j is updated to R. ij =R ik This process continues until all intermediate nodes have been traversed. For details, please refer to [link / reference]. Figure 4 ;

[0139] Obtain the maximum distance in the final distance matrix, and calculate the maximum distance relative to the actual time v elapsed in a single clock cycle. c The product of these two factors yields the shortest solution time T for the control system. min .

[0140] Step 102: Solve the hardware resource optimization model of the control system and output the hardware resource optimization results.

[0141] The hardware resource optimization model of the control system established in step 101 is solved using the linear programming method, and the hardware resource optimization results are output, including: the number of computing units used in the control system solution, the start time and end time of each calculation in the control system solution, and the number of the computing unit used.

[0142] Step 103: Download the hardware resource optimization results to the FPGA real-time simulator for simulation.

[0143] Download the optimized hardware resource results to the FPGA real-time simulator, start the FPGA real-time simulator for simulation, and refer to [reference needed]. Figure 5 This application provides a schematic diagram of the overall architecture of an FPGA real-time simulator. Based on the topology and computation type of the control system, a hardware resource optimization model for control system solving is constructed, with the objective function being the minimum weighted sum of computational, storage, and time resources for control system solution. The hardware resource optimization results obtained from the optimization model are used to plan the hardware design of the entire control system, thereby obtaining a hardware design scheme with minimal resource overhead. This improves upon the technical problems of long hardware debugging time and low efficiency inherent in existing technologies that rely on manual hardware design during simulation preparation.

[0144] This application uses Altera's Stratix V series FPGA EP5SGSMD5K2F40C2 and its accompanying development board as the simulation platform. The real-time simulation system is driven by a 125MHz clock. The simulation step size is set to 9μs. Table 1 shows the resource overhead of the general optimized design and the conventional design in the permanent magnet direct-drive wind turbine cluster example. The comparison of resource overhead shows that the general optimized design significantly reduces computational resource consumption compared to the conventional design, demonstrating the effectiveness of the real-time simulation system designed in this application.

[0145] Table 1 Comparison of Control System Resource Costs

[0146]

[0147] This application addresses the issues of improving the utilization efficiency of computing resources and hardware design in the simulation of complex control systems. For any control system topology, the topology can be analyzed by a program to obtain the shortest solution time for the entire control system. Based on time-division multiplexing technology, a linear programming method is used to plan the hardware design of the entire control system, thereby obtaining a hardware design scheme with minimal resource overhead. The program automatically obtains the hardware design code of the control system based on this scheme, which is a new and general solution for the real-time simulation hardware design of pipelined control systems.

[0148] The above is an embodiment of a control system hardware resource optimization method provided by this application. The following is an embodiment of a control system hardware resource optimization device provided by this application.

[0149] Please refer to Figure 6 This application provides a control system hardware resource optimization device, comprising:

[0150] The model building unit is used to divide the system to be simulated into an electrical system and a control system. Based on the topology of the control system and the type of computation, it builds a hardware resource optimization model for the control system with the objective function of minimizing the weighted sum of computational resources, storage resources and time resources for solving the control system.

[0151] The model solving unit is used to solve the hardware resource optimization model of the control system and output the hardware resource optimization results.

[0152] The simulation unit is used to download the hardware resource optimization results to the FPGA real-time simulator for simulation.

[0153] As a further improvement, the model building unit is specifically used for:

[0154] The system to be simulated is divided into an electrical system and a control system;

[0155] Based on the topology of the control system, the number of the first intermediate node encountered on the way from the i-th computing node to the j-th computing node is defined as follows: Define the distance from the i-th computing node to the j-th computing node as D. ij The control system is defined to have performed M types of calculations, and the calculation of the m-th type of the control system has performed N calculations. m Next, define a flag indicating whether the result of the j-th computation of the m-th type of computation is used as the input of the i-th computation of the l-th type of computation.

[0156] Node R is initialized based on the dependencies and computation types of each computing node in the topology of the control system. ij Distance D ij and flags

[0157] A hardware resource optimization model for solving the control system is obtained by constructing a model with the objective function of minimizing the weighted sum of computational, storage, and time resources for solving the control system, and setting time series constraints on the computational data flow of the control system and constraints on the use of computational resources for solving the control system.

[0158] As a further improvement, the objective function is:

[0159] minf = w1A ctr +w2B ctr +pT p

[0160]

[0161]

[0162]

[0163]

[0164]

[0165]

[0166] In the formula, f represents the objective function, w1 and w2 are the weighted coefficients of the computational and storage resource overhead caused by the control system's solution, p is the penalty coefficient for the additional solution time overhead of the control system, and T p This represents the additional computation time overhead of the control system. A represents the computational and storage resource overhead incurred by the control system solution. ctr B represents the computational resource overhead incurred in solving the control system. ctr This represents the storage resource overhead incurred by the control system's computation. This represents the computational resource overhead incurred by the multiplexers used in the time-division multiplexing solution of the control system. This represents the computational resource overhead caused by data buffering in the solution of the control system, and M represents the total number of computational types during the solution of the control system. This indicates that the control system solution used a total of The m-th type of computational unit This represents the computational resource overhead incurred by the computational unit used for the m-th type of computation. This represents the storage resource overhead caused by data buffering in the control system solution. A represents the storage resource overhead incurred by the computing unit used for the m-th type of computation. db,ALM B represents the computational resource overhead caused by a single data latency. db,BMB N represents the storage resource overhead caused by a single data latency. m N represents the number of times the m-th calculation type is used in the control system solution. l This indicates the number of times the l-th type of calculation is used in the control system solution. A is a flag indicating whether there is a data stream delay between the j-th computation of the m-th computation and the i-th computation of the l-th computation. ms,ini A represents the computational resource overhead of a multiplexer with zero inputs. ms,com This parameter represents the computational resource overhead of the multiplexer as the number of inputs increases. This indicates that the control system solution used a total of The first type of computational unit.

[0167] As a further improvement, the time-series constraints for the control system's computational data stream include:

[0168]

[0169]

[0170]

[0171]

[0172]

[0173]

[0174] In the formula, This represents the starting clock cycle of the i-th computation of the l-th type of computation. This is a flag indicating whether the result of the j-th computation in the m-th type of computation is used as the input to the i-th computation in the l-th type of computation. This is a flag indicating whether the result of the i-th computation in the l-th type of computation is used as the input to the k-th computation in the o-th type of computation. This indicates the end clock cycle of the j-th computation of the m-th computation, where the output result serves as the i-th computational input for the l-th computation. This represents the computation output delay for the l-th type of computation. This indicates that the input to the o-th computation is the starting clock cycle of the k-th computation output result. For the time overhead of the control system solution, T min T represents the shortest time cost of solving a control system based on its topology. p v represents the additional solution time overhead incurred by the control system solution, excluding the shortest solution time. c This represents the actual time elapsed in a single clock cycle. The delay in the data stream is represented by the output of the j-th computation of the m-th computation being used as the input of the i-th computation of the l-th computation, and C is a large number introduced to make the constraints linearize;

[0175] The constraints on the use of computational resources for solving the control system include:

[0176]

[0177]

[0178]

[0179]

[0180]

[0181]

[0182]

[0183] In the formula, A flag indicating whether the i-th computation of type l computation begins in clock cycle v. A flag indicating whether the i-th computation of type l ended in the v-th clock cycle. A flag indicating whether the i-th computation of type l is performed in the v-th clock cycle, n s This indicates the number of subsystems that the control system is solving.

[0184] As a further improvement, the specific process of obtaining the shortest solution time cost of the control system based on the topology of the control system is as follows:

[0185] A distance matrix is ​​generated based on the distance between computing nodes in the topology of the control system, where the distance between two computing nodes is the time cost of obtaining the computing result of one computing node from another computing node.

[0186] Generate a routing matrix based on the topology and the number of the first intermediate node of the two computing nodes;

[0187] Determine the distance D between computation node i and computation node j. ij The sum of the distances D from computation node i to intermediate node k and from intermediate node k to computation node j ik +D kj The size of D, if ik +D kj Greater than D ij Then update D ij =D ik +D kj The updated distance matrix is ​​obtained, and the first intermediate node between computation node i and computation node j is updated to R. ij =R ik Continue until all intermediate nodes have been traversed;

[0188] Obtain the maximum distance in the final distance matrix, calculate the product of this maximum distance and the actual time elapsed in a single clock cycle, and obtain the shortest solution time T of the control system. min .

[0189] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above-described apparatus and unit can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0190] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0191] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0192] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0193] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0194] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0195] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for executing all or part of the steps of the methods described in the various embodiments of this application through a computer device (which may be a personal computer, server, or network device, etc.). The aforementioned storage medium includes: USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, optical disks, and other media capable of storing program code.

[0196] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A method for optimizing hardware resources in a control system, characterized in that, include: The system to be simulated is divided into an electrical system and a control system. Based on the topology and computation type of the control system, a hardware resource optimization model for the control system is constructed with the objective function of minimizing the weighted sum of computational resources, storage resources and time resources for the control system solution. The construction of a hardware resource optimization model for solving the control system, based on the topology and computation type of the control system and with the objective function of minimizing the weighted sum of computational, storage, and time resources for solving the control system, includes: Based on the topology of the control system, the first intermediate node encountered on the way from the i-th computing node to the j-th computing node is defined as R. ij , , Let i ≠ j, and define the distance from the i-th computing node to the j-th computing node as D. ij The control system is defined to have performed M types of calculations, and the calculation of the m-th type of the control system has performed N calculations. m Next, define a flag indicating whether the result of the j-th computation of the m-th type of computation is used as the input of the i-th computation of the l-th type of computation. , l=1,2,...,M, i=1,2,...,N l j=1,2,...,N m i≠j; Node R is initialized based on the dependencies and computation types of each computing node in the topology of the control system. ij Distance D ij and flags ; A hardware resource optimization model for solving the control system is obtained by constructing a model with the objective function of minimizing the weighted sum of computational resources, storage resources and time resources for solving the control system, and setting time series constraints on the computational data flow of the control system and constraints on the use of computational resources for solving the control system. Solve the hardware resource optimization model of the control system and output the hardware resource optimization results; The hardware resource optimization results are downloaded to the FPGA real-time simulator for simulation.

2. The control system hardware resource optimization method according to claim 1, characterized in that, The objective function is: ； ； ； ； ； ； ； In the formula, f represents the objective function, w1 and w2 are the weighted coefficients of the computational and storage resource overhead caused by the control system's solution, p is the penalty coefficient for the additional solution time overhead of the control system, and T p This represents the additional computation time overhead of the control system. This represents the computational and storage resource overhead incurred by the control system solution. This represents the computational resource overhead incurred in solving the control system. This represents the storage resource overhead incurred by the control system's computation. This represents the computational resource overhead incurred by the multiplexers used in the time-division multiplexing solution of the control system. This represents the computational resource overhead caused by data buffering in the solution of the control system, and M represents the total number of computational types during the solution of the control system. This indicates that the control system solution used a total of The m-th type of computational unit This represents the computational resource overhead incurred by the computational unit used for the m-th type of computation. This represents the storage resource overhead caused by data buffering in the control system solution. This represents the storage resource overhead incurred by the computing unit used for the m-th type of computation. This represents the computational resource overhead caused by a single data latency. N represents the storage resource overhead caused by a single data latency. m N represents the number of times the m-th calculation type is used in the control system solution. l This indicates the number of times the l-th type of calculation is used in the control system solution. A is a flag indicating whether there is a data stream delay between the j-th computation of the m-th computation and the i-th computation of the l-th computation. ms,ini A represents the computational resource overhead of a multiplexer with zero inputs. ms,com This parameter represents the computational resource overhead of the multiplexer as the number of inputs increases. This indicates that the control system solution used a total of The first type of computational unit.

3. The control system hardware resource optimization method according to claim 2, characterized in that, The time-series constraints for the data stream calculated by the control system include: ； ； ； ； ； ； In the formula, This represents the starting clock cycle of the i-th computation of the l-th type of computation. This is a flag indicating whether the result of the j-th computation in the m-th type of computation is used as the input to the i-th computation in the l-th type of computation. This is a flag indicating whether the result of the i-th computation in the l-th type of computation is used as the input to the k-th computation in the o-th type of computation. This indicates the end clock cycle of the j-th computation of the m-th computation, where the output result serves as the i-th computational input for the l-th computation. This represents the computation output delay for the l-th type of computation. This indicates that the input to the o-th computation is the starting clock cycle of the k-th computation output result. For the time overhead of the control system solution, T min T represents the shortest time cost of solving a control system based on its topology. p v represents the additional solution time overhead incurred by the control system solution, excluding the shortest solution time. c This represents the actual time elapsed in a single clock cycle. The delay in the data stream is represented by the output of the j-th computation of the m-th computation being used as the input of the i-th computation of the l-th computation, and C is a large number introduced to make the constraints linearize; The constraints on the use of computational resources by the control system include: ； ； ； ； ； ； ； In the formula, A flag indicating whether the i-th computation of type l computation begins in clock cycle v. A flag indicating whether the i-th computation of type l ended in the v-th clock cycle. A flag indicating whether the i-th computation of type l is performed in the v-th clock cycle, n s This indicates the number of subsystems that the control system is solving.

4. The control system hardware resource optimization method according to claim 3, characterized in that, The specific process for obtaining the shortest solution time cost of the control system based on its topology is as follows: A distance matrix is ​​generated based on the distance between computing nodes in the topology of the control system, wherein the distance between two computing nodes is the time cost of obtaining the computing result of one computing node from another computing node. Generate a routing matrix based on the topology and the number of the first intermediate node of the two computing nodes; Determine the distance D between computation node i and computation node j. ij The sum of the distances D from computation node i to intermediate node k and from intermediate node k to computation node j ik +D kj The size of D, if ik +D kj Greater than D ij Then update D ij =D ik +D kj The updated distance matrix is ​​obtained, and the first intermediate node between computation node i and computation node j is updated to R. ij =R ik Continue until all intermediate nodes have been traversed; Obtain the maximum distance in the final distance matrix, calculate the product of this maximum distance and the actual time elapsed in a single clock cycle, and obtain the shortest solution time T of the control system. min .

5. A hardware resource optimization device for a control system, characterized in that, include: The model building unit is used to divide the system to be simulated into an electrical system and a control system. Based on the topology and computing type of the control system, it constructs a hardware resource optimization model for the control system with the objective function of minimizing the weighted sum of computing resources, storage resources and time resources for the control system solution. The model building unit is specifically used for: The system to be simulated is divided into an electrical system and a control system; Based on the topology of the control system, the first intermediate node encountered on the way from the i-th computing node to the j-th computing node is defined as R. ij , , Let i ≠ j, and define the distance from the i-th computing node to the j-th computing node as D. ij The control system is defined to have performed M types of calculations, and the calculation of the m-th type of the control system has performed N calculations. m Next, define a flag indicating whether the result of the j-th computation of the m-th type of computation is used as the input of the i-th computation of the l-th type of computation. , l=1,2,...,M, i=1,2,...,N l j=1,2,...,N m i≠j; Node R is initialized based on the dependencies and computation types of each computing node in the topology of the control system. ij Distance D ij and flags ; A hardware resource optimization model for solving the control system is obtained by constructing a model with the objective function of minimizing the weighted sum of computational resources, storage resources and time resources for solving the control system, and setting time series constraints on the computational data flow of the control system and constraints on the use of computational resources for solving the control system. The model solving unit is used to solve the hardware resource optimization model of the control system and output the hardware resource optimization results. The simulation unit is used to download the hardware resource optimization results to the FPGA real-time simulator for simulation.

6. The control system hardware resource optimization device according to claim 5, characterized in that, The objective function is: ； ； ； ； ； ； ； In the formula, f represents the objective function, w1 and w2 are the weighted coefficients of the computational and storage resource overhead caused by the control system's solution, p is the penalty coefficient for the additional solution time overhead of the control system, and T p This represents the additional computation time overhead of the control system. This represents the computational and storage resource overhead incurred by the control system solution. This represents the computational resource overhead incurred in solving the control system. This represents the storage resource overhead incurred by the control system's computation. This represents the computational resource overhead incurred by the multiplexers used in the time-division multiplexing solution of the control system. This represents the computational resource overhead caused by data buffering in the solution of the control system, and M represents the total number of computational types during the solution of the control system. This indicates that the control system solution used a total of The m-th type of computational unit This represents the computational resource overhead incurred by the computational unit used for the m-th type of computation. This represents the storage resource overhead caused by data buffering in the control system solution. This represents the storage resource overhead incurred by the computing unit used for the m-th type of computation. This represents the computational resource overhead caused by a single data latency. N represents the storage resource overhead caused by a single data latency. m N represents the number of times the m-th calculation type is used in the control system solution. l This indicates the number of times the l-th type of calculation is used in the control system solution. A is a flag indicating whether there is a data stream delay between the j-th computation of the m-th computation and the i-th computation of the l-th computation. ms,ini A represents the computational resource overhead of a multiplexer with zero inputs. ms,com This parameter represents the computational resource overhead of the multiplexer as the number of inputs increases. This indicates that the control system solution used a total of The first type of computational unit.

7. The control system hardware resource optimization device according to claim 6, characterized in that, The time-series constraints for the data stream calculated by the control system include: ； ； ； ； ； ； In the formula, This represents the starting clock cycle of the i-th computation of the l-th type of computation. This is a flag indicating whether the result of the j-th computation in the m-th type of computation is used as the input to the i-th computation in the l-th type of computation. This is a flag indicating whether the result of the i-th computation in the l-th type of computation is used as the input to the k-th computation in the o-th type of computation. This indicates the end clock cycle of the j-th computation of the m-th computation, where the output result serves as the i-th computational input for the l-th computation. This represents the computation output delay for the l-th type of computation. This indicates that the input to the o-th computation is the starting clock cycle of the k-th computation output result. For the time overhead of the control system solution, T min T represents the shortest time cost of solving a control system based on its topology. p v represents the additional solution time overhead incurred by the control system solution, excluding the shortest solution time. c This represents the actual time elapsed in a single clock cycle. The delay in the data stream is represented by the output of the j-th computation of the m-th computation being used as the input of the i-th computation of the l-th computation, and C is a large number introduced to make the constraints linearize; The constraints on the use of computational resources by the control system include: ； ； ； ； ； ； ； In the formula, A flag indicating whether the i-th computation of type l computation begins in clock cycle v. A flag indicating whether the i-th computation of type l ended in the v-th clock cycle. A flag indicating whether the i-th computation of type l is performed in the v-th clock cycle, n s This indicates the number of subsystems that the control system is solving.

8. The control system hardware resource optimization device according to claim 7, characterized in that, The specific process for obtaining the shortest solution time cost of the control system based on its topology is as follows: A distance matrix is ​​generated based on the distance between computing nodes in the topology of the control system, wherein the distance between two computing nodes is the time cost of obtaining the computing result of one computing node from another computing node. Generate a routing matrix based on the topology and the number of the first intermediate node of the two computing nodes; Determine the distance D between computation node i and computation node j. ij The sum of the distances D from computation node i to intermediate node k and from intermediate node k to computation node j ik +D kj The size of D, if ik +D kj Greater than D ij Then update D ij =D ik +D kj The updated distance matrix is ​​obtained, and the first intermediate node between computation node i and computation node j is updated to R. ij =R ik Continue until all intermediate nodes have been traversed; Obtain the maximum distance in the final distance matrix, calculate the product of this maximum distance and the actual time elapsed in a single clock cycle, and obtain the shortest solution time T of the control system. min .

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