Memory and access method

Abstract

The embodiment of the present application provides a memory, wherein the memory comprises: a first storage unit, a sensitive amplifier, a first bit line, a second bit line, a first isolator, a second isolator, a third isolator, a fourth isolator and a controller; the first bit line is connected with the first storage unit and a first output of the sensitive amplifier; the second bit line is connected with a second output of the sensitive amplifier; the first isolator is connected with the first bit line and the first output of the sensitive amplifier; the second isolator is connected with the second bit line and the second output of the sensitive amplifier; the third isolator is connected with the first bit line and the second output of the sensitive amplifier; and the fourth isolator is connected with the second bit line and the first output of the sensitive amplifier. The technical scheme of the present application can convert one-side disturbance in the whole access period of the storage unit into double-side disturbance, and reduces the influence of one-side disturbance on the capacitor.

Description

Technical Field

[0001] This application relates to the semiconductor field, specifically to a memory and an access method. Background Technology

[0002] In recent years, the increasing demands of emerging application scenarios such as artificial intelligence and edge computing have posed challenges to the capacity, power consumption, and speed of traditional memory, prompting the continuous development of new types of memory. Ferroelectric memory, as a novel type of memory, possesses advantages such as non-volatility, high read / write speeds, and low power consumption. The emergence of the m transistor and n capacitor (mTnC) structure has greatly improved the storage density of ferroelectric memory. However, its current read method, similar to dynamic random access memory (DRAM-like), suffers from half-select voltage disturbances in ferroelectric capacitors, especially one-sided disturbances, which severely reduce the data reliability of the memory and increase system power consumption.

[0003] Therefore, how to reduce the unilateral disturbances experienced by capacitors and improve the reliability of data storage is an urgent problem to be solved. Summary of the Invention

[0004] This application provides a memory and access method that can convert a one-sided disturbance during the entire access cycle of a memory cell into a two-sided disturbance, thereby reducing the impact of one-sided disturbances on capacitors.

[0005] In a first aspect, a memory is provided, comprising: a first memory cell selected for read or write operations; a sensitive amplifier, a first bit line, and a second bit line, the first bit line being connected to the first memory cell and a first output of the sensitive amplifier, and the second bit line being connected to a second output of the sensitive amplifier; a first isolator, a second isolator, a third isolator, and a fourth isolator, the first isolator being connected to the first bit line and the first output of the sensitive amplifier, the second isolator being connected to the second bit line and the second output of the sensitive amplifier, the third isolator being connected to the first bit line and the second output of the sensitive amplifier, and the fourth isolator being connected to the second bit line and the first output of the sensitive amplifier; and a controller configured to turn on the first isolator and the second isolator and turn off the third isolator and the fourth isolator before the write-back of the first memory cell is completed, and to turn off the first isolator and the second isolator and turn on the third isolator and the fourth isolator after the write-back of the first memory cell is completed.

[0006] The memory in this embodiment includes a first isolator, a second isolator, a third isolator, and a fourth isolator. These four isolators can exchange the voltages of the first bit line and the second bit line after the first memory cell is written back, forming an interchange phase. This converts the one-sided disturbance during the entire access cycle of the memory cell into a two-sided disturbance, reducing the impact of the one-sided disturbance on the capacitor.

[0007] It should be understood that the first memory cell can be any memory cell in the memory array. The first memory cell provided in this application has a structure of m transistors and n capacitors (mTnC), that is, the first memory cell includes m transistors and n capacitors. Wherein, m≥1, n≥2. Exemplarily, the memory can be a ferroelectric memory, or it can be a memory made of other materials that has a one-sided perturbation problem.

[0008] It should be understood that the first and second outputs of the sensitive amplifier include output ports. The sensitive amplifier can be connected to multiple memory cells via bit lines.

[0009] It should be understood that the first bit line and the second bit line are connected to the same sensitive amplifier, which can be regarded as the second bit line and the first bit line sharing the readout circuit.

[0010] Optionally, the first bit line can be represented by BL, and the second bit line can be represented by BLN. At least one first isolator can be placed on the first bit line, connecting the first bit line and the first output of the sensitive amplifier. At least one second isolator can be placed on the second bit line, connecting the second bit line and the second output of the sensitive amplifier. A third isolator connects the first bit line and the second output of the sensitive amplifier, and a fourth isolator connects the second bit line and the first output of the sensitive amplifier. Exemplarily, the first bit line and the second bit line are connected via a first conductor, and the third and fourth isolators are located on the first conductor.

[0011] A sensitive amplifier is used to amplify the voltages of BL and BLN. Exemplarily, the sensitive amplifier includes a sense-amplifier n-FET control (SAN) and a sense-amplifier p-FET control (SAP), with SAN and SAP providing power for the sensitive amplifier's operation. The power values ​​of SAN and SAP determine the voltage state to which the sensitive amplifier amplifies the voltages of BL and BLN. Exemplarily, when SAN and SAP are 0 and Vw respectively, after the sensitive amplifier completes its operation, the voltages of BL and BLN will be pulled down to 0 or Vw; when SAN and SAP are Vw and Vw / 2 respectively, after the sensitive amplifier completes its operation, the voltages of BL and BLN will be pulled down to Vw or Vw / 2, where Vw represents the write operation voltage of the first memory cell.

[0012] It should be understood that the controller can provide control signals to turn on the first and second isolators and turn off the third and fourth isolators before the write-back of the first memory cell is completed, and to turn off the first and second isolators and turn on the third and fourth isolators after the write-back of the first memory cell is completed.

[0013] Optionally, the sensitive amplifier, the first isolator, the second isolator, the third isolator and the fourth isolator can be integrated into the controller, and this application does not limit this.

[0014] It should be understood that turning on an isolator means making the lines at both ends of the isolator conductive, while turning off an isolator means disconnecting the lines at both ends of the isolator.

[0015] It should be understood that the write-back of the first memory cell includes the write-back of the selected capacitor in the first memory cell.

[0016] In this embodiment, before the write-back of the first memory cell is completed, the first and second isolators are on, while the third and fourth isolators are off. After the write-back is completed, the first and second isolators are turned off, and the third and fourth isolators are turned on, allowing the voltages of BL and BLN to be interchanged, forming an interchange phase. This converts the unilateral disturbance during the entire access cycle of the memory cell into a bilateral disturbance, reducing the impact of unilateral disturbances on the capacitors.

[0017] In conjunction with the first aspect, in one possible implementation, if the voltage of the first bit line is a first positive voltage and the voltage of the second bit line is a second positive voltage before the write-back is completed, then after the write-back is completed, the voltage of the first bit line is the second positive voltage and the voltage of the second bit line is the first positive voltage; if the voltage of the first bit line is the second positive voltage and the voltage of the second bit line is the first positive voltage before the write-back is completed, then after the write-back is completed, the voltage of the first bit line is the first positive voltage and the voltage of the second bit line is the second positive voltage.

[0018] Optionally, the first positive voltage = Vw / 2, and the second positive voltage = Vw, where Vw represents the write operation voltage of the first memory cell.

[0019] For example, if the voltage of the first bit line is Vw / 2 and the voltage of the second bit line is Vw before the write-back is completed, then the voltage of the first bit line will be Vw and the voltage of the second bit line will be Vw / 2 after the write-back is completed; if the voltage of the first bit line is Vw and the voltage of the second bit line is Vw / 2 before the write-back is completed, then the voltage of the first bit line will be Vw / 2 and the voltage of the second bit line will be Vw after the write-back is completed.

[0020] The memory in this embodiment includes a first isolator, a second isolator, a third isolator, and a fourth isolator. These four isolators can exchange the voltages of the first bit line and the second bit line after the first memory cell is written back, forming an interchange phase. This converts the one-sided disturbance during the entire access cycle of the memory cell into a two-sided disturbance, reducing the impact of the one-sided disturbance on the capacitor.

[0021] In conjunction with the first aspect, in one possible implementation, the first isolator is located between the third isolator and the sensitive amplifier, and the second isolator is located between the fourth isolator and the sensitive amplifier.

[0022] The memory in this embodiment includes a first isolator, a second isolator, a third isolator, and a fourth isolator. These four isolators can exchange the voltages of the first bit line and the second bit line after the first memory cell is written back, forming an interchange phase. This converts the one-sided disturbance during the entire access cycle of the memory cell into a two-sided disturbance, reducing the impact of the one-sided disturbance on the capacitor.

[0023] In conjunction with the first aspect, in one possible implementation, after the write-back is completed, the voltage of the floating gate of the first memory cell is the same as that of the first bit line, and the first plates of the plurality of capacitors of the first memory cell are connected to the floating gate.

[0024] It should be understood that the first memory cell includes multiple capacitors. The first plate of each capacitor is connected to the floating gate (FG), and the second plate is connected to the plate line. The floating gate is connected to the first bit line. After the write-back is completed, the voltages of the first bit line and the second bit line are swapped. Since the floating gate is connected to the first bit line, the voltage of the floating gate of the first memory cell is the same as that of the first bit line.

[0025] The memory in this embodiment includes a first isolator, a second isolator, a third isolator, and a fourth isolator. These four isolators can exchange the voltages of the first bit line and the second bit line after the first memory cell is written back, forming an interchange phase. This converts the one-sided disturbance during the entire access cycle of the memory cell into a two-sided disturbance, reducing the impact of the one-sided disturbance on the capacitor.

[0026] In conjunction with the first aspect, in one possible implementation, the first isolator and the second isolator include isolation (ISO) tubes.

[0027] In conjunction with the first aspect, in one possible implementation, the first bit line and the second bit line are connected by a first conductor, the first isolator is located on the first bit line, the second isolator is located on the second bit line, and the third isolator and the fourth isolator are located on the first conductor.

[0028] The memory in this embodiment includes a first isolator, a second isolator, a third isolator, and a fourth isolator. These four isolators can exchange the voltages of the first bit line and the second bit line after the first memory cell is written back, forming an interchange phase. This converts the one-sided disturbance during the entire access cycle of the memory cell into a two-sided disturbance, reducing the impact of the one-sided disturbance on the capacitor.

[0029] In a second aspect, an integrated circuit is provided, including a memory in the first aspect or any possible implementation thereof.

[0030] Thirdly, an electronic device is provided, including a circuit board and the memory described in the first aspect, the memory being disposed on the circuit board and electrically connected to the circuit board.

[0031] Fourthly, a method for accessing a memory is provided, the method being applied to a memory comprising a first memory cell, a sensitive amplifier, a first bit line, a second bit line, a first isolator, a second isolator, a third isolator, a fourth isolator, and a controller. The first memory cell is a memory cell selected for a read or write operation. The first bit line connects the first memory cell to a first output of the sensitive amplifier, the second bit line connects to a second output of the sensitive amplifier, the first isolator connects the first bit line to the first output of the sensitive amplifier, the second isolator connects the second bit line to the second output of the sensitive amplifier, the third isolator connects the first bit line to the second output of the sensitive amplifier, and the fourth isolator connects the second bit line to the first output of the sensitive amplifier. The method includes: the controller turning on the first isolator and the second isolator and turning off the third isolator and the fourth isolator before the write-back of the first memory cell is completed; and the controller turning off the first isolator and the second isolator and turning on the third isolator and the fourth isolator after the write-back of the first memory cell is completed.

[0032] It should be understood that the first memory cell can be any memory cell in the memory array. The first memory cell provided in this application has a structure of m transistors and n capacitors (mTnC), that is, the first memory cell includes m transistors and n capacitors. Wherein, m≥1, n≥2. Exemplarily, the memory can be a ferroelectric memory, or it can be a memory made of other materials that has a one-sided perturbation problem.

[0033] It should be understood that the first and second outputs of the sensitive amplifier include output ports.

[0034] It should be understood that the first bit line and the second bit line are connected to the same sensitive amplifier, which can be regarded as the second bit line and the first bit line sharing the readout circuit.

[0035] Optionally, the first bit line can be represented by BL, and the second bit line can be represented by BLN. At least one first isolator can be placed on the first bit line, connecting the first bit line and the first output of the sensitive amplifier. At least one second isolator can be placed on the second bit line, connecting the second bit line and the second output of the sensitive amplifier. A third isolator connects the first bit line and the second output of the sensitive amplifier, and a fourth isolator connects the second bit line and the first output of the sensitive amplifier. Exemplarily, the first bit line and the second bit line are connected via a first conductor, and the third and fourth isolators are arranged on the first conductor.

[0036] It should be understood that turning on an isolator means making the lines at both ends of the isolator conductive, while turning off an isolator means disconnecting the lines at both ends of the isolator.

[0037] The memory in this embodiment includes a first isolator, a second isolator, a third isolator, and a fourth isolator. These four isolators can exchange the voltages of the first bit line and the second bit line after the first memory cell is written back, forming an interchange phase. This converts the one-sided disturbance during the entire access cycle of the memory cell into a two-sided disturbance, reducing the impact of the one-sided disturbance on the capacitor.

[0038] In conjunction with the fourth aspect, in one possible implementation, if the voltage of the first bit line is a first positive voltage and the voltage of the second bit line is a second positive voltage before the write-back is completed, then after the write-back is completed, the voltage of the first bit line is the second positive voltage and the voltage of the second bit line is the first positive voltage; if the voltage of the first bit line is the second positive voltage and the voltage of the second bit line is the first positive voltage before the write-back is completed, then after the write-back is completed, the voltage of the first bit line is the first positive voltage and the voltage of the second bit line is the second positive voltage.

[0039] In conjunction with the fourth aspect, in one possible implementation, the first positive voltage = Vw / 2, and the second positive voltage = Vw, where Vw represents the write operation voltage of the first memory cell.

[0040] The memory in this embodiment includes a first isolator, a second isolator, a third isolator, and a fourth isolator. These four isolators can exchange the voltages of the first bit line and the second bit line after the first memory cell is written back, forming an interchange phase. This converts the one-sided disturbance during the entire access cycle of the memory cell into a two-sided disturbance, reducing the impact of the one-sided disturbance on the capacitor.

[0041] In conjunction with the fourth aspect, in one possible implementation, after the write-back is completed, the voltage of the floating gate of the first memory cell is the same as that of the first bit line, and the first plates of the plurality of capacitors of the first memory cell are connected to the floating gate.

[0042] It should be understood that the first memory cell includes multiple capacitors. The first plate of each capacitor is connected to the floating gate (FG), and the second plate is connected to the plate line. The floating gate is connected to the first bit line. After the write-back is completed, the voltages of the first bit line and the second bit line are swapped. Since the floating gate is connected to the first bit line, the voltage of the floating gate of the first memory cell is the same as that of the first bit line.

[0043] The memory in this embodiment includes a first isolator, a second isolator, a third isolator, and a fourth isolator. These four isolators can exchange the voltages of the first bit line and the second bit line after the first memory cell is written back, forming an interchange phase. This converts the one-sided disturbance during the entire access cycle of the memory cell into a two-sided disturbance, reducing the impact of the one-sided disturbance on the capacitor. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of a typical mTnC memory array structure.

[0045] Figure 2 This is a schematic diagram of the structure of a memory provided by existing technology.

[0046] Figure 3 This is a waveform diagram of a read / write operation of a memory provided by existing technology.

[0047] Figure 4 This is a schematic diagram illustrating a scenario where a ferroelectric capacitor is disturbed, as provided in an embodiment of this application.

[0048] Figure 5 This is a schematic diagram illustrating a unilateral disturbance situation provided in an embodiment of this application.

[0049] Figure 6 This is a schematic diagram of another memory structure provided by existing technology.

[0050] Figure 7 This is a schematic diagram of the structure of a memory provided in an embodiment of this application.

[0051] Figure 8 This is a schematic diagram of another memory structure provided in an embodiment of this application.

[0052] Figure 9 This is a schematic diagram of the read / write operation waveform of a memory provided in an embodiment of this application. Detailed Implementation

[0053] Figure 1 This is a schematic diagram of a typical mTnC memory array structure.

[0054] Figure 1Each memory cell in the illustrated memory array includes m transistors and n capacitors, where m ≥ 1 and n ≥ 2. Taking a memory array comprising 5 word lines (WL), 5 bit lines (BL), and 4 plate lines (PL) as an example, word lines WL0–WL4 are arranged along the row direction, with each WL connecting to the gate of the access transistor in the same row of memory cells. Bit lines BL0–BL4 are arranged along the column direction, with each BL connecting to the source of the access transistor in the same column of memory cells. Plate lines PL0–PL3 are distributed across different metal layers. It should be understood that the marked positions of WL, PL, and BL in the figure represent the hierarchical positions of the interconnects.

[0055] Figure 2 This is a schematic diagram of the structure of a memory provided by existing technology.

[0056] WL stands for word line, PL for board line, BL and BLN for bit lines, and FG for floating gate (FG). Memory cell 210 in the diagram includes a transistor and multiple ferroelectric capacitors. The lower plate of each ferroelectric capacitor is connected to FG, and the upper plate is connected to PL. Sensitive amplifier 230 amplifies the voltages on BL and BLN.

[0057] It should be understood that BL and BLN are used to distinguish different bit lines in a memory array. For example, the bit line containing the selected memory cell is called BL, and the bit line sharing the read circuit with it is called BLN. This naming should not be construed as a limitation of this application.

[0058] Figure 3 This is a waveform diagram of a read / write operation of a memory provided by existing technology. Figure 3 Read and write operations and Figure 2 The array structure shown mainly includes a standby phase 310, a pre-charge phase 320, an activation phase 330, an amplification phase 340, a read / write phase 350, and a write-back phase 360. The dashed line of BL / BLN represents the voltage change on BL during the read / write process when the ferroelectric capacitor stores information of 1. The solid line of BL / BLN represents the voltage change in BLN when the ferroelectric capacitor stores information of 1.

[0059] Standby Phase 310: In the initial standby phase, WL is in a low voltage state V0, PL and BL / BLN are in a half-selection voltage state (1 / 2Vw), and the voltage of FG is also Vw / 2. At this time, the voltage difference of the ferroelectric capacitor is 0. Vw represents the write operation voltage. Under the voltage difference of Vw, the polarization state of the ferroelectric capacitor will change. V0 refers to a voltage of 0 volts.

[0060] Precharge phase 320: A read / write command begins in the precharge phase, pulling the BL voltage down to V0 and the BLN voltage up to the preset reference voltage value Vref.

[0061] Activation Phase 330: Pull WL up to Vw to turn on the selector transistor, passing the voltage (V0) of BL to FG, allowing BL to enter a floating state. Then pull PL up to Vw. If the information stored in the ferroelectric capacitor is 0, the voltage difference between PL and FG is Vw. During the activation operation, the voltage difference between PL and FG across the ferroelectric capacitor remains Vw. At this time, the polarization state of the ferroelectric capacitor does not change, there is no charge release, and the voltages of BL and FG will remain at V0. If the information stored in the ferroelectric capacitor is 1, the voltage difference between PL and FG is -Vw. During the activation operation, the voltage difference between PL and FG across the ferroelectric capacitor is Vw. At this time, the polarization state of the ferroelectric capacitor changes, and the charge release causes a certain increase in the voltages of FG and BL.

[0062] Amplification stage 340: In the amplification stage, the reference voltages Vref of BL and BLN are compared, and the voltage of BL is amplified to V0 or Vw by a sense amplifier (SA) 230. For example, if the voltage of BL is less than the reference voltage Vref, the voltage of BL is amplified to V0; if it is greater than the reference voltage Vref, it is amplified to Vw.

[0063] Read / Write Phase 350: Enters the continuous read / write phase. If a read operation is performed, the information stored on the BL is read. If a write operation is performed, the information stored on the BL is rewritten.

[0064] Write-back phase 360: Since the read operation is destructive and may affect the state of the ferroelectric capacitor, a "write-back" action is needed after the read / write operation is completed to rewrite the original data back into the memory cell; otherwise, errors may occur during the next read. During the write-back phase, the PL voltage is pulled low to V0, which allows the information stored on BL and FG to be written back to the ferroelectric capacitor.

[0065] Precharge phase 370: Restore the voltage of BL and FG to 1 / 2Vw, and then pull down the voltage of WL to V0 to turn off the selection transistor, thereby completing a read / write operation.

[0066] Figure 4 This is a schematic diagram illustrating a scenario where a ferroelectric capacitor is disturbed, as provided in an embodiment of this application.

[0067] Figure 4The two memory cells shown are connected to the same bit line BL0. The first memory cell is connected to word line WL0, and the second memory cell is connected to word line WL1. Each memory cell includes one transistor and n ferroelectric capacitors, where n ≥ 2. The capacitors in the first memory cell include a selected ferroelectric capacitor 410 and an unselected ferroelectric capacitor 420, and the capacitors in the second memory cell include unselected ferroelectric capacitors 430 and 440. The lower plate of the i-th ferroelectric capacitor in each memory cell is connected to FG, and the upper plate of the i-th ferroelectric capacitor is connected to PLi, where 0 ≤ i < n.

[0068] It should be understood that if either FG or PL is not selected for a ferroelectric capacitor, the ferroelectric capacitor is not selected. If both FG and PL for a ferroelectric capacitor are selected, the ferroelectric capacitor is selected. Figure 4 In the selected ferroelectric capacitor 410, both FG and PL are selected. In the unselected ferroelectric capacitor 420, FG is selected but PL is not selected. In the unselected ferroelectric capacitor 430, FG is not selected but PL is selected. In the unselected ferroelectric capacitor 440, neither FG nor PL is selected.

[0069] When m≥1 and n≥2, in the mTnC operation scheme, the unselected ferroelectric capacitor exhibits the following two types of half-selection voltage stress disturbances:

[0070] (1) Unilateral disturbance occurs at the selected FG and the unselected PL ferroelectric capacitor 420.

[0071] Figure 5 This is a schematic diagram illustrating a unilateral disturbance situation provided in an embodiment of this application. During a complete read / write cycle, the ferroelectric capacitor 420 at the selected FG and unselected PL locations experiences two types of unilateral disturbances under different stresses.

[0072] The first type of unilateral perturbation is a long-term stress unilateral perturbation that occurs during the read / write phase 350. Since the selected FG and BL are pulled to Vw or V0 by the sensitive amplifier, while the PL voltage connected to the unselected ferroelectric capacitor 420 is Vw / 2, there is a unidirectional voltage difference of +Vw / 2 or -Vw / 2 on the unselected ferroelectric capacitor 420 on the selected FG. This voltage difference can last from 4 nanoseconds (ns) to 72 microseconds (μs).

[0073] The second type of short-duration stress unilateral disturbance occurs in the activation phase 330 and the write-back phase 360. In the activation phase 330, the pre-charge voltage of the ferroelectric capacitor (FG) is V0, and in the write-back phase 360, the voltage of FG depends on the write-back information (V0 for write-back "0", Vw for write-back "1"). The duration of these two phases is related to the switching time of the ferroelectric capacitor and is therefore a short-duration stress.

[0074] These two types of unilateral disturbances will cause the loss of the residual polarization (Pr) of the ferroelectric capacitor 420 at the selected FG and the unselected PL, ultimately resulting in the loss of stored information.

[0075] (2) Bilateral disturbance, which occurs at the ferroelectric capacitor 430 at the unselected FG and the selected PL.

[0076] During a complete read / write cycle, the voltage of the unselected FG is Vw / 2. Since the PL is Vw during the activation phase and V0 during the write-back phase, the unselected ferroelectric capacitor 430 experiences a bidirectional voltage difference of ±Vw / 2 during a complete read / write operation cycle. Because the stress on the ferroelectric capacitor is relatively symmetrical due to bilateral disturbances, this scenario has little impact on the ferroelectric capacitor.

[0077] One-sided disturbances have severely hampered the development of mTnC ferroelectric memory. In addition to continuing to optimize the ferroelectric material itself, there are also some improvements in circuitry and operation to address the one-sided disturbance problem of ferroelectric capacitors during a complete access cycle.

[0078] Figure 6 This is a schematic diagram of another memory structure provided by existing technology.

[0079] Figure 6 The illustrated technical solution addresses the unilateral disturbance caused by prolonged stress on the ferroelectric capacitors at the selected FG and unselected PL points during the read / write phase 350 by adding two isolation (ISO) transistors to the circuit. Specifically, two ISO transistors are added between the sensitive amplifier 520 and the equalizer 510. After the sensitive amplifier 520 completes amplification, the two ISO transistors are turned off. At this point, the information from the ferroelectric capacitors is sensed by the sensitive amplifier 520, and then the equalizer 510 pre-charges BL and FG back to Vw / 2. Since all unselected PL points on the selected FG are at Vw / 2, there is no voltage difference across the ferroelectric capacitors. During the write-back phase 360, the ISO transistors are turned on, and FG is charged by the sensitive amplifier 320 to the required write-back voltage, completing the write-back process.

[0080] Figure 6 The technical solution shown solves the one-sided disturbance caused by long-term stress during the read / write phase 350, but one-sided disturbances caused by short-term stress during the activation phase 330 and write-back phase 360 ​​still exist. As the number of row activations increases, these one-sided disturbances caused by short-term stress accumulate, resulting in Pr loss in the ferroelectric capacitor. Therefore, this one-sided disturbance problem urgently needs to be solved.

[0081] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort should fall within the scope of protection of this application.

[0082] Figure 7 This is a schematic diagram of the structure of a memory provided in an embodiment of this application.

[0083] The memory provided in this application may include one or more memory arrays, wherein the first memory cell and the second memory cell can be regarded as any memory cell of the memory array, and each memory cell of the memory array includes multiple capacitors.

[0084] The memory provided in this application also includes a sensitive amplifier 610, a first isolator, a second isolator, a third isolator, and a fourth isolator. The first isolator is located on the first bit line and connects the first bit line to the first output of the sensitive amplifier. The second isolator is located on the second bit line and connects the second bit line to the second output of the sensitive amplifier. The first bit line and the second bit line are connected via a first conductor. The third and fourth isolators are located on two different first conductors; the third isolator connects the first bit line to the second output of the sensitive amplifier, and the fourth isolator connects the second bit line to the first output of the sensitive amplifier.

[0085] The first, second, third, and fourth isolators can be ISO tubes. Optionally, the first bit line can be represented by BL, and the second bit line can be represented by BLN.

[0086] The memory provided in this application also includes a controller 600, which can provide control signals to turn on the first and second isolators and turn off the third and fourth isolators before the write-back of the first memory cell is completed, and to turn off the first and second isolators and turn on the third and fourth isolators after the write-back of the first memory cell is completed.

[0087] Figure 8 This is a schematic diagram of another memory structure provided in an embodiment of this application.

[0088] The gate of memory cell 720 is connected to word line WL0, and its source or drain is connected to BL. The gate of memory cell 730 is connected to word line WL1, and its source or drain is connected to BLN. PCH0 and PCH1 are pre-charge (PCH) signals, used to pre-charge BL and BLN respectively. The pre-charge voltage can include V0, Vw / 2, and Vref. ISO0 is used to control the on and off of the sensitive amplifier 710 and BL / BLN, and ISO1 is used to control the on and off of BL and BLN.

[0089] Sensitive amplifier 710 amplifies the voltages of BL and BLN. The sense-amplifier n-FET control (SAN) and sense-amplifier p-FET control (SAP) provide power to the sensitive amplifier 710. The power values ​​of SAN and SAP determine the voltage levels to which the sensitive amplifier 710 amplifies the voltages of BL and BLN. For example, when SAN and SAP are 0 and Vw respectively, after SA completes its operation, the voltages of BL and BLN will be pulled down to 0 or Vw; when SAN and SAP are Vw and Vw / 2 respectively, after SA completes its operation, the voltages of BL and BLN will be pulled down to Vw or Vw / 2.

[0090] Figure 9 This is a schematic diagram of the read / write operation waveform of a memory provided in an embodiment of this application. Figure 9 The read and write operations shown are Figure 8 The storage array structure shown corresponds to this. The dashed line in FG represents the voltage change process during the read and write operation of the ferroelectric capacitor when the stored information is 1. The solid line in FG represents the voltage change process when the stored information is 0.

[0091] The read / write operations provided in this application mainly include a standby phase 810, an activation phase 820, a read / write phase 830, a write-back phase 840, and an exchange phase 850. Among them, the activation phase 820 includes a pre-charge phase 821, a destruction phase 823, a read phase 825, and an amplification phase 827.

[0092] (1) Standby stage 810: WL maintains voltage V0, BL, BLN and PL maintain voltage Vw / 2. At this time, the access transistor is turned off, the voltage of each FG is Vw / 2, the voltage difference across the ferroelectric capacitor is 0, and the polarization state remains unchanged.

[0093] (2) Activation phase 820:

[0094] a) Precharge stage 821: By setting the voltage on word line WL to the operating voltage (Vdd), the access transistor is turned on, and the V0 voltage on bit line BL is transferred to the floating gate FG. Additionally, BLN is precharged to V0 by transistor PCH1. In this embodiment, the precharge operation provides an initial potential for FG to ensure subsequent activation of the ferroelectric capacitor. Since it is undesirable for any ferroelectric capacitor's polarization state to change during this stage, the PL connected to the upper plates of the ferroelectric capacitors remains in a half-selected state with a voltage of Vw / 2.

[0095] b) Destruction stage 823: The voltages of BL and BLN are pre-charged to Vref using PCH0 and PCH1 transistors to prepare for subsequent reading and amplification by the sensitive amplifier 710.

[0096] The destruction of a ferroelectric capacitor is achieved by reducing WL to V0 to shut down the access transistor, causing FG to enter a floating state, thus ensuring that the precharge voltage on BL does not affect the voltage on FG.

[0097] In this embodiment, a ferroelectric capacitor is defined as being in a negative polarization state when its stored information is 1, and in a positive polarization state when its stored information is 0. A positive voltage difference between PL and FG represents the positive polarization direction, and a negative voltage difference between PL and FG represents the negative polarization direction.

[0098] Set the voltage on PL where the selected ferroelectric capacitor is located to Vw. If the selected ferroelectric capacitor is in a negative polarization state (the selected ferroelectric capacitor stores information 1), the polarization state of the selected ferroelectric capacitor will change from negative polarization to positive polarization because the voltage difference between PL and FG becomes positive polarization. During this process, the charge on the selected ferroelectric capacitor will enter FG, causing the voltage of FG to rise to Vfg1.

[0099] If the selected ferroelectric capacitor is in a positive polarization state (the selected ferroelectric capacitor stores 0 information), since the voltage difference between PL and FG is still in the positive polarization direction, the polarization state of the ferroelectric capacitor will not change, and the voltage of FG will not change, remaining at Vfg0. Because it is undesirable for the polarization state of unselected ferroelectric capacitors to change during this stage, the PL of unselected ferroelectric capacitors remains in a half-selection state with a voltage of Vw / 2.

[0100] Optionally, a negative voltage difference between PL and FG can be defined to represent the positive polarization direction, and a positive voltage difference between PL and FG can be defined to represent the negative polarization direction. This application does not impose any restrictions on this.

[0101] It should be understood that the destruction phase in this application can also be called the activation phase, and the activation phase can also be called the destruction phase. The specific name should not be construed as a limitation on this application.

[0102] c) Reading Phase 825: WL is raised to Vdd, the access transistor is turned on, and FG and BL begin charge sharing. Before charge sharing begins, the capacitance on FG is Cfg, and the voltage is Vfg. Before charge sharing begins, the capacitance on BL is CBL, and the voltage is Vref. After charge sharing is complete, the voltages on FG and BL become Vrd.

[0103] When the selected ferroelectric capacitor stores information 1, the voltage of FG before charge sharing begins is Vfg1, and after charge sharing is completed, the voltages on FG and BL become Vrd1; when the selected ferroelectric capacitor stores information 0, the voltage of FG before charge sharing begins is Vfg0, and after charge sharing is completed, the voltages on FG and BL become Vrd0.

[0104] According to the law of conservation of charge, it satisfies the following two relationships, where * represents multiplication:

[0105] Cfg*Vfg1+CBL*Vref=(Cfg+CBL)*Vrd1

[0106] Cfg*Vfg0+CBL*Vref=(Cfg+CBL)*Vrd0

[0107] d) Amplification stage 827: In this stage, the sensitive amplifier 710 starts to work. The two ends of the sensitive amplifier 710 are connected to BL and BLN respectively. Since the voltage of BL becomes Vrd0 or Vrd1 after charge sharing, while BLN is still Vref. When the information "1" is read, the voltage on BL is Vrd1 and BLN is Vref. Vrd1 is greater than Vref. At this time, BL is pulled to Vw / 2 by the sensitive amplifier 710, and BLN is pulled to V0 by the sensitive amplifier 710. When the information "0" is read, the voltage on BL is Vrd0 and BLN is Vref. Vrd0 is less than Vref. At this time, BL is pulled to V0 by the sensitive amplifier 710, and BLN is pulled to Vw / 2 by the sensitive amplifier 710.

[0108] (3) Read / Write Stage 830: During this stage, the sensitive amplifier 710 continuously drives BL and BLN at V0 or Vw / 2 to ensure normal read / write operations.

[0109] (4) Write-back stage 840: The voltage on WL is Vdd, and the access transistor is always in the on state. To write back the ferroelectric capacitor, a voltage difference of Vw needs to be established across the ferroelectric capacitor to change its polarization state and complete the write-back. In the read / write stage 830, the voltage of BL is always driven at V0 or Vw / 2. At this time, pulling PL to V0 will not complete the write-back because the voltage difference is insufficient. Therefore, in the write-back stage 840, SAN needs to be pulled from V0 to Vw / 2, and SAP needs to be pulled from Vw / 2 to Vw.

[0110] If the read information is "0", the positive polarization state is not destroyed during the destruction of the ferroelectric capacitor. BL is pulled to Vw / 2 by the sensitive amplifier 710, the voltage on FG is transferred to Vw / 2 through BL, and PL is V0. At this time, the voltage difference between PL and FG is -Vw / 2, and the ferroelectric capacitor continues to maintain its positive polarization state.

[0111] If the read information is "1", during the destruction of the ferroelectric capacitor, the negative polarization state is changed to positive polarization. In the write-back stage 840, BL is pulled to Vw by the sensitive amplifier 710, and the voltage on FG is transferred to Vw through BL. At this time, since the voltage difference between PL and FG is -Vw, the ferroelectric capacitor will be negatively polarized, thus completing the write-back.

[0112] (5) Swap Phase 850: After the write-back is completed, WL continues to maintain voltage Vdd, the access transistor is turned on, PL rises to Vw / 2, at this time the two ISO0s are turned off and the two ISO1s are turned on, and the voltages of BL and BLN will be swapped. It should be understood that before the swap phase, the two ISO1s are always in the off state.

[0113] If the write-back voltage of 840 is Vw / 2, then the FG voltage in the swapping stage becomes Vw through BL.

[0114] Table 1 shows the voltage values ​​of different lines at different stages of the read / write operation in this embodiment of the application. The voltage difference is the voltage difference between the ferroelectric capacitors at the selected FG and the unselected PL. For writing back "1", the precharge stage 821 and the write-back stage 840 form a bilateral disturbance; for writing back "0", the precharge stage 821 and the swapping stage 850 form a bilateral disturbance. This embodiment of the application converts the unilateral disturbance throughout the entire access cycle into a bilateral disturbance, reducing the impact of unilateral disturbances on the ferroelectric capacitors.

[0115] Table 1. Voltage of different lines at different stages of read / write operations.

[0116]

[0117] It should be understood that the mTnC ferroelectric memory in the above embodiments of this application is only an example. The technical solutions provided in the embodiments of this application can also be applied to memories made of other materials that have unilateral perturbation problems. Ferroelectric materials should not be construed as a limitation of this application.

[0118] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0119] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., optical disk), or a semiconductor medium (e.g., solid-state drive (SSD)).

[0120] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A memory, characterized in that, include: The first storage unit is a storage unit selected for read or write operations. The first storage unit includes a transistor and a plurality of ferroelectric capacitors. The first plate of each of the plurality of ferroelectric capacitors is connected to the floating gate of the transistor. A sensitive amplifier, a first bit line, and a second bit line, wherein the first bit line is connected to the first memory cell and the first output of the sensitive amplifier, and the second bit line is connected to the second output of the sensitive amplifier; A first isolator, a second isolator, a third isolator, and a fourth isolator, wherein the first isolator connects the first bit line and the first output of the sensitive amplifier, the second isolator connects the second bit line and the second output of the sensitive amplifier, the third isolator connects the first bit line and the second output of the sensitive amplifier, and the fourth isolator connects the second bit line and the first output of the sensitive amplifier; The controller is configured to turn on the first isolator and the second isolator and turn off the third isolator and the fourth isolator before the write-back of the first storage cell is completed, and to turn off the first isolator and the second isolator and turn on the third isolator and the fourth isolator after the write-back of the first storage cell is completed.

2. The memory according to claim 1, characterized in that, If the voltage of the first bit line is a first positive voltage and the voltage of the second bit line is a second positive voltage before the write-back is completed, then after the write-back is completed, the voltage of the first bit line is the second positive voltage and the voltage of the second bit line is the first positive voltage. If the voltage of the first bit line is the second positive voltage before the write-back is completed, and the voltage of the second bit line is the first positive voltage, then after the write-back is completed, the voltage of the first bit line is the first positive voltage, and the voltage of the second bit line is the second positive voltage.

3. The memory according to claim 2, characterized in that, The first positive voltage = Vw / 2, the second positive voltage = Vw, where Vw represents the write operation voltage of the first memory cell.

4. The memory according to claim 1, characterized in that, The first isolator is located between the third isolator and the sensitive amplifier, and the second isolator is located between the fourth isolator and the sensitive amplifier.

5. The memory according to claim 1, characterized in that, After the write-back is completed, the voltage of the floating gate is the same as that of the first bit line.

6. The memory according to claim 1, characterized in that, The first isolator, the second isolator, the third isolator, and the fourth isolator all include isolating ISO tubes.

7. The memory according to any one of claims 1 to 6, characterized in that, The first bit line and the second bit line are connected by a first conductor. The first isolator is located on the first bit line, the second isolator is located on the second bit line, and the third isolator and the fourth isolator are located on the first conductor.

8. A method for accessing a memory, characterized in that, The method is applied to a memory comprising a first storage cell, a sensitive amplifier, a first bit line, a second bit line, a first isolator, a second isolator, a third isolator, a fourth isolator, and a controller. The first storage cell is a selected storage cell for read or write operations. The first storage cell includes a transistor and a plurality of ferroelectric capacitors. The first plate of each ferroelectric capacitor is connected to the floating gate of the transistor. The first bit line connects the first storage cell and the first output of the sensitive amplifier. The second bit line connects the second output of the sensitive amplifier. The first isolator connects the first bit line and the first output of the sensitive amplifier. The second isolator connects the second bit line and the second output of the sensitive amplifier. The third isolator connects the first bit line and the second output of the sensitive amplifier. The fourth isolator connects the second bit line and the first output of the sensitive amplifier. The method includes: Before the write-back of the first storage cell is completed, the controller turns on the first isolator and the second isolator, and turns off the third isolator and the fourth isolator. After the write-back of the first storage unit is completed, the controller shuts down the first isolator and the second isolator, and turns on the third isolator and the fourth isolator.

9. The method according to claim 8, characterized in that, If the voltage of the first bit line is a first positive voltage and the voltage of the second bit line is a second positive voltage before the write-back is completed, then after the write-back is completed, the voltage of the first bit line is the second positive voltage and the voltage of the second bit line is the first positive voltage. If the voltage of the first bit line is the second positive voltage before the write-back is completed, and the voltage of the second bit line is the first positive voltage, then after the write-back is completed, the voltage of the first bit line is the first positive voltage, and the voltage of the second bit line is the second positive voltage.

10. The method according to claim 9, characterized in that, The first positive voltage = Vw / 2, the second positive voltage = Vw, where Vw represents the write operation voltage of the first memory cell.

11. The method according to any one of claims 8 to 10, characterized in that, After the write-back is completed, the voltage of the floating gate is the same as that of the first bit line.

12. An integrated circuit, characterized in that, Includes the memory as described in any one of claims 1 to 7.

13. An electronic device, characterized in that, The invention includes a circuit board and a memory according to any one of claims 1 to 7, wherein the memory is disposed on the circuit board and electrically connected to the circuit board.

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