Non-zero offset determination method and apparatus
By classifying and analyzing historical batch wafer stacking data, non-zero offsets are dynamically determined, solving the problem of low stacking error accuracy in traditional compensation methods and improving compensation accuracy and device performance in semiconductor manufacturing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-06-28
- Publication Date
- 2026-05-19
AI Technical Summary
In traditional semiconductor manufacturing processes, a fixed non-zero offset is used for compensation, which results in low accuracy of stacking error compensation and affects device performance.
By acquiring wafer stacking data of multiple historical batches in the target material layer, classifying them according to the process environment, and calculating the stacking error under various process environments based on big data analysis, the non-zero offset of the current batch is dynamically determined.
It improves the accuracy of stacking error compensation, ensures the performance stability of semiconductor devices, and reduces device failures caused by stacking errors.
Smart Images
Figure CN117352407B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method and apparatus for determining non-zero offset (NZO). Background Technology
[0002] Semiconductor devices are manufactured by producing stacked patterned and unpatterned material layers. Since the features of the patterned material layers are spatially related, each patterned material layer needs to be aligned with the previous patterned material layer.
[0003] In the semiconductor manufacturing process, it is necessary to inspect the alignment between material layers on the semiconductor substrate, i.e., the overlay condition. If the overlay error is large, corresponding compensation measures need to be taken; otherwise, it will directly affect the performance of the semiconductor device.
[0004] However, traditional compensation methods typically use a fixed non-zero offset for all batches of semiconductor devices, resulting in low compensation accuracy. Summary of the Invention
[0005] This disclosure provides a method and apparatus for determining non-zero offsets, which can solve the technical problem of low accuracy in the compensation methods for overlapping errors in the prior art.
[0006] In a first aspect, embodiments of this disclosure provide a method for determining a non-zero offset, the method comprising:
[0007] Obtain the stacking data of wafers in the target material layer from multiple historical batches prior to the current batch;
[0008] The wafers from each of the aforementioned historical batches were classified according to their process environment;
[0009] Based on the stacking data of wafers in various process environments for each historical batch, the stacking error of wafers in each historical batch under various process environments is determined.
[0010] Based on the stacking errors of wafers in each historical batch under various process environments, the non-zero offset of the target material layer corresponding to the current batch of wafers under various process environments is determined.
[0011] In some embodiments, obtaining wafer stacking data in the target material layer from multiple historical batches prior to the current batch includes:
[0012] Acquire the after-development inspection (ADI) and after-etch inspection (AEI) overlay data of the wafers in the target material layer from the multiple historical batches.
[0013] In some embodiments, determining the stacking error of each historical batch of wafers under various process environments based on the stacking data corresponding to each historical batch of wafers under various process environments includes:
[0014] By iterating through each of the historical batches and various process environments, the difference between the ADI stacking data and the AEI stacking data of the wafers in the first historical batch under the first process environment is calculated, and the difference is determined as the stacking error of the wafers in the first historical batch under the first process environment.
[0015] In some embodiments, determining the non-zero offset of the target material layer corresponding to the current batch of wafers under various process environments based on the stacking errors of wafers in each historical batch under various process environments includes:
[0016] By iterating through all the aforementioned process environments, the average stacking error of each historical batch of wafers under the first process environment is calculated, and the average value is determined as the non-zero offset of the target material layer corresponding to the current batch of wafers under the first process environment.
[0017] In some embodiments, determining the non-zero offset of the target material layer corresponding to the current batch of wafers under various process environments based on the stacking errors of wafers in each historical batch under various process environments includes:
[0018] The weight of each historical batch of wafers is determined based on the exposure time.
[0019] By traversing all the aforementioned process environments, and based on the weights corresponding to the wafers of each historical batch, the weighted average of the stacking errors of the wafers in each historical batch under the traversed first process environment is calculated, and the weighted average is determined as the non-zero offset of the target material layer corresponding to the wafer of the current batch under the first process environment.
[0020] In some embodiments, classifying the wafers from each historical batch according to the process environment includes:
[0021] The wafers from the various historical batches are classified according to the process environment information of each historical batch during the photolithography process.
[0022] The process environment information includes at least one of the following: exposure machine identifier, exposure machine suction cup identifier, etching machine identifier, etching chamber identifier, and etching machine running time;
[0023] And / or, including at least one of the following process environment information: the exposure machine identifier, exposure machine chuck identifier, etching machine identifier, etching chamber identifier, and etching machine runtime of the reference material layer of the target material layer corresponding to each of the historical batches of wafers during the photolithography process.
[0024] In some embodiments, it also includes:
[0025] Based on the alignment tree and stacking error tree corresponding to the target material layer, the reference material layer corresponding to the target material layer is determined. The reference material layer is the material layer in each of the historical batches of wafers that was photolithographically processed before the target material layer.
[0026] Obtain the stacking data of wafers from multiple historical batches prior to the current batch on the reference material layer;
[0027] The step of determining the stacking error of each historical batch of wafers under various process environments based on the stacking data corresponding to each historical batch of wafers under various process environments includes:
[0028] Based on the stacking data corresponding to the target material layer and the reference material layer for each of the historical batches of wafers under various process environments, the stacking error of each of the historical batches of wafers under various process environments is determined.
[0029] Secondly, embodiments of this disclosure provide a non-zero offset determination device, the device comprising:
[0030] The acquisition module is used to acquire the stacking data of wafers in the target material layer from multiple historical batches prior to the current batch.
[0031] The classification module is used to classify the wafers from each of the historical batches according to the process environment;
[0032] The first calculation module is used to determine the stacking error of the wafers in each historical batch under various process environments based on the stacking data corresponding to the wafers in each historical batch under various process environments.
[0033] The second calculation module is used to determine the non-zero offset of the target material layer corresponding to the current batch of wafers under various process environments based on the stacking error of the wafers in each historical batch under various process environments.
[0034] In some embodiments, the acquisition module is used to:
[0035] Acquire the ADI stacking data and AEI stacking data of the wafers in the target material layer from the multiple historical batches.
[0036] In some embodiments, the first computing module is used to:
[0037] By iterating through each of the historical batches and various process environments, the difference between the ADI stacking data and the AEI stacking data of the wafers in the first historical batch under the first process environment is calculated, and the difference is determined as the stacking error of the wafers in the first historical batch under the first process environment.
[0038] In some embodiments, the second computing module is used for:
[0039] By iterating through all the aforementioned process environments, the average stacking error of each historical batch of wafers under the first process environment is calculated, and the average value is determined as the non-zero offset of the target material layer corresponding to the current batch of wafers under the first process environment.
[0040] In some embodiments, the second computing module is used for:
[0041] The weight of each historical batch of wafers is determined based on the exposure time.
[0042] By traversing all the aforementioned process environments, and based on the weights corresponding to the wafers of each historical batch, the weighted average of the stacking errors of the wafers in each historical batch under the traversed first process environment is calculated, and the weighted average is determined as the non-zero offset of the target material layer corresponding to the wafer of the current batch under the first process environment.
[0043] In some embodiments, the classification module is used for:
[0044] The wafers from the various historical batches are classified according to the process environment information of each historical batch during the photolithography process.
[0045] The process environment information includes at least one of the following: exposure machine identifier, exposure machine suction cup identifier, etching machine identifier, etching chamber identifier, and etching machine running time;
[0046] And / or, including at least one of the following process environment information: the exposure machine identifier, exposure machine chuck identifier, etching machine identifier, etching chamber identifier, and etching machine runtime of the reference material layer of the target material layer corresponding to each of the historical batches of wafers during the photolithography process.
[0047] In some embodiments, a determining module is further included, configured to:
[0048] Based on the alignment tree and stacking error tree corresponding to the target material layer, the reference material layer corresponding to the target material layer is determined. The reference material layer is the material layer in each of the historical batches of wafers that was photolithographically processed before the target material layer.
[0049] The acquisition module is also used for:
[0050] Obtain the stacking data of wafers from multiple historical batches prior to the current batch on the reference material layer;
[0051] The first calculation module is also used for:
[0052] Based on the stacking data corresponding to the target material layer and the reference material layer for each of the historical batches of wafers under various process environments, the stacking error of each of the historical batches of wafers under various process environments is determined.
[0053] Thirdly, embodiments of this disclosure provide an electronic device, including: at least one processor and a memory;
[0054] The memory stores computer-executed instructions;
[0055] The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the non-zero offset determination method as provided in the first aspect.
[0056] Fourthly, this disclosure provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the non-zero offset determination method provided in the first aspect.
[0057] The non-zero offset determination method and apparatus provided in this disclosure classify wafers from multiple historical batches prior to the current batch according to the process environment, and dynamically determine the non-zero offset of the target material layer corresponding to the current batch wafer under various process environments based on the stacking error of each historical batch wafer under various process environments. Compared with the method of using a fixed non-zero offset for compensation, the accuracy is higher. Attached Figure Description
[0058] Figure 1 A schematic diagram of the architecture of a non-zero offset control system provided in an embodiment of this disclosure;
[0059] Figure 2 A flowchart illustrating a method for determining a non-zero offset provided in an embodiment of this disclosure;
[0060] Figure 3 This is a schematic diagram of a portion of a material layer on a wafer provided in an embodiment of this disclosure;
[0061] Figure 4 This is a schematic diagram of a program module for a non-zero offset determination device provided in an embodiment of the present disclosure;
[0062] Figure 5 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation
[0063] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. Furthermore, although the disclosure in this disclosure is based on one or several exemplary examples, it should be understood that each aspect of these disclosures can also constitute a complete implementation method on its own.
[0064] It should be noted that the brief descriptions of terms in this disclosure are only for the convenience of understanding the embodiments described below, and are not intended to limit the embodiments of this disclosure. Unless otherwise stated, these terms should be understood in their ordinary and common meaning.
[0065] The terms "first," "second," etc., used in this disclosure, the specification, claims, and the accompanying drawings are used to distinguish similar or related objects or entities and do not necessarily imply a specific order or sequence, unless otherwise specified. It should be understood that such terms can be used interchangeably where appropriate, for example, in situations where implementation can proceed in an order other than those given in the illustrations or description of embodiments of this disclosure.
[0066] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover but not exclusively include, for example, a product or device that includes a series of components is not necessarily limited to those that are explicitly listed, but may include other components that are not explicitly listed or that are inherent to such product or device.
[0067] As used in this disclosure, the term "module" means any known or subsequently developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and / or software code capable of performing the functions associated with that element.
[0068] In the field of semiconductor technology, semiconductor devices are manufactured by producing stacked patterned and unpatterned material layers. Since the features of the patterned material layers are spatially related, each patterned material layer needs to be aligned with the previous patterned material layer during the manufacturing process.
[0069] In the semiconductor manufacturing process, the overlay error between material layers on the semiconductor substrate (such as a wafer) is usually detected. If the overlay error is large, corresponding compensation measures need to be taken. Otherwise, it will directly affect the performance of the semiconductor device, and may even cause the device to fail due to short circuit caused by misalignment of the interconnect layers.
[0070] In some embodiments of this disclosure, taking photolithography as an example, photolithography is an important step in semiconductor device manufacturing. This step uses exposure and development to etch geometric patterns on a photoresist layer, and then uses an etching process to transfer the pattern on the photomask onto the substrate. During the fabrication of each material layer, the alignment accuracy between it and the previous layer must be measured. If the measured value exceeds the requirements, i.e., there is a positioning error between the upper and lower exposed imaging pattern layers, an overlap error will occur.
[0071] In some embodiments, the after-development inspection (ADI) stack and the after-etch inspection (AEI) stack are typically measured separately. When the ADI stack meets the requirements, there may be a stacking error between the AEI stack and the ADI stack. Therefore, in order to ensure that the AEI stack meets the requirements, an offset needs to be given to the ADI stack. This offset is the non-zero offset, i.e., NZO.
[0072] The value of NZO is usually determined based on the difference between the ADI stack and the AEI stack, such as NZO = ADI - AEI.
[0073] Overlay errors can be introduced from various sources. For example, overlay errors can occur during exposure steps in one or more exposure fields; or they can be caused by process errors, such as deformation of the exposed pattern during photolithography, etching-induced errors, or errors associated with variations in the sample.
[0074] In traditional photolithography, a run-to-run (R2R) system is typically used to control the stacking of semiconductor devices. After determining the non-zero offset of the first batch of semiconductor devices, this non-zero offset is usually applied to the manufacturing process of all subsequent batches. However, the stacking errors caused by different batches of semiconductor devices, or even within the same batch but under different photolithography environments, may vary. If a fixed non-zero offset is used to compensate for all batches of semiconductor devices, the compensation accuracy will be low.
[0075] To address the aforementioned technical problems, this disclosure provides a non-zero offset control method. During the photolithography process, wafers from multiple historical batches preceding the current batch are classified according to the process environment. Based on the stacking errors of each historical batch under various process environments, big data analysis is used to dynamically determine the non-zero offset of the target material layer corresponding to the current batch of wafers under various process environments. Compared to using a fixed non-zero offset for compensation, this method offers higher accuracy. Detailed embodiments are described below.
[0076] Reference Figure 1 , Figure 1 This is a schematic diagram of the architecture of a non-zero offset control system provided in an embodiment of the present disclosure.
[0077] The photolithography process typically includes three steps: exposure, development, and etching. In some embodiments of this disclosure, ADI metrology tools can be used to measure ADI stacking data on the substrate near the development step without damaging the substrate.
[0078] In some embodiments, the ADI metrology tools described above include optical metrology tools that perform non-destructive measurements with high accuracy and high sampling rates.
[0079] In some embodiments, AEI stack data can be measured using an AEI metrology tool after the etching step.
[0080] In some embodiments, the aforementioned AEI metrology tool may be a particle-based metrology tool, such as an electron beam metrology tool or an ion beam metrology tool.
[0081] In some embodiments, the same material layer of multiple batches of wafers can be photolithographically processed sequentially according to the above photolithography steps, and during the photolithography process, the ADI stacking data and AEI stacking data of each batch of wafers corresponding to the above material layer can be statistically analyzed using a statistical module.
[0082] In some embodiments, the calculation and analysis module can obtain the ADI stacking data and AEI stacking data of the most recently statistically analyzed batches of wafers in the above-mentioned material layer from the statistics module according to the exposure time, and then use a preset big data processing method to calculate the non-zero offset of the current batch of wafers in the above-mentioned material layer, and use the non-zero offset to perform photolithography on the above-mentioned material layer of the current batch of wafers.
[0083] Reference Figure 2 , Figure 2 This is a flowchart illustrating a non-zero offset determination method provided in an embodiment of this disclosure. In one feasible implementation, the non-zero offset determination method includes:
[0084] S201. Obtain the stacking data of wafers in the target material layer from multiple historical batches prior to the current batch.
[0085] In some embodiments, before performing photolithography on the current batch of wafers, the above-mentioned calculation and analysis module can obtain the stacking data of wafers from multiple historical batches before the current batch in the target material layer from the above-mentioned statistics module, including ADI stacking data and AEI stacking data.
[0086] Each batch of wafers may include multiple material layers, and each material layer may contain various materials, such as, but not limited to, photoresist, dielectric materials, conductive materials, or semiconductive materials.
[0087] S202. Classify the wafers from each historical batch according to the process environment.
[0088] It is understandable that wafers from the same batch may undergo photolithography processing in different environments. For example, a single exposure machine typically includes multiple chucks, while a single etching machine typically includes multiple etching chambers. After multiple wafers from the same batch have undergone photolithography processing using different exposure machine chucks or different etching chambers, the stacking errors between the individual wafers may differ.
[0089] In some embodiments of this disclosure, wafers from different historical batches can be classified according to the photolithography process environment.
[0090] S203. Based on the stacking data of wafers in various historical batches under various process environments, determine the stacking error of wafers in various historical batches under various process environments.
[0091] For example, suppose that before performing photolithography on the target material layer of the current batch of wafers, the stacking data of the wafers from the previous three historical batches on the target material layer were obtained based on the exposure time; and suppose that the exposure machine has two chucks, chuck1 and chuck2, and in each historical batch, half of the wafers are exposed on chuck1 and the other half of the wafers are exposed on chuck2, then the stacking error of each historical batch of wafers under the two process environments can be calculated in the following way:
[0092] NZO (Chuck1) lotN =ADI(Chuck1) lotN -AEI(Chuck1) lotN ;
[0093] NZO (Chuck2) lotN =ADI(Chuck2) lotN -AEI(Chuck2) lotN ;
[0094] Among them, NZO(Chuck1) lotN ADI(Chuck1) represents the stacking error of the target material layer corresponding to the Nth historical batch of wafers in the chuck1 environment. lotN This represents the ADI stacking data of the target material layer corresponding to the Nth historical batch of wafers in the chuck1 environment, AEI(Chuck1). lotN This represents the AEI stacking data of the target material layer corresponding to the Nth historical batch of wafers in the chuck1 environment. NZO(Chuck2) lotN ADI(Chuck2) represents the stacking error of the target material layer corresponding to the Nth historical batch of wafers in the chuck2 environment. lotN This represents the ADI stacking data of the target material layer corresponding to the Nth historical batch of wafers in the chuck2 environment, AEI(Chuck2). lotN This represents the AEI stacking data of the target material layer corresponding to the Nth historical batch of wafers in the chuck2 environment; N = 1, 2, 3;
[0095] S204. Based on the stacking errors of wafers in various historical batches under various process environments, determine the non-zero offset of the target material layer corresponding to the current batch of wafers under various process environments.
[0096] In some embodiments of this disclosure, big data analysis can be used to determine the non-zero offset of the target material layer corresponding to the current batch of wafers under various process environments, based on the stacking errors of wafers in various historical batches under various process environments.
[0097] For example, the average of the stacking errors of wafers in various historical batches under various process environments can be calculated as the non-zero offset of the target material layer corresponding to the current batch of wafers under various process environments:
[0098] NZO (Chuck1) avg =[NZO(Chuck1)] lot1 +NZO(Chuck1) lot2 +NZO(Chuck1) lot3 ] / 3;
[0099] NZO (Chuck2) avg =[NZO(Chuck2)] lot1 +NZO(Chuck2) lot2 +NZO(Chuck2) lot3 ] / 3;
[0100] Among them, NZO(Chuck1) avg NZO (Chuck2) can be used as the target material layer for the current batch of wafers in a chuck1 environment. avg It can be used as the non-zero offset of the target material layer corresponding to the current batch of wafers in the chuck2 environment.
[0101] In some embodiments of this disclosure, after determining the non-zero offset of the target material layer corresponding to the current batch of wafers under various process environments, photolithography is performed on the target material layer corresponding to the current batch of wafers according to the process environment corresponding to the target material layer corresponding to the current batch of wafers.
[0102] It is understandable that after photolithography is performed on the target material layer corresponding to the current batch of wafers, when photolithography is performed on the next batch of wafers, the stacking data of the target material layer of the previous batches (including the current batch) are also obtained, and then the non-zero offset of the target material layer corresponding to the next batch of wafers under various process environments is re-determined.
[0103] The non-zero offset determination method provided in this embodiment classifies wafers from multiple historical batches prior to the current batch according to the process environment, and dynamically determines the non-zero offset of the target material layer corresponding to the current batch wafer under various process environments based on the stacking error of each historical batch wafer under various process environments. Compared with the method of using a fixed non-zero offset for compensation, it has higher accuracy.
[0104] Based on the content described in the above embodiments, in some embodiments of this disclosure, the wafers of the above-mentioned multiple historical batches are classified according to the process environment information of each historical batch of wafers during the photolithography process.
[0105] The aforementioned process environment information includes at least one of the following: exposure machine identifier, exposure machine suction cup identifier, etching machine identifier, etching chamber identifier, and etching machine running time.
[0106] For example, in some embodiments, wafers can be classified according to the chuck markings of the exposure machine, such that wafers exposed by the same chuck in the same batch are classified into the same category.
[0107] For example, assuming that wafers in the same batch are exposed using an exposure machine with n suction cups, the wafers in the same batch can be divided into n categories based on the suction cup markings.
[0108] In some embodiments, wafers can be classified according to the etching machine identifier and the etching chamber identifier, such that wafers etched by the same etching machine and the same etching chamber in the same batch are classified into the same category.
[0109] For example, assuming that wafers in the same batch are etched simultaneously using two etching machines (represented by EHtool1 and EHtool2 respectively), and each etching machine has two etching chambers (represented by Chamber1 and Chamber2 respectively), then the wafers in the same batch can be divided into 4 categories based on the etching machine identifier and the etching chamber identifier: EHtool1_Chamber1, EHtool1_Chamber2, EHtool2_Chamber1, and EHtool2_Chamber2.
[0110] In some embodiments, the wafers can be classified according to the etching machine lifetime, such as classifying wafers from the same batch whose etching machine lifetime is within the same range into the same category.
[0111] For example, wafers etched before the etching machine runs for 600 minutes are classified into one category, and wafers etched after the etching machine runs for 600 minutes are classified into another category.
[0112] In some embodiments, classification can also be achieved by combining any combination of the above-mentioned exposure machine chuck markings, etching machine markings, etching chamber markings, and etching machine runtime. For example, wafers from the same batch that are exposed by the same chuck and etched by the same etching machine and the same etching chamber can be classified into the same category. This will not be elaborated further in the embodiments of this disclosure.
[0113] Based on the content described in the above embodiments, in some embodiments of this disclosure, the above process environment information may include at least one of the following process environment information: the exposure machine identifier, exposure machine chuck identifier, etching machine identifier, etching cavity identifier, and etching machine runtime of the reference material layer of the target material layer corresponding to each historical batch of wafers during the photolithography process.
[0114] Understandably, in the photolithography process, assuming material layer A is processed before material layer B, since the alignment marks are located in material layer A, the photolithography machine uses the alignment marks formed on material layer A on the wafer for alignment when exposing material layer B. Simultaneously, the required stacking accuracy of material layer B relative to material layer A means that stacking accuracy control needs to compensate for the stacking error of layer B relative to material layer A, ensuring that the stacking error of material layer B relative to material layer A is within a preset range.
[0115] In some embodiments of this disclosure, wafers from different historical batches can be classified based on the exposure machine identifier and exposure machine chuck identifier corresponding to the reference material layer of the target material layer in the photolithography process.
[0116] For example, assuming that the reference material layer of the target material layer of the wafers in the same batch is exposed using two exposure machines (represented by Referencetool1 and Referencetool2 respectively) during the photolithography process, and each exposure machine includes two chucks (represented by Chuck1 and Chuck2 respectively), then the wafers in the same batch can be divided into 4 categories according to the exposure machine identifier and the chuck identifier: Referencetool1_Chuck1, Referencetool1_Chuck2, Referencetool2_Chuck1, and Referencetool2_Chuck2.
[0117] In some embodiments of this disclosure, wafers can be classified according to the etching machine identifier and etching cavity identifier corresponding to the reference material layer of the target material layer in the photolithography process for each historical batch of wafers. For example, wafers etched by the same etching machine and the same etching cavity can be classified into the same category.
[0118] For example, assuming that the reference material layer of the target material layer of wafers in the same batch is etched simultaneously using two etching machines (represented by Pretool1 and Pretool2 respectively) during the photolithography process, and each etching machine has two etching chambers (represented by Chamber1 and Chamber2 respectively), then wafers in the same batch can be divided into 4 categories based on the etching machine identifier and the etching chamber identifier, namely: Pretool1_Chamber1, Pretool1_Chamber2, Pretool2_Chamber1, and Pretool2_Chamber2.
[0119] In some embodiments, the wafers can be classified according to the etching machine identifier and etching machine lifetime corresponding to the reference material layer of the target material layer in each historical batch during the photolithography process.
[0120] For example, suppose that the reference material layer of the target material layer of the wafers in the same batch is etched simultaneously using two etching machines (referred to as Pretool1 and Pretool2 respectively) during the photolithography process. If the wafers etched before the etching machine runs for 600 minutes are divided into one category and the wafers etched after the etching machine runs for 600 minutes are divided into another category, then the wafers in the same batch can be divided into 4 categories: Pretool1_before 600 minutes, Pretool1_after 600 minutes, Pretool2_before 600 minutes, and Pretool2_before 600 minutes.
[0121] In some embodiments, classification can also be performed by combining any combination of the above-mentioned exposure machine identifier, exposure machine chuck identifier, etching machine identifier, etching chamber identifier, and etching machine runtime of the reference material layer of the target material layer corresponding to each historical batch of wafers during the photolithography process. For example, wafers in the same batch that are exposed by the same chuck and etched by the same etching machine and the same etching chamber can be classified into the same category, which will not be elaborated further in this disclosure.
[0122] The non-zero offset determination method provided in this disclosure can provide differentiated non-zero offset compensation by classifying wafers from multiple historical batches prior to the current batch according to the process environment, which helps to improve the accuracy of compensation.
[0123] Based on the content described in the above embodiments, in some embodiments of this disclosure, after classifying the wafers of each historical batch according to the process environment, the stacking error of each historical batch of wafers in various process environments can be determined based on the stacking data corresponding to each historical batch of wafers in various process environments.
[0124] In one feasible implementation, each historical batch and various process environments can be traversed, and the difference between the ADI stacking data and the AEI stacking data corresponding to the wafer of the first historical batch traversed in the first process environment can be calculated, and the difference can be determined as the stacking error of the wafer of the first historical batch in the first process environment.
[0125] In some embodiments of this disclosure, after determining the stacking error of wafers in various historical batches under various process environments, the non-zero offset of the target material layer corresponding to the current batch of wafers under various process environments can be determined based on the stacking error of wafers in various historical batches under various process environments.
[0126] In one feasible implementation, various process environments can be traversed, and the average value of the stacking error of each historical batch of wafers in the traversed first process environment can be calculated. This average value is then determined as the non-zero offset of the target material layer corresponding to the current batch of wafers in the first process environment.
[0127] In some embodiments of this disclosure, the weight of each historical batch of wafers can be predetermined based on the exposure time. For example, the historical batch whose exposure time is closer to the current batch has a greater weight.
[0128] After determining the stacking error of wafers in various historical batches under various process environments, it is possible to iterate through various process environments, calculate the weighted average of the stacking error of wafers in the first process environment traversed according to the weight of wafers in each historical batch, and determine the weighted average as the non-zero offset of the target material layer corresponding to the current batch of wafers in the first process environment.
[0129] In some embodiments of this disclosure, a non-zero offset standard value can be preset. After determining the non-zero offset of the target material layer corresponding to the current batch of wafers in any type of process environment, if the determined non-zero offset is greater than the above-mentioned non-zero offset standard value, the non-zero offset can be automatically filtered. The filtered non-zero offset is not sent to the exposure machine.
[0130] The non-zero offset determination method provided in this embodiment classifies wafers from multiple historical batches prior to the current batch according to the process environment, and dynamically determines the non-zero offset of the target material layer corresponding to the current batch wafer under various process environments based on the stacking error of each historical batch wafer under various process environments. Compared with the method of using a fixed non-zero offset for compensation, it has higher accuracy.
[0131] Based on the description in the above embodiments, in some embodiments, before measuring the stacking data of each batch of wafers on the target material layer, a reference material layer corresponding to the target material layer can be determined according to the alignment tree and stacking error tree corresponding to the target material layer. The reference material layer is the material layer in each batch of wafers that undergoes photolithography processing before the target material layer. For example, the reference material layer can be the material layer preceding the target material layer.
[0132] In some embodiments, stacking data of wafers from multiple historical batches prior to the current batch on the aforementioned reference material layer can also be obtained. When determining the stacking error of wafers in various historical batches under various process environments, the stacking error of wafers in various historical batches under various process environments can be determined based on the stacking data of wafers in various historical batches on the target material layer and on the reference material layer under various process environments.
[0133] To better understand the embodiments of this disclosure, please refer to... Figure 3 , Figure 3 This is a schematic diagram of a portion of the material layer of a wafer provided in an embodiment of this disclosure.
[0134] exist Figure 3 In this process, layer A is lithographically processed before layer B, and layer B is lithographically processed before layer C. Assuming the alignment mark is located in layer A, the lithography machine uses the alignment mark formed on layer A on the wafer for alignment when exposing layers B and C. Simultaneously, the stacking accuracy requirements for layers B and C are relative to layer A. This means that in controlling the stacking accuracy, it is necessary to compensate for the stacking errors of layer B relative to layer A, as well as the stacking errors of layer C relative to layer A, so that these errors are within a preset range.
[0135] In some embodiments of this disclosure, it can be determined whether layer C and layer B are aligned with the same reference layer by checking if their alignment trees are identical. The alignment tree of the current layer describes the alignment marks of a certain layer on the wafer used during the exposure of the current layer. When the alignment trees of layer C and layer B are identical, it indicates that they are aligned with the alignment marks of the same layer during exposure, meaning they are aligned with the same reference layer.
[0136] Optionally, whether the stacking accuracy requirements of layers C and B are both relative to the reference layer can be determined by the overlay error trees of layers C and B. The overlay error tree of the current layer describes the measurement and feedback compensation of the stacking data of a certain layer on the wafer by the current layer. If the overlay error trees of layers C and B are the same, it means that both are performing overlay error control relative to the same layer, i.e., their stacking accuracy requirements are both relative to the same reference layer.
[0137] The non-zero offset determination method provided in this disclosure determines the reference material layer corresponding to the target material layer based on the alignment tree and stacking error tree corresponding to the target material layer. This allows for more accurate measurement of the stacking data of each batch of wafers on the target material layer according to the same standard, thereby improving the accuracy of non-zero offset compensation.
[0138] Based on the content described in the above embodiments, this disclosure also provides a non-zero offset determination device. (Refer to...) Figure 4 , Figure 4 This is a schematic diagram of a program module for a non-zero offset determination device provided in an embodiment of this disclosure. The non-zero offset determination device includes:
[0139] The acquisition module 401 is used to acquire the stacking data of wafers in the target material layer from multiple historical batches prior to the current batch.
[0140] The classification module 402 is used to classify the wafers of each of the historical batches according to the process environment;
[0141] The first calculation module 403 is used to determine the stacking error of the wafers in each historical batch under various process environments based on the stacking data corresponding to the wafers in each historical batch under various process environments.
[0142] The second calculation module 404 is used to determine the non-zero offset of the target material layer corresponding to the current batch of wafers under various process environments based on the stacking error of the wafers in each historical batch under various process environments.
[0143] The non-zero offset determination device provided in this embodiment classifies wafers from multiple historical batches prior to the current batch according to the process environment, and dynamically determines the non-zero offset of the target material layer corresponding to the current batch wafer under various process environments based on the stacking error of each historical batch wafer under various process environments. Compared with the method of using a fixed non-zero offset for compensation, it has higher accuracy.
[0144] In some embodiments, the acquisition module 401 is used for:
[0145] Acquire the ADI stacking data and AEI stacking data of the wafers in the target material layer from the multiple historical batches.
[0146] In some embodiments, the first computing module 403 is used for:
[0147] By iterating through each of the historical batches and various process environments, the difference between the ADI stacking data and the AEI stacking data of the wafers in the first historical batch under the first process environment is calculated, and the difference is determined as the stacking error of the wafers in the first historical batch under the first process environment.
[0148] In some embodiments, the second computing module 404 is used for:
[0149] By iterating through all the aforementioned process environments, the average stacking error of each historical batch of wafers under the first process environment is calculated, and the average value is determined as the non-zero offset of the target material layer corresponding to the current batch of wafers under the first process environment.
[0150] In some embodiments, the second computing module 404 is used for:
[0151] The weight of each historical batch of wafers is determined based on the exposure time.
[0152] By traversing all the aforementioned process environments, and based on the weights corresponding to the wafers of each historical batch, the weighted average of the stacking errors of the wafers in each historical batch under the traversed first process environment is calculated, and the weighted average is determined as the non-zero offset of the target material layer corresponding to the wafer of the current batch under the first process environment.
[0153] In some embodiments, the classification module 402 is used for:
[0154] The wafers from the various historical batches are classified according to the process environment information of each historical batch during the photolithography process.
[0155] The process environment information includes at least one of the following: exposure machine identifier, exposure machine suction cup identifier, etching machine identifier, etching chamber identifier, and etching machine running time;
[0156] And / or, including at least one of the following process environment information: the exposure machine identifier, exposure machine chuck identifier, etching machine identifier, etching chamber identifier, and etching machine runtime of the reference material layer of the target material layer corresponding to each of the historical batches of wafers during the photolithography process.
[0157] In some embodiments, a determining module is further included, configured to:
[0158] Based on the alignment tree and stacking error tree corresponding to the target material layer, the reference material layer corresponding to the target material layer is determined. The reference material layer is the material layer in each of the historical batches of wafers that was photolithographically processed before the target material layer.
[0159] The acquisition module 401 is also used for:
[0160] Obtain the stacking data of wafers from multiple historical batches prior to the current batch on the reference material layer;
[0161] The first calculation module 403 is also used for:
[0162] Based on the stacking data corresponding to the target material layer and the reference material layer for each of the historical batches of wafers under various process environments, the stacking error of each of the historical batches of wafers under various process environments is determined.
[0163] It should be noted that the specific execution of the acquisition module 401, classification module 402, first calculation module 403, and second calculation module 404 in this embodiment can be found in the [reference needed]. Figures 1 to 3 The relevant content in the illustrated embodiments will not be repeated here.
[0164] Furthermore, based on the content described in the above embodiments, this disclosure also provides an electronic device, which includes at least one processor and a memory; wherein the memory stores computer execution instructions; the at least one processor executes the computer execution instructions stored in the memory to implement the various steps in the non-zero offset determination method described in the above embodiments, which will not be repeated here.
[0165] To better understand the embodiments of this disclosure, please refer to... Figure 5 , Figure 5 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this disclosure.
[0166] like Figure 5 As shown, the electronic device 50 of this embodiment includes: a processor 501 and a memory 502; wherein:
[0167] Memory 502 is used to store instructions executed by the computer;
[0168] The processor 501 is used to execute computer execution instructions stored in the memory to implement the various steps in the non-zero offset determination method described in the above embodiments, which will not be repeated here.
[0169] Alternatively, the memory 502 can be either standalone or integrated with the processor 501.
[0170] When the memory 502 is set up independently, the device also includes a bus 503 for connecting the memory 502 and the processor 501.
[0171] Furthermore, based on the content described in the above embodiments, this disclosure also provides a computer-readable storage medium storing computer-executable instructions. When a processor executes the computer-executable instructions, it implements the various steps in the non-zero offset determination method described in the above embodiments. These steps will not be repeated here.
[0172] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms.
[0173] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.
[0174] Furthermore, the functional modules in the various embodiments of this disclosure can be integrated into one processing unit, or each module can exist physically separately, or two or more modules can be integrated into one unit. The unit integrating the above modules can be implemented in hardware or in the form of hardware plus software functional units.
[0175] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.
Claims
1. A method for determining a non-zero offset, characterized in that, The method includes: Obtain the stacking data of wafers in the target material layer from multiple historical batches prior to the current batch; The wafers from each of the aforementioned historical batches were classified according to their process environment; Based on the stacking data of wafers in various process environments for each historical batch, the stacking error of wafers in each historical batch under various process environments is determined. Based on the stacking errors of wafers in each historical batch under various process environments, the non-zero offset of the target material layer corresponding to the current batch of wafers under various process environments is determined.
2. The method according to claim 1, characterized in that, The step of obtaining the stacking data of wafers in the target material layer from multiple historical batches prior to the current batch includes: Acquire the stacking data of the wafers after development and after etching of the target material layer from the multiple historical batches.
3. The method according to claim 2, characterized in that, The step of determining the stacking error of each historical batch of wafers under various process environments based on the stacking data corresponding to each historical batch of wafers under various process environments includes: By iterating through each of the historical batches and various process environments, the difference between the post-development detection stacking data and the post-etch detection stacking data of the wafers of the first historical batch under the first process environment is calculated, and the difference is determined as the stacking error of the wafers of the first historical batch under the first process environment.
4. The method according to claim 1 or 3, characterized in that, The step of determining the non-zero offset of the target material layer corresponding to the current batch of wafers under various process environments based on the stacking errors of wafers in each historical batch under various process environments includes: By iterating through all the aforementioned process environments, the average stacking error of each historical batch of wafers under the first process environment is calculated, and the average value is determined as the non-zero offset of the target material layer corresponding to the current batch of wafers under the first process environment.
5. The method according to claim 1 or 3, characterized in that, The step of determining the non-zero offset of the target material layer corresponding to the current batch of wafers under various process environments based on the stacking errors of wafers in each historical batch under various process environments includes: The weight of each historical batch of wafers is determined based on the exposure time. By traversing all the aforementioned process environments, and based on the weights corresponding to the wafers of each historical batch, the weighted average of the stacking errors of the wafers in each historical batch under the traversed first process environment is calculated, and the weighted average is determined as the non-zero offset of the target material layer corresponding to the wafer of the current batch under the first process environment.
6. The method according to claim 1, characterized in that, The classification of wafers from each historical batch according to the process environment includes: The wafers from the various historical batches are classified according to the process environment information of each historical batch during the photolithography process. The process environment information includes at least one of the following: exposure machine identifier, exposure machine suction cup identifier, etching machine identifier, etching chamber identifier, and etching machine running time; And / or, including at least one of the following process environment information: the exposure machine identifier, exposure machine chuck identifier, etching machine identifier, etching chamber identifier, and etching machine runtime of the reference material layer of the target material layer corresponding to each of the historical batches of wafers during the photolithography process.
7. The method according to claim 6, characterized in that, Also includes: Based on the alignment tree and stacking error tree corresponding to the target material layer, the reference material layer corresponding to the target material layer is determined. The reference material layer is the material layer in each of the historical batches of wafers that was photolithographically processed before the target material layer. Obtain the stacking data of wafers from multiple historical batches prior to the current batch on the reference material layer; The step of determining the stacking error of each historical batch of wafers under various process environments based on the stacking data corresponding to each historical batch of wafers under various process environments includes: Based on the stacking data corresponding to the target material layer and the reference material layer for each of the historical batches of wafers under various process environments, the stacking error of each of the historical batches of wafers under various process environments is determined.
8. A non-zero offset determination device, characterized in that, The device includes: The acquisition module is used to acquire the stacking data of wafers in the target material layer from multiple historical batches prior to the current batch. The classification module is used to classify the wafers from each of the historical batches according to the process environment; The first calculation module is used to determine the stacking error of the wafers in each historical batch under various process environments based on the stacking data corresponding to the wafers in each historical batch under various process environments. The second calculation module is used to determine the non-zero offset of the target material layer corresponding to the current batch of wafers under various process environments based on the stacking error of the wafers in each historical batch under various process environments.
9. The apparatus according to claim 8, characterized in that, The acquisition module is used for: Acquire the stacking data of the wafers after development and after etching of the target material layer from the multiple historical batches.
10. The apparatus according to claim 9, characterized in that, The first calculation module is used for: By iterating through each of the historical batches and various process environments, the difference between the post-development detection stacking data and the post-etch detection stacking data of the wafers of the first historical batch under the first process environment is calculated, and the difference is determined as the stacking error of the wafers of the first historical batch under the first process environment.
11. The apparatus according to claim 8 or 10, characterized in that, The second calculation module is used for: By iterating through all the aforementioned process environments, the average stacking error of each historical batch of wafers under the first process environment is calculated, and the average value is determined as the non-zero offset of the target material layer corresponding to the current batch of wafers under the first process environment.
12. The apparatus according to claim 8 or 10, characterized in that, The second calculation module is used for: The weight of each historical batch of wafers is determined based on the exposure time. By traversing all the aforementioned process environments, and based on the weights corresponding to the wafers of each historical batch, the weighted average of the stacking errors of the wafers in each historical batch under the traversed first process environment is calculated, and the weighted average is determined as the non-zero offset of the target material layer corresponding to the wafer of the current batch under the first process environment.
13. The apparatus according to claim 8, characterized in that, The classification module is used for: The wafers from the various historical batches are classified according to the process environment information of each historical batch during the photolithography process. The process environment information includes at least one of the following: exposure machine identifier, exposure machine suction cup identifier, etching machine identifier, etching chamber identifier, and etching machine running time; And / or, including at least one of the following process environment information: the exposure machine identifier, exposure machine chuck identifier, etching machine identifier, etching chamber identifier, and etching machine runtime of the reference material layer of the target material layer corresponding to each of the historical batches of wafers during the photolithography process.
14. The apparatus according to claim 13, characterized in that, It also includes a determination module, used for: Based on the alignment tree and stacking error tree corresponding to the target material layer, the reference material layer corresponding to the target material layer is determined. The reference material layer is the material layer in each of the historical batches of wafers that was photolithographically processed before the target material layer. The acquisition module is also used for: Obtain the stacking data of wafers from multiple historical batches prior to the current batch on the reference material layer; The first calculation module is also used for: Based on the stacking data corresponding to the target material layer and the reference material layer for each of the historical batches of wafers under various process environments, the stacking error of each of the historical batches of wafers under various process environments is determined.
15. An electronic device, characterized in that, include: At least one processor and memory; The memory stores computer-executed instructions; The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the non-zero offset determination method as described in any one of claims 1 to 7.
16. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, implement the non-zero offset determination method as described in any one of claims 1 to 7.