Display device

Abstract

The display device is characterized in that, in the chip mounting portion (M), a plurality of chip terminals (18g, 18h, 18j) arranged in a row, and a plurality of terminal wirings (14tc, 14td, 14tf) corresponding to the plurality of chip terminals (18g, 18h, 18j) and extending in parallel with each other and electrically connected to the plurality of chip terminals (18g, 18h, 18j) are provided, and a chip support body (Sa, Sb) is provided between the plurality of chip terminals (18g, 18h, 18j).

Description

Technical Field

[0001] This invention relates to a display device. Background Technology

[0002] In recent years, self-emissive organic EL display devices, which use organic electroluminescent (EL) elements, have attracted much attention as an alternative to liquid crystal display devices. Among these organic EL display devices, flexible organic EL display devices have been proposed, in which organic EL elements are formed on a flexible resin substrate.

[0003] For example, Patent Document 1 discloses a flexible wiring board for mounting an LSI chip, which has an spacing retention unit provided in the opening of the insulating film formed in the area where the LSI (large scale integration) chip is mounted, for maintaining the minimum spacing between the LSI terminal and the LSI chip when the LSI chip is mounted. Existing technical documents Patent documents

[0004] Patent Document 1: Japanese Patent No. 3914478 Summary of the Invention The technical problem to be solved by the present invention

[0005] However, in the LSI chip mounting flexible wiring board disclosed in Patent Document 1, although the bending of the flexible wiring board can be suppressed by the spacer holding unit, since the spacer holding unit is configured to span multiple terminals arranged side by side, the conductive particles constituting the anisotropic conductive film will aggregate between the spacer holding unit and the bumps of the LSI chip, and the aggregated conductive particles may connect. As a result, adjacent terminals may short-circuit due to the connected conductive particles, so there is room for improvement.

[0006] The present invention was made in view of this purpose, and its object is to suppress short circuits between terminals in the chip mounting section. Technical solutions for solving technical problems

[0007] To achieve the above objectives, the display device of the present invention includes: a flexible substrate layer; a thin-film transistor layer disposed on the flexible substrate layer; and a light-emitting element layer disposed on the thin-film transistor layer, wherein a plurality of light-emitting elements are arranged corresponding to a plurality of sub-pixels constituting a display area, a border area is disposed around the display area, a terminal portion is disposed at the end of the border area extending in one direction, and a chip mounting portion is disposed between the display area and the terminal portion. The chip mounting portion is rectangular when viewed from above, with its long side extending along the extending direction of the terminal portion. The chip mounting portion is provided with a plurality of chip terminals arranged in a row, and a plurality of terminal wirings extending parallel to each other and electrically connected to the plurality of chip terminals. In the chip mounting portion, a chip support is disposed between the plurality of chip terminals. Beneficial effects

[0008] According to the present invention, short circuits between terminals in the chip mounting portion can be suppressed. Attached Figure Description

[0009] Figure 1 This is a top view showing the schematic configuration of the organic EL display device according to the first embodiment of the present invention. Figure 2 This is a top view of the organic EL display panel constituting the organic EL display device according to the first embodiment of the present invention. Figure 3 This is a cross-sectional view of the organic EL display panel constituting the organic EL display device according to the first embodiment of the present invention. Figure 4 This is an equivalent circuit diagram of the thin-film transistor layer of the organic EL display panel of the organic EL display device according to the first embodiment of the present invention. Figure 5 This is a cross-sectional view showing the organic EL layer of the organic EL display panel constituting the organic EL display device according to the first embodiment of the present invention. Figure 6 This is a top view of the chip mounting portion and its surrounding portion in the bezel area of ​​the organic EL display panel of the organic EL display device according to the first embodiment of the present invention. Figure 7 This is a top view showing the output terminal and chip support in the chip mounting section of the frame area of ​​the organic EL display panel of the organic EL display device according to the first embodiment of the present invention. Figure 8 This is a top view showing the input terminals and chip support in the chip mounting section of the frame area of ​​the organic EL display panel of the organic EL display device according to the first embodiment of the present invention. Figure 9It means in Figure 7 A top view of the end of the integrated circuit chip installed in the middle and the conductive particles. Figure 10 It is along Figure 9 A cross-sectional view of an organic EL display device with XX lines in the image. Figure 11 It is along Figure 9 A cross-sectional view of an organic EL display device with XI-XI lines. Figure 12 It is along Figure 9 A cross-sectional view of an organic EL display device along the XII-XII line. Figure 13 This is a cross-sectional view of a modified example of the organic EL display device according to the first embodiment of the present invention, which is equivalent to... Figure 10 The image. Figure 14 This is a top view of the output terminals and chip support in the chip mounting portion of the OLED display panel in the bezel area of ​​the OLED display device according to the second embodiment of the present invention, which is equivalent to... Figure 7 The image. Figure 15 This is a top view showing a modified example of an organic EL display device according to the second embodiment of the present invention, which is equivalent to... Figure 14 The image. Figure 16 This is a top view of the output terminals and chip support in the chip mounting portion of the OLED display panel in the bezel area of ​​the OLED display device according to the third embodiment of the present invention, which is equivalent to... Figure 7 The image. Figure 17 This is a top view showing a first modified example of an organic EL display device according to the third embodiment of the present invention, which is equivalent to... Figure 16 The image. Figure 18 This is a top view showing a second modified example of the organic EL display device according to the third embodiment of the present invention, which is equivalent to... Figure 16 The image. Figure 19 This is a top view showing a third modified example of an organic EL display device according to the third embodiment of the present invention, which is equivalent to... Figure 16 The image. Figure 20 This is an enlarged top view of the chip mounting portion in the bezel area of ​​the organic EL display panel constituting the organic EL display device of the fourth embodiment of the present invention, which is equivalent to... Figure 6 The image. Detailed Implementation

[0010] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments.

[0011] First Implementation Method Figures 1 to 13 A first embodiment of the display device according to the present invention is shown. Furthermore, as a display device including a light-emitting element layer, an organic EL display device including an organic EL element is exemplified in the following embodiments. Here, Figure 1 This is a top view showing the organic EL display device 70a according to this embodiment. Furthermore, Figure 2 This is a top view of the display area D of the organic EL display panel 50a that constitutes the organic EL display device 70a. Furthermore, Figure 3 This is a cross-sectional view of the display area D of the organic EL display panel 50a. Additionally, Figure 4 This is an equivalent circuit diagram of the thin-film transistor layer 30 that constitutes the organic EL display panel 50a. Furthermore, Figure 5 This is a cross-sectional view of the organic EL layer 33 that constitutes the organic EL display panel 50a. Additionally, Figure 6 This is a top view of the chip mounting section M and its surroundings in the bezel area F of the organic EL display panel 50a. Additionally, Figure 7 This is a top view showing the first output terminal 18g, the second output terminal 18h, and the chip support Sa in the chip mounting section M of the bezel area F of the organic EL display panel 50a. Additionally, Figure 8 This is a top view showing the input terminal 18j of the chip mounting section M and the chip support Sb in the bezel area F of the organic EL display panel 50a. Furthermore, Figure 9 It means in Figure 7 A top view of the end E of the integrated circuit chip 60 and the conductive particle 64 installed in the middle. Furthermore, Figure 10 , Figure 11 and Figure 12 It is along Figure 9 A cross-sectional view of the organic EL display device 70a showing the XX line, XI-XI line, and XII-XII line. Additionally, Figure 13 This is a cross-sectional view of a modified example of the organic EL display device 70aa, namely the organic EL display device 70aa. Figure 10 A fairly accurate diagram.

[0012] like Figure 1 As shown, the organic EL display device 70a includes an organic EL display panel 50a, an integrated circuit chip 60 mounted on the chip mounting portion M of the organic EL display panel 50a (described later), and a flexible printed circuit board 55 mounted on the terminal portion T of the organic EL display panel 50a (described later).

[0013] like Figure 1As shown, the organic EL display panel 50a includes, for example, a display area D that is rectangular and displays images, and a border area F that is provided around the display area D and is frame-shaped. Furthermore, in this embodiment, a rectangular display area D is exemplified, but this rectangle also includes, for example, shapes with rounded sides, rounded corners, or cutouts on a portion of the side, etc., generally rectangular shapes.

[0014] like Figure 2 As shown, in display area D, multiple sub-pixels P are arranged in a matrix. Furthermore, in display area D, as... Figure 2 As shown, for example, a sub-pixel P having a red emitting area Lr for displaying red, a sub-pixel P having a green emitting area Lg for displaying green, and a sub-pixel P having a blue emitting area Lb for displaying blue are arranged adjacent to each other. Furthermore, in the display area D, a pixel is formed by three adjacent sub-pixels P having the red emitting area Lr, the green emitting area Lg, and the blue emitting area Lb.

[0015] In the border area F Figure 1 At the lower end of the portion, the terminal portion T is configured to extend in one direction (horizontally in the figure). Furthermore, in the border area F, as... Figure 1 As shown, between the display area D and the terminal area T, the chip mounting portion M is configured to extend in one direction (horizontally in the figure). Furthermore, as... Figure 1 As shown, the chip mounting portion M is rectangular when viewed from above, with its long side extending along the extension direction of the terminal portion T.

[0016] like Figure 3 As shown, the organic EL display device 50a includes: a flexible substrate layer 10; a thin film transistor (TFT) layer 30 disposed on the flexible substrate layer 10; an organic EL element layer 40 disposed on the TFT layer 30 as a light-emitting element layer; a sealing film 40 disposed to cover the organic EL element layer 40; and a touch panel layer 45 disposed on the sealing film 40.

[0017] The flexible substrate layer 10 is made of, for example, polyimide resin and is flexible. Furthermore, although a flexible substrate layer 10 made of resin such as polyimide resin is shown as an example in this embodiment, the flexible substrate layer 10 may also be made of metal such as a metal film or a thin metal sheet.

[0018] like Figure 3 As shown, the TFT layer 30 includes: a base coating film 11 disposed on the flexible substrate layer 10; and a plurality of first TFTs 9a and a plurality of second TFTs 9b disposed on the base coating film 11 (see reference). Figure 4), a plurality of third TFTs 9c and a plurality of capacitors 9d; and a first planarization film 19a and a second planarization film 21a sequentially disposed on each of the first TFTs 9a, each of the second TFTs 9b, each of the third TFTs 9c and each of the capacitors 9d.

[0019] In TFT layer 30, such as Figure 3 As shown, a base coating film 11, a semiconductor pattern layer such as a semiconductor layer 12a (described later), a gate insulating film 13, a first wiring layer such as a gate line 14g (described later), a first interlayer insulating film 15, a third wiring layer such as an upper conductive layer 16c (described later), a second interlayer insulating film 17, a second wiring layer such as a source line 18f (described later), a first planarization film 19a, a fourth wiring layer such as a power line 20a, and a second planarization film 21a are sequentially stacked on the flexible substrate layer 10. Furthermore, the base coating film 11, the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 are, for example, single-layer or multi-layered films of inorganic insulating films such as silicon nitride, silicon oxide, and silicon oxynitride.

[0020] like Figure 2 as well as Figure 4 As shown, in the TFT layer 30, multiple gate lines 14g are arranged as a first wiring layer, extending parallel to each other in the lateral direction shown in the figure. Additionally, as... Figure 2 as well as Figure 4 As shown, in the TFT layer 30, multiple light-emitting control lines 14e are arranged as a first wiring layer, extending parallel to each other in the lateral direction shown in the figure. Additionally, as... Figure 2 As shown, each light-emitting control line 14e is positioned adjacent to each gate line 14d. Additionally, as... Figure 2 as well as Figure 4 As shown, in the TFT layer 30, multiple source lines 18f are arranged as a second wiring layer, extending parallel to each other in the vertical direction shown in the figure. Additionally, as... Figure 3 As shown, in the TFT layer 30, between the first planarization film 19a and the second planarization film 21a, power lines 20a are arranged in a grid pattern as a fourth wiring layer. Additionally, as... Figure 4 As shown, in the TFT layer 30, each sub-pixel P is provided with a first TFT 9a, a second TFT 9b, a third TFT 9c, and a capacitor 9d.

[0021] like Figure 4 As shown, in each sub-pixel P, the first TFT 9a is electrically connected to the corresponding gate line 14d, source line 18f, and second TFT 9b. Figure 3 As shown, the first TFT 9a includes a semiconductor layer 12a, a gate insulating film 13, a gate electrode 14a, a first interlayer insulating film 15, a second interlayer insulating film 17, a source electrode 18a, and a drain electrode 18b sequentially disposed on the base coating film 11. Here, as... Figure 3 As shown, the semiconductor layer 12a is disposed on the base coating film 11 in an island-like manner, as described later, and has a channel region, a source region, and a drain region. Furthermore, as... Figure 3 As shown, the gate insulating film 13 is provided in a manner that covers the semiconductor layer 12a. Furthermore, as... Figure 3 As shown, the gate electrode 14a is disposed on the gate insulating film 13 in a manner that overlaps with the channel region of the semiconductor layer 12a. Furthermore, as... Figure 3 As shown, the first interlayer insulating film 15 and the second interlayer insulating film 17 are sequentially disposed to cover the gate electrode 14b. Additionally, as... Figure 3 As shown, the source electrode 18c and drain electrode 18b are disposed separately on the second interlayer insulating film 17. Furthermore, as... Figure 3 As shown, the source electrode 18a and the drain electrode 18b are connected to the source region and the drain region of the semiconductor layer 12a respectively via contact holes formed in the stacked film of the gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 17.

[0022] like Figure 4 As shown, the second TFT9b is electrically connected to the corresponding first TFT9a, power line 20a, and third TFT9c in each sub-pixel P. Furthermore, the second TFT9b has a substantially identical structure to the first TFT9a and the third TFT9c, which will be described later.

[0023] like Figure 4 As shown, the third TFT9c is electrically connected in each sub-pixel P to the corresponding second TFT9b, the first electrode 31a of the organic EL layer 35 (described later), and the light-emitting control line 14e. Additionally, as... Figure 3 As shown, the third TFT 9c includes a semiconductor layer 12b, a gate insulating film 13, a gate electrode 14b, a first interlayer insulating film 15, a second interlayer insulating film 17, a source electrode 18c, and a drain electrode 18d sequentially disposed on the base coating film 11. Here, as... Figure 3 As shown, semiconductor layer 12b is disposed on the base coating film 11 in an island-like manner, and similarly to semiconductor layer 12a, has a channel region, a source region, and a drain region. Additionally, as... Figure 3 As shown, the gate insulating film 13 is provided in a manner that covers the semiconductor layer 12b. Additionally, as... Figure 3 As shown, the gate electrode 14b is disposed on the gate insulating film 13 in a manner that overlaps with the channel region of the semiconductor layer 12b. Furthermore, as... Figure 3 As shown, the first interlayer insulating film 15 and the second interlayer insulating film 17 are sequentially disposed to cover the gate electrode 14b. Additionally, as... Figure 3 As shown, the source electrode 18c and drain electrode 18d are disposed on the second interlayer insulating film 17 in a manner separate from each other. Furthermore, as... Figure 3As shown, the source electrode 18c and the drain electrode 18d are connected to the source region and drain region of the semiconductor layer 12b respectively via contact holes formed in the stacked film of the gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 17.

[0024] Furthermore, in this embodiment, a first TFT 9a, a second TFT 9b, and a third TFT 9c of the top gate type are illustrated, but the first TFT 9a, the second TFT 9b, and the third TFT 9c may also be bottom gate type TFTs.

[0025] like Figure 4 As shown, capacitor 9d is electrically connected to the corresponding first TFT 9a and power line 20a in each sub-pixel P. Here, as... Figure 3 As shown, the capacitor 9d includes a lower conductive layer 14c, which serves as a first wiring layer; a first interlayer insulating film 15, which covers the lower conductive layer 14c; and an upper conductive layer 16c, which serves as a second wiring layer on the first interlayer insulating film 15, overlapping the lower conductive layer 14c. Furthermore, the upper conductive layer 16c is electrically connected to the power line 20a via contact holes (not shown) formed in the second interlayer insulating film 17 and the first planarization film 19a.

[0026] The first planarization film 19a and the second planarization film 21a have flat surfaces in the display area D, for example, they are made of organic resin materials such as polyimide resin and acrylic resin, or polysiloxane-based SOG (spin on glass) materials. Here, as Figure 3 As shown, between the first planarization film 19a and the second planarization film 21a, in addition to the power line 20a mentioned above, a relay electrode 20b is also provided as a fourth wiring layer.

[0027] The organic EL element layer 40 includes a plurality of first electrodes 31a, a shared edge mask 32a, a plurality of organic EL layers 33, and a shared second electrode 34, which are sequentially disposed corresponding to a plurality of sub-pixels P. Here, in each sub-pixel P, the first electrode 31a, the organic EL layer 33, and the second electrode 34 constitute an organic EL element 35 (see reference). Figure 4 In the organic EL element layer 40, multiple organic EL elements 35 are arranged in a matrix.

[0028] like Figure 3 As shown, a plurality of first electrodes 31a are arranged in a matrix on the second planarization film 21a in a manner corresponding to a plurality of sub-pixels P. Here, as Figure 3As shown, in each sub-pixel P, the first electrode 31a is electrically connected to the drain 18d of each third TFT 9c via a contact hole formed in the first planarization film 19a, a relay electrode 20b, and a contact hole formed in the second planarization film 21a. Furthermore, the first electrode 31a also functions to inject holes (positive holes) into the organic EL layer 33. In addition, to improve the hole injection efficiency into the organic EL layer 33, the first electrode 31a is more preferably formed of a material with a high work function. Examples of materials constituting the first electrode 31a include, for example, silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), titanium (Ti), ruthenium (Ru), manganese (Mn), indium (In), ybium (Yb), lithium fluoride (LiF), platinum (Pt), palladium (Pd), molybdenum (Mo), iridium (Ir), and tin (Sn). Furthermore, the material constituting the first electrode 31a can also be an alloy such as astatine (At) / atstatine oxide (AtO2). Further, the material constituting the first electrode 31a can also be a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), or indium zinc oxide (IZO). Additionally, the first electrode 31a can be formed by stacking multiple layers composed of the above-mentioned materials. Furthermore, compound materials with high work functions include, for example, indium tin oxide (ITO) and indium zinc oxide (IZO).

[0029] like Figure 3 As shown, the edge cover 32a is arranged in a grid pattern to cover the periphery of each first electrode 31a. Here, the edge cover 32a is made of organic resin materials such as polyimide resin and acrylic resin, or SOG material based on polysiloxane.

[0030] like Figure 3 As shown, multiple organic EL layers 33 are disposed on each first electrode 31a and arranged in a matrix manner corresponding to multiple sub-pixels. Here, as... Figure 5 As shown, each organic EL layer 33 includes a hole injection layer 1, a hole transport layer 2, a light emission layer 3, an electron transport layer 4, and an electron injection layer 5 sequentially disposed on the first electrode 31a.

[0031] The hole injection layer 1 is also referred to as the anode buffer layer, which brings the energy levels of the first electrode 31a and the organic EL layer 33 closer together, thereby improving the hole injection efficiency from the first electrode 31a to the organic EL layer 33. Examples of materials constituting the hole injection layer 1 include triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkyl derivatives, pyrazoline derivatives, phenylenediamine derivatives, oxazole derivatives, styrene-anthracene derivatives, fluorenone derivatives, hydrazone derivatives, and stilbene derivatives.

[0032] The hole transport layer 2 has the function of improving the transport efficiency of holes from the first electrode 31a to the organic EL layer 33. Examples of materials constituting the hole transport layer 2 include porphyrin derivatives, aromatic tertiary amine compounds, phenylethylamine derivatives, polyvinylcarbazole, poly-p-phenylacetylene, polysilanes, triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkyl derivatives, pyrazoline derivatives, pyrazolone derivatives, phenylenediamine derivatives, aromatic amine derivatives, amine-substituted chalcone derivatives, oxazole derivatives, styrene-anthracene derivatives, fluorenone derivatives, hydrazone derivatives, stilbene derivatives, hydrogenated amorphous silicon, hydrogenated amorphous silicon carbide, zinc sulfide, and zinc selenide.

[0033] The light-emitting layer 3 is a region in which holes and electrons are injected from the first electrode 31a and the second electrode 34 respectively when a voltage is applied to the first electrode 31a and the second electrode 34, and the holes and electrons recombine. Here, the light-emitting layer 3 is formed of a material with high luminous efficiency. Moreover, examples of materials constituting the light-emitting layer 3 include metal hydroxyquinoline compounds [8-hydroxyquinoline metal complex], naphthalene derivatives, anthracene derivatives, stilbene derivatives, vinyl acetone derivatives, triphenylamine derivatives, butadiene derivatives, coumarin derivatives, benzoxazole derivatives, oxadiazole derivatives, oxazole derivatives, benzimidazole derivatives, thiadiazole derivatives, benzothiazazole derivatives, styryl derivatives, styrylamine derivatives, stilbeneylbenzene derivatives, tristyrylbenzene derivatives, perylene derivatives, pyrene derivatives, aminopyrene derivatives, pyridine derivatives, rhodamine derivatives, acridine derivatives, phenoxazinone, quinacridone derivatives, rubrene, poly(p-phenylenevinylene), polysilane, etc.

[0034] The electron transport layer 4 has the function of enabling electrons to migrate to the light-emitting layer 3 with high efficiency. Here, the materials constituting the electron transport layer 4 can be listed as organic compounds such as diazole derivatives, triazole derivatives, benzoquinone derivatives, naphthoquinone derivatives, anthraquinone derivatives, tetracyanoanthraquinone dimethane derivatives, biphenylquinone derivatives, fluorenone derivatives, thiophene derivatives, and metal hydroxyquinoline compounds.

[0035] The electron injection layer 5 is close to the energy levels of the second electrode 34 and the organic EL layer 33, and has the function of improving the efficiency of electron injection from the second electrode 34 to the organic EL layer 33. Through this function, the driving voltage of the organic EL element can be reduced. In addition, the electron injection layer 5 is also called the cathode buffer layer. Here, the materials constituting the electron injection layer 5 include, for example, inorganic alkali compounds such as lithium fluoride (LiF), magnesium fluoride (MgF2), calcium fluoride (CaF2), strontium fluoride (SrF2), and barium fluoride (BaF2), as well as aluminum oxide (Al2O3) and strontium oxide (SrO).

[0036] The second electrode 34 is configured to be shared across multiple organic EL layers 33 and multiple sub-pixels P, i.e., as shown below. Figure 3 As shown, each organic EL layer 33 and the edge mask 32a are covered. Furthermore, the second electrode 34 has the function of injecting electrons into each organic EL layer 33. In addition, to improve the electron injection efficiency into the organic EL layer 33, the second electrode 34 is more preferably made of a material with a low work function. Examples of materials constituting the second electrode 34 include silver (Ag), aluminum (Al), vanadium (V), calcium (Ca), titanium (Ti), yttrium (Y), sodium (Na), manganese (Mn), indium (In), magnesium (Mg), lithium (Li), ytterbium (Yb), and lithium fluoride (LiF). Furthermore, the second electrode 34 may also be formed of alloys such as magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), astatine (At) / astatine oxide (AtO2), lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), and lithium fluoride (LiF) / calcium (Ca) / aluminum (Al). Furthermore, the second electrode 34 may also be formed of conductive oxides such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO). Additionally, the second electrode 34 may be formed by stacking multiple layers of the above-mentioned materials. Furthermore, materials with low work function include, for example, magnesium (Mg), lithium (Li), lithium fluoride (LiF), magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), and lithium fluoride (LiF) / calcium (Ca) / aluminum (Al).

[0037] like Figure 3 As shown, the sealing film 45 includes a first inorganic sealing film 41, an organic sealing film 42, and a second inorganic sealing film 43, which are disposed on the second electrode 34 in a manner covering the second electrode 34, and have the function of protecting the organic EL layer 33 of the organic EL element 35 from moisture and oxygen. Here, the first inorganic sealing film 41 and the second inorganic sealing film 43 are, for example, made of inorganic insulating films such as silicon nitride film, silicon oxide film, and silicon oxynitride film. In addition, the organic sealing film 42 is made of organic resin materials such as acrylic resin, epoxy resin, silicone resin, polyurea resin, parylene resin, polyimide resin, and polyamide resin. Furthermore, in the frame area F of the organic EL display panel 50a, a first barrier wall is set in a frame shape to suppress the diffusion of ink that becomes the organic sealing film 42, which is set in a frame shape to surround the display area D, and a second barrier wall is set in a frame shape to surround the first barrier wall.

[0038] In addition, such as Figure 6As shown, the OLED display panel 50a includes a chip mounting portion M in the bezel area F: a lower chip circuit portion C, which is rectangular in shape extending laterally as shown in the figure; a plurality of first output-side terminal wirings 14tc and a plurality of second output-side terminal wirings 14td, which are arranged in parallel to each other on the display area D side (upper side in the figure) of the lower chip circuit portion C; and a plurality of input-side terminal wirings 14tf, which are arranged in parallel to each other on the terminal portion T side (lower side in the figure). Here, as Figure 6 as well as Figure 7 As shown, multiple first output-side terminal wirings 14tc and multiple second output-side terminal wirings 14td are alternately arranged along the extension direction (lateral direction in the figure) of the chip mounting portion M. Furthermore, the first output-side terminal wirings 14tc, second output-side terminal wirings 14td, and input-side terminal wirings 14tf are arranged as a first wiring layer.

[0039] In addition, such as Figure 6 As shown, the organic EL display panel 50a includes the following in the chip mounting section M of the bezel region F: a plurality of first output terminals 18g, which are arranged in a row along the long side of the display region D side of the lower chip circuit section C as chip terminals (upper side in the figure); a plurality of second output terminals 18h, which are arranged in a row along the long side of the display region D side of the lower chip circuit section C as chip terminals (lower side in the figure); and a plurality of input terminals 18j, which are arranged in a row along the long side of the terminal T side of the lower chip circuit section C as chip terminals (lower side in the figure). Here, as Figure 6 as well as Figure 7 As shown, multiple first output terminals 18g and multiple second output terminals 18h are alternately arranged in a staggered manner along the extending direction (lateral direction in the figure) of the chip mounting portion M. Furthermore, the first output terminals 18g, second output terminals 18h, and input terminals 18j are provided as a second wiring layer. Additionally, multiple first output terminals 18g are respectively stacked on multiple first output side terminal wirings 14tc and electrically connected to the multiple first output side terminal wirings 14tc. Furthermore, as... Figure 10 As shown, multiple second output terminals 18h are stacked on multiple second output side terminal wirings 14td and electrically connected to the multiple second output side terminal wirings 14td respectively. In addition, multiple input terminals 18j are stacked on multiple input side terminal wirings 14tf and electrically connected to the multiple input side terminal wirings 14tf respectively.

[0040] In addition, such as Figure 6 as well as Figure 8 As shown, the organic EL display panel 50a includes: a chip support Sa, which is integrally disposed in a double comb-like manner in the chip mounting portion M of the bezel region F between a plurality of first output terminals 18g and between a plurality of second output terminals 18h; and a chip support Sb, which is disposed island-like among a plurality of input terminals 18j.

[0041] like Figure 10 As shown, the chip support Sa includes: a first inorganic insulating layer 15a, which is formed on the same layer as the first interlayer insulating film 15; a second inorganic insulating layer 17a, which is disposed on the first inorganic insulating layer 15a and is formed on the same layer as the second interlayer insulating film 17; and an organic insulating layer 19b, which is disposed on the second inorganic insulating layer 17a and is formed on the same layer as the first planarization film 19a. Here, as Figure 10 As shown, the central portion of the organic insulating layer 19b in the width direction is formed to be thicker than the two ends in the width direction. Furthermore, as... Figure 10 As shown, the second output-side terminal wiring 14td and the second output terminal 18h (as well as the first output-side terminal wiring 14tc and the first output terminal 18g) extend to both ends of the chip support Sa in the width direction. Therefore, the gap between the integrated circuit chip 60 and the chip support Sa is narrowed, thus suppressing panel deflection at the first output terminal 18g and the second output terminal 18h during chip bonding, and suppressing wire breakage at the first output terminal 18g, the second output terminal 18h, the first output-side terminal wiring 14tc, and the second output-side terminal wiring 14td (see reference). Figure 11 Additionally, such as Figure 6 As shown, the display area D side of the chip support Sa is positioned outside the chip mounting portion M (the peripheral end E of the integrated circuit chip 60). Therefore, in the absence of the bump 61, the gap between the integrated circuit chip 60 and the chip support Sa is also narrowed, thus suppressing panel deflection during chip bonding (see reference). Figure 12 ).

[0042] The chip support Sb, like the chip support Sa, includes: a first inorganic insulating layer 15a formed on the same layer using the same material as the first interlayer insulating film 15; a second inorganic insulating layer 17a formed on the same layer using the same material as the second interlayer insulating film 17, disposed on the first inorganic insulating layer 15a; and an organic insulating layer 19b formed on the same layer using the same material as the first planarization film 19a, disposed on the second inorganic insulating layer 17a. Furthermore, since the input-side terminal wiring 14tf and the input terminal 18j extend to both ends in the width direction of the chip support Sb, the gap between the integrated circuit chip 60 and the chip support Sb is narrowed. Therefore, the panel deflection at the input terminal 18j during chip bonding is suppressed, and the breakage of the input terminal 18j and the input-side terminal wiring 14tf can be suppressed. Additionally, the terminal portion T side of the chip support Sb... Figure 6 As shown, the chip mounting portion M is positioned on the outside of the chip mounting portion M. Therefore, in the area without the bump 61, the gap between the integrated circuit chip 60 and the chip support Sb is also narrowed, thus suppressing panel deflection during chip pressing.

[0043] Furthermore, in this embodiment, an organic EL display device 70a is illustrated with a chip support Sa and Sb having an organic insulating layer structure, but the chip support Sa and Sb may also be... Figure 13 The organic insulating layer shown is part of an organic EL display device 70aa, which includes a two-layer chip support Saa. Here, in the organic EL display device 70aa, the chip support Sa is as follows: Figure 3 The device includes: a first inorganic insulating layer 15a, which is formed on the same layer as the first interlayer insulating film 15; a second inorganic insulating layer 17a, which is disposed on the first inorganic insulating layer 15a and is formed on the same layer as the second interlayer insulating film 17; a first organic insulating layer 19b, which is disposed on the second inorganic insulating layer 17a and is formed on the same layer as the first planarization film 19a; and a second organic insulating layer 21b, which is disposed on the first organic insulating layer 19b and is formed on the same layer as the second planarization film 21a. Furthermore, as... Figure 13 As shown, the central portion of the first organic insulating layer 19b in the width direction is formed to be thicker than the two ends in the width direction. Additionally, as... Figure 13 As shown, the second organic insulating layer 21b is configured to be narrower than the width of the first organic insulating layer 19b.

[0044] like Figure 10 As shown, multiple bumps 61 are provided on the back side of the integrated circuit chip 60. Here, as... Figure 7As shown, the plurality of chip terminals including the plurality of first output terminals 18g, the plurality of second output terminals 18h and the plurality of input terminals 18j provided at the chip mounting portion M in the frame region F of the organic EL display panel 50a are arranged to correspond to the plurality of bumps 61. In addition, as Figure 9 and Figure 10 shown, the plurality of chip terminals (the first output terminals 18g, the second output terminals 18h, and the input terminals 18j) are respectively electrically connected to the plurality of bumps 61 via an anisotropic conductive film 65, specifically via conductive particles 64 in the anisotropic conductive film 65. Here, as Figure 10 shown, the anisotropic conductive film 65 includes, for example, a resin material 63 made of thermosetting resin and conductive particles 64 dispersed in the resin material 63.

[0045] A flexible printed circuit (FPC) board 55 is mounted on the terminal portion T via the anisotropic conductive film 65.

[0046] In the above organic EL display device 70a, in each sub-pixel P, a gate signal is input to the first TFT 9a via the gate line 14g, so that the first TFT 9a is turned on, a predetermined voltage corresponding to the source signal is written into the gate electrode 14g of the second TFT 9b and the capacitor 9d via the source line 18f, and when a light emission control signal is input to the third TFT 9c via the light emission control line 14e, the third TFT 9c is turned on, and a current corresponding to the gate voltage of the second TFT 9b is supplied from the power line 20a to the organic EL layer 33, thereby the light emitting layer 3 of the organic EL layer 33 emits light to perform image display. In addition, in the organic EL display device 70a, even if the first TFT 9a is turned off, since the gate voltage of the second TFT 9b is held by the capacitor 9d, the light emission of the light emitting layer 3 is maintained for each pixel P until the gate signal of the next frame is input.

[0047] Next, a method of manufacturing the organic EL display device 70a according to the present embodiment will be described. In addition, the method of manufacturing the organic EL display device 70a according to the present embodiment includes a TFT layer forming step, an organic EL element layer forming step and a sealing film forming step.

[0048] ~ Organic EL Display Panel Manufacturing Step ~ <TFT layer forming step> First, for example, after a non-photosensitive polyimide resin (with a thickness of about 10 μm) is coated on a glass substrate, pre-baking and post-baking are performed on the coated film to form the flexible substrate layer 6.

[0049] Subsequently, a silicon oxide film (approximately 500 nm thick) and a silicon nitride film (approximately 100 nm thick) are sequentially formed on the surface of the substrate on which the flexible substrate layer 10 is formed by, for example, plasma CVD, thereby forming a base coating film 11.

[0050] Next, an amorphous silicon film (with a thickness of about 50 nm) is formed on the surface of a substrate on which the base coating film 11 is formed by plasma CVD. After the amorphous silicon film is crystallized by laser annealing or the like to form a polycrystalline silicon semiconductor film, the semiconductor film is patterned to form a semiconductor patterned layer such as semiconductor layer 12a.

[0051] Subsequently, an inorganic insulating film (around 100 nm) such as a silicon oxide film is deposited on the surface of a substrate on which a semiconductor pattern layer is formed by, for example, plasma CVD, to form a gate insulating film 13 covering the semiconductor layer 12a.

[0052] Furthermore, after a molybdenum film (approximately 250 nm thick) is formed on the surface of the substrate on which the gate insulating film 13 is formed, the molybdenum film is patterned to form a first wiring layer, including gate line 14g, first output side terminal wiring 14tc, second output side terminal wiring 14td, and input side terminal wiring 14tf.

[0053] Next, by using the first wiring layer as a mask, impurity ions are doped, thereby forming intrinsic regions and conductor regions in semiconductor layer 12a.

[0054] Then, by using, for example, plasma CVD, an inorganic insulating film (about 100 nm thick) such as a silicon oxide film is formed on the surface of a substrate having an intrinsic region and a conductor region, thereby forming a first interlayer insulating film 15.

[0055] Next, for example, a molybdenum film (about 250 nm thick) is deposited on the surface of a substrate on which the first interlayer insulating film 15 is formed by sputtering, and the molybdenum film is patterned to form a third wiring layer such as an upper conductive layer 16c.

[0056] Furthermore, a second interlayer insulating film 17 is formed by sequentially depositing a silicon oxide film (approximately 300 nm thick) and a silicon nitride film (approximately 200 nm thick) on the surface of the substrate on which the third wiring layer is formed, for example, by plasma CVD.

[0057] Then, by patterning the gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 17, a contact hole is formed, and a first inorganic insulating layer 15a and a second inorganic insulating layer 17a are formed.

[0058] Then, on the substrate surface where the above-mentioned contact holes are formed, for example by sputtering, titanium film (thickness of about 50 nm), aluminum film (thickness of about 600 nm) and titanium film (thickness of about 50 nm) are sequentially formed. These metal stacked films are then patterned to form a second wiring layer including source line 18f, first output terminal 18g, second output terminal 18h, input terminal 18j, etc.

[0059] Furthermore, after coating a photosensitive polyimide resin (approximately 2.5 μm thick) onto the substrate surface where the second wiring layer is formed using methods such as spin coating or slot coating, the coated film is pre-baked, exposed, developed, and then post-baked to form a first planarization film 19a and an organic insulating layer 19b. In addition, regarding the organic insulating layer 19b, a half-exposure is performed, for example, using a grayscale mask, so that the central portion in the width direction is thicker than the two ends in the width direction.

[0060] Then, by means of, sputtering, titanium film (thickness of about 50 nm), aluminum film (thickness of about 600 nm), and titanium film (thickness of about 50 nm) are sequentially deposited on the substrate surface on which the first planarization film 19a is formed, and these metal stacked films are patterned to form the fourth wiring layer such as power line 20a.

[0061] Finally, by using, for example, spin coating or slot coating, a polyimide photosensitive resin film (approximately 2.5 μm thick) is coated on the surface of the substrate on which the fourth wiring layer is formed. The coated film is then pre-baked, exposed, developed, and post-baked to form the second planarization film 21a.

[0062] As described above, TFT layer 30 can be manufactured.

[0063] <Organic EL Component Formation Process> An organic EL element 40 is formed on the second planarization film 21a of the TFT layer 30 formed in the above-mentioned TFT layer formation process by using a known method, forming a first electrode 31a, an edge mask 32a, an organic EL layer 33 (hole injection layer 1, hole transport layer 2, light emission layer 3, electron transport layer 4, electron injection layer 5) and a second electrode 34.

[0064] <Sealing film formation process> First, on the surface of the substrate on which the organic EL element layer 40 is formed in the above-mentioned organic EL element layer formation process, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed by plasma CVD using a mask, thereby forming a first inorganic sealing film 41.

[0065] Next, an organic sealing film 42 is formed on the surface of the substrate on which the first inorganic sealing film 41 is formed, for example, using an organic resin material such as an acrylic resin formed by inkjet printing.

[0066] Subsequently, an inorganic insulating film, such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film, is formed on the substrate surface on which the organic sealing film 42 is formed using a mask, for example, by plasma CVD, and a sealing film 45 is formed by forming a second inorganic sealing film 43.

[0067] Furthermore, after attaching a surface-side protective sheet (not shown) to the substrate surface on which the sealing film 45 is formed, the glass substrate is peeled off from the lower surface of the flexible substrate layer 10 by irradiating a laser from the glass substrate side of the flexible substrate layer 10. Further, an inner-side protective sheet (not shown) is attached to the lower surface of the flexible substrate layer 10 after the glass substrate has been peeled off.

[0068] As described above, it is possible to manufacture an organic EL display panel 50a.

[0069] -Installation Procedure- First, by irradiating the protective sheet on the surface side of the organic EL display panel 50a manufactured in the above-mentioned organic EL display panel manufacturing process with a laser, the protective sheet is partially removed, exposing the chip mounting portion M and the terminal portion T.

[0070] Next, the anisotropic conductive film 65 is temporarily fixed to the chip mounting part M and the terminal part T.

[0071] Furthermore, after aligning the integrated circuit chip 60 and the flexible printed wiring substrate 55 with the chip mounting portion M and the terminal portion T respectively, the integrated circuit chip 60 and the flexible printed wiring substrate 55 are pressed by a crimping tool to install the integrated circuit chip 60 and the flexible printed wiring substrate 55 onto the chip mounting portion M and the terminal portion T respectively.

[0072] As described above, the organic EL display device 70a of this embodiment can be manufactured.

[0073] As explained above, in the organic EL display device 70a according to this embodiment, chip supports Sa are arranged in a double-comb pattern between multiple first output terminals 18g and multiple second output terminals 18h in the chip mounting section M of the bezel region F, and chip supports Sb are arranged in an island pattern between multiple input terminals 18j. Therefore, during the mounting process, the conductive particles 64 in the anisotropic conductive film 65 are squeezed out and moved by the chip supports Sa and Sb, thereby becoming relatively dense on the chip terminals of the first output terminals 18g, second output terminals 18h, and input terminals 18j, and relatively sparse between the chip terminals. As a result, it is difficult for conductive particles 64 to connect between adjacent chip terminals, thus suppressing short circuits between adjacent chip terminals caused by the connection of conductive particles 64, and suppressing short circuits between terminals of the chip mounting section M.

[0074] Furthermore, in the organic EL display device 70a according to this embodiment, chip supports Sa and Sb are provided near each chip terminal of a plurality of first output terminals 18g, a plurality of second output terminals 18h, and a plurality of input terminals 18j in the chip mounting section M of the bezel region F. Therefore, it is possible to suppress the bending of the organic EL display panel 50a near each bump 61 of the integrated circuit chip 60 during the mounting process. As a result, it is possible to suppress the generation of cracks in the substrate film 11, gate insulating film 13, first interlayer insulating film 15, and second interlayer insulating film 17 of the organic EL display panel 50a, and it is possible to suppress the breakage of the first output side terminal wiring 14tc, the second output side terminal wiring 14td, and the input side terminal wiring 14tf disposed between the gate insulating film 13 and the first interlayer insulating film 15.

[0075] Second Implementation Method Figures 14-15 A second embodiment of the display device according to the present invention is shown. Here, Figure 14 This is a top view showing the first output terminal 18g, second output terminal 18h, third output terminal 18i, and chip support Sc of the chip mounting portion M in the bezel area F of the organic EL display panel 50b constituting the organic EL display device of this embodiment. It is equivalent to... Figure 7 The image. Additionally. Figure 15 This is a top view of a modified example of the organic EL display panel 50b, namely the organic EL display panel 50ba. Figure 14 A comparable diagram. Furthermore, in the following embodiments, regarding... Figures 1 to 13 Identical parts are labeled with the same reference numerals, and their detailed descriptions are omitted.

[0076] In the first embodiment described above, an organic EL display panel 50a with output terminals 18g and 18h ​​having a two-level structure when viewed from above was exemplified. However, in this embodiment, an organic EL display device with an organic EL display panel 50b having output terminals 18g, 18h and 18i having a three-level structure when viewed from above was exemplified.

[0077] The organic EL display device of this embodiment is similar to the organic EL display device 70a of the first embodiment described above, including an organic EL display panel 50b, an integrated circuit chip 60 mounted on the chip mounting portion M of the organic EL display panel 50b, and a flexible printed wiring substrate 55 mounted on the terminal portion T of the organic EL display panel 50b.

[0078] Similar to the organic EL display panel 50a of the first embodiment described above, for example, the organic EL display panel 50b is provided with a rectangular display area D for displaying images and a frame-shaped border area F disposed around the display area D.

[0079] In addition, similar to the organic EL display panel 50a of the first embodiment described above, the organic EL display panel 50b includes a flexible substrate layer 10, a TFT layer 30 disposed on the flexible substrate layer 10, an organic EL element layer 40 disposed on the TFT layer 30, and a sealing film 45 disposed to cover the organic EL element layer 40.

[0080] Furthermore, the organic EL display panel 50b includes a chip mounting section M in the bezel area F: a chip under-circuit section C; and multiple first output-side terminal wirings 14tc, multiple second output-side terminal wirings 14td, and multiple third output-side terminal wirings 14te (see reference) arranged in parallel to each other on the display area D side of the chip under-circuit section C. Figure 14 ); and multiple input-side terminal wirings 14tf (refer to) arranged in a manner that extends parallel to each other on the terminal T side of the lower circuit section C of the chip. Figure 6 Here, as Figure 14 As shown, each third output-side terminal wiring 14te is configured to be adjacent to each first output-side terminal wiring 14tc and each second output-side terminal wiring 14td. Furthermore, the third output-side terminal wiring 14te, the first output-side terminal wiring 14tc, and the second output-side terminal wiring 14td are configured as a first wiring layer.

[0081] Furthermore, the organic EL display panel 50b includes, in the chip mounting section M of the bezel region F: a plurality of first output terminals 18g, arranged in a row along the long side of the display region D of the lower circuit section C as chip terminals; a plurality of second output terminals 18h, arranged in a row along the long side of the display region D of the lower circuit section C as chip terminals; and a plurality of third output terminals 18i (see reference 18h). Figure 14 On the display area D side of the lower circuit section C, multiple first output terminals 18g and multiple second output terminals 18h are arranged in a row along the long side of the display area D side of the lower circuit section C; and multiple input terminals 18j are arranged in a row along the long side of the terminal section T side of the lower circuit section C as chip terminals. Here, as Figure 14 As shown, a plurality of first output terminals 18g, a plurality of third output terminals 18i, and a plurality of second output terminals 18h are repeatedly arranged in the order of first output terminals 18g, third output terminals 18i, and second output terminals 18h. Furthermore, the third output terminals 18i, like the first output terminals 20c and second output terminals 18h, are provided as a second wiring layer. Additionally, the plurality of third output terminals 18i are respectively stacked on a plurality of third output side terminal wirings 14te and are electrically connected to the plurality of third output side terminal wirings 14te. Moreover, the plurality of third output terminals 18i, like the plurality of first output terminals 18j and the plurality of second output terminals 18h, are configured to correspond to a plurality of bumps 61 on the back side of the integrated circuit chip 60 and are electrically connected to the plurality of bumps 61 via an anisotropic conductive film 65.

[0082] In addition, such as Figure 14 As shown, the organic EL display panel 50b includes: a chip support Sc, which is arranged in an island-like manner between a plurality of first output terminals 18g and a plurality of second output terminals 18h in the chip mounting portion M of the bezel region F; and a chip support Sb (see reference). Figure 6 as well as Figure 8 The chips are arranged in an island-like pattern among multiple input terminals 18j. Additionally, the chip support Sc... Figure 14 As shown, it is not positioned among the multiple third output terminals 18i.

[0083] Similar to the chip support Sa of the first embodiment described above, the chip support Sc includes: a first inorganic insulating layer 15a formed on the same layer using the same material as the first interlayer insulating film 15; a second inorganic insulating layer 17a formed on the same layer using the same material as the second inorganic insulating film 17, disposed on the first inorganic insulating layer 15a; and an organic insulating layer 19b formed on the same layer using the same material as the first planarization film 19a, disposed on the second inorganic insulating layer 17a. Furthermore, since the first output-side terminal wiring 14tc and the first output terminal 18g, as well as the second output-side terminal wiring 14td and the second output terminal 18h, extend to both ends in the width direction of the chip support Sc, the gap between the integrated circuit chip 60 and the chip support Sc is narrowed. Therefore, panel deflection at the first output terminal 18g and the second output terminal 18h during chip bonding can be suppressed, and line breakage at the first output terminal 18g, the second output terminal 18h, the first output-side terminal wiring 14tc, and the second output-side terminal wiring 14td can be suppressed. Additionally, as... Figure 14 As shown, the chip support Sc located on the display area D side (the upper side in the figure) is positioned outside the chip mounting part M (the peripheral end E of the integrated circuit chip 60). Therefore, in the absence of the bump 61, the gap between the integrated circuit chip 60 and the chip support Sc is also narrowed, thus suppressing panel deflection during chip pressing.

[0084] Furthermore, in this embodiment where the spacing between the third output terminal 18i and the first output terminal 18g and the second output terminal 18h is relatively narrow, an organic EL display panel 50b is illustrated where chip supports are not provided on the plurality of third output terminals 18i. However, it is also possible to use an organic EL display panel 50b such as the one shown above. Figure 15 The organic EL display panel 50ba is shown. Specifically, in the organic EL display panel 50ba, the spacing between the third output terminal 18i and the first output terminal 18g and the second output terminal 18h is designed to be relatively wide, and a chip support Sd is disposed between the plurality of third output terminals 18i. Here, as Figure 15 As shown, the chip support Sd is connected to the chip support (Sd) disposed between the plurality of first output terminals 18g and the chip support (Sd) disposed between the plurality of second output terminals 18h. Furthermore, in this modified example, a chip support Sd is shown in which the portion between the plurality of third output terminals 18i is connected to the portions between the plurality of first output terminals 18g and the portions between the plurality of second output terminals 18h respectively. However, the portion between the plurality of third output terminals 18i may also be separate from the portions between the plurality of first output terminals 18g and the portions between the plurality of second output terminals 18h, or it may be connected to the portions between the plurality of first output terminals 18g or the portions between the plurality of second output terminals 18h respectively.

[0085] The organic EL display device 70a of this embodiment, which includes the organic EL display panel 50b described above, is flexible in the same way as the organic EL display device 70a of the first embodiment described above, and in each sub-pixel P, the light-emitting layer 3 of the organic EL layer 33 is appropriately illuminated by the first TFT 9a, the second TFT 9b and the third TFT 9c to display an image.

[0086] Furthermore, in this embodiment, an organic EL display device is illustrated, which has an organic EL display panel 50b having an output terminal 18g, 18h and 18i with a three-segment structure when viewed from above. However, it may also be an organic EL display device having an organic EL display panel having an output terminal with a structure of four or more segments when viewed from above.

[0087] The organic EL display device equipped with the organic EL display panel 50b of this embodiment can be manufactured by changing the pattern shape of the first wiring layer, the second wiring layer, the first inorganic insulating layer 15a, the second inorganic insulating layer 17a and the organic insulating layer 19b in the manufacturing method of the organic EL display device 70a of the first embodiment described above.

[0088] As described above, in the OLED display device with OLED display panel 50b according to this embodiment, in the chip mounting section M of the bezel region F, chip supports Sc are arranged in an island-like pattern between multiple first output terminals 18g and multiple second output terminals 18h, and chip supports Sb are arranged in an island-like pattern between multiple input terminals 18j. Therefore, during the mounting process, the conductive particles 64 in the anisotropic conductive film 65 are pushed out and moved by the chip supports Sc and Sb, thereby becoming relatively dense on the chip terminals of the first output terminals 18g, second output terminals 18h, and input terminals 18j, and relatively sparse between the chip terminals. As a result, it is difficult for conductive particles 64 to connect between adjacent chip terminals, thus suppressing short circuits between adjacent chip terminals caused by the connection of conductive particles 64, and suppressing short circuits between terminals of the chip mounting section M.

[0089] Furthermore, in the organic EL display device with organic EL display panel 50b according to this embodiment, chip supports Sc and Sb are provided near each chip terminal of a plurality of first output terminals 18g, a plurality of second output terminals 18h, and a plurality of input terminals 18j in the chip mounting section M of the bezel region F. Therefore, it is possible to suppress the deflection of the organic EL display panel 50b near each bump 61 of the integrated circuit chip 60 during the mounting process. As a result, it is possible to suppress the generation of cracks in the substrate film 11, gate insulating film 13, first interlayer insulating film 15, and second interlayer insulating film 17 of the organic EL display panel 50b, and it is possible to suppress the breakage of the first output side terminal wiring 14tc, second output side terminal wiring 14td, third output side terminal wiring 14te, and input side terminal wiring 14tf provided on the second interlayer insulating film 17.

[0090] Third Implementation Method Figures 16 to 19 A third embodiment of the display device according to the present invention is shown. Here, Figure 16 This is a top view showing the first output terminal 18g, the second output terminal 18h, and the chip support Se of the chip mounting portion M in the bezel area F of the organic EL display panel 50c constituting the organic EL display device of this embodiment. It is equivalent to... Figure 7 The image. Figure 17 , Figure 18 and Figure 19 This is a top view of the first modified example of the organic EL display panel 50ca, the second modified example of the organic EL display panel 50cb, and the third modified example of the organic EL display panel 50cc, which is equivalent to... Figure 16 The image.

[0091] In the first embodiment described above, an organic EL display device 70a with an organic EL display panel 50a is illustrated, wherein the organic EL display panel 50a is provided with a chip support formed with a certain width. However, in this embodiment, an organic EL display device with an organic EL display panel 50c is illustrated, wherein the organic EL display panel 50c is provided with a chip support partially formed as wide or narrow.

[0092] The organic EL display device of this embodiment is similar to the organic EL display device 70a of the first embodiment described above, including an organic EL display panel 50c, an integrated circuit chip 60 mounted on the chip mounting portion M of the organic EL display panel 50c, and a flexible printed circuit board 55 mounted on the terminal portion T of the organic EL display panel 50c.

[0093] Similar to the organic EL display panel 50a of the first embodiment described above, for example, the organic EL display panel 50c is configured with a rectangular display area D for displaying images and a frame-shaped border area F surrounding the display area D.

[0094] In addition, similar to the organic EL display panel 50a of the first embodiment described above, the organic EL display panel 50c includes a flexible substrate layer 10, a TFT layer 30 disposed on the flexible substrate layer 10, an organic EL element layer 40 disposed on the TFT layer 30, and a sealing film 45 disposed to cover the organic EL element layer 40.

[0095] Furthermore, similar to the OLED display panel 50b of the first embodiment described above, the OLED display panel 50c includes, in the chip mounting portion M of the bezel region F: a chip under-circuit portion C; a plurality of first output-side terminal wirings 14tc and a plurality of second output-side terminal wirings 14td respectively provided in a manner that extends parallel to each other on the display region D side of the chip under-circuit portion C; and a plurality of input-side terminal wirings 14tf provided in a manner that extends parallel to each other on the terminal portion T side of the chip under-circuit portion C (see reference). Figure 6 as well as Figure 8 ).

[0096] In addition, such as Figure 16 As shown, similarly to the OLED display panel 50a of the first embodiment described above, the OLED display panel 50c includes the following in the chip mounting portion M of the bezel region F: a plurality of first output terminals 18g, which are arranged in a row along the long side of the display region D of the lower circuit section C as chip terminals (upper side in the figure); a plurality of second output terminals 18h, which are arranged in a row along the long side of the display region D of the lower circuit section C as chip terminals (lower side in the figure); and a plurality of input terminals 18j, which are arranged in a row along the long side of the terminal portion T of the lower circuit section C as chip terminals (lower side in the figure) (see reference). Figure 6 as well as Figure 8 ).

[0097] Additionally, as shown in the figure Figure 16 As shown, the organic EL display panel 50c includes, in the chip mounting portion M of the bezel region F: a chip support Se, integrally disposed in a double-comb-like pattern between a plurality of first output terminals 18g and a plurality of second output terminals 18h; and a chip support Sb, disposed in an island-like pattern between a plurality of input terminals 18j (see reference). Figure 6 as well as Figure 8 ).

[0098] Similar to the chip support Sa of the first embodiment described above, the chip support Se includes: a first inorganic insulating layer 15a formed on the same layer using the same material as the first interlayer insulating film 15; a second inorganic insulating layer 17a formed on the same layer using the same material as the second inorganic insulating film 17, disposed on the first inorganic insulating layer 15a; and an organic insulating layer 19b formed on the same layer using the same material as the first planarization film 19a, disposed on the second inorganic insulating layer 17a. Furthermore, since the first output-side terminal wiring 14tc and the first output terminal 18g, as well as the second output-side terminal wiring 14td and the second output terminal 18h, extend to both ends in the width direction of the chip support Se, the gap between the integrated circuit chip 60 and the chip support Se is narrowed. Therefore, panel deflection at the first output terminal 18g and the second output terminal 18h during chip bonding can be suppressed, and line breakage at the first output terminal 18g, the second output terminal 18h, the first output-side terminal wiring 14tc, and the second output-side terminal wiring 14td can be suppressed. Additionally, as... Figure 16 As shown, the display area D side (upper side in the figure) of the chip support Se, which is located on the display area D side, is positioned outside the chip mounting portion M (the peripheral end E of the integrated circuit chip 60). Therefore, in the absence of the bump 61, the gap between the integrated circuit chip 60 and the chip support Se is narrowed, thus suppressing panel deflection during chip bonding. Furthermore, the display area D side (upper side in the figure) and the terminal portion T side (lower side in the figure) of the chip support Se are as follows... Figure 16 As shown, the anisotropic conductive film 65 is set in a triangular pyramid shape that tapers towards the front end. Therefore, the outlet of the resin material 63 of the anisotropic conductive film 65 used in the installation process is widened, and the resin material 63 flows easily. As a result, the conductive particles 64 of the anisotropic conductive film 65 are dispersed, which can further suppress short circuits between adjacent chip terminals caused by the connection of conductive particles 64.

[0099] Furthermore, in this embodiment, an organic EL display panel 50c is exemplified, which is provided with a chip support Se that widens in the middle and tapers at the top of the peripheral end E of the integrated circuit chip 60, but it may also be provided with... Figure 17 The organic EL display panel 50ca of the chip support Sea shown is equipped with... Figure 18 The organic EL display panel 50cb with the chip support Seb shown is provided with Figure 19 The organic EL display panel with a chip support Sec as shown is 50cc.

[0100] In the organic EL display panel 50ca, the display area D side (the upper side in the figure) of the chip support Sea is as follows: Figure 17The portion shown is located on the outer side of the chip mounting portion M (the peripheral end E of the integrated circuit chip 60). The outer portion is wider at the peripheral end E of the integrated circuit chip 60. Therefore, in areas without bumps 61, the gap between the integrated circuit chip 60 and the chip support Sea is narrowed, thus further suppressing panel deflection during chip bonding. Additionally, as shown... Figure 17 As shown, the display area D side (upper side in the figure) and the terminal T side (lower side in the figure) of the chip support Sea are set to be approximately hemispherical in a manner that tapers towards the front end.

[0101] In the organic EL display panel 50cb, the display area D side (the upper side in the figure) of the chip support Seb is as follows: Figure 18 The portion shown is located on the outer side of the chip mounting portion M (the peripheral end E of the integrated circuit chip 60), and its outer portion is configured as a triangular pyramid shape that gradually tapers towards the front end. Here, the display area D side (upper side in the figure) and the terminal portion T side (lower side in the figure) of the chip support Seb are as follows... Figure 18 As shown, the anisotropic conductive film 65 is set in a triangular pyramid shape that tapers towards the front end. Therefore, the outlet of the resin material 63 of the anisotropic conductive film 65 used in the installation process is widened, and the resin material 63 flows easily. As a result, the conductive particles 64 of the anisotropic conductive film 65 are dispersed, which can further suppress short circuits between adjacent chip terminals caused by the connection of conductive particles 64.

[0102] In the 50cc organic EL display panel, the display area D side (the upper side in the figure) of the chip support Sec is as follows: Figure 19 The portion shown is located on the outer side of the chip mounting portion M (the peripheral end E of the integrated circuit chip 60), and its outer portion is configured as a triangular pyramid shape that gradually tapers towards the front end. Here, the display area D side (upper side in the figure) and the terminal portion T side (lower side in the figure) of the chip support Sec are as follows... Figure 18 As shown, these front ends are alternately arranged in an alternating pattern along the long side of the chip mounting portion M. The outlet of the resin material 63 of the anisotropic conductive film 65 used in the mounting process is widened at an angle relative to the long side of the chip mounting portion M. The resin material 63 flows easily, so the conductive particles 64 of the anisotropic conductive film 65 are dispersed, which can further suppress short circuits between adjacent chip terminals caused by the connection of conductive particles 64.

[0103] The organic EL display device 70a of this embodiment, which includes the organic EL display panel 50c described above, is flexible in the same way as the organic EL display device 70a of the first embodiment described above, and in each sub-pixel P, the light-emitting layer 3 of the organic EL layer 33 is appropriately illuminated by the first TFT 9a, the second TFT 9b and the third TFT 9c to display an image.

[0104] The organic EL display device equipped with the organic EL display panel 50c of this embodiment can be manufactured by changing the pattern shape of the first inorganic insulating layer 15a, the second inorganic insulating layer 17a and the organic insulating layer 19b in the manufacturing method of the organic EL display device 70a of the first embodiment described above.

[0105] As described above, in the OLED display device with OLED display panel 50c according to this embodiment, chip supports Se are arranged in a double-comb pattern between multiple first output terminals 18g and multiple second output terminals 18h in the chip mounting section M of the bezel region F, and chip supports Sb are arranged in an island pattern between multiple input terminals 18j. Therefore, during the mounting process, the conductive particles 64 in the anisotropic conductive film 65 are pushed out and moved by the chip supports Se and Sb, thereby becoming relatively dense on the chip terminals of the first output terminals 18g, second output terminals 18h, and input terminals 18j, and relatively sparse between the chip terminals. As a result, it is difficult for conductive particles 64 to connect between adjacent chip terminals, thus suppressing short circuits between adjacent chip terminals caused by the connection of conductive particles 64, and suppressing short circuits between terminals of the chip mounting section M.

[0106] Furthermore, in the organic EL display device with organic EL display panel 50c according to this embodiment, chip supports Se and Sb are provided near each chip terminal of a plurality of first output terminals 18g, a plurality of second output terminals 18h, and a plurality of input terminals 18j in the chip mounting section M of the bezel region F. Therefore, it is possible to suppress the deflection of the organic EL display panel 50c near each bump 61 of the integrated circuit chip 60 during the mounting process. As a result, it is possible to suppress the generation of cracks in the substrate film 11, gate insulating film 13, first interlayer insulating film 15, and second interlayer insulating film 17 of the organic EL display panel 50c, and it is possible to suppress the breakage of the first output side terminal wiring 14tc, the second output side terminal wiring 14td, and the input side terminal wiring 14tf disposed between the gate insulating film 13 and the first interlayer insulating film 15.

[0107] [Fourth Implementation Method] Figure 20 A fourth embodiment of the display device according to the present invention is shown. Here, Figure 20 This is an enlarged top view of the chip mounting portion M in the bezel area F of the organic EL display panel 50d constituting the organic EL display device of this embodiment, which is equivalent to... Figure 6 The image.

[0108] In the first embodiment described above, an organic EL display device 70a is illustrated, which has an organic EL display panel 50a having chip terminals provided along the long side of the chip mounting portion M. However, in this embodiment, an organic EL display device is illustrated, which has an organic EL display panel 50d having chip terminals provided along the short side of the chip mounting portion M.

[0109] The organic EL display device of this embodiment is similar to the organic EL display device 70a of the first embodiment described above, including an organic EL display panel 50d, an integrated circuit chip 60 mounted on the chip mounting portion M of the organic EL display panel 50d, and a flexible printed circuit board 55 mounted on the terminal portion T of the organic EL display panel 50d.

[0110] Similar to the organic EL display panel 50a of the first embodiment described above, for example, the organic EL display panel 50d is configured with a rectangular display area D for displaying images and a frame-shaped border area F surrounding the display area D.

[0111] In addition, similar to the organic EL display panel 50a of the first embodiment described above, the organic EL display panel 50d includes a flexible substrate layer 10, a TFT layer 30 disposed on the flexible substrate layer 10, an organic EL element layer 40 disposed on the TFT layer 30, and a sealing film 45 disposed to cover the organic EL element layer 40.

[0112] In addition, such as Figure 20 As shown, the organic EL display panel 50d includes the following in the chip mounting section M of the bezel area F: a chip under-circuit section C; a plurality of first output side terminal wirings 14tc and a plurality of second output side terminal wirings 14td respectively arranged in parallel to each other on the display area D side of the chip under-circuit section C; a plurality of input side terminal wirings 14tf arranged in parallel to each other on the terminal section T side of the chip under-circuit section C; and a plurality of short side terminal wirings 14tg arranged in parallel to each other on the left side of the chip under-circuit section C in the figure.

[0113] In addition, such as Figure 20As shown, the organic EL display panel 50a includes the following in the chip mounting section M of the bezel area F: a plurality of first output terminals 18g, which are arranged in a row along the long side of the display area D side of the lower chip circuit section C as chip terminals; a plurality of second output terminals 18h, which are arranged in a row along the long side of the display area D side of the lower chip circuit section C as chip terminals; a plurality of input terminals 18j, which are arranged in a row along the long side of the terminal T side of the lower chip circuit section C as chip terminals; and a plurality of short side terminals 18k, which are arranged in a row along the short side of the chip mounting section M on the left side of the lower chip circuit section C as chip terminals.

[0114] In addition, such as Figure 20 As shown, the organic EL display panel 50d includes: a chip support Sa, which is integrally disposed in a double comb-like manner in the chip mounting portion M of the bezel region F between a plurality of first output terminals 18g and a plurality of second output terminals 18h; a chip support Sb, which is disposed island-like among a plurality of input terminals 18j; and a chip support Sg, which is disposed island-like among a plurality of short-side terminals 18k.

[0115] Similar to the chip support Sa of the first embodiment described above, the chip support Sg includes: a first inorganic insulating layer 15a formed on the same layer using the same material as the first interlayer insulating film 15; a second inorganic insulating layer 17a formed on the same layer using the same material as the second inorganic insulating film 17, disposed on the first inorganic insulating layer 15a; and an organic insulating layer 19b formed on the same layer using the same material as the first planarization film 19a, disposed on the second inorganic insulating layer 17a. Furthermore, since the short-side terminal wiring 14tg and the short-side terminal 18k extend to both ends in the width direction of the chip support Sg, the gap between the integrated circuit chip 60 and the chip support Sg is narrowed. Therefore, bending of the panel at the short-side terminal 18k during chip bonding can be suppressed, and breakage of the short-side terminal 18k and the short-side terminal wiring 14tg can be suppressed. Additionally, as... Figure 20 As shown, the chip support Sg on the display area D side (upper side in the figure) and the chip support Sg on the terminal T side (lower side in the figure) of the plurality of chip supports Sg are respectively integrated with chip support Sa and chip support Sb. In addition, even when adjacent chip supports are integrated, the flowability of resin material 63 can be ensured as long as there is at least one outlet for resin material 63 of anisotropic conductive film 65 used in the mounting process.

[0116] The organic EL display device 70a of this embodiment, which includes the organic EL display panel 50d described above, is flexible in the same way as the organic EL display device 70a of the first embodiment described above, and in each sub-pixel P, the light-emitting layer 3 of the organic EL layer 33 is appropriately illuminated by the first TFT 9a, the second TFT 9b and the third TFT 9c to display an image.

[0117] The organic EL display device equipped with the organic EL display panel 50d of this embodiment can be manufactured by changing the pattern shape of the first wiring layer, the second wiring layer, the first inorganic insulating layer 15a, the second inorganic insulating layer 17a and the organic insulating layer 19b in the manufacturing method of the organic EL display device 70a of the first embodiment described above.

[0118] As described above, in the organic EL display device with organic EL display panel 50d according to this embodiment, chip supports Sa are arranged in a double-comb pattern between multiple first output terminals 18g and multiple second output terminals 18h in the chip mounting section M of the bezel region F. Chip supports Sb are arranged in an island pattern between multiple input terminals 18j, and chip supports Sg are arranged in an island pattern between multiple short-side terminals 18k. Therefore, during the mounting process, the conductive particles 64 in the anisotropic conductive film 65 are squeezed out and moved by the chip supports Sa, Sb, and Sg, thereby becoming relatively dense on the chip terminals of the first output terminals 18g, second output terminals 18h, input terminals 18j, and short-side terminals 18k, and relatively sparse between the chip terminals. As a result, it is difficult for conductive particles 64 to connect between adjacent chip terminals, thus suppressing short circuits between adjacent chip terminals caused by the connection of conductive particles 64, and suppressing short circuits between terminals of the chip mounting section M.

[0119] Furthermore, in the organic EL display device with organic EL display panel 50d according to this embodiment, chip supports Sa, Sb, and Sg are provided near each chip terminal of a plurality of first output terminals 18g, a plurality of second output terminals 18h, a plurality of input terminals 18j, and a plurality of short-side terminals 18k in the chip mounting section M of the bezel region F. Therefore, bending of the organic EL display panel 50d near each bump 61 of the integrated circuit chip 60 during the mounting process can be suppressed. As a result, cracks can be suppressed in the substrate film 11, gate insulating film 13, first interlayer insulating film 15, and second interlayer insulating film 17 of the organic EL display panel 50d, and breakage of the first output-side terminal wiring 14tc, second output-side terminal wiring 14td, input-side terminal wiring 14tf, and short-side terminal wiring 14tg provided on the gate insulating film 13 and the first interlayer insulating film 15 can be suppressed.

[0120] Other Implementation Methods In the above embodiments, an organic EL display device having organic EL display panels 50a, 50b, 50c and 50d is shown as an example. However, the present invention can also be applied to organic EL display devices and the like by appropriately combining the feature parts of each embodiment.

[0121] Furthermore, in the above embodiments, an organic EL display device in which bumps are arranged in a regular and correct manner in a direction parallel or perpendicular to the long and short sides of the integrated circuit chip is exemplified. However, the present invention is not limited to this. For example, it can also be applied to an organic EL display device in which bumps are arranged in a way that is tilted relative to the long and short sides of the integrated circuit chip.

[0122] Furthermore, in the above embodiments, an organic EL layer with a five-layer stacked structure of a hole injection layer, a hole transport layer, a light emission layer, an electron transport layer, and an electron injection layer is exemplified. However, the organic EL layer may also be a three-layer stacked structure of a hole injection layer that also serves as a hole transport layer, a light emission layer, and an electron transport layer that also serves as an electron injection layer.

[0123] Furthermore, in the above embodiments, an organic EL display device is illustrated in which the first electrode is set as the anode and the second electrode is set as the cathode. However, the present invention can also be applied to an organic EL display device in which the stacked structure of the organic EL layer is reversed and the first electrode is set as the cathode and the second electrode is set as the anode.

[0124] Furthermore, in the above embodiments, an organic EL display device in which the electrode of the TFT connected to the first electrode is designated as the drain electrode is illustrated. However, the present invention can also be applied to organic EL display devices in which the electrode of the TFT connected to the first electrode is designated as the source electrode.

[0125] Furthermore, in the above embodiments, an organic EL display device was described as an example of a display device, but the present invention can be applied to display devices having multiple light-emitting elements driven by current, such as a display device having a QLED (Quantum-dot Light Emitting Diode), which is a light-emitting element using a quantum dot layer. Practicality in industry

[0126] As explained above, the present invention can be used in flexible display devices. Explanation of reference numerals in the attached figures

[0127] D display area F Border Area M chip mounting section P-subpixel Sa, Sb, Sc, Sd, Sg, Saa, Se, Sea, Seb, Sec chip support T-terminal section 10 Flexible substrate layer 13 Gate insulating film 14a, 14b gate electrodes (first wiring layer) 14c lower conductive layer (first wiring layer) 14g gate line (first wiring layer) 14e Light Emitting Control Line (First Wiring Layer) 14TC, 14TD, 14TE output side terminal wiring 14tf input side terminal wiring 15 First interlayer insulating film 15a First Inorganic Insulation Layer 17 Second interlayer insulating film 17a Second Inorganic Insulation Layer 18a, 18c source electrodes (second wiring layer) 18b, 18d drain electrodes (second wiring layer) 18f source line (second wiring layer) 18g First output terminal (chip terminal) 18h Second Output Terminal (Chip Terminal) 18i Third Output Terminal (Chip Terminal) 18J Input Terminal (Chip Terminal) 18k short-side terminal 19a First planarization film 19b Organic Insulation Layer, First Organic Insulation Layer 21a Second planarization film 21b Second organic insulating layer 30 TFT layers (thin-film transistor layers) 35 Organic EL components (organic electroluminescent components, light-emitting components) 40 Organic EL element layer (light-emitting element layer) 41 First Inorganic Sealing Membrane 42 Organic sealing film 43 Second Inorganic Sealing Membrane 45 Sealing film 50a, 50a, 50b, 50ba, 50c, 50ca, 50cb, 50cc, 50d Organic EL Display Panels 60 Integrated circuit chips 61 bumps 64 Conductive particles 65 Anisotropic conductive film 70a, 70aa organic EL display devices

Claims

1. A display device, characterized in that, include: Flexible substrate layer; A thin-film transistor layer is disposed on the flexible substrate layer; and A light-emitting element layer is disposed on the thin-film transistor layer, and multiple light-emitting elements are arranged corresponding to the multiple sub-pixels constituting the display area. A border area is provided around the display area. The terminal portion is provided at the end of the frame area in a manner that extends in one direction. A chip mounting portion is provided between the display area and the terminal portion. This chip mounting portion is a rectangle whose longer side extends along the extension direction of the terminal portion when viewed from above. The chip mounting section has a plurality of chip terminals arranged in a row, and a plurality of terminal wirings extending parallel to each other and electrically connected to the plurality of chip terminals. In the chip mounting section, a chip support is provided between the plurality of chip terminals. On the chip mounting portion, a plurality of input terminals are arranged in a row along the long side of the terminal portion as terminals for the plurality of chips. The chip support is arranged in an island-like pattern among the multiple input terminals. The terminal portion of each chip support provided for the plurality of input terminals is positioned on the outer side relative to the chip mounting portion.

2. The display device according to claim 1, characterized in that, The portion of the chip support that is located on the outer side of the chip mounting portion is wider at the periphery of the chip mounting portion.

3. The display device according to claim 1 or 2, characterized in that, The portion of the chip support that is located on the outer side relative to the chip mounting portion is designed to gradually taper towards the front end.

4. The display device according to claim 1 or 2, characterized in that, The front end of the chip support relative to the outer part of the chip mounting part is alternately and staggered along the long side of the chip mounting part.

5. The display device according to claim 1 or 2, characterized in that, On the chip mounting portion, a plurality of short-side terminals are arranged in a row along the short side of the chip mounting portion as terminals for the plurality of chips. The chip support is arranged in an island-like pattern among the multiple short-side terminals.

6. The display device according to claim 1 or 2, characterized in that, On the chip mounting section, an integrated circuit chip is mounted via an anisotropic conductive film.

7. The display device according to claim 6, characterized in that, include: On the back side of the integrated circuit chip, a plurality of bumps are provided in a manner corresponding to the terminals of the plurality of chips. The anisotropic conductive film contains conductive particles. The plurality of bumps and the plurality of chip terminals are electrically connected via the conductive particles.

8. The display device according to claim 1 or 2, characterized in that, It also includes a sealing film, which is disposed in such a way as to cover the light-emitting element layer, and is composed of a first inorganic sealing film, an organic sealing film and a second inorganic sealing film stacked in sequence.

9. The display device according to claim 1 or 2, characterized in that, Each of the light-emitting elements is an organic electroluminescent element.

10. A display device, characterized in that, include: Flexible substrate layer; A thin-film transistor layer is disposed on the flexible substrate layer; and A light-emitting element layer is disposed on the thin-film transistor layer, and multiple light-emitting elements are arranged corresponding to the multiple sub-pixels constituting the display area. A border area is provided around the display area. The terminal portion is provided at the end of the frame area in a manner that extends in one direction. A chip mounting portion is provided between the display area and the terminal portion. This chip mounting portion is a rectangle whose longer side extends along the extension direction of the terminal portion when viewed from above. The chip mounting section has a plurality of chip terminals arranged in a row, and a plurality of terminal wirings extending parallel to each other and electrically connected to the plurality of chip terminals. In the chip mounting section, a chip support is provided between the plurality of chip terminals. On the chip mounting section, a plurality of output terminals are arranged in a row along the long side of the display area as terminals for the plurality of chips. The plurality of output terminals includes: a plurality of first output terminals arranged in a row on the display area side; and a plurality of second output terminals arranged in a row on the terminal portion side. The plurality of first output terminals and the plurality of second output terminals are alternately and staggered along the long side of the chip mounting portion. The chip support is integrally disposed in a double comb-like shape between the plurality of first output terminals and between the plurality of second output terminals.

11. The display device according to claim 10, characterized in that, The display area side of the chip support disposed on the plurality of first output terminals and the plurality of second output terminals is positioned on the outer side relative to the chip mounting portion.

12. The display device according to claim 11, characterized in that, The portion of the chip support that is located on the outer side of the chip mounting portion is wider at the periphery of the chip mounting portion.

13. The display device according to claim 11 or 12, characterized in that, The portion of the chip support that is located on the outer side relative to the chip mounting portion is designed to gradually taper towards the front end.

14. The display device according to claim 11 or 12, characterized in that, The front end of the chip support relative to the outer part of the chip mounting part is alternately and staggered along the long side of the chip mounting part.

15. The display device according to any one of claims 10 to 12, characterized in that, On the chip mounting portion, a plurality of short-side terminals are arranged in a row along the short side of the chip mounting portion as terminals for the plurality of chips. The chip support is arranged in an island-like pattern among the multiple short-side terminals.

16. The display device according to any one of claims 10 to 12, characterized in that, On the chip mounting section, an integrated circuit chip is mounted via an anisotropic conductive film.

17. The display device according to claim 16, characterized in that, include: On the back side of the integrated circuit chip, a plurality of bumps are provided in a manner corresponding to the terminals of the plurality of chips. The anisotropic conductive film contains conductive particles. The plurality of bumps and the plurality of chip terminals are electrically connected via the conductive particles.

18. The display device according to any one of claims 10 to 12, characterized in that, It also includes a sealing film, which is disposed in such a way as to cover the light-emitting element layer, and is composed of a first inorganic sealing film, an organic sealing film and a second inorganic sealing film stacked in sequence.

19. The display device according to any one of claims 10 to 12, characterized in that, Each of the light-emitting elements is an organic electroluminescent element.

20. A display device, characterized in that, include: Flexible substrate layer; A thin-film transistor layer is disposed on the flexible substrate layer; and A light-emitting element layer is disposed on the thin-film transistor layer, and multiple light-emitting elements are arranged corresponding to the multiple sub-pixels constituting the display area. A border area is provided around the display area. The terminal portion is provided at the end of the frame area in a manner that extends in one direction. A chip mounting portion is provided between the display area and the terminal portion. This chip mounting portion is a rectangle whose longer side extends along the extension direction of the terminal portion when viewed from above. The chip mounting section has a plurality of chip terminals arranged in a row, and a plurality of terminal wirings extending parallel to each other and electrically connected to the plurality of chip terminals. In the chip mounting section, a chip support is provided between the plurality of chip terminals. The thin-film transistor layer includes a gate insulating film, a first wiring layer, an interlayer insulating film, a second wiring layer, and a planarization film sequentially stacked on the flexible substrate layer. The chip terminals are disposed on the terminal wiring formed on the same layer as the first wiring layer, and on the same layer as the second wiring layer. The chip support includes: An inorganic insulating layer, formed on the same layer of the same material as the interlayer insulating film; and An organic insulating layer, disposed on the inorganic insulating layer, is formed on the same layer of the same material as the planarization film. The central portion of the organic insulating layer in the width direction is formed to be thicker than the two ends in the width direction.

21. The display device according to claim 20, characterized in that, The planarization film includes a first planarization film disposed on one side of the flexible substrate layer and a second planarization film disposed on the opposite side of the flexible substrate layer. The organic insulating layer includes: A first organic insulating layer is formed in the same layer of the same material as the first planarization film; and A second organic insulating layer is disposed on the first organic insulating layer and is formed in the same layer by the same material as the second planarization film. The second organic insulating layer is configured to be narrower than the first organic insulating layer.

22. The display device according to claim 20 or 21, characterized in that, The terminal wiring and the chip terminals extend to both ends in the width direction of the chip support.

23. The display device according to claim 20 or 21, characterized in that, On the chip mounting portion, a plurality of short-side terminals are arranged in a row along the short side of the chip mounting portion as terminals for the plurality of chips. The chip support is arranged in an island-like pattern among the multiple short-side terminals.

24. The display device according to claim 20 or 21, characterized in that, On the chip mounting section, an integrated circuit chip is mounted via an anisotropic conductive film.

25. The display device according to claim 24, characterized in that, include: On the back side of the integrated circuit chip, a plurality of bumps are provided in a manner corresponding to the terminals of the plurality of chips. The anisotropic conductive film contains conductive particles. The plurality of bumps and the plurality of chip terminals are electrically connected via the conductive particles.

26. The display device according to claim 20 or 21, characterized in that, It also includes a sealing film, which is disposed in such a way as to cover the light-emitting element layer, and is composed of a first inorganic sealing film, an organic sealing film and a second inorganic sealing film stacked in sequence.

27. The display device according to claim 20 or 21, characterized in that, Each of the light-emitting elements is an organic electroluminescent element.

28. A display device, characterized in that, include: Flexible substrate layer; A thin-film transistor layer is disposed on the flexible substrate layer; and A light-emitting element layer is disposed on the thin-film transistor layer, and multiple light-emitting elements are arranged corresponding to the multiple sub-pixels constituting the display area. A border area is provided around the display area. The terminal portion is provided at the end of the frame area in a manner that extends in one direction. A chip mounting portion is provided between the display area and the terminal portion. This chip mounting portion is a rectangle whose longer side extends along the extension direction of the terminal portion when viewed from above. The chip mounting section has a plurality of chip terminals arranged in a row, and a plurality of terminal wirings extending parallel to each other and electrically connected to the plurality of chip terminals. In the chip mounting section, a chip support is provided between the plurality of chip terminals. On the chip mounting section, a plurality of output terminals are arranged in a row along the long side of the display area as terminals for the plurality of chips. The plurality of output terminals include: Multiple first output terminals are arranged in a row on the display area side; Multiple second output terminals are arranged in a row on the side of the terminal section; and Multiple third output terminals are arranged in a row between the multiple first output terminals and the multiple second output terminals. The plurality of first output terminals, the plurality of third output terminals, and the plurality of second output terminals are repeatedly arranged along the long side of the chip mounting portion in the order of the first output terminal, the third output terminal, and the second output terminal. The chip support is disposed between the plurality of first output terminals and between the plurality of second output terminals. The chip support is not positioned between the multiple third output terminals.

29. The display device according to claim 28, characterized in that, On the chip mounting portion, a plurality of short-side terminals are arranged in a row along the short side of the chip mounting portion as terminals for the plurality of chips. The chip support is arranged in an island-like pattern among the multiple short-side terminals.

30. The display device according to claim 28 or 29, characterized in that, On the chip mounting section, an integrated circuit chip is mounted via an anisotropic conductive film.

31. The display device according to claim 30, characterized in that, include: On the back side of the integrated circuit chip, a plurality of bumps are provided in a manner corresponding to the terminals of the plurality of chips. The anisotropic conductive film contains conductive particles. The plurality of bumps and the plurality of chip terminals are electrically connected via the conductive particles.

32. The display device according to claim 28 or 29, characterized in that, It also includes a sealing film, which is disposed in such a way as to cover the light-emitting element layer, and is composed of a first inorganic sealing film, an organic sealing film and a second inorganic sealing film stacked in sequence.

33. The display device according to claim 28 or 29, characterized in that, Each of the light-emitting elements is an organic electroluminescent element.

Images