Decoding architecture for a memory block

Abstract

This application relates to a decoding architecture for memory blocks. Word line blocks of a memory array may each include a plurality of word line plates, and each of the plurality of word line plates may include a thin sheet of conductive material that includes a first portion extending in a first direction in a plane and a plurality of fingers extending in a second direction in the plane. A pillar block may include one or more pillars extending vertically between the word line plate fingers. Memory cells may each be coupled to a corresponding word line plate finger and a corresponding pillar. Word line decoding circuitry, pillar decoding circuitry, or both may be located below the memory array and in some cases may be shared between adjacent pillar blocks.

Description

[0001] Cross-reference

[0002] This patent application is a national stage application of International Patent Application No. PCT / US2022 / 071623, titled "DECODING ARCHITECTURE FOR MEMORY TILES", filed on April 8, 2022 by Fantini et al., which claims priority to U.S. Patent Application No. 17 / 231,668, titled "DECODING ARCHITECTURE FOR MEMORY TILES", filed on April 15, 2021 by Fantini et al., each of which is assigned to its assignee and the entire text of each of which is hereby expressly incorporated by reference.

[0003] The technical field relates to a decoding architecture for memory tiles. Background Art

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device into various states. For example, binary memory cells can be programmed into one of two supported states, which are typically represented by a logic 1 or a logic 0. In some instances, a single memory cell can support more than two states and can store any of the states. To access the stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write or program a state into the memory device.

[0005] There are various types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technologies, and the like. Memory cells can be volatile or non-volatile. Summary of the Invention

[0006] Describe a device. The device may include: a first word line block including a first word line board including a plurality of first word lines, each of the plurality of first word lines being coupled to one or more corresponding memory cells of a plurality of first memory cells; a first pillar block including a plurality of first pillars associated with the first word line block, each first pillar being coupled to one or more corresponding first memory cells of the plurality of first memory cells; a second word line block including a second word line board including a plurality of second word lines, each of the plurality of second word lines being coupled to one or more corresponding memory cells of a plurality of second memory cells; a second pillar block different from the first pillar block, the second pillar block including a plurality of second pillars each associated with the second word line block and each coupled to one or more corresponding second memory cells of the plurality of second memory cells; and a first decoding circuit system associated with the first pillar block and the second pillar block, the first decoding circuit system being operable to activate the plurality of first word lines included in the first word line board associated with the first pillar block and the plurality of second word lines included in the second word line board associated with the second pillar block.

[0007] Describe a device. The device may include: a first word line block including a first word line board including a plurality of first word lines, each of the plurality of first word lines being coupled to one or more respective memory cells of a plurality of first memory cells; a first pillar block including a plurality of first pillars associated with the first word line block and each being coupled to one or more respective first memory cells of the plurality of first memory cells; a second word line block including a second word line board including a plurality of second word lines, each of the plurality of second word lines being coupled to one or more respective memory cells of a plurality of second memory cells; a second pillar block including a plurality of second pillars associated with the second word line block and each being coupled to one or more respective second memory cells of the plurality of second memory cells; a first decoding circuitry associated with the first word line block and the second word line block; a second decoding circuitry associated with the first pillar block; a third decoding circuitry associated with the second pillar block; and a controller operable to cause the device to: apply a first voltage to the first word line board using the first decoding circuitry; apply a second voltage to the second word line board using the first decoding circuitry; apply a third voltage to a first pillar of the plurality of first pillars included in the first pillar block, the first pillar being coupled to a first memory cell of the plurality of first memory cells, wherein the first memory cell is operable to be accessed at least in part based on applying the first voltage to the first word line board and applying the third voltage to the first pillar; and apply a fourth voltage to a second pillar of the plurality of second pillars included in the second pillar block, the second pillar being coupled to a second memory cell of the plurality of second memory cells, wherein the second memory cell is operable to be accessed at least in part based on applying the second voltage to the second word line board and applying the fourth voltage to the second pillar.

[0008] Describe a device. The device may include: a first word line block including a plurality of first word line plates stacked in a vertical direction, each of the plurality of first word line plates including a respective plurality of first word lines each coupled to one or more corresponding memory cells among a plurality of first memory cells; a second word line block including a plurality of second word line plates stacked in the vertical direction, each of the plurality of second word line plates including a respective plurality of second word lines each coupled to one or more corresponding memory cells among a plurality of second memory cells, wherein each second word line plate is positioned in the same plane as a corresponding first word line plate; a first pillar block including a plurality of first pillars associated with the first word line block and the second word line block, each first pillar coupled to a respective subset of first memory cells within the plurality of first memory cells or a respective subset of second memory cells within the plurality of second memory cells; a third word line block including a plurality of third word line plates stacked in the vertical direction, each of the plurality of third word line plates including a respective plurality of third word lines each coupled to one or more corresponding memory cells among a plurality of third memory cells, wherein each third word line plate is positioned in the same plane as a corresponding first word line plate; a second pillar block including a plurality of second pillars associated with the third word line block, each second pillar coupled to a respective subset of third memory cells within the plurality of third memory cells; and a first decoding circuit system associated with the first pillar block and the second pillar block, the first decoding circuit system positioned below the plurality of first memory cells, the plurality of second memory cells, and the plurality of third memory cells, wherein the first decoding circuit system is operable to activate a first word line plate among the plurality of first word line plates, a second word line plate among the plurality of second word line plates, and a third word line plate among the plurality of third word line plates, and wherein the first decoding circuit system is aligned with a respective edge of the first pillar block and a respective edge of the second pillar block. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Illustrate an example of a system supporting a decoding architecture for a memory block according to an example as disclosed herein.

[0010] Figure 2 Illustrate an example of a memory die supporting a decoding architecture for a memory block according to an example as disclosed herein.

[0011] Figure 3 Illustrate aspects of an example of a memory array supporting a decoding architecture for a memory block according to an example as disclosed herein.

[0012] Figure 4A AND 4BAspects of examples of a memory array supporting a decode architecture for memory slices according to examples as disclosed herein are described.

[0013] Figure 5A , 5B 5C illustrate aspects of an example of a memory array supporting a decode architecture for memory slices according to examples as disclosed herein.

[0014] Figure 6 An example of an array architecture supporting a decode architecture for memory slices according to examples as disclosed herein is illustrated.

[0015] Figure 7A An example of a memory cell architecture supporting a decode architecture for memory slices according to examples as disclosed herein is illustrated.

[0016] Figure 7B An example of a pillar selector supporting a decode architecture for a memory slice according to examples as disclosed herein is described.

[0017] Figure 7C An example of a pillar tile supporting a decode architecture for a memory tile according to examples as disclosed herein is illustrated.

[0018] Figure 8A and 8B An example of a pillar tile architecture supporting a decode architecture for memory tiles according to examples as disclosed herein is illustrated.

[0019] Figure 9A and 9B An example of a word line driver supporting a decoding architecture for a memory slice according to examples as disclosed herein is illustrated.

[0020] Figure 10 A block diagram of a memory device supporting a decoding architecture for memory slices according to examples as disclosed herein is shown.

[0021] Figure 11

[0013] Flowcharts are shown illustrating one or several methods of supporting a decode architecture for memory slices according to examples as disclosed herein. DETAILED DESCRIPTION

[0022] The word line plates of the memory array may each include a plurality of word lines in a "comb" structure (e.g., a structure of a tool that may appear to have a ridge, fingers extending from the ridge, and spaces between each pair of adjacent fingers). The word line plate may include, for example, a thin sheet of conductive material that includes a first portion extending in a first direction in a plane and a plurality of fingers extending in a second direction in the plane. Each finger of the word line plate may represent a word line as described herein, although the word lines (e.g., fingers) of the same word line plate may be electrically coupled to each other through the ridge of the comb and may thus be activated or deactivated together. The word line plate may be activated to access the corresponding memory cells of the memory array (e.g., the memory cells coupled to the fingers of the word line plate).

[0023] The word line plate and the corresponding memory cells may be vertically stacked above or below one or more other word line plates and corresponding memory cells to form a hierarchy of the memory array. The word line plate stack may be coupled to an electrode structure (e.g., a staircase as described elsewhere herein), and a word line decoder may be operable to apply a voltage to any selected word line plate of the word line plate stack via the electrode structure to support accessing one or more memory cells coupled to the selected word line plate. The word line decoder for the word line plate stack may include one or more word line drivers, each of the one or more word line drivers being configured to selectively activate or deactivate the corresponding word line plate in the stack (e.g., the word line plate coupled to the word line driver). The word line decoding circuitry may be located below the memory cells and word line plates of the memory array. As used herein, a first group of one or more components being described as "below" (or alternatively "under") a second group of one or more components may refer to the first group of one or more components being located between the second group of one or more components and a substrate (e.g., the first group of one or more components and the second group of one or more components are formed on the substrate) and within the coverage area of the second group of one or more components. The circuitry below the memory array may be referred to as the circuit under array (CuA) or alternatively as being within the CuA region.

[0024] In some cases, two or more word line plates in the same plane (e.g., word line plates in different vertical stacks but at the same level or tier) can share electrodes and corresponding drivers for activating the word line plates. For example, such sharing can beneficially reduce the footprint of the support circuitry for operating the memory array (e.g., can reduce the area of the decoder and drivers within CuA), among other possible benefits. Memory cells coupled to the word line plates sharing the electrodes and drivers can be (or alternatively include) pages for accessing the memory cells (e.g., logical pages for accessing the memory cells of the memory array). In some cases, groups of electrodes coupled to different word line plates at different tiers or planes of the stack can be referred to as ladders. A word line decoder can operate to activate any of the electrodes of the group of electrodes to concurrently activate two or more corresponding word line plates in the same plane but in different vertical stacks.

[0025] The memory cells can be accessed via a first voltage applied to a word line plate coupled to the memory cell and a second voltage applied to a pillar (e.g., an electrode extending vertically between word line plate fingers) also coupled to the memory cell. A pillar block can represent a portion of the pillars within the memory array that can be accessed using the same set of complementary pillar decoders, e.g., one X-direction pillar decoder for decoding pillar access lines extending in the Y direction and one Y-direction pillar decoder for decoding pillar access lines extending in the X direction. Pillar access lines extending in the X and Y directions can be referred to as pillar row lines and pillar column lines, respectively, and a pillar selector (e.g., for activating the pillars of the block) at the intersection of the pillar row line and the pillar column line can operate to activate based on activation of the pillar row and pillar column lines.

[0026] In some cases, a pillar block can be associated with multiple word line blocks (e.g., each word line block can include a certain number of word line plates, e.g., one or two word line plates). Associating a pillar block with multiple word line blocks (e.g., such that the pillar block is larger than the word line block and includes memory cells within multiple word line blocks) can reduce the footprint of the decoding circuitry for the memory array, e.g., by resulting in one set of complementary pillar decoders for all of the pillars of the pillar block (e.g., as opposed to one set of complementary pillar decoders for each word line block), one set of word line decoders for all of the word line plates of the pillar block (e.g., the tier of word line plates), or both.

[0027] As described herein, the pillar decoding circuitry and word line decoding circuitry for a memory array may be located under the memory array (e.g., in the CuA), where at least a portion of the pillar decoding circuitry, the word line decoding circuitry, or both for a pillar block is located under the pillar block. In some cases, the pillar decoding circuitry, the word line decoding circuitry, or both may be shared by multiple pillar blocks (e.g., a word line decoder may be coupled to word line plates within two adjacent pillar blocks, or a pillar decoder may be coupled to pillar access lines included within two adjacent pillar blocks or both), where the shared circuitry is located under the pillar blocks sharing it. Sharing the word line decoding circuitry across pillar blocks may also reduce the footprint of the decoding circuitry for the memory array, since the number of word line decoders per pillar block may be reduced (e.g., halved).

[0028] For these or other reasons, the decoding structures and configurations described herein may support a reduced area or footprint occupied by the decoding circuitry for accessing memory cells (e.g., as compared to some other memory array structures). The reduction in the area occupied by the decoding circuitry may, for example, reduce the total device footprint (e.g., by allowing all of the decoding circuitry for the memory array to be located under the memory array rather than at least partially occupying some peripheral area), thereby allowing more memory cells to be included in a device of a given footprint or both. Additionally, the memory arrays described herein may support parallel or concurrent (e.g., at least partially simultaneous) access operations to two or more memory cells within the same page of memory cells. For example, memory cells coupled to different word lines and associated with a left-facing word line plate (e.g., having fingers extending leftward), a right-hand word line plate (e.g., having fingers extending rightward), or both may be accessed in parallel, which may increase the access operation speed, data throughput, or both. These and other benefits described herein are merely exemplary, and additional benefits may be appreciated by those of ordinary skill in the art.

[0029] The features of the present disclosure are first described in the context of a memory system, die, and array as described in reference Figures 1 to 3 The features of the present disclosure are further described in the context of a memory array and array architecture as described in reference to FIGS. 4 through 9 and various components associated with or related thereto. These and other features of the present disclosure are further illustrated by and described with reference to device diagrams and flowcharts related to a decoding architecture for a memory block, as described in reference Figures 10 to 11 described.

[0030] Figure 1Describe an example of system 100 that supports a decoding architecture for memory blocks according to an example disclosed herein. System 100 may include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 to the memory device 110. System 100 may include one or more memory devices, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0031] System 100 may include portions of an electronic device, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other systems. For example, system 100 may illustrate aspects of a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, or the like. The memory device 110 may be an operative component of a system that stores data for one or more other components of system 100.

[0032] At least a portion of system 100 may be an example of host device 105. Host device 105 may be an example of a processor or other circuitry within a device (e.g., within a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, a system-on-chip (SoC), or some other fixed or portable electronic device, and other examples) that uses memory to perform processes. In some examples, host device 105 may refer to hardware, firmware, software, or a combination thereof that implements the functions of external memory controller 120. In some examples, external memory controller 120 may be referred to as the host or host device 105.

[0033] Memory device 110 may be an independent device or component that provides physical memory addresses / spaces that may be used or referenced by system 100. In some examples, memory device 110 may be configured to work with one or more different types of host devices 105. Signaling between host device 105 and memory device 110 may be operative to support one or more of the following: modulation schemes for modulating signals; various pin configurations for communicating signals; various form factors for the physical packages of host device 105 and memory device 110; clock signaling and synchronization between host device 105 and memory device 110; timing conventions; or other factors.

[0034] The memory device 110 is operable to store data for components of the host device 105. In some instances, the memory device 110 can act as a slave device of the host device 105 (e.g., in response to and executing commands provided by the host device 105 via the external memory controller 120). Such commands can include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

[0035] The host device 105 can include one or more of the external memory controller 120, the processor 125, the basic input / output system (BIOS) component 130, or other components (e.g., one or more peripheral components or one or more input / output controllers). The components of the host device 105 can be coupled to each other using the bus 135.

[0036] The processor 125 is operable to provide control or other functionality for at least part of the system 100 or at least part of the host device 105. The processor 125 can be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware component, or a combination of these components. In such instances, the processor 125 can be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or a system on a chip (SoC) and other examples. In some instances, the external memory controller 120 can be implemented by the processor 125 or be part of the processor 125.

[0037] The BIOS component 130 can be a software component that includes a BIOS that operates as firmware, which can initialize and run various hardware components of the system 100 or the host device 105. The BIOS component 130 can also manage the data flow between the processor 125 and the various components of the system 100 or the host device 105. The BIOS component 130 can include a program or software stored in one or more of read-only memory (ROM), flash memory, or other non-volatile memory.

[0038] The memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 (e.g., memory die 160-a, memory die 160-b, memory die 160-N) may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). The memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more banks, one or more blocks, one or more segments), where each memory cell may be operable to store at least one data bit. A memory device 110 that includes two or more memory dies may be referred to as a multi-die memory or a multi-die package or a multi-chip memory or a multi-chip package.

[0039] The memory die 160 may be an instance of a two-dimensional (2D) memory cell array or may be an instance of a three-dimensional (3D) memory cell array. A 2D memory die 160 may include a single memory array 170. A 3D memory die 160 may include two or more memory arrays 170 that may be stacked on top of each other or positioned adjacent to each other (e.g., relative to a substrate). In some instances, the memory arrays 170 in a 3D memory die 160 may be referred to as tiers, levels, layers, or dies. A 3D memory die 160 may include any number of stacked memory arrays 170 (e.g., two high, three high, four high, five high, six high, seven high, eight high). In some instances, multiple tiers, levels, or layers of memory cells (e.g., stacked vertically) may be considered a single 3D memory array 170 (e.g., as opposed to a stack of multiple memory arrays 170).

[0040] The device memory controller 155 may include circuitry, logic, or components operable to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations and may be operable to receive, transmit, or execute commands, data, or control information related to the components of the memory device 110. The device memory controller 155 may be operable to communicate with one or more of an external memory controller 120, one or more memory dies 160, or a processor 125. In some instances, the device memory controller 155 may control the operation of the memory device 110 as described herein in connection with the local memory controller 165 of the memory die 160.

[0041] The local memory controller 165 (e.g., local to the memory die 160) may include circuitry, logic, or components operable to control the operation of the memory die 160. In some instances, the local memory controller 165 may be operable to communicate with the device memory controller 155 (e.g., receive or transmit data or commands or both). In some instances, the memory device 110 may not include the device memory controller 155 and the local memory controller 165, or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be operable to communicate with the device memory controller 155, communicate with other local memory controllers 165, or communicate directly with the external memory controller 120 or the processor 125 or a combination thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165 or both may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating the received signals, an encoder for encoding or modulating the signals to be transmitted, or various other circuitry or controllers operable to support the described operations of the device memory controller 155 or the local memory controller 165 or both.

[0042] The external memory controller 120 may be operable to effectuate the conveyance of one or more of information, data, or commands between components of the system 100 or the host device 105 (e.g., the processor 125) and the memory device 110. The external memory controller 120 may translate or transpose the communications exchanged between the components of the host device 105 and the memory device 110. In some instances, the external memory controller 120 described herein or other components of the system 100 or the host device 105, or their functionality, may be implemented by the processor 125. For example, the external memory controller 120 may be hardware, firmware, software, or some combination thereof implemented by the processor 125 or other components of the system 100 or the host device 105. Although the external memory controller 120 is depicted as being external to the memory device 110, in some instances, the external memory controller 120 described herein or its functionality may be implemented by one or more components of the memory device 110 (e.g., the device memory controller 155, the local memory controller 165), or vice versa.

[0043] Components of the host device 105 may exchange information with the memory device 110 using one or more channels 115. The channels 115 may be operable to support communication between the external memory controller 120 and the memory device 110. Each channel 115 may be an instance of a transmission medium that carries information between the host device 105 and the memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of the system 100. The signal path may be an instance of a conductive path operable to carry a signal. For example, the channel 115 may include a first terminal that includes one or more pins or pads at the host device 105 and one or more pins or pads at the memory device 110. A pin may be an instance of a conductive input or output point of a device of the system 100, and the pin may be operable to act as part of the channel.

[0044] The channels 115 (and associated signal paths and terminals) may be dedicated to conveying one or more types of information. For example, the channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or a combination thereof. In some instances, signaling may be conveyed via the channels 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal may be registered for each clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal may be registered for each clock cycle (e.g., on both the rising edge and the falling edge of the clock signal).

[0045] The memory arrays described herein may include any number of word line tiles, where each word line tile includes one or more word line boards vertically stacked (e.g., one or more combs vertically stacked). The word line boards within the vertical stack can be independently activated or deactivated by an associated word line decoding circuitry. The pillars can extend vertically between the fingers of the word line boards (which can extend horizontally), and each memory cell of the memory array can be coupled to a corresponding word line (e.g., a corresponding finger of a corresponding word line board) and a corresponding pillar. Each pillar can be independently activated or deactivated using one or more pillar access lines (e.g., one or more pillar-based access lines for the pillar are coupled to a corresponding pillar selector for the pillar). A pillar tile can include a set of pillars that can be decoded (e.g., independently activated or deactivated) using the same set of pillar decoding circuitry, which can be or include a pair of complementary pillar decoders for the pillar tile (e.g., an X-direction pillar decoder and a Y-direction pillar decoder for the pillar tile, where each pillar is activated or deactivated via a corresponding Y-direction pillar access line and a corresponding X-direction pillar access line). In some cases, a pillar tile can include multiple word line tiles (e.g., for the pillars within the pillar tile, the memory cells coupled to the pillars can also be coupled to word lines included in the multiple word line tiles).

[0046] The word line and pillar decoding circuitry for the word line tiles and pillar tiles within the memory array can be located beneath the memory array (e.g., within the footprint of the memory array, above the substrate on which the memory array is formed, or both). For example, the pillar decoding circuitry for a pillar tile can be located beneath the pillar tile (e.g., within the footprint of the pillar tile). Additionally or alternatively, the pillar decoding circuitry, the word line decoding circuitry, or both can be shared across pillar tiles and located beneath those pillar tiles. In some cases, additional circuitry can also be located beneath the pillar tiles described herein, such as, for example, sense amplifiers. The decoding structures and configurations described herein can beneficially support a reduced area occupied by the decoding circuitry or other circuitry associated with operating the memory cells of the memory array (e.g., compared to other memory array configurations), and in some cases can allow all of the support circuitry for the memory array to be located beneath the memory array (e.g., as a CuA).

[0047] Figure 2 An example of a memory die 200 that supports a decoding architecture for a memory tile according to an example disclosed herein is illustrated. The memory die 200 can be as described with reference to Figure 1An example of the described memory die 160. In some examples, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory die 200 may include one or more memory cells 205, which may each be programmed to store different logic states (e.g., a programmed state of a set of two or more possible states). For example, the memory cells 205 may operate to store one information bit at a time (e.g., a logic 0 or a logic 1). In some examples, the memory cells 205 (e.g., multi-level memory cells 205) may operate to store more than one information bit at a time (e.g., logic 00, logic 01, logic 10, logic 11). In some examples, the memory cells 205 may be arranged in an array, such as the memory array 170 described with reference to Figure 1 The described memory array 170.

[0048] Figure 2 Various features related to the electrical operation of the memory array may be illustrated, but the physical location and configuration of the components may be different from the Figure 2 depiction in Figure 2 For example, the features illustrated by Figure 2 may indicate that the memory cells 205 are located at the intersection of corresponding access lines (e.g., row lines 210 and column lines 215), may represent the electrical functions of the memory cells and other array components, or both, but the memory array may have a different physical architecture or structure in some cases relative to the physical architecture or structure illustrated by Figure 3 described below with reference to

[0049] Figure 3 In some cases, the memory cells 205 may use configurable materials (which may be referred to as memory elements, memory storage elements, material elements, material memory elements, material portions, or polar write material portions, etc.) to store logic states. The configurable materials of the memory cells 205 may refer to chalcogenide-based storage components, as described in more detail with reference to

[0050] For example, chalcogenide storage elements may be used in phase change memory (PCM) cells, threshold memory cells, or self-selecting memory cells. The memory die 200 may include access lines (e.g., row lines 210 and column lines 215). The access lines may be formed of one or more conductive materials. In some examples, the row lines 210 may be referred to as word lines. In some examples, the column lines 215 may be referred to as digit lines or bit lines. In some cases, there may be additional types of access lines, as described elsewhere herein. References to access lines, row lines, column lines, word lines, digit lines, or bit lines or the like may be interchangeable without loss of understanding or operation. The memory cells 205 may be located, for example, at the intersection of the row lines 210 (e.g., fingers of a word line plate) and the column lines 215 (e.g., pillars or other vertical electrode structures).

[0051] In some cases, one or more column lines 215 (e.g., column line CL_j) may extend perpendicular to the substrate and one or more row lines 210 (e.g., row line RL_i) may be on a different level than illustrated (e.g., each row line 210 may be a word line finger of a word line board stacked in the vertical direction). In such cases, memory cells 205 may be formed at the intersection of column line CL_j and row line RL_i (e.g., between a pillar and a word line finger of a stacked word line board). One or more other memory cells 205 may be coupled between one or more other row lines 210 ( Figure 2 not shown in) and column line CL_j of one or more other stacked word line boards ( Figure 2 not shown in) and between one or more other row lines 210 ( Figure 2 not shown in) and one or more other column lines 215 (e.g., pillars, not depicted).

[0052] Operations such as reading and writing may be performed on memory cells 205 by activating or selecting access lines (e.g., one or more of row lines 210 or column lines 215). By biasing row line 210 and column line 215 (e.g., applying a voltage to row line 210 or column line 215), a single memory cell 205 may be accessed at their intersection. The intersections of row lines 210 and column lines 215 in a two - dimensional or three - dimensional configuration may be referred to as the addresses of memory cells 205. The access lines may be conductive lines coupled to memory cells 205 and may be used to perform access operations on memory cells 205.

[0053] Access to memory cells 205 may be controlled by row decoder 220 or column decoder 225. For example, row decoder 220 may receive a row address from local memory controller 245 and activate row line 210 based on the received row address. Column decoder 225 may receive a column address from local memory controller 245 and may activate column line 215 based on the received column address. In some cases, the functions attributed herein to column decoder 225 may be performed by one or more pillar decoders (e.g., complementary X - direction and Y - direction pillar decoders) configured to decode among the pillars of a pillar block.

[0054] The sensing component 230 is operable to detect the state of the memory cell 205 (e.g., material state, resistance, threshold state) and determine the logical state of the memory cell 205 based on the stored state. The sensing component 230 may include one or more sense amplifiers for amplifying or otherwise converting a signal resulting from accessing the memory cell 205. The sensing component 230 may compare the signal detected from the memory cell 205 with a reference 235 (e.g., a reference voltage). The detected logical state of the memory cell 205 may be provided as an output of the sensing component 230 (e.g., to the input / output 240), and may indicate the detected logical state to another component of the memory device including the memory die 200.

[0055] The local memory controller 245 may control access to the memory cells 205 through various components (e.g., the row decoder 220, the column decoder 225, the sensing component 230). The local memory controller 245 may be an instance of the local memory controller 165 as described in reference Figure 1 In some instances, one or more of the row decoder 220, the column decoder 225, and the sensing component 230 may be collocated with the local memory controller 245. The local memory controller 245 is operable to receive one or more of commands or data from one or more different memory controllers (e.g., the external memory controller 120 associated with the host device 105, another controller associated with the memory die 200), translate the command or data (or both) into information usable by the memory die 200, perform one or more operations on the memory die 200, and communicate data from the memory die 200 to the host device 105 based on performing the one or more operations. The local memory controller 245 may generate row signals and column address (e.g., stud address) signals to activate the target row line 210 and the target column line 215. The local memory controller 245 may also generate and control various voltages or currents used during operation of the memory die 200. Generally, the amplitude, shape, or duration of the applied voltage or current discussed herein may vary and may be different for the various operations discussed in operating the memory die 200.

[0056] The local memory controller 245 is operable to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activation operations, etc. In some instances, the access operations may be performed or otherwise coordinated by the local memory controller 245 in response to various access commands (e.g., from the host device 105). The local memory controller 245 is operable to perform other access operations not listed herein or other operations related to the operation of the memory die 200 but not directly related to accessing the memory cells 205.

[0057] The local memory controller 245 is operable to perform a write operation (e.g., a programming operation) on one or more memory cells 205 of the memory die 200. During the write operation, the memory cells 205 of the memory die 200 may be programmed to store a desired logical state. The local memory controller 245 may identify the target memory cells 205 on which the write operation is performed. The local memory controller 245 may identify the target row line 210 and the target column line 215 coupled to the target memory cells 205 (e.g., the address of the target memory cells 205). The local memory controller 245 may activate the target row line 210 and the target column line 215 (e.g., apply a voltage to the row line 210 or the column line 215) to access the target memory cells 205. The local memory controller 245 may apply a specific signal (e.g., a write pulse) to the column line 215 during the write operation to store a specific state in the storage element of the memory cell 205. The pulse that is part of the write operation may include one or more voltage levels within a duration.

[0058] The local memory controller 245 is operable to perform a read operation (e.g., a sensing operation) on one or more memory cells 205 of the memory die 200. During the read operation, the logical state stored in the memory cells 205 of the memory die 200 may be determined. The local memory controller 245 may identify the target memory cells 205 on which the read operation is performed. The local memory controller 245 may identify the target row line 210 and the target column line 215 coupled to the target memory cells 205 (e.g., the address of the target memory cells 205). The local memory controller 245 may activate the target row line 210 and the target column line 215 (e.g., apply a voltage to the row line 210 or the column line 215) to access the target memory cells 205. The sensing component 230 may detect the signal received from the memory cell 205, where the signal is based on the pulse applied to the row line 210, the pulse applied to the column line, and / or the resistance or threshold characteristics of the memory cell 205. The sensing component 230 may amplify the signal. The local memory controller 245 may activate the sensing component 230 (e.g., latch the sensing component) and thereby compare the signal received from the memory cell 205 with the reference signal 235. Based on the comparison, the sensing component 230 may determine the logical state stored on the memory cell 205. The pulse that is part of the read operation may include one or more voltage levels within a duration.

[0059] The word line board or its fingers as described herein may be electrically corresponding to row lines 210 or column lines 215, but the word line board may be configured as a "comb" structure (e.g., a structure of a tool that may appear to have multiple fingers extending from a common ridge and spaces between each pair of adjacent fingers). The word line board may be coupled to a word line decoder (e.g., row decoder 220) via an electrode, and the electrode may be operable to apply a voltage to the word line board for accessing associated memory cells. The word line decoder may be operable to independently activate or deactivate individual word line boards within a vertical stack of word line boards. To reduce the footprint of the support circuitry (e.g., word line decoding circuitry) for the memory device, two word line boards in the same plane (e.g., in different vertical stacks but at the same tier within the stack) may share an electrode for activating the word line boards. The two word line boards sharing the electrode may be (or alternatively include) for accessing a page of memory cells 205 (e.g., a logical page for accessing memory cells).

[0060] Memory cell 205 may be accessed via a first voltage applied to a word line board coupled to memory cell 205 and a second voltage applied to a pillar (e.g., a vertical electrode structure electrically isolated from the word line board) coupled to memory cell 205. In some cases, column lines 215 or row lines 210 as described with reference to Figure 2 may correspond to pillars as described herein. A pillar block may be associated with multiple word line blocks (e.g., each word line block representing one or two word line boards or one or two of their vertical stacks), where the pillar block may represent a portion of the pillars within the memory array that may be accessed using a set of complementary decoders, such as a set of one X-direction pillar decoder and one Y-direction pillar decoder, where the X and Y directions may respectively correspond to access lines coupled to a pillar selector and which may be described in more detail elsewhere herein. In some instances, decoding circuitry including pillar decoders, word line decoders, or both may potentially be located under the memory array as a CuA together with other support circuitry (e.g., sensing component 230 or at least its sense amplifier) for operating the memory array. Additionally or alternatively, word line decoders, pillar decoders, or both may be shared across adjacent pillar blocks in some cases, which may reduce the footprint of the support circuitry (e.g., decoding circuitry) for the memory device.

[0061] Figure 3 An example portion of a memory array 300 illustrating a decoding architecture supporting memory blocks as disclosed herein. Memory array 300 may be a reference to Figure 1 and 2An example of the described memory array. The memory array 300 may include multiple tiers of memory cells 310 stacked in a vertical direction relative to a substrate 340 to create a memory cell stack 335, which may be an example of the memory cells and memory cell stacks described with reference to Figure 1 and 2 . Thus, in some examples, the memory array 300 may be referred to as a 3D memory array. The memory array 300 may include word line plates 315 and pillars 325, which may electrically serve as examples of word lines and bit lines (e.g., row lines 210 and column lines 215) described with reference to Figure 2 .

[0062] The word line plate 315 may include multiple word lines in a "comb-like" structure (e.g., a structure that may resemble a tool having multiple fingers extending from a common ridge and spaces between each pair of adjacent fingers). The word line plate 315 may include, for example, a thin sheet of conductive material that includes a first portion (e.g., the ridge) extending in a first direction in a plane and multiple fingers extending in a second direction in the plane. Each word line plate 315 or its fingers may represent a word line as described herein. The number of fingers (e.g., word lines) and the length of the fingers may define the size of the word line plate 315, where the size of the word line plate may be based on the capacitance of the word line plate 315 relative to one or more storage class memory (SCM) specifications. Various exemplary details of the comb-like structure, fingers, and other aspects of the word line plate 315 may be further illustrated or described elsewhere herein.

[0063] Each pillar 325 may be selectively coupled to a corresponding pillar row line 320 via a pillar selector 345 (e.g., a transistor or switching component). For example, a pillar column line 350 for the pillar 325 may be coupled to the pillar selector 345 for the pillar 325, and based on the voltage of the pillar column line 350 (e.g., the voltage difference between the voltage of the pillar column line 350 and the voltage of the pillar row line 320), the pillar selector 345 may be selectively activated or deactivated. When activated (e.g., turned on, closed, conducting), the pillar selector 345 for the pillar 325 may couple the pillar 325 to the pillar row line 320 for the pillar 325, and thus the voltage of the pillar 325 may become equal to or approximately equal to the voltage of the pillar row line 320. In some cases, the pillar selector 345 may be a transistor (e.g., a thin film transistor (TFT) or other type of transistor), and the gate of the transistor may be coupled to the pillar column line 350, the source of the transistor may be coupled to the pillar row line 320, and the drain of the transistor may be coupled to the pillar 325. Thus, in some cases, the pillar column line 350 may alternatively be referred to as a pillar gate line, and the pillar row line 320 may alternatively be referred to as a pillar source line.

[0064] A pillar decoder as described herein is operable to selectively activate (e.g., apply a select voltage to) or deactivate (e.g., apply a deselect voltage to) a pillar column line 350 in a set of pillar column lines 350 associated with the pillar decoder, or selectively activate (e.g., apply a select voltage to) or deactivate (e.g., apply a deselect voltage to) a pillar row line 320 in a set of pillar row lines 320 associated with the pillar decoder. Although Figure 3 An example is described in which the pillar selectors 345, pillar row lines 320, and pillar column lines 350 are above the pillars 325, but it should be understood that the pillar selectors 345, pillar row lines 320, and pillar column lines 350 may alternatively be positioned below the pillars 325 (e.g., where the respective pillar selectors 345 are coupled to the bottom of each pillar 325).

[0065] Pillar column lines 350 and pillar row lines 320 may span and thus couple to pillar selectors 345 corresponding to rows or columns of pillars 325 coupled to memory cells, which in turn are coupled to a single word line plate, word line plates within a single word line block, or word line plates within multiple word line blocks, as described herein. One of ordinary skill in the art will appreciate that what direction (e.g., X or Y direction) is considered to be rows and columns may be arbitrary. In some cases, pillars 325 may correspond (e.g., in terms of one or more functionalities) to pillars 325 as described in reference to FIG. Figure 2 Similarly, the pillar decoder, pillar column line 350, pillar row line 320, and pillar selector 345 may correspond (e.g., in terms of one or more functionalities) to the pillar decoder described in reference to FIG. Figure 2 Column decoder 225 is described.

[0066] In some cases, pillars 325 coupled to the same pillar column line 350 may be viewed as a comb structure having vertical comb fingers (e.g., pillars 325) that may be selected via corresponding pillar row lines 320 (e.g., individually relative to other pillars 325 coupled to the same pillar column line 350), and each memory cell 310 may be positioned at the intersection of horizontal fingers of a word line plate 315 (e.g., a word line) and vertical fingers (e.g., pillars 325, which may be viewed as digital lines or portions of digital lines), but the teachings herein are not limited to such conceptualizations.

[0067] The memory array 300 may also include an insulating layer 305, a trench insulating layer 306, a via 330, and a substrate 340. Figure 3 The example illustrates pillar row lines 320 and pillar column lines 350 as being above pillars 325, but in some implementations, pillar row lines 320 and pillar column lines 350 may alternatively be below pillars 325 (e.g., between pillars 325 and substrate 340).

[0068] The insulating layer 305 can be electrically insulating and can provide insulation between the alternating word line plates 315. As described herein, various logic states can be stored by programming the resistance of the memory cells 310. In some cases, programming the resistance includes passing a current through the memory cell 310, heating the memory cell 310, melting the material (e.g., all or part) of the memory cell 310, applying a voltage of a specific polarity to the memory cell, or any combination thereof. The insulating layer 305 can be composed of multiple sub-layers to create one or more interfaces between the memory cells 310.

[0069] The memory array 300 can include an array of memory cell stacks 335, and each memory cell stack 335 can include multiple memory cells 310. The memory array 300 can be made by forming a stack of conductive layers (e.g., word line plates 315), where each conductive layer can be separated from an adjacent conductive layer by one or more electrically insulating layers 305. The electrically insulating layer can include an oxide or nitride material, such as silicon oxide, silicon nitride, or other electrically insulating materials. In some cases, the insulating layer 305 can include one or more sub-layers. The layers of the memory array 300 can be formed on a substrate 340, such as a silicon wafer, or any other semiconductor or oxide substrate (e.g., above). The vias 330 (e.g., openings) can be formed by removing material from the layer stack by means of etching or mechanical techniques or both. In some cases, CuA as described herein can refer to circuitry formed between the substrate 340 and the memory array (e.g., within the footprint of the memory array, which can correspond to or include the footprint of the memory cells 310, word line plates 315, pillars 325, possibly along with associated interconnect structures, as opposed to peripheral circuitry that can be formed next to or otherwise external to the footprint of the memory array). For example, CuA can be formed above the substrate 340, and then the memory array can be formed above CuA.

[0070] In some cases, a memory cell 310 (e.g., a memory element) can be formed by removing material from a conductive layer to create a recess adjacent to a via 330 and forming a variable resistance material in the recess. For example, material can be removed from the conductive layer by etching, and the variable resistance material can be deposited in the resulting recess to form the memory cell 310 (e.g., a memory element, which can be a storage element). Each via 330 can be filled with an electrically conductive material and a dielectric material to create a pillar 325, which can be coupled (e.g., selectively, such as using a pillar selector 345) to a pillar row line 320. In other words, the memory cells 310 in a memory cell stack 335 can share a common electrode (e.g., the pillar 325). Thus, each memory cell 310 can be coupled to a word line plate 315 and a pillar 325. In some cases, each pillar 325 (e.g., within each via 330) can be coupled to a first word line finger via a corresponding first memory cell and to a second word line finger via a corresponding second memory cell, as described in further detail with reference to FIG. 4. The trench insulating layer 306 can be electrically insulating and can provide insulation between alternating (e.g., interdigitated) word line fingers of each word line plate 315 (e.g., word line fingers on each side of a via 330 in the direction of a pillar column line 350, where the word line fingers on opposite sides of the trench insulating layer 306 can extend away from the ridge of their respective word line plates in parallel but opposite directions, e.g., where a first word line finger adjacent to a side of the trench insulating layer 306 extends to the right and a second word line finger adjacent to the opposite side of the trench insulating layer 306 extends to the left).

[0071] In some instances, the material of the memory cell 310 (e.g., a memory element) can include a chalcogenide material or other alloy, including selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (In) or various combinations thereof. In some instances, a chalcogenide material primarily having selenium (Se), arsenic (As), and germanium (Ge) can be referred to as a SAG alloy. In some instances, the SAG alloy can also include silicon (Si) and this chalcogenide material can be referred to as a SiSAG alloy. In some instances, the SAG alloy can include silicon (Si) or indium (In) or a combination thereof, and such chalcogenide materials can be referred to as a SiSAG alloy or an InSAG alloy or a combination thereof, respectively. In some instances, the chalcogenide glass can include additional elements in atomic or molecular form, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F). Other chalcogenide alloys not specifically enumerated herein can also be employed.

[0072] In some instances, such as for thresholded memory cells or self-selective memory cells 310, some or all of the set of logic states supported by the memory cell 310 may be associated with the same state, e.g., the amorphous state of a chalcogenide material as opposed to the crystalline state of the chalcogenide material (e.g., the material may be operable to store different or multiple logic states while remaining in the amorphous state). In some such instances, the memory cell 310 may be an instance of a self-selective memory cell 310. In such instances, the material used in the memory cell 310 may be based on an alloy (such as the alloys listed above) and may be operable to undergo a state change during normal operation of the memory cell (e.g., due to ion migration or segregation within the memory cell 310). For example, the self-selective memory cell 310 may have a high threshold voltage state and a low threshold voltage state. The high threshold voltage state may correspond to a first logic state (e.g., a reset state) and the low threshold voltage state may correspond to a second logic state (e.g., a set state). In some instances, the memory cell 310 may alternately switch between amorphous and crystalline states during operation, where the amorphous and crystalline states correspond to different resistances or threshold voltages and thus different logic states, and in some cases this operation may be referred to as a phase change operation.

[0073] In some cases, during a programming (write) operation of the self-selective memory cell 310, the polarity of one or more pulses used for the write operation may affect (determine, set, program) a particular behavior or property of the material of the memory cell 310, e.g., the threshold voltage of the material. The difference in the threshold voltage of the material of the memory cell 310 depending on the logic state stored by the material of the memory cell 310 (e.g., the difference between the threshold voltage when the material stores the logic state '0' and the threshold voltage when it stores the logic state '1') may correspond to the read window of the memory cell 310.

[0074] Various techniques may be used to form materials or components on the substrate 340. These may include, for example, chemical vapor deposition (CVD), metalorganic vapor deposition (MOCVD), physical vapor deposition (PVD), sputter deposition, atomic layer deposition (ALD), or molecular beam epitaxy (MBE), as well as other thin film growth techniques. Various techniques may be used to remove materials, which may include, for example, chemical etching (also referred to as "wet etching"), plasma etching (also referred to as "dry etching"), or chemical mechanical planarization.

[0075] As described herein, regions separating memory cells 310, such as insulating layer 305, trench insulating layer 306, or both, may include one or more interfaces. In some instances, the interfaces of insulating layer 305 separate memory cells 310 stacked in a vertical direction. In other words, memory cells 310 may be stacked on top of each other and separated from each other by the interfaces. In some instances, the interfaces of trench insulating layer 306 separate word line fingers from each other in a horizontal direction.

[0076] The memory cells 310 described herein may include, but are not limited to, phase change materials. Other types of memory cells 310 may include, for example, resistive memory or resistive RAM. In some cases, resistive RAM may use a metal oxide material and change the resistance of the metal oxide material by controlling the ionic state of atoms in the material or by controlling the number or position of atomic vacancies (e.g., missing atoms) in the material.

[0077] Figure 4A and 4B Illustrate examples of memory arrays 400-a and 400-b that support a decoding architecture for a memory block according to examples as disclosed herein. For example, Figure 4A and 4B Illustrate various views (e.g., top views) of cross-sections of example 3D memory arrays 400-a and 400-b, which may be examples of 3D memory arrays according to examples as disclosed herein. A plurality of openings 460 may be formed through alternating planes of conductive material 445 (e.g., word line plane or word line plate), dielectric material 418, and a second dielectric material in trenches 450, for example. As shown, the diameter of the plurality of openings 460 may be approximately the same width as the trenches 450. In some instances, the diameter of the plurality of openings 460 may be greater than the width of the trenches 450.

[0078] Each of the plurality of openings 460 may be substantially concentric with a different corresponding conductive contact. As Figure 4A and 4B shown, pillars 480 (e.g., circular pillars 480) may be formed in a geometric pattern in each corresponding opening 460, for example, above and coupled to a corresponding conductive contact (e.g., which may be a pillar selector 345 or coupled to the pillar selector). In some instances, the openings 460 (e.g., and corresponding pillars 480) may be square or another shape. In some cases, the plurality of openings 460 may have a staggered (e.g., hexagonal) arrangement of conductive contacts associated with the pillars 480. For example, a corresponding conductive contact may be surrounded by six other conductive contacts.

[0079] An interleaved pattern may refer to any pattern in which the positions of objects (e.g., contacts, openings 460, or pillars 480) in a first row are offset in a given direction from the positions of objects (e.g., contacts, openings 460, or pillars 480) in a second row adjacent to the first row. For example, an interleaved pattern may have objects (e.g., contacts, openings 460, or pillars 480) that are adjacent to each other in the x-direction (e.g., row or horizontal direction) rather than in the y-direction (e.g., column or vertical direction). For example, as Figure 4A and 4B illustrate, conductive contacts may be adjacent to each other and in a straight line in the x-direction. However, the conductive contacts may not be adjacent to each other in the y-direction and may, for example, alternate (e.g., skip) rows in the y-direction. Although Figure 4A and 4B show substantially the same spacing between conductive contacts throughout the substrate, examples in accordance with the present disclosure are not limited thereto. For example, the spacing between conductive contacts may vary throughout the substrate.

[0080] Figure 4B illustrate that a 3D memory array may include a variety of memory element materials 465, each including a chalcogenide material or other memory element positioned between at least one word line board, at least one pillar 480, and at least one dielectric material 418. In some instances (e.g., depending on decoding optimization), each pillar 480 may be coupled to a corresponding pillar selector (e.g., switching element, e.g., transistor) positioned at the top, bottom, or both the top and bottom of the 3D memory array 400 (e.g., below or above a set of word line boards).

[0081] Figure 5A 、 5B and 5C illustrate examples of memory arrays 500-a, 500-b, and 500-c that support a decoding architecture for memory blocks in accordance with examples as disclosed herein. For example, Figure 5A 、 5B and 5C may illustrate various views of cross-sections of example 3D memory arrays 500-a, 500-b, and 500-c, which may be examples of 3D memory arrays in accordance with examples as disclosed herein, where Figure 5A and 5B are top views and Figure 5C is a side view. Memory arrays 500-a, 500-b, and 500-c may include similar to reference Figure 4A and 4BFeatures of the described memory array 400. Specific isolation trenches 450' that can be filled with an insulating or dielectric material can be formed between two sub-arrays (e.g., a first sub-array 500-a1 and a second sub-array 500-a2) such that the first sub-array 500-a1 and the second sub-array 500-a2 can be electrically isolated from each other. In some instances, the memory array 500-a can include a set of vertically stacked word line plates separated from each other by respective dielectric layers (refer to the side view of the memory array shown in Figure 5C ).

[0082] The word line plates can be formed of the conductive material 445 of the memory arrays 500-a, 500-b, and 500-c. In the first sub-array 500-a1, a first word line plate (e.g., of a first word line plate stack) can be isolated from a second word line plate (e.g., of a second word line plate stack) in the same plane using a dielectric material extending in a serpentine shape (e.g., the shape of the trench 450). In the second sub-array 500-a2, a third word line plate (e.g., of a third word line plate stack) can be similarly isolated from a fourth word line plate (e.g., of a fourth word line plate stack) in the same plane using a dielectric material extending in a serpentine shape (e.g., the shape of the trench 450). The first word line plate and the second word line plate can be isolated from the third word line plate and the fourth word line plate by the isolation trench 450'. In Figures 5A to 5C an isolation trench 450' is illustrated for illustrative purposes. The number of the isolation trench 450' and the sub-arrays 500-a1 and 500-a2 is not limited to the number illustrated in Figures 5A to 5C . For example, a plurality of isolation trenches 450' can be formed in the 3D memory array as needed (e.g., to isolate various sub-arrays of the 3D memory array).

[0083] By using the isolation trench 450' (which can also be referred to as an isolation layer) filled with an insulating or dielectric material, the power consumption of the 3D memory array can be reduced when meeting the SCM specification. For example, compared with a 3D memory array in which multiple sub-arrays are coupled to each other, a 3D memory array interposed with several isolation layers can experience a corresponding decrease in the capacitance value of the memory array (e.g., of an individual sub-array) and can further reduce power consumption without increasing the decoding burden.

[0084] As in Figure 5AAs shown, in some instances, after forming trenches 450 in a serpentine shape in the 3D memory array 500-a, a portion of the trenches 450 can be selected as isolation trenches 450', which can be used to divide the 3D memory array 500-a into a first sub-array 500-a1 and a second sub-array 500-a2. For example, the isolation trenches 450' can be subjected to another etching operation such that the two sub-arrays on both sides of a particular isolation trench 450' can be separated, which can cut off one or more word line board structures to create individual word line boards or sets of word line boards (e.g., stacks) on either side of the isolation trench 450'. In some instances, during subsequent processing steps, the isolation trenches 450' can be filled with an insulating material or a dielectric material, for example, without any other materials (e.g., memory element materials or conductive materials) formed therein. In some instances, portions from the serpentine trenches 450 can be used as isolation trenches 450' between different groups of word line board fingers (e.g., every X fingers, where X is a certain number).

[0085] In another instance, a group of sub-arrays can be formed above the same substrate and an isolation layer 450' can be deposited on one or both sides of each sub-array along the horizontal direction of the serpentine trenches 450 such that the group of sub-arrays can be electrically isolated from each other. In another instance, after forming the 3D memory array and based on one or more dimensions of the 3D memory array, a certain number of isolation trenches 450' can be formed to cut the 3D memory array into a group of sub-arrays, where an etching operation can be performed on the memory array to form the isolation trenches 450'.

[0086] The position of forming the isolation trenches 450' (or the isolation layer 450') can be adjusted according to the dimensions of the 3D memory array to achieve the desired size of the sub-arrays or both, as illustrated by Figure 5B and 5C For example, the position of the isolation trenches 450' can be adjusted relative to the first sub-array 500-b1 and the second sub-array 500-b2 illustrated in Figure 5B In some instances, the 3D memory array can be formed based on an example pitch of adjacent pillars.

[0087] In some instances, the insertion of the isolation layer 450' can assist in making the corresponding capacitance value low enough such that the word lines can be biased by a driver that consumes a desired low amount of energy (e.g., in some cases, the order of the energy used to drive the word lines can be calculated as (1 / 2CV 2 ))). Additionally, dividing the 3D memory array using pillars can support decoding CuA optimization, such as minimizing the number of pillar decoders, sense amplifiers, or the like, while conforming to SCM specifications (e.g., due to the word line cuts from the insertion of the isolation layer 450') based on a higher-level memory array segmentation.

[0088] In some instances, depending on the decoding implementation, each pillar 480 may be coupled to a corresponding pillar selector (e.g., a switching component or transistor) located at the top, bottom, or both the top and bottom of the 3D memory array (e.g., below or above the set of word line plates). Spatial relative terms, including but not limited to “top,” “bottom,” “lower,” “upper,” “below,” “beneath,” “above,” etc., if used herein, are used for convenience in describing the spatial relationship of one (or more) elements to another (or more) element. Such spatial relative terms encompass different orientations of the device in addition to the specific orientation depicted in the figures and described herein. For example, if the structure depicted in the figures is inverted or flipped, then the portions previously described as below or beneath other elements will be above or on those other elements.

[0089] Figure 6 An example of an array architecture 600 that supports a decoding architecture for memory blocks as disclosed herein is illustrated. The array architecture 600 may represent an array that includes a plurality of pillars 630, which may represent, for example, an example of the pillars described elsewhere herein with reference Figure 3 to 5. For example, each pillar 630 may extend through a stack of materials that includes alternating layers of dielectric or insulating material and word line plates. Each pillar 630 may also be coupled to one or more memory cells (e.g., two memory cells) at each word line plate layer. The view Figure 6 illustrated may represent a top or bottom view of the array such that the pillars 630 may extend into and out of the page. The pillars 630 may be arranged in rows and columns throughout the array architecture 600, e.g., including positions not illustrated for visual clarity Figure 6 (e.g., the pillar columns and rows may largely fill each word line block 605). Although the pillars 630 are shown arranged in a linear fashion, the pillars 630 may alternatively or additionally be arranged in another geometric pattern (e.g., staggered), as described with reference to FIGS. 4 and 5.

[0090] The array architecture 600 may include a plurality of word line blocks 605, which may each represent, for example, a set of word line plates that are separated from the word lines of other word line blocks 605 by steps 620 and 625 and by slots 655 (e.g., slots 655-a, 655-b, 655-c, and 655-d). Each word line block 605 may include one or more sets of two independently addressable word line plates that may face each other (e.g., as an interlocking comb structure, which may alternatively be referred to as a comb with finger-like fingers, but such details may be Figure 6 omitted herein and are omitted for clarity with respect to Figure 6(Other details described in [reference] are described in more detail elsewhere), and it can be separated by a dielectric or insulating material in a serpentine or other shape, as described with reference to FIGS. 4 and 5. Additionally or alternatively, the word line block 605 can represent a vertical stack of word line boards (e.g., memory cells coupled thereto) that can be independently (e.g., individually) activated or deactivated using a word line decoder. The word line boards within the word line block 605 can be located at alternating layers of the material stack, as described with reference to Figure 3 such that the word line boards of the array architecture 600 can be located above or below one or more other word line boards of the same word line block 605.

[0091] The size of the word line block 605 (e.g., length and width, based on the number and length of the fingers of the associated word line board) can be based on the capacitance of the word line block 605 or the word line boards therein relative to one or more SCM specifications (e.g., can be sized to conform to SCM specifications).

[0092] A word line decoding circuit system (e.g., one or more word line decoders) can be used to access or activate different word line boards (and thus different word lines) at different levels (e.g., tiers) of the stack and at different positions of the array architecture 600. For example, the word line decoder can activate one or more selected word line boards of a word line board stack (e.g., having multiple tiers) via the ladders 620 or 625 (e.g., electrodes or a series of electrodes having different heights), while deactivating or maintaining the deactivation of one or more other word line boards of the stack. Similarly, a pillar decoding circuit system (e.g., a pillar decoder) can be used to access or activate different pillars 630, and the pillar decoding circuit system can activate or access the pillar row lines (e.g., pillar source lines) and pillar column lines (e.g., pillar gate lines) associated with the selected pillars 630.

[0093] To reduce the footprint of a decoding circuit system, sense amplifier, or other support circuit system for operating a memory array having an array architecture 600 (e.g., to support implementation of such a circuit system as a CuA), two word line plates of different word line tiles 605 may share a ladder 620 or 625. The two word line plates of the electrodes within the shared ladder 620 or 625 may be (or alternatively include) pages 610 or 615 for accessing memory cells at the same tier of the array architecture 600 (e.g., a logical page for accessing memory cells). For example, a first page 610 (e.g., an even page) may include two first word line plates extending (e.g., left and right) away from a first ladder 620 and a second page 615 (e.g., an odd page) may include two second word line plates extending (e.g., left and right) away from a second ladder 625. Thus, for example, the word lines or fingers of the right-extending word line plate of the first page 610 may interlock with (but be separated therefrom by a serpentine trench) the word lines or fingers of the left-extending word line plate of the second page 615.

[0094] In some instances, referring to Figure 6 , the word line decoding circuit system included in the CuA under the pillar tile 635 may be operable to activate (e.g., individually) any word line plate in a set of vertically stacked word line plates (e.g., tiers) included in the word line tile 605 of the pillar tile 635. The word line decoder of the decoding circuit system may include one or more word line drivers or be coupled to one or more word line drivers, and each word line driver may be associated with (e.g., coupled to) a word line plate or a pair of word line plates (e.g., word line plates associated with an adjacent word line tile 605 and coupled to the shared ladder 620 or 625) in the same respective tier of the word line plate stack (e.g., the pair of word line plates may be in the same plane as each other). Thus, activating a word line driver may activate a selected word line plate of the word line plate stack (e.g., one or more word line plates coupled to the word line driver).

[0095] For example, a first word line driver (e.g., included in or coupled to) of a first word line decoder is operable to activate a first selected word line board within a first word line block 605 to the left of a first ladder 620 and (e.g., concurrently) activate a second selected word line board within a second word line block 605 to the right of the first ladder 620. The first selected word line board within the first word line block 605 to the left of the first ladder 620 and the second selected word line board within the second word line block 605 to the right of the first ladder 620 may both be coupled to the same electrode within the first ladder 620, and thus the first word line driver may concurrently activate the two word line boards within two adjacent word line blocks and thus corresponding pages 610 by applying a select voltage to the shared electrode within the first ladder 620 for the two word line boards. A second word line driver of the first word line decoder may similarly be operable to activate a third selected word line board within the first word line block 605 and a fifth selected word line board within the second word line block 605, where the third selected word line and the fifth selected word line may be located above or below the first word line board and the second word line board, respectively, within a word line board stack.

[0096] A second word line decoder may similarly be operable to activate a driver to activate or access a first selected word line board within a first word line block 605 to the left of a second ladder 625 and (e.g., concurrently) activate a second selected word line board within a second word line block 605 to the right of the second ladder 625, e.g., by applying a select voltage to an electrode within the second ladder 625 coupled to the two selected word line boards and thereby selecting a corresponding page 615 of memory cells.

[0097] In some instances, e.g., based on being able to concurrently access half of the memory cells associated with two different word line blocks 605 or their tiers (e.g., via respective first or second word line boards of those two word line blocks 605), a page 610 or 615 may include the same or substantially the same number of memory cells as included within a word line block 605 or its tier (e.g., plane, level). For example, sharing an electrode of a ladder 620 or 625 between two word line boards may reduce the total number of ladder electrodes and the total number of word line decoders associated with the array architecture 600 (e.g., may halve the total number) compared to an architecture where word line boards within adjacent word line blocks 605 do not share electrodes (e.g., where a ladder is dedicated to a single word line block 605 rather than a pair or other group of word line blocks 605).

[0098] Each first word line board may be selectively activated using a respective first word line driver of a first word line decoder (e.g., a first decoding circuitry), and each second word line board may be selectively activated using a respective second word line driver of a second word line decoder. In some examples, to activate a first word line board (or a pair of first word line boards), the first word line decoder may activate or apply a voltage to a corresponding electrode within the first ladder 620 (e.g., using the respective word line driver of the word line decoder). Similarly, to activate a second word line board (or a pair of second word line boards), the second word line decoder may selectively activate or apply a voltage to a corresponding electrode within the second ladder 625 (e.g., using the respective word line driver of the word line decoder).

[0099] Similarly, to reduce the footprint of the CuA and other peripheral or support circuitry for the array architecture, the pillar block 635 may be associated with a plurality of word line blocks 605 (e.g., any number of word line blocks 605, such as 15 or 16 word line blocks 605). In some cases, e.g., based on one or more connection capabilities and spacing constraints (e.g., to reduce the connection capabilities between the clustered array and the CuA), the pillar block 635 may include or be associated with a non-integer number of word line blocks 605 (e.g., based on the independence between the word line block 605 and the pillar block 635). The pillar block 635 may represent a portion of the pillar 630 of the array architecture 600 that may be accessed using a set of complementary decoders, such as an X-direction pillar decoder (e.g., a first pillar decoder for decoding pillar column lines) for decoding pillar lines extending in the Y direction and a Y-direction pillar decoder (e.g., a second pillar decoder for decoding pillar row lines) for decoding pillar lines extending in the X direction.

[0100] The pillar block 635 may define (e.g., independent of the boundaries of the word line block 605) the total area (e.g., the maximum area) of the pillar 630 and associated memory cells that may be decoded using the first pillar decoder (e.g., in the X direction) and the corresponding second pillar decoder (e.g., in the Y direction). The size of the pillar block 635 (e.g., length and width, based on the length of the pillar decoder and the associated number of pillars 630) may be based on the capacitance of the pillar block 635 relative to one or more SCM specifications (e.g., may be sized to conform to the SCM specifications).

[0101] A first pillar decoder and a second pillar decoder (e.g., a pillar decoding circuitry) for the pillar tiles 635 can be used to selectively access the pillars 630 within the pillar tiles 635. For example, the first pillar decoder can be used to access or activate pillar column lines and the second pillar decoder can be used to selectively access or activate pillar row lines. The pillar column lines can activate one or more switching components coupled to the pillar column lines, and the one or more switching components can couple the pillars 630 to the activated pillar row lines and thereby select or activate the pillars 630 associated with the activated pillar column lines and the activated pillar row lines (e.g., because the switching components, such as pillar selector 345, can be activated based on a difference between a voltage of a corresponding pillar column line and a voltage of a corresponding pillar row line, and in cases where the switching components are or include transistors, the corresponding pillar row lines can be coupled to a source or a drain of the switching components). A voltage can be applied to the pillars 630 via the pillar row lines (e.g., when activating an associated pillar selector).

[0102] In some cases, e.g., if a multi-TFT decoder is located under each pillar 630 (e.g., for coupling the pillar 630 and the pillar row line to activate the pillar 630, as the pillar selector 345), then the first pillar decoder and the second pillar decoder can represent regions for contacting other decoders that can operate at a more global level (e.g., device level). In cases where a single TFT is located under each pillar 630, the first pillar decoder and the second pillar decoder can represent the decoding level of the pillars of the pillar tile 635.

[0103] Associating the pillar tile 635 with a plurality of word line tiles 605 (e.g., such that the pillar tile 635 is larger than the word line tile 605 and includes the pillars 630 coupled to memory cells within the plurality of word line tiles 605) can reduce the footprint of the pillar decoder, e.g., by supporting one pillar decoder or a set of complementary pillar decoders for all the pillars 630 of the pillar tile 635 (e.g., as opposed to supporting one pillar decoder or a set of complementary pillar decoders for each word line tile 605).

[0104] In some cases, word line decoding circuitry (e.g., word line decoders and word line drivers) operable to access word line plates in the pillar block 635 may be located below a memory array having the array architecture 600 (e.g., may be included in the CuA of the memory array). For example, all or a portion of the word line decoding circuitry for the word line plates (and thus the word line block 605) included in the pillar block 635 may be located below the pillar block 635 (e.g., between the pillar block 635 and the substrate, within the coverage area of the pillar block 635). In some instances, at least a portion of the word line decoding circuitry for the pillar block 635 may be below the pillar block and aligned with an edge of the pillar block 635 (e.g., adjacent to or closely positioned to the edge) (e.g., aligned with an edge of the coverage area of the pillar block 635), and may be shared among one or more adjacent pillar blocks 635 (e.g., is also operable to access word line plates in one or more adjacent pillar blocks 635).

[0105] Similarly, pillar decoding circuitry (e.g., pillar decoders) operable to access the pillars 630 in the pillar block 635 may be located below a memory array having the array architecture 600 (e.g., may be included in the CuA of the memory array). For example, all or a portion of the pillar decoding circuitry for the pillars 630 included in the pillar block 635 may be located below the pillar block 635 (e.g., between the pillar block 635 and the substrate, within the coverage area of the pillar block 635). In some instances, at least a portion of the pillar decoding circuitry may be below the pillar block 635 and aligned with an edge of the pillar block 635 (e.g., adjacent to or closely positioned to the edge) (e.g., aligned with an edge of the coverage area of the pillar block 635), and may be shared among one or more adjacent pillar blocks 635 (e.g., is also operable to access the pillars 630 in one or more adjacent pillar blocks 635).

[0106] Memory cells may be accessed (e.g., for read or write operations) by activating corresponding pillars 630 and word line plates. For example, a first voltage may be applied to a pillar column line using a first pillar decoder for the pillar block 635 and a second voltage may be applied to a pillar row line using a second complementary pillar decoder for the pillar block 635, which may activate or access a corresponding pillar 630 (e.g., at the intersection of the pillar column line and the pillar row line). Similarly, a third voltage may be applied to the word line plate using the word line decoding circuitry for the pillar block 635 (e.g., may activate the word line plate) to access a memory cell coupled to the activated pillar 630. For example, the memory cell may be coupled to the word line plate and the pillar 630 and may be accessed based on the respective voltages applied to the word line plate and the pillar 630.

[0107] In some cases, the array architecture 600 may support parallel or simultaneous access operations to two or more memory cells within the same page 610 or 615 (e.g., two or more memory cells coupled to the same column of the struts 630), which can increase the access operation speed and / or data throughput. In some cases, as long as memory cells on opposite sides of the same word line finger are not accessed concurrently, two or more memory cells associated with the same column of the struts 630 can be accessed concurrently. For example, within the strut block 635, one strut column line can be activated by a first strut decoder, and every other strut row line (or some other subset of strut row lines where no two strut row lines are adjacent) can be activated concurrently by a second strut decoder, thereby concurrently activating every other strut 630 within the column of the struts 630 (or some other subset of struts 630 where no two activated struts within the column are adjacent). In some such cases, one word line board of each word line block 605 can be activated at a time by the corresponding word line decoder (e.g., for a given activated strut 630, one memory cell can be accessed based on the word line board coupled to the one memory cell among the multiple vertically stacked word line boards coupled to the memory cell coupled to the strut 630 that is concurrently activated). And in some cases, any number of word line boards within the even pages 610 or odd pages 615 can be activated concurrently by the corresponding word line decoder, thus supporting concurrent access to two or more memory cells associated with the same column of the struts 630 across any number of word line blocks 605.

[0108] Additionally or alternatively, in some cases, the array architecture 600 may support partially parallel access operations to two or more memory cells within the same page 610 or 615 (e.g., two or more memory cells coupled to the same row of the struts 630), which can increase the access operation speed and / or data throughput. For example, within the strut block 635, a first strut column line can be activated by a first strut decoder, and every other strut row line (or some other subset of strut row lines where no two strut row lines are adjacent) can be activated concurrently by a second strut decoder, thereby concurrently activating every other strut 630 within the first column of the struts 630 (or some other subset of struts 630 where no two activated struts within the first column are adjacent). One or more word line boards can also be activated concurrently by one or more corresponding word line decoders to access the memory cells coupled to the activated struts 630 within the first row. Subsequently, the first strut column line can be deactivated by the first strut decoder, and a second strut column line can be activated by the first strut decoder, possibly while one or more word line boards remain activated.

[0109] Accordingly, by activating different pillar column lines in a sequential manner, different memory cells coupled to the pillars 630 in different rows of the pillar 630 can be accessed while one or more word line plates remain activated. In some cases, the same one or more pillar row lines can also remain activated while one or more word line plates remain activated, such that different memory cells coupled to different pillars 630 in the same one or more rows but different columns of the pillar 630 can be accessed in a partially parallel manner (e.g., while the same group of one or more word line plates remain activated, while the same group of one or more pillar row lines remain activated, or both). And in some cases, different pillar row lines can be activated when different pillar column lines are activated, such that different memory cells coupled to different pillars 630 in different rows and different columns of the pillar 630 can be accessed in a partially parallel manner. In some cases, this partially parallel access may occur for two or more memory cells distributed across the left and right hand word line plates of the page 610 or page 615.

[0110] Figure 7A An example of a memory cell architecture 705 that supports a decoding architecture for a memory bank according to an example as disclosed herein is illustrated. The memory cell architecture 705 can be used for the memory cells 750, which can be examples of memory cells that can be included in the memory arrays described herein. The memory cells 750 can be accessed via corresponding word lines 720 (e.g., word line 720-a or word line 720-b) and pillars 740 (e.g., bit lines or selectable portions thereof). The pillars 740 can represent examples of the pillars described Figures 3 to 6 and other examples described herein. The word line 720-a can represent a first word line finger of a first word line plate, and the word line 720-b can represent a second word line finger of a second word line plate, as described herein. For example, as described with reference to FIG. 4 (e.g., and other examples), the fingers of the first and second word line plates can be parallel but extend in opposite directions (e.g., one to the right and away from the spine of the first word line plate, the other to the left and away from the spine of the second word line plate) and can be interlocked with each other. The Figure 7A view illustrated can represent a top view of the memory cell architecture 705 such that the pillars 740 can extend out of the page.

[0111] The memory cell architecture 705 may include a first memory cell 750-a (e.g., which may be or include a first chalcogenide element) and a second memory cell 750-b (e.g., which may be or include a second chalcogenide element). As described herein, a chalcogenide element may be a storage element that includes one or more chalcogenide glasses for storing a logical state within the memory cell 750. The memory cells 750-a and 750-b may be coupled to the pillar 740 via a first electrode 730-a and 730-b, respectively. The memory cells 750-a and 750-b may be coupled to corresponding word lines 720 via second electrodes 725-a and 725-b, respectively. The first electrode 730 may provide a sufficient conductive level while preventing direct contact between the memory cell 750 and the pillar 740, and the second electrode 725 may similarly provide a sufficient conductive level while preventing direct contact between the memory cell 750 and the corresponding word line 720, e.g., to reduce contamination (e.g., chemical contamination between the chalcogenide glass and the material of the word line 720 or the pillar 740). In some cases, the first electrode 730 and the second electrode 725 may represent carbon electrodes or carbon-based electrodes. The memory cell architecture 705 may additionally include one or more dielectric materials 745 (e.g., which may provide electrical insulation between two or more components).

[0112] In some cases, the overall shape of the memory cell architecture 705 (e.g., of a pair of complementary memory cells 750 at the same tier of vertically stacked word line plates and on either side of the pillar 740) may be a rectangular shape. For example, the shape of the memory cell architecture 705 may include a first dimension in the y direction (e.g., P Y ), which may be greater than a second dimension in the x direction (e.g., P X ), or vice versa.

[0113] Figure 7B An example of a pillar selector 710 that supports a decoding architecture for a memory bank according to an example as disclosed herein is illustrated. The pillar selector 710 may represent an example of the pillar selector 345 described with reference to Figure 3 and other examples described herein. The pillar selector 710 may represent a transistor (e.g., a TFT or other type of transistor) and may be positioned below the memory cell architecture 705. For example, the pillar selector may be positioned below the corresponding pillar 740 and may be coupled to the corresponding pillar. The view illustrated by Figure 7B may represent a top view of the pillar selector 710 such that the pillar may be positioned on top of the pillar selector 710 (coming out of the page). The pillar selector 710 may be operative to select the pillar 740 during an access operation for the memory cell architecture 705 by coupling the pillar 740 to a pillar row line (e.g., a pillar source line), e.g., as referencedFigure 3 as described.

[0114] The pillar selector 710 (e.g., a TFT) may include a gate 755, a gate oxide material 765, and a channel material 760. The channel material 760 may be a semiconductor (e.g., a polysilicon material) or other material suitable for use as a transistor channel and may be coupled to the gate 755 via the gate oxide material 765. The gate 755 may be formed in a U-shape in the z-direction (where the two sides of the U extend upward out of the page, and the bottom of the U is below the channel material and the gate oxide material 765, where the gate oxide material may also be formed in a similar (e.g., concentric) U-shape in some cases). Thus, for example, as Figure 7B illustrated, the two sides of the gate 755 may be connected under the gate oxide material 765 to form a single gate 755. This transistor gate architecture may increase the drive capability of the pillar selector 710.

[0115] In some cases, the effective transistor width of the pillar selector 710 (and thus the corresponding drive strength of the pillar selector 710, based on the transistor width) may be greater than (e.g., twice) the physical width of the pillar selector 710 in the x-direction based on the two sides of the gate 755 (e.g., the U-shaped transistor architecture may have functional benefits similar to a double-gate architecture). For example, compared to other transistors having a similar physical width in the x-direction, this greater effective transistor width may increase the drive strength of the pillar selector 710. Thus, for example, this U-shaped transistor gate architecture may allow an increased effective aspect ratio of the pillar selector 710 while maintaining the elongated dimension of the gate 755 aligned (e.g., parallel) with the elongated direction of the memory cell architecture 705 (e.g., both the gate 755 and the memory cell architecture 705 may be longer in the y-direction than in the x-direction).

[0116] This alignment may have space-saving benefits for the memory array as described herein. For example, in some cases, the dimension of the pillar selector 710 in the y-direction may be less than or equal to the dimension of the memory cell architecture 705 in the y-direction and / or the dimension of the pillar selector 710 in the x-direction may be less than or equal to the dimension of the memory cell 705 in the x-direction. Thus, the pillar selector 710 may be positioned (e.g., may fit) under the corresponding pillar 740 (e.g., and the corresponding memory cell architecture 705). The structure and alignment of the memory cell architecture 705 and the pillar selector 710 may thus support an increased drive capability of the pillar selector 710 (e.g., the maximum drive capability of the pillar selector 710), overall space savings for the memory array, or both, as well as other possible benefits understood by those of ordinary skill in the art.

[0117] The gate 755 of the support pillar selector 710 can be coupled to the support pillar column line, and the source of the support pillar selector 710 (e.g., the left or right side of the channel 760 in the x direction) can be coupled to the support pillar row line. Thus, in some cases, the support pillar column line can be referred to as the support pillar gate line, and the support pillar row line can be referred to as the support pillar source line. The drain of the support pillar selector 710 (e.g., the side of the channel 760 opposite to the source in the x direction) can be coupled to the support pillar 740, such that for example when the corresponding support pillar row line applies an activation voltage to the gate 755 of the support pillar selector 710, the support pillar selector 710 can couple the support pillar 740 to the support pillar row line.

[0118] Figure 7C An example of a support pillar block 715 that supports a decoding architecture for a memory block as described herein is illustrated. The support pillar block 715 can be an example of a support pillar block as described herein, for example with reference to Figure 6 that which is described. The support pillar block 715 can include a plurality of support pillar units 770, where each support pillar unit 770 can include or represent an example of the memory cell architecture 705 described herein (e.g., can each include a corresponding support pillar 740 and two memory cell stacks coupled to the support pillar 740). The support pillar units 770 and the corresponding support pillars 740 can be distributed across the support pillar block 715 in the x and y directions. Although the support pillar units 770 and the corresponding support pillars 740 are shown as being arranged in a linear manner, the support pillar units 770 and the support pillars 740 can alternatively or additionally be arranged in another geometric pattern (e.g., staggered), as described, for example, with reference to FIGS. 4 and 5.

[0119] The support pillar block 715 can include a plurality of support pillar rows 775 and support pillar columns 780 (e.g., rows and columns of the support pillars 740). Each support pillar column 780 can be respectively associated with a corresponding support pillar column line (e.g., support pillar gate line) extending in the y direction, and each support pillar row 775 can be respectively associated with a corresponding support pillar row line (e.g., support pillar source line) extending in the x direction. The support pillar column lines can be associated with a first support pillar decoder for the support pillar block 715 (e.g., support pillar gate line or support pillar column line decoder) and the support pillar row lines can be associated with a second support pillar decoder for the support pillar block 715 (e.g., support pillar source line or support pillar row line decoder).

[0120] The first pillar decoder is operable to selectively activate (e.g., apply a select or activation voltage) or deactivate (e.g., apply a deselect or deactivation voltage to) the pillar column lines of the pillar tile 715 independently of each other (e.g., one at a time, or any subset or all of them concurrently). The second pillar decoder is operable to selectively activate (e.g., apply a select or activation voltage) or deactivate (e.g., apply a deselect or deactivation voltage to) the pillar row lines of the pillar tile 715 (e.g., one at a time, or any subset or all of them concurrently). Thus, the pillar tile 715 can include the total area or number (e.g., maximum area) of the pillars 740 and associated memory cells 750 that can be activated or selected using the first pillar decoder (e.g., in the X direction) and the second complementary pillar decoder (e.g., in the Y direction).

[0121] A pillar 740 of the pillar tile 715 can be activated by applying a first voltage (e.g., a first select voltage) to the corresponding pillar column line and a second voltage to the corresponding pillar row line. Applying the first voltage can activate the pillar selector 710 coupled to the pillar column line. When activated, each pillar selector 710 can couple the corresponding pillar 740 on the pillar column line to the respective pillar row line. Applying the second voltage (e.g., a second select voltage) to the pillar row line can cause the second voltage (e.g., or a voltage close to the second voltage) to be applied to the pillar 740 located at the junction of the activated pillar column line and the pillar row line (e.g., based on the pillar 740 being coupled to the pillar row line via the corresponding, activated pillar selector 710). In such cases, the pillar 740 can be referred to as being selected or activated.

[0122] Each pillar row 775 can include a first number of pillars 740 (e.g., P X ) distributed in the x direction, and each pillar column 780 can include a second number of pillars 740 (e.g., P Y ) distributed in the y direction. In some instances, there can be more pillars 740 included in the pillar row 775 than in the pillar column 780, or alternatively, there can be more pillars 740 included in the pillar column 780 than in the pillar row 775. Additionally or alternatively, based on the rectangular shape of the associated memory cell architecture (e.g., the memory cell architecture 705), the pillar tile 715 can have dimensions in the x direction that are different from those in the y direction (e.g., having a greater number of pillars 740 in the x direction).

[0123] In some cases, the dimension of the pillar block 715 in the y direction (e.g., the length of the pillar gate line) may be based on the capacitance or other quality of the pillar gate line (e.g., the pillar column line) of the pillar block 715, such that the speed for activating the pillar gate line may meet one or more thresholds (e.g., the specification of the memory speed). In some cases, the capacitance or other quality of the pillar source line may support the dimension of the pillar block 715 in the x direction (e.g., the length of the pillar source line) being greater than the dimension of the pillar block 715 in the y direction, may support the pillar block 715 including more pillars in the x direction than in the y direction or both. However, it should be understood that without departing from the teachings herein, the pillar block 715 may include any number of pillars 740 in any direction.

[0124] The pillar block 715 may include a plurality of word line blocks as described elsewhere herein, and the plurality of word line blocks may each include one or more word line plates having a comb-like structure with interleaved word line fingers. The word line plates within a word line block may be stacked in the z direction (out of the page). The fingers of each word line plate may extend horizontally across the corresponding word line block in the x direction.

[0125] The size of the word line driver included in or coupled to the word line decoder may be determined based on the capacitance of the word line plate and the desired activation response time, and thus the desired drive current capability. As the number of word line blocks included in the pillar block 715 increases, the number of word line plates in each vertical stack within the word line block increases (e.g., the number of levels of the memory array in the z direction) or both, and the number of word line drivers for driving (e.g., applying a voltage to) the corresponding word line plates included in the pillar block 715 may increase proportionally (e.g., the drive capability of the word line decoder may increase as the total capacity of the word line blocks increases). In such cases, the area of the pillar block 715 occupied by such word line drivers (e.g., the area within the CuA) may thus increase.

[0126] Figure 8A And 8B Illustrate corresponding examples of pillar block architectures 800-a and 800-b that support a decoding architecture for a memory block according to an example as disclosed herein. The pillar block architectures 800-a and 800-b may illustrate an architecture in which the decoding circuitry and support circuitry for operating the memory array may be located below one or more pillar blocks 805 (e.g., may be implemented as a CuA for one or more pillar blocks 805). The pillar blocks 805 may represent herein, for example, with reference to Figure 6Examples of the pillar chunks as described in 7. The CuA for each pillar chunk 805 may include a word line decoding circuit system 810 (e.g., which may include a word line decoder), a pillar decoding circuit system 815 (e.g., which may include a pillar decoder), and sense amplifiers 820 positioned below (e.g., within its coverage area) a corresponding set of memory cells and access lines included in the pillar chunk 805, each of which may be an example of such components described elsewhere herein.

[0127] The word line decoding circuit system 810 may be shared across two or more adjacent pillar chunks 805. For example, the word line decoding circuit system 810 may be aligned with the edges of two or more pillar chunks 805 and may be shared across two or more pillar chunks 805. The word line decoding circuit system 810 may include a number of word line drivers, each of which may be operable to drive a corresponding word line plate (or a corresponding set of word line plates, where multiple word line plates may be driven via a common electrode) to a desired voltage (e.g., a select voltage or a deselect voltage). In some cases, the word line decoding circuit system 810 may occupy a continuous region underlying multiple pillar chunks 805 (e.g., a portion spanning its coverage area), such as a continuous region underlying two or four pillar chunks 805 as shown in FIG. 8, and may include one or more word line decoders each operable to drive at least one word line plate within two or more of the overlying pillar chunks 805.

[0128] For example, a word line decoding circuitry 810 occupying a continuous region underlying two or more pillar blocks 805 may be coupled to a first word line board within a first pillar block 805 of the two or more pillar blocks 805 and a second word line board within a second pillar block 805 of the two or more pillar blocks 805 (and also possibly a third word line board within a third pillar block 805 of the two or more pillar blocks 805 and a fourth word line board within a fourth pillar block 805 of the two or more pillar blocks 805). The word line decoding circuitry 810 may thus be operable to activate (e.g., concurrently or non - concurrently activate) word line boards associated with two or more adjacent pillar blocks 805 (e.g., coupled to memory cells which are in turn coupled to pillars within the two or more adjacent pillar blocks 805). The word line decoding circuitry 810 may include one or more word line decoders each of which may include a plurality of word line drivers. Each word line decoder may correspond to one or more word line segments and may be operable to activate or de - activate individual word line boards within the corresponding word line segment. For example, each word line decoder may include a set of word line drivers where each word line driver may be operable to activate one word line board within a set of word line boards (e.g., a stack) within the corresponding word line segment, or in some cases may be operable to concurrently activate a plurality of word line boards each in a different corresponding word line segment (e.g., different stacks, possibly at the same tier within different stacks) but coupled to the word line driver via a common electrode (e.g., a common stepped electrode). Thus, sharing word line decoders, drivers, or both across adjacent pillar blocks 805 as described herein may reduce the number of word line decoders, drivers, or both included in the word line decoding circuitry 810 located beneath individual pillar blocks 805, thereby enhancing the ability to locate all associated word line decoding circuitry 810 beneath a memory array having a plurality of pillar blocks 805.

[0129] The area occupied by the word line decoding circuitry 810 beneath a given pillar block 805 may increase as the number of word line boards associated with each pillar block 805 increases (e.g., based on the number of word line segments in the pillar block 805, based on the number of word line boards within the word line segment, e.g., the number of tiers of the memory array and thus the number of word line segments in the z - direction or both). Figure 8A and 8B The views illustrated in may represent a top view of the pillar block 805 such that the word line board stacks within the word line segments (e.g., each word line board corresponding to one tier of the memory array of the stack) may extend out of the page. The area occupied by the continuous region of the word line decoding circuitry 810 may be associated with the number of word line drivers for driving the respective word line boards in each pillar block 805 (e.g., where each word line driver drives a respective word line board within the corresponding word line segment or a set of respective word line boards within a set of corresponding word line segments).

[0130] In some cases, the size of each bit line driver can be independent of the number of word line plates (and thus the number of word line segments) in the support block 805. For example, each word line driver can drive one or more word line plates that each have a known capacitance to a desired access voltage during a desired time period (e.g., a timing specification), and the size (e.g., transistor width) of each word line driver can be associated with the corresponding drive strength of the word line driver (e.g., for driving one or more word line plates). Thus, the size of the individual word line drivers within the word line decoding circuitry 810 can be based on the size and electrical quality (e.g., capacitance, length) of the word line plates of the memory array.

[0131] The number of word line drivers associated with the support block 805 can be based on the number of independently addressable (e.g., capable of being activated or deactivated independently of each other) word line plates in the support block 805. For example, within the hierarchy of the memory array, the total number of word line fingers can depend on the number of pillars along a given dimension within the support block 805 (e.g., if the word line fingers extend in the x direction, then the total number of word line fingers within the support block 805 can depend on the number of pillars included in a column of pillars spanning the support block 805 in the y direction). The word line fingers can be grouped into separate word line plates within the hierarchy to reduce the capacitance of the individual word line plates. For example, if a column of pillars within the support block 805 contains 1,024 pillars, then the hierarchy of the support block 805 can include 512 word line fingers extending to the right and 512 word line fingers extending to the left that can span the support block 805 in the y direction, where each word line finger extends between two pillars of the column (e.g., as shown in FIGS. 4 and 5). It should be understood that these and any other specific numerical examples provided herein are for illustrative clarity only and do not limit the claims or the present disclosure.

[0132] Two sets of 512 word line fingers rather than a single word line comb with 512 fingers can be divided across a set of separate word line plates (e.g., to reduce the capacitance associated with each individual word line plate). For example, in the y direction within a given hierarchy of the support block 805, a first set of eight (8) word line plates each having 64 fingers can provide a total of 512 word line fingers extending to the right, and a second set of 8 word line plates each having 64 fingers can provide a total of 512 word line fingers extending to the left. Each of the 16 word line plates can be included in a separate word line segment, where the word line segments can include word line plates each having 64 fingers stacked vertically (e.g., stacked in the z direction). The number of word line plates in the vertical stack can be equal to the number of hierarchies of the memory array.

[0133] In some cases, each word line board within the support pillar block 805 that is vertically stacked (e.g., each word line block) can be independently addressable. Within the vertical stack of word line boards, different word line boards can be independently addressable relative to each other (e.g., one word line board can be activated or deactivated at a time within the vertical stack). For example, each vertical stack of word line boards within the support pillar block 805 can be coupled to a different respective word line decoder, and the respective word line decoder for the vertical stack can include different respective word line drivers for each word line board of the vertical stack. Thus, the number of word line drivers associated with operating the word line boards of the support pillar block 805 can depend on the number of word line boards within each level of the support pillar block and the number of levels. For example, if in the y direction, the support pillar block 805 includes 8 vertical stacks of word line boards with right-extending fingers and 8 vertical stacks of word line boards with left-extending fingers (where each vertical stack includes 64 word line boards), then a total of 1,024 independently addressable word line boards can be included within the support pillar block 805, thus resulting in a total of 1,024 associated word line drivers, which can be considered as a first group of 512 word line drivers associated with the word line boards with right-extending fingers and a second group of 512 word line drivers associated with the word line boards with left-extending fingers. Thus, through this sharing, for example, the number of word line drivers associated with the support pillar block 805 can be equal to half of the value determined by multiplying the number of levels in the support pillar block 805 by the number of word line boards in each level (i.e., equal to the total number of word line boards of the support pillar block 805), which can be considered as two groups of word line drivers each being half of the product quantity.

[0134] If the word line decoder (and thus the drivers therein) is shared by adjacent support pillar blocks 805, then the total number of word line drivers located beneath individual ones of the support pillar blocks 805 can be reduced. For example, as described elsewhere herein, a first word line board (e.g., with right-extending fingers) in a first word line block within a first support pillar block 805 can be coupled to a word line driver that is the same as a second word line board (e.g., with left-extending fingers) in a second word line block within a second support pillar block 805 via a common electrode. For example, the first word line board and the second word line board can be at the same level within their respective word line blocks (e.g., can be coplanar).

[0135] Thus, in this example, from the perspective of a single pillar block 805, the number of associated word line drivers for placement under the pillar block 805 can be halved (e.g., 512 word line drivers under the pillar block 805, which can be considered to include a first group of 256 word line drivers associated with a word line plate having right-extending fingers and a second group of 256 word line drivers associated with a word line plate having left-extending fingers), because some of the word line drivers associated with the pillar block 805 can be located adjacent to and under the pillar block. Additionally, in this example, the word line decoder can be considered to be shared between a first word line block within the first pillar block 805 and a second word line block within the second pillar block 805, and an individual word line decoder can be entirely located under one of the two pillar blocks 805, or can include a first portion located under the first pillar block 805 and a second portion located under the second pillar block 805. As shown in FIG. 8, the word line decoding circuitry located under the pillar block 805 can be aligned with one or more edges of the pillar block 805 (e.g., adjacent to one or more edges of the coverage area of the pillar block 805).

[0136] In some cases, the CuA of each pillar block 805 can additionally or alternatively include pillar decoding circuitry 815 for activating the pillars, where in some cases each of the pillars can be individually addressed. For example, a pillar decoder (e.g., a gate line pillar decoder or a source line pillar decoder) within the pillar decoding circuitry 815 can selectively activate and deactivate corresponding pillar column lines or pillar row lines of individual pillar rows or columns. As described herein, for example, with reference to FIG. 7, the activated pillar column lines and pillar row lines can activate corresponding pillars of the memory array at the junctions of the pillar column lines and the pillar row lines. For example, a pillar column line can activate a corresponding pillar selector (or its column), such as the pillar selector 710 described with reference to Figure 7B As described, and a pillar row line can be used to apply a voltage to the pillar via the activated pillar selector. In some cases, the pillar row lines and pillar column lines associated with the pillar decoder can have relatively low capacitance compared to the word line plates associated with the word line decoder. Thus, the pillar decoder can include pillar line drivers each including one or more transistors that are smaller than the transistors associated with the word line drivers, and thus in some cases, the pillar decoding circuitry 815 under the pillar block 805 can occupy less area than the word line decoding circuitry 810 under the pillar block 805.

[0137] The first part of the stanchion decoding circuitry 815 (e.g., the stanchion column line or stanchion gate line decoder) can be divided into two parts (e.g., subsets) each oriented in the x-direction within the stanchion tile 805, where each of the two parts can be located near opposite edges of the stanchion tile 805 (e.g., can be aligned with the opposite edges respectively, e.g., adjacent to the opposite edges of the coverage area of the stanchion tile 805 respectively). As Figure 8A depicted, the second part of the stanchion decoding circuitry 815 (e.g., the stanchion row line or stanchion source line decoder) can be oriented in the y-direction near the middle section of the stanchion tile 805. In some cases, the second part of the stanchion decoding circuitry 815 can be further divided into two interleaved (e.g., offset in the x-direction) parts (e.g., subsets), as Figure 8A shown. As described herein, the stanchion decoder of the stanchion decoding circuitry 815 can operate to selectively activate individual stanchion row lines or stanchion column lines. It should be understood that the stanchion tile 805 as Figure 8A shown in or 8B or otherwise described herein can be rotated 90 degrees clockwise or counterclockwise such that the references to the x-direction and y-direction can be reversed.

[0138] For example, the two first parts of the stanchion decoding circuitry 815 oriented in the x-direction can operate to activate corresponding stanchion column lines extending in the y-direction, and the second subset of the stanchion decoding circuitry 815 extending in the y-direction can operate to activate corresponding stanchion row lines extending in the x-direction. By activating the stanchion column lines (e.g., gate lines), the stanchion decoder of the stanchion decoding circuitry 815 can activate the gates of the corresponding stanchion selectors (or their columns) coupled to the activated stanchion column lines. Similarly, by activating the stanchion row lines (e.g., source lines), the stanchion decoder of the stanchion decoding circuitry 815 can activate the sources of the corresponding stanchion selectors (or their corresponding rows) coupled to the activated stanchion row lines (e.g., and thereby apply a voltage to the stanchions located at the intersections of the stanchion column lines and the stanchion row lines).

[0139] The size of the pillar line drivers of the pillar decoding circuitry 815 (e.g., and thus the size of the area occupied by the pillar decoder) can be based on the resistivity and capacitance of each pillar access line (e.g., pillar column or row line), which can be based on the length of the access line, the number of pillar selectors coupled to the pillar access line, or both. For example, if the resistivity or capacitance of a pillar access line increases, then the drive capability of the associated pillar line driver (e.g., transistor) can be increased to drive the access line to meet the desired timing specifications, which can result in an increased area (e.g., width) of the corresponding pillar line driver. In one example, the number of pillars and corresponding pillar selectors associated with each pillar column line in the y direction can correspond to a first capacitance. The pillar line driver associated with a respective pillar row line (e.g., pillar gate line driver) can drive a first current through the pillar column line during a time period to charge the pillar column line to the desired voltage. The pillar line driver can have a minimum width to support such drive capability. Each pillar row line driver can be associated with a similar corresponding width for driving the respective pillar row line based on the resistivity and capacitance of the pillar row line.

[0140] In some cases, the pillar decoding circuitry 815 under the pillar tile 805 can include one pillar column line driver (e.g., for each pillar column line within the pillar tile 805) and one pillar row line driver (e.g., for each pillar row line within the pillar tile 805) for each pillar column within the pillar tile 805. Thus, the area of the pillar decoding circuitry 815 under the pillar tile 805 can be based on the number of pillar columns and the number of pillar rows within the pillar tile 805. Advantageously, the area of the pillar decoding circuitry 815 under the pillar tile 805 (e.g., based on the number of pillar line drivers or decoders in the pillar decoding circuitry 815) can be independent of the number of tiers of the memory array, which can support an increase in tiers while maintaining the ability to implement the pillar decoding circuitry 815 along with other circuitry as a CuA.

[0141] The remaining area of the CuA of each pillar tile 805 (e.g., the area within the coverage area of the pillar tile 805 not occupied by the word line decoding circuitry 810 or the pillar decoding circuitry 815) can include other circuitry for supporting the operation of the pillar tile 805, such as sense amplifiers 820. Each pillar tile 805 can include a certain number of sense amplifiers 820 for supporting a desired number of parallel or concurrent access operations (e.g., parallelism) to the multiple memory cells within the pillar tile. For example, each pillar tile can include a number of sense amplifiers 820 corresponding to (e.g., equal to) the number of pillar row lines (and thus pillar rows) within the pillar tile 805. While in Figure 8A and 8Billustrates some locations of the sense amplifier 820, but it should be understood that the sense amplifier 820 may be located in any area under the pillar tile 805 not occupied by the decoding circuitry (e.g., the word line decoding circuitry 810 and the pillar decoding circuitry 815).

[0142] Figure 8B illustrates a pillar tile architecture 800-b that includes a plurality of pillar tiles 805. As Figure 8B illustrated, in some cases, the pillar decoding circuitry 815 (e.g., pillar decoder) in each pillar tile 805 may be aligned with a respective edge of the pillar tile 805 (e.g., adjacent to a respective edge of the coverage area of the pillar tile 805) and may be shared across adjacent pillar tiles 805. For example, a pillar column decoder (e.g., occupying an area and aligned with an edge of the pillar tile 805 extending in the x direction), a source pillar decoder (e.g., occupying an area and aligned with an edge of the pillar tile 805 extending in the y direction), or both may be shared between adjacent pillar tiles 805. If a pillar column decoder is shared between a first pillar tile 805 and an adjacent second pillar tile 805, the pillar column decoder may be operable to selectively and concurrently activate a first pillar column line within the first pillar tile 805 and a second pillar column line within the second pillar tile 805. Similarly, if a pillar row decoder is shared between a first pillar tile 805 and an adjacent second pillar tile 805, the pillar row decoder may be operable to selectively and concurrently activate a first pillar row line within the first pillar tile 805 and a second pillar row line within the second pillar tile 805. This sharing of the pillar decoding circuitry 815 between pillar tiles 805 may halve the number of pillar line drivers per pillar tile 805 and, thus, may beneficially halve the number of pillar line drivers located under the pillar tiles 805. For example, the number of pillar column line drivers under the pillar tiles 805 may be equal to half the number of pillar columns (and thus pillar column lines) of the pillar tiles 805, the number of pillar row line drivers under the pillar tiles 805 may be equal to half the number of pillar rows (and thus pillar row lines) of the pillar tiles 805, or both.

[0143] Figure 9A and 9BDescribe examples of word line drivers 900-a and 900-b that support a decoding architecture for memory blocks according to examples disclosed herein. The word line driver 900 may represent an example of a portion (e.g., among other portions) of a word line decoder as described herein, e.g., with reference to FIG. 8. For example, word line driver 900-a, word line driver 900-b, one or more other word line drivers 900, or any combination thereof may be included in a CuA under a corresponding memory array and may be used to activate one or more corresponding word line plates of the memory array. The word line decoder may include multiple word line drivers 900 and may be operable to activate one word line driver 900 at a time to activate one or more corresponding word line plates coupled to the word line driver 900. Word line drivers 900-a and 900-b may be operable to activate or access the word line plate by applying a voltage bias to an electrode coupled to the corresponding word line plate, as described herein, e.g., with reference to FIG. 8.

[0144] Figure 9A Describe word line driver 900-a, which may include n-type transistors 905-a and 905-b (e.g., negative metal oxide semiconductor (N-MOS) transistors 905) and may be referred to as a 2N-MOS driver. Word line driver 900-a may be operable to drive (e.g., select or activate) a corresponding word line plate. In some examples, word line plate signal 930-a may be output by transistors 905-a and 905-b. Word line plate signal 930-a may be applied to the word line plate via an electrode coupled to transistors 905-a and 905-b (e.g., coupled to the source of transistor 905-a and the drain of transistor 905-b), where, based on one or more input signals to word line driver 900-a, word line plate signal 930-a may keep the word line plate deactivated or may activate (e.g., select) the word line plate. For example, word line plate signal 930-a may be set in an inactive state (e.g., a low state) until a voltage combination is applied to transistors 905-a and 905-b, which may cause word line plate signal 930-a to transition to an active state (e.g., a high state), e.g., to activate the word line plate by applying a voltage bias to the electrode (e.g., and via the electrode to the word line plate). Word line plate signal 930-a may transition from the active state to the inactive state in response to the voltage combination no longer being applied to transistors 905-a and 905-b.

[0145] The drain node of transistor 905-a may be configured to receive block selection signal 915-a, and the source of transistor 905-b may be coupled to a lower voltage supply 920 (e.g., ground). As shown by Figure 8AAs described, the source node of transistor 905-a can be coupled to the drain node of transistor 905-b. The gate of transistor 905-a can be configured to receive a first-level select signal 925-a, and the gate of transistor 905-b can be configured to receive a second-level select signal 925-b. The nodes at the source of transistor 905-a and the drain of transistor 905-b can be further coupled to respective word line plates (e.g., via the electrodes, such as the stepped electrodes described herein). In some cases, the block select signal 915-a, the first-level select signal 925-a, or the second-level select signal 925-b can be provided by a memory controller (e.g., local memory controller 165). In other cases, the block select signal 915-a, the first-level select signal 925-a, or the second-level select signal 925-b can be provided by other aspects of the word line decoding circuitry (e.g., the word line decoder including word line driver 900-a).

[0146] The word line driver 900-a can be associated with a word line plate of a word line plate stack in a word line block (e.g., at any tier or level located within the word line plate stack), as described herein. To activate the word line plate, the memory device can cause the block select signal 915-a to transition from a deselected voltage to a selected voltage (e.g., from a low to a high voltage) based on word line block j including the respective word line plate for word line driver 900-a being selected for activation. For example, the memory device can cause the block select signal 915-a to transition from a deselected voltage to a selected voltage based on a command from a host device or a controller of the memory device. In some cases, the block select signal 915-a can be applied in a similar manner to each word line driver 900 associated with word line block j.

[0147] Concurrent with the transition of the block select signal 915-a from an unselected voltage to a selected voltage, the memory device may cause the first-level select signal 925-a to transition from an unselected voltage to a selected voltage (e.g., from a low to a high voltage) based on level i including the corresponding word line boards for the word line driver 900-a being selected for activation. For example, the memory device may cause the first-level select signal 925-a to transition from an unselected voltage to a selected voltage based on a command from a host device or a controller of the memory device. In some cases, the second-level select signal 925-b may be the complement of the first-level select signal 925-a and may thus transition in a complementary manner (e.g., from a high to a low voltage) based on the first-level select signal 925-a transitioning from an unselected voltage to a selected voltage. In some cases, the first-level select signal 925-a and the second-level select signal 925-b may be applied in a similar manner to each word line driver 900 associated with level i, but only the word line driver 900 that selects the corresponding word line block may cause the corresponding word line board signal 930-a to transition to an active state.

[0148] The block select signal 915-a, the first-level select signal 925-a, and the second-level select signal 925-b may set the corresponding transistors 905-a and 905-b in an on or off state to set the word line board signal 930-a (e.g., the signal for activating the word line board at level i within word line block j) in an active state when the corresponding word line board is activated, or to set the word line board signal 930-a in an inactive state when the corresponding word line board is not activated. For example, when the word line board is activated (e.g., to access one or more corresponding memory cells), the voltage difference between the first-level select signal 925-a and the active state of the word line board signal 930-a may be greater than the threshold voltage of the transistor 905-a such that the transistor 905-a may turn on, and the voltage difference between the second-level select signal 925-b and the lower voltage supply 920 may be less than the threshold voltage of the transistor 905-b such that the transistor 905-b may turn off (e.g., to reduce the likelihood of shorting to the lower voltage supply 920). Thus, based on the block select signal 915-a, the first-level select signal 925-a, and the second-level select signal 925-b being in a particular voltage combination, the word line board signal 930-a may transition to an active state (e.g., a high voltage) (e.g., the block select signal 915-a may be transmitted from the drain to the source of the transistor 905-a).

[0149] When the word line board is not accessed, the word line board signal 930-a can be set to an inactive state (e.g., a low voltage, such as a ground voltage). For example, the voltage difference between the first level select signal 925-a and the word line board signal 930-a can be less than the threshold voltage of the transistor 905-a, and the voltage difference between the second level select signal 925-b and the lower voltage supply 920 can be greater than the threshold voltage of the transistor 905-b, such that the transistor 905-b can be turned on and the transistor 905-a can be turned off. Accordingly, the block select signal 915-a may not be coupled to the word line board signal 930-a, and the word line board signal 930-a can be transitioned to the voltage of the lower voltage supply 920 through the transistor 905-b. Additionally or alternatively, the block select signal 915-a can be transitioned to a deselected voltage (e.g., a low voltage) to set the word line board signal 930-a in an inactive state.

[0150] Figure 9B Describe an example of a word line driver 900-b that can include a p-type transistor 910 (e.g., a positive metal oxide semiconductor (P-MOS) transistor) and an n-type transistor 905-c (e.g., such that the word line driver 900-b can have an N+P-MOS structure). The word line driver 900-b can be operable to drive (e.g., select or activate) a corresponding word line board using the word line board signal 930-b, which can represent the word line board signal as described in reference Figure 9A as described.

[0151] The source node of the transistor 910 can be configured to receive a first block select signal 915-b (e.g., a signal that can be referred to as a positive block select signal), and the source node of the transistor 905-c can be configured to receive a second block select signal 915-c (e.g., a signal that can be referred to as a negative block select signal). The gate of the transistor 910 can be configured to receive a first level select signal 925-c, and the gate of the transistor 905-c can be configured to receive a second level select signal 925-d. As illustrated by Figure 9B as illustrated, the drain node of the transistor 910 can be coupled to the drain node of the transistor 905-b. The nodes at the drain of the transistor 910 and the drain of the transistor 905-c can be further coupled to a corresponding word line board (e.g., via an electrode, such as the stepped electrode described herein).

[0152] The word line driver 900-b may be associated with a word line board that is stackable with word line boards in a word line block (e.g., located at any tier or level within the word line board stack), as described herein. To activate the word line board, the memory device may cause the first block select signal 915-b to transition from an unselected voltage to a selected voltage (e.g., from a low to a high voltage), cause the second block select signal 915-c to transition from an unselected voltage to a selected voltage (e.g., from a high to a low voltage), or both, based on the word line block j that includes the corresponding word line board for the word line driver 900-b being selected for activation. For example, the memory device may cause such a transition based on a command from a host device or a controller of the memory device. In some cases, the first block select signal 915-b and the second block select signal 915-c may be applied in a similar manner to each word line driver 900 associated with the word line block j.

[0153] Concurrent with causing the first block select signal 915-b to transition from an unselected voltage to a selected voltage, the second block select signal 915-c to transition from an unselected voltage to a selected voltage, or both, the memory device may cause the first tier select signal 925-c (e.g., a signal that may be referred to as a positive tier select signal) and the second tier select signal 925-d (e.g., a signal that may be referred to as a negative tier select signal) to transition from an unselected voltage to a selected voltage (e.g., from a high to a low voltage, e.g., to the voltage of the low voltage supply 920) based on the tier i that includes the corresponding word line board for the word line driver 900-b being selected for activation. In some cases, the first tier select signal 925-c and the second tier select signal 925-d may be applied in a similar manner to each word line driver 900 associated with the tier i, but only the word line drivers 900 that select the corresponding word line block may cause the corresponding word line board signal 930-b to transition to an active state.

[0154] The positive block selection signal 915-b, the negative block selection signal 915-c, the positive level selection signal 925-c, and the negative level selection signal 925-d can set the corresponding transistors 910 and 905-c in an on or off state so that when the corresponding word line board is activated, the word line board signal 930-b (e.g., a signal for activating the word line board at level i in block j of the word line) can be set in an active state, or when the corresponding word line board is not activated, the word line board signal 930-b can be set in an inactive state. For example, when the word line board is activated (e.g., to access one or more corresponding memory cells), the voltage difference between the first level selection signal 925-c and the first block selection signal 915-b can be greater than the threshold voltage of the transistor 910, such that the transistor 910 can be turned on, and the voltage difference between the second level selection signal 925-d and the second block selection signal 915-c can be less than the threshold voltage of the transistor 905-c, such that the transistor 905-c can be turned off (e.g., to reduce the likelihood of shorting to the lower voltage supply 920). Thus, based on the first block selection signal 915-b, the first level selection signal 925-c, the second level selection signal 925-d, and the second block selection signal 915-c being in a particular voltage combination, the word line board signal 930-b can transition to an active state (e.g., high voltage) (e.g., the first block selection signal 915-b can be transferred from the drain of the transistor 910 to the drain).

[0155] When the word line board is not accessed, the word line board signal 930-b can be set to an inactive state (e.g., low voltage, such as ground voltage). For example, the voltage difference between the first level selection signal 925-c and the first block selection signal 915-b can be less than the threshold voltage of the transistor 910, and the voltage difference between the second level selection signal 925-d and the second block selection signal 915-c can be greater than the threshold voltage of the transistor 905-c, such that the transistor 905-c can be turned on and the transistor 910 can be turned off. Thus, the first block selection signal 915-b can be uncoupled from the word line board signal 930-b, and the word line board signal 930-b can transition to the voltage of the lower voltage supply 920 through the transistor 905-c. Additionally or alternatively, the first block selection signal 915-b can transition to a deselected voltage (e.g., low voltage) to set the word line board signal 930-b in an inactive state.

[0156] Accordingly, the word line decoding circuitry for driving word line boards of a memory array may include a set of word line drivers 900-a, each including two n-type transistors 905, a set of word line drivers 900-b, each including an n-type transistor 905 and a p-type transistor 910, or both. Each word line driver 900 may activate one or more corresponding word line boards by applying a voltage (e.g., an activation bias, e.g., a word line board signal 930 having an activation voltage) to the one or more corresponding word line boards based on a block select and a level select signal applied to the word line driver 900.

[0157] The size (e.g., transistor width) of each word line driver 900 may be associated with the corresponding drive strength of the word line driver 900 (e.g., for driving a word line board). Accordingly, the size of the word line driver 900 may be based on the amount of current and voltage that the driver 900 can apply to a corresponding word line board, which may be based on the size and electrical quality (e.g., capacitance) of the word line board. For example, if the capacitance or resistivity of a word line board increases, then the drive capability of the associated word line driver 900 may be increased to drive the word line board, which may result in an increased area (e.g., width) of the word line driver 900. In some instances, the width of the word line driver 900 may be based on the type of transistor of the word line driver 900. For example, the width of the n-type transistor 905 may be the same as or different from the width of the p-type transistor 910 used to drive the corresponding word line board.

[0158] Figure 10 FIG. 1000 is a block diagram showing a memory device 1020 supporting a decoding architecture for memory blocks as disclosed herein. The memory device 1020 may be an example of aspects of the memory device described with reference Figure 1 to FIGS. 1-9. The memory device 1020 or its various components may be examples of components for performing aspects of the decoding architecture for memory blocks described herein. For example, the memory device 1020 may include a word line decoding component 1025, a first pillar decoding component 1030, a second pillar decoding component 1035, a first pillar row decoding component 1040, a first pillar column decoding component 1045, a second pillar row decoding component 1050, a second pillar column decoding component 1055, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0159] The word line decoding component 1025 can be configured or otherwise support components for applying a first voltage to a first word line board of a first word line block associated with a first pillar block using a first decoding circuitry, the first word line board including a set of first word lines each coupled to one or more corresponding memory cells of a set of first memory cells, where the first pillar block includes a set of first pillars each coupled to one or more corresponding first memory cells of the set of first memory cells. In some instances, the word line decoding component 1025 can be further configured or otherwise support components for applying a second voltage to a second word line board of a second word line block associated with a second pillar block using the first decoding circuitry, the second word line board including a set of second word lines each coupled to one or more corresponding memory cells of a set of second memory cells, where the second pillar block includes a set of second pillars each coupled to one or more corresponding second memory cells of the set of second memory cells.

[0160] The first pillar decoding component 1030 can be configured or otherwise support components for applying a third voltage to a first pillar of the set of first pillars included in the first pillar block using a second decoding circuitry associated with the first pillar block, the first pillar being coupled to a first memory cell of the set of first memory cells, where the first memory cell is operable to be accessed based on applying the first voltage to the first word line board and applying the third voltage to the first pillar. The second pillar decoding component 1035 can be configured or otherwise support components for applying a fourth voltage to a second pillar of the set of second pillars included in the second pillar block using a third decoding circuitry, the second pillar being coupled to a second memory cell of the set of second memory cells, where the second memory cell is operable to be accessed based on applying the second voltage to the second word line board and applying the fourth voltage to the second pillar.

[0161] In some instances, the first decoding circuitry can be located below the set of first memory cells and the set of second memory cells, and the first decoding circuitry can be aligned with corresponding edges of the first pillar block and corresponding edges of the second pillar block.

[0162] In some instances, the third word line block associated with the first pillar block may include a third word line plate including a set of third word lines that are in the same plane as the set of first word lines, and each of the plurality of third word lines is coupled to one or more corresponding memory cells of a plurality of third memory cells each coupled to a respective first pillar of the first pillar block. The word line decoding component 1025 may be further configured or otherwise support components for concurrently applying the first voltage to the first word line plate and the third word line plate using the first decoding circuitry, wherein the first word line plate and the third word line plate share a word line driver included in or coupled to the first decoding circuitry.

[0163] In some instances, the fourth word line plate associated with the first pillar block may be addressable independently of the first word line plate and include a set of fourth word lines that are in the same plane as the set of first word lines, and each of the plurality of fourth word lines is coupled to one or more corresponding memory cells of a plurality of fourth memory cells each coupled to a respective first pillar of the first pillar block, wherein each fourth word line is positioned between a pair of corresponding first word lines. The word line decoding component 1025 may be further configured or otherwise support components for applying the first voltage to the fourth word line plate independently of the first word line plate using the first decoding circuitry, wherein the first word line plate and the fourth word line plate are coupled to different word line decoders of the first decoding circuitry.

[0164] In some instances, the first word line block may include a set of first word line plates stacked in a vertical direction and including the first word line plate, wherein each first word line extends in a horizontal direction and each first pillar extends in the vertical direction. The word line decoding component 1025 may be further configured or otherwise support components for applying the first voltage to one of the set of first word line plates for a corresponding access operation.

[0165] In some instances, the second decoding circuitry may include a first pillar decoder and a second pillar decoder, and the first pillar row decoding component 1040 may be configured to or otherwise support components for applying the third voltage to a pillar row line associated with the first pillar using the first pillar decoder. In some instances, the second decoding circuitry includes a first pillar decoder and a second pillar decoder, and the first pillar column decoding component 1045 may be configured to or otherwise support components for applying the fifth voltage to a pillar column line associated with the first pillar using the second pillar decoder, wherein a pillar selector for the first pillar is operable to couple the first pillar to the pillar row line based on applying the fifth voltage to the pillar column line, and wherein applying the third voltage to the first pillar is based on coupling the first pillar to the pillar row line.

[0166] In some instances, the third decoding circuitry may include a third pillar decoder and a fourth pillar decoder, and the second pillar row decoding component 1050 may be configured to or otherwise support components for applying the fourth voltage to a pillar row line associated with the second pillar using the third pillar decoder. In some instances, the third decoding circuitry includes a third pillar decoder and a fourth pillar decoder, and the second pillar column decoding component 1055 may be configured to or otherwise support components for applying the fifth voltage to a pillar column line associated with the second pillar using the fourth pillar decoder, wherein a pillar selector for the second pillar is operable to couple the second pillar to the pillar row line based on applying the fifth voltage to the pillar column line, and wherein applying the fourth voltage to the second pillar is based on coupling the second pillar to the pillar row line.

[0167] Figure 11 FIG. 1100 is a flow chart illustrating a method 1100 for supporting a decoding architecture for a memory bank according to an example as disclosed herein. Operations of method 1100 may be implemented by a memory device or components thereof as described herein. For example, operations of method 1100 may be performed by a memory device as described with reference to Figures 1 to 10 In some instances, the memory device may execute a set of instructions to control functional elements of the device to perform the described functions. Additionally or alternatively, the memory device may perform aspects of the described functions using dedicated hardware.

[0168] At 1105, the method may include applying a first voltage to a first word line plate of a first word line block associated with a first pillar block using a first decoding circuitry, the first word line plate including a set of first word lines each coupled to one or more respective memory cells of a set of first memory cells, wherein the first pillar block includes a set of first pillars each coupled to one or more respective first memory cells of the set of first memory cells. The operation of 1105 may be performed according to the examples disclosed herein. In some examples, aspects of the operation of 1105 may be performed by a word line decoding component 1025 as described with reference to Figure 10 as described.

[0169] At 1110, the method may include applying a second voltage to a second word line plate of a second word line block associated with a second pillar block using the first decoding circuitry, the second word line plate including a set of second word lines each coupled to one or more respective memory cells of a set of second memory cells, wherein the second pillar block includes a set of second pillars each coupled to one or more respective second memory cells of the set of second memory cells. The operation of 1110 may be performed according to the examples disclosed herein. In some examples, aspects of the operation of 1110 may be performed by a word line decoding component 1025 as described with reference to Figure 10 as described.

[0170] At 1115, the method may include applying a third voltage to a first pillar of the set of first pillars included in the first pillar block using a second decoding circuitry associated with the first pillar block, the first pillar being coupled to a first memory cell of the set of first memory cells, wherein the first memory cell is operable to be accessed based on applying the first voltage to the first word line plate and applying the third voltage to the first pillar. The operation of 1115 may be performed according to the examples disclosed herein. In some examples, aspects of the operation of 1115 may be performed by a first pillar decoding component 1030 as described with reference to Figure 10 as described.

[0171] At 1120, the method may include applying a fourth voltage to a second pillar of the set of second pillars included in the second pillar block using a third decoding circuitry, the second pillar being coupled to a second memory cell of the set of second memory cells, wherein the second memory cell is operable to be accessed based on applying the second voltage to the second word line plate and applying the fourth voltage to the second pillar. The operation of 1120 may be performed according to the examples disclosed herein. In some examples, aspects of the operation of 1120 may be performed by a second pillar decoding component 1035 as described with reference to Figure 10 as described.

[0172] In some instances, a device as described herein may execute one or more methods, such as method 1100. The device may include operations, features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: applying a first voltage to a first word line plate of a first word line block associated with a first pillar block using a first decoding circuitry, the first word line plate including a set of first word lines each coupled to one or more respective memory cells of a set of first memory cells, wherein the first pillar block includes a set of first pillars each coupled to one or more respective first memory cells of the set of first memory cells. The device may further include operations, features, circuitry, logic, components, or instructions for: applying a second voltage to a second word line plate of a second word line block associated with a second pillar block using the first decoding circuitry, the second word line plate including a set of second word lines each coupled to one or more respective memory cells of a set of second memory cells, wherein the second pillar block includes a set of second pillars each coupled to one or more respective second memory cells of the set of second memory cells. The device may further include operations, features, circuitry, logic, components, or instructions for: applying a third voltage to a first pillar of the set of first pillars included in the first pillar block using a second decoding circuitry associated with the first pillar block, the first pillar being coupled to a first memory cell of the set of first memory cells, wherein the first memory cell is operable to be accessed based on applying the first voltage to the first word line plate and applying the third voltage to the first pillar. The device may further include operations, features, circuitry, logic, components, or instructions for: applying a fourth voltage to a second pillar of the set of second pillars included in the second pillar block using a third decoding circuitry, the second pillar being coupled to a second memory cell of the set of second memory cells, wherein the second memory cell is operable to be accessed based on applying the second voltage to the second word line plate and applying the fourth voltage to the second pillar.

[0173] In some instances of method 1100 and the device described herein, the first decoding circuitry may be located below the set of first memory cells and the set of second memory cells, and the first decoding circuitry may be aligned with respective edges of the first pillar block and the second pillar block.

[0174] In some examples of the method 1100 and apparatus described herein, the third word line block associated with the first pillar block may include a third word line plate including a set of third word lines in the same plane as the set of first word lines, each of the plurality of third word lines being coupled to one or more respective memory cells of a plurality of third memory cells each coupled to a respective first pillar of the first pillar block. The method, apparatus, and non-transitory computer-readable medium may further include operations, features, circuitry, logic, components, or instructions for: concurrently applying the first voltage to the first word line plate and the third word line plate using the first decoding circuitry, wherein the first word line plate and the third word line plate share a word line driver included in or coupled to the first decoding circuitry.

[0175] In some examples of the method 1100 and apparatus described herein, the fourth word line plate associated with the first pillar block may be addressable independently of the first word line plate and include a set of fourth word lines in the same plane as the set of first word lines, each of the plurality of fourth word lines being coupled to one or more respective memory cells of a plurality of fourth memory cells each coupled to a respective first pillar of the first pillar block, wherein each fourth word line is positioned between a pair of corresponding first word lines. The method, apparatus, and non-transitory computer-readable medium may further include operations, features, circuitry, logic, components, or instructions for: applying the first voltage to the fourth word line plate independently of the first word line plate using the first decoding circuitry, wherein the first word line plate and the fourth word line plate may be coupled to different word line decoders of the first decoding circuitry.

[0176] In some examples of the method 1100 and apparatus described herein, the first word line block may include a set of first word line plates stacked in a vertical direction and including the first word line plate, wherein each first word line extends in a horizontal direction and each first pillar extends in the vertical direction. The method, apparatus, and non-transitory computer-readable medium may further include operations, features, circuitry, logic, components, or instructions for: applying the first voltage to one of the set of first word line plates for a respective access operation.

[0177] In some examples of the method 1100 and apparatus described herein, the second decoding circuitry may include a first pillar decoder and a second pillar decoder. The method, apparatus, and non-transitory computer-readable medium may further include operations, features, circuitry, logic, components, or instructions for: applying the third voltage to a pillar row line associated with the first pillar using the first pillar decoder and applying the fifth voltage to a pillar column line associated with the first pillar using the second pillar decoder, wherein a pillar selector for the first pillar is operable to couple the first pillar to the pillar row line based on applying the fifth voltage to the pillar column line, and wherein applying the third voltage to the first pillar is based on coupling the first pillar to the pillar row line.

[0178] In some examples of the method 1100 and apparatus described herein, the third decoding circuitry may include a third pillar decoder and a fourth pillar decoder. The method, apparatus, and non-transitory computer-readable medium may further include operations, features, circuitry, logic, components, or instructions for: applying the fourth voltage to a pillar row line associated with the second pillar using the third pillar decoder and applying the fifth voltage to a pillar column line associated with the second pillar using the fourth pillar decoder, wherein a pillar selector for the second pillar is operable to couple the second pillar to the pillar row line based on applying the fifth voltage to the pillar column line, and wherein applying the fourth voltage to the second pillar is based on coupling the second pillar to the pillar row line.

[0179] Note that the method descriptions herein describe possible implementations, and the operations and steps may be rearranged or otherwise modified and other implementations are possible. Additionally, portions from two or more methods may be combined.

[0180] Describe a device. The device may include a first word line block including a first word line board including a set of first word lines, each word line of the set of first word lines being coupled to one or more corresponding memory cells of a set of first memory cells. The device may further include a first pillar block including a set of first pillars associated with the first word line block, each first pillar being coupled to one or more corresponding first memory cells of the set of first memory cells. The device may further include a second word line block including a second word line board including a set of second word lines, each word line of the set of second word lines being coupled to one or more corresponding memory cells of a set of second memory cells. The device may further include a second pillar block different from the first pillar block, the second pillar block including a set of second pillars each associated with the second word line block and each coupled to one or more corresponding second memory cells of the set of second memory cells. The device may further include a first decoding circuitry associated with the first pillar block and the second pillar block, the first decoding circuitry being operable to activate the set of first word lines included in the first word line board associated with the first pillar block and the set of second word lines included in the second word line board associated with the second pillar block.

[0181] In some examples, the first decoding circuitry may be located below the set of first memory cells and the set of second memory cells (e.g., between a substrate and the set of first memory cells and the set of second memory cells) and may be aligned with corresponding edges of the first pillar block and the second pillar block.

[0182] In some examples, the device may include a third word line block including a third word line board including a set of third word lines in the same plane as the set of first word lines, each word line of the set of third word lines being coupled to one or more corresponding memory cells of a set of third memory cells each of which may be coupled to a corresponding first pillar of the first pillar block. The first decoding circuitry may further be operable to: concurrently activate the set of first word lines of the first word line board and the set of third word lines of the third word line board.

[0183] In some examples, the first decoding circuitry may include or be coupled to a word line driver, the word line driver being coupled to the first word line board and the third word line board.

[0184] In some instances, the device may include a fourth word line plate that may be addressed independently of the first word line plate and includes a set of fourth word lines in the same plane as the set of first word lines, each word line of the set of fourth word lines being coupled to one or more respective memory cells of a set of fourth memory cells that may each be coupled to a respective first post of the first post block, wherein each fourth word line may be positioned between a pair of corresponding first word lines.

[0185] In some instances, the first word line block includes a set of first word line plates stacked in a vertical direction (e.g., orthogonal to the substrate) and including the first word line plate, each first word line extending in a horizontal direction (e.g., parallel to the substrate) and each first post extending in the vertical direction.

[0186] In some instances, the first decoding circuitry may be operable to activate one of the set of first word line plates for a respective access operation (e.g., an operation to access one or more memory cells coupled to the one activated first word line plate).

[0187] In some instances, the device may include second decoding circuitry associated with the first post block and operable to activate one or more first posts of the set of first posts. The second decoding circuitry may include two first subsets oriented in a first direction and closer to opposite edges of the first post block. The second decoding circuitry may further include a second subset oriented in a second direction.

[0188] In some instances, the two first subsets may be operable to activate access lines that each extend in the second direction and are each coupled to a post selector for a respective column of first posts. The second subset may be operable to activate access lines that each extend in the first direction and are each coupled to a post selector for a respective row of first posts.

[0189] In some instances, the device may include second decoding circuitry, wherein at least a subset of the second decoding circuitry may be associated with the first post block and the second post block. At least the subset of the second decoding circuitry may be operable to activate one or more first posts of the set of first posts and one or more second posts of the set of second posts.

[0190] In some instances, the device may include a second decoding circuitry associated with the first pillar block and operable to activate one or more of the first pillars of the set of first pillars, the second decoding circuitry including a first pillar decoder and a second pillar decoder. The device may further include: a set of pillar column lines, each associated with a respective column of the first pillars and operable to be activated by the first pillar decoder; a set of pillar row lines, each associated with a respective row of the first pillars and operable to be activated by the second pillar decoder; and a set of pillar selectors. Each pillar selector is operable to be activated by a respective pillar column line to couple the respective first pillar of the set of first pillars to a respective pillar row line of the set of pillar row lines.

[0191] In some instances, the device may include a set of sense amplifiers positioned below the set of first memory cells and associated with the first pillar block. The set of sense amplifiers is operable to read one or more respective logic values from one or more of the set of first memory cells. In some instances, the number of the set of sense amplifiers may be equal to the number of the set of pillar row lines.

[0192] In some instances, one or both of the first pillar block and the second pillar block may have a first length in a first direction and a second length different from the first length in a second direction.

[0193] In some instances, the first decoding circuitry may include a set of word line drivers, each of the set of word line drivers including at least a respective n-type transistor and a respective p-type transistor.

[0194] In some instances, the first decoding circuitry may include a set of word line drivers, each of the set of word line drivers including two or more respective n-type transistors.

[0195] Describe another device. The device may include a first word line block including a first word line plate including a set of first word lines, each word line in the set of first word lines being coupled to one or more corresponding memory cells in a set of first memory cells. The device may further include a first pillar block including a set of first pillars associated with the first word line block and each coupled to one or more corresponding first memory cells in the set of first memory cells. The device may further include a second word line block including a second word line plate including a set of second word lines, each word line in the set of second word lines being coupled to one or more corresponding memory cells in a set of second memory cells. The device may further include a second pillar block including a set of second pillars associated with the second word line block and each coupled to one or more corresponding second memory cells in the set of second memory cells. The device may further include: a first decoding circuitry associated with the first word line block and the second word line block; a second decoding circuitry associated with the first pillar block; and a third decoding circuitry associated with the second pillar block. The device may further include a controller operable to cause the device to apply a first voltage to the first word line plate using the first decoding circuitry. The controller may further be operable to cause the device to apply a second voltage to the second word line plate using the first decoding circuitry. The controller may further be operable to cause the device to apply a third voltage to a first pillar in the set of first pillars included in the first pillar block, the first pillar being coupled to a first memory cell in the set of first memory cells, wherein the first memory cell is operable to be accessed based on applying the first voltage to the first word line plate and applying the third voltage to the first pillar. The controller may further be operable to cause the device to apply a fourth voltage to a second pillar in the set of second pillars included in the second pillar block, the second pillar being coupled to a second memory cell in the set of second memory cells, wherein the second memory cell is operable to be accessed based on applying the second voltage to the second word line plate and applying the fourth voltage to the second pillar.

[0196] In some examples, the first decoding circuitry may be located below the set of first memory cells and the set of second memory cells (e.g., between a substrate and the set of first memory cells and the set of second memory cells), and the first decoding circuitry may be aligned with corresponding edges of the first pillar block and the second pillar block.

[0197] In some instances, the device may include a third word line block that includes a third word line plate including a set of third word lines that are in the same plane as the set of first word lines, where each third word line in the set of third word lines is coupled to one or more respective memory cells in a set of third memory cells each coupled to a respective first pillar of the first pillar block. In some instances, the controller may further be operable to cause the device to concurrently apply the first voltage to the first word line plate and the third word line plate using the first decoding circuitry, where the first word line plate and the third word line plate may share a word line driver included in or coupled to the first decoding circuitry.

[0198] In some instances, the device may include a fourth word line plate that is independently addressable from the first word line plate and includes a set of fourth word lines that are in the same plane as the set of first word lines, where each word line in the set of fourth word lines is coupled to one or more respective memory cells in a set of fourth memory cells each coupled to a respective first pillar of the first pillar block, and where each fourth word line may be positioned between a pair of corresponding first word lines. In some instances, the controller may further be operable to apply the first voltage to the fourth word line plate independently of the first word line plate using the first decoding circuitry, where the first word line plate and the fourth word line plate may be coupled to different word line decoders of the first decoding circuitry.

[0199] In some instances, the first word line block may include a set of first word line plates stacked in a vertical direction (e.g., orthogonal to the substrate) and including the first word line plate, where each first word line extends in a horizontal direction (e.g., parallel to the substrate) and each first pillar extends in the vertical direction. In some instances, the controller may further be operable to apply the first voltage to one of the set of first word line plates for a respective access operation (e.g., an operation to access one or more memory cells coupled to the first word line plate to which the first voltage is applied).

[0200] In some instances, the second decoding circuitry may include a first pillar decoder and a second pillar decoder. The controller may further be operable to cause the device to: apply the third voltage to a pillar row line associated with the first pillar using the first pillar decoder; and apply a fifth voltage to a pillar column line associated with the first pillar using the second pillar decoder, where a pillar selector for the first pillar is operable to couple the first pillar to the pillar row line based on applying the fifth voltage to the pillar column line, and where applying the third voltage to the first pillar is based on coupling the first pillar to the pillar row line.

[0201] In some examples, the third decoding circuitry may include a third pillar decoder and a fourth pillar decoder. The controller may further be operable to cause the device to: apply the fourth voltage to a pillar row line associated with the second pillar using the third pillar decoder; and apply a fifth voltage to a pillar column line associated with the second pillar using the fourth pillar decoder, wherein a pillar selector for the second pillar is operable to couple the second pillar to the pillar row line based on applying the fifth voltage to the pillar column line, and wherein applying the fourth voltage to the second pillar is based on coupling the second pillar to the pillar row line.

[0202] Describe another device. The device may include a first word line block including a set of first word line plates stacked in a vertical direction, each first word line plate of the set of first word line plates including a set of corresponding first word lines respectively coupled to one or more corresponding memory cells of a set of first memory cells. The device may further include a second word line block including a set of second word line plates stacked in the vertical direction, each second word line plate of the set of second word line plates including a set of corresponding second word lines respectively coupled to one or more corresponding memory cells of a set of second memory cells, wherein each second word line plate is positioned in the same plane as a corresponding first word line plate. The device may further include a first pillar block including a set of first pillars associated with the first word line block and the second word line block, each first pillar coupled to a corresponding subset of first memory cells within the set of first memory cells or a corresponding subset of second memory cells within the set of second memory cells. The device may further include a third word line block including a set of third word line plates stacked in the vertical direction, each third word line plate of the set of third word line plates including a set of corresponding third word lines respectively coupled to one or more corresponding memory cells of a set of third memory cells, wherein each third word line plate is positioned in the same plane as a corresponding first word line plate. The device may further include a second pillar block including a set of second pillars associated with the third word line block, each second pillar coupled to a corresponding subset of third memory cells of the set of third memory cells. The device may further include a first decoding circuit system associated with the first pillar block and the second pillar block, the first decoding circuit system positioned below the set of first memory cells, the set of second memory cells, and the set of third memory cells (e.g., between a substrate and the set of first memory cells, the set of second memory cells, and the set of third memory cells). The first decoding circuit system may be operable to activate the first word line plates of the set of first word line plates, the second word line plates of the set of second word line plates, and the third word line plates of the set of third word line plates, and the first decoding circuit system may be aligned with corresponding edges of the first pillar block and the second pillar block.

[0203] In some instances, the first decoding circuit system may further be operable to: concurrently activate the set of corresponding first word lines of the first word line plates and the set of corresponding second word lines of the second word line plates, wherein the first word line plates and the second word line plates share word line drivers included in or coupled to the first decoding circuit system.

[0204] In some instances, the device may include a set of fourth word line plates, which may be addressed independently of the set of first word line plates and each located in the same plane as a corresponding first word line plate. Each fourth word line plate may include a set of corresponding fourth word lines each coupled to one or more corresponding memory cells in a set of fourth memory cells each coupled to a corresponding first post of the first post blocks, wherein each fourth word line may be located between a pair of corresponding first word lines.

[0205] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some figures may illustrate the signal as a single signal; however, the signal may represent a signal bus, where the bus may have a variety of bit widths.

[0206] The terms "electronically communicate", "conductive contact", "connected", and "coupled" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be electronically communicating with each other (or in conductive contact with each other or connected to each other or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components that are electronically communicating with each other (or in conductive contact with each other or connected to each other or coupled to each other) may be open or closed based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components (such as switches, transistors, or other components). In some instances, the flow of signals between the connected components may be interrupted, for example, using one or more intermediate components (such as switches or transistors) over a period of time.

[0207] The term "couple" refers to a state of moving from an open relationship between components (where signals cannot currently pass between the components through a conductive path) to a closed relationship between components (where signals can pass between the components through a conductive path). When a component, such as a controller, couples other components together, the component causes a change that allows signals to flow between the other components through a conductive path that previously did not allow signal flow.

[0208] The term "isolate" refers to a relationship between components where signals cannot currently flow between the components. Components are isolated from each other if there is an open circuit between them. For example, when a switch is open, two components separated by the switch located between them are isolated from each other. When a controller isolates two components, the controller brings about a change that prevents signals from flowing between the components using a conductive path that previously permitted signal flow.

[0209] As used herein, the term "layer" or "stratum" refers to a layer or sheet of a geometric structure (e.g., relative to a substrate). Each layer or stratum can have three dimensions (e.g., height, width, and depth) and can cover at least a portion of a surface. For example, a layer or stratum can be a three-dimensional structure in which two dimensions are greater than the third dimension, such as a thin film. A layer or stratum can include different elements, components, and / or materials. In some instances, a layer or stratum can be composed of two or more sub-layers or sub-strata.

[0210] As used herein, the term "electrode" can refer to an electrical conductor and, in some instances, can be used as an electrical contact to a memory cell or other components of a memory array. An electrode can include a trace, wire, conductive line, conductive layer, or the like that provides a conductive path between elements or components of a memory array.

[0211] The devices discussed herein, including memory arrays, can be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In some other instances, the substrate can be a silicon-on-insulator (SOI) substrate such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate can be controlled by doping using various chemical species including (but not limited to) phosphorus, boron, or arsenic. Doping can be performed by ion implantation or by any other doping method during the initial formation or growth of the substrate.

[0212] The switching components or transistors discussed herein can represent field-effect transistors (FETs) and include three-terminal devices comprising a source, a drain, and a gate. The terminals can be connected to other electronic components by a conductive material such as metal. The source and drain can be conductive and can include heavily doped (e.g., degenerate) semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET can be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET can be referred to as a p-type FET. The channel can be covered by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor can be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor can be "turned off" or "deactivated".

[0213] The description set forth herein, in combination with the accompanying drawings, describes example configurations and does not represent all examples that may be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and not "preferred" or "better than other examples". The detailed description includes specific details for providing an understanding of the described techniques. However, the techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0214] In the drawings, like components or features may have the same reference label. Additionally, various components of the same type may be distinguished by following the reference label with a hyphen and a second label that differentiates among the like components. If only the first reference label is used in the specification, the description applies to any one of the like components having the same first reference label, regardless of the second reference label.

[0215] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on a computer-readable medium as one or more instructions or code or transmitted via a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions may also be physically located in various positions, including being distributed such that portions of the functions are implemented at different physical locations.

[0216] For example, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or executed with a general-purpose processor, a DSP, an ASIC, an FPGA, or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0217] As used herein, including the content in the claims, the "or" used in a list of items (e.g., a list of items beginning with phrases such as "at least one of..." or "one or more of...") indicates an inclusive list, such that (e.g.) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" should not be construed as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0218] Computer-readable media includes both non-transitory computer storage media and communication media, where communication media includes any media that facilitates transfer of a computer program from one place to another. The non-transitory storage media can be any available media that can be accessed by a general or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD) ROM or other optical disc storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory media that can be used to carry or store the desired program code components in the form of instructions or data structures and that can be accessed by a general or special purpose computer or a general or special purpose processor. Also, any connection is properly termed a computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (such as infrared, radio, and microwave), then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (such as infrared, radio, and microwave) is included in the definition of the media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks typically reproduce data magnetically, while discs reproduce data optically with a laser. Combinations of these are also included within the scope of computer-readable media.

[0219] The description provided herein enables a person of ordinary skill in the art to make or use the present disclosure. Those of ordinary skill in the art will appreciate various modifications to the present disclosure, and without departing from the scope of the present disclosure, the general principles defined herein can be applied to other variations. Thus, the present disclosure is not limited to the examples and designs described herein, but should be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device, comprising: A first word line slice block, which includes a first word line board including a plurality of first word lines, and each of the plurality of first word lines is coupled to one or more corresponding memory cells among a plurality of first memory cells; A first pillar slice block, which includes a plurality of first pillars associated with the first word line slice block, and each first pillar is coupled to one or more corresponding first memory cells among the plurality of first memory cells; A second word line slice block, which includes a second word line board including a plurality of second word lines, and each of the plurality of second word lines is coupled to one or more corresponding memory cells among a plurality of second memory cells; A second pillar slice block, which is different from the first pillar slice block, and the second pillar slice block includes a plurality of second pillars respectively associated with the second word line slice block and respectively coupled to one or more corresponding second memory cells among the plurality of second memory cells; and A first decoding circuit system, which is associated with the first pillar slice block and the second pillar slice block, and the first decoding circuit system is operable to activate the plurality of first word lines included in the first word line board associated with the first pillar slice block and the plurality of second word lines included in the second word line board associated with the second pillar slice block.

2. The memory device according to claim 1, wherein the first decoding circuitry is positioned below the plurality of first memory cells and the plurality of second memory cells and is aligned with corresponding edges of the first pillar block and the second pillar block.

3. The memory device according to claim 1, further comprising: A third word line slice block, which includes a third word line board including a plurality of third word lines in the same plane as the plurality of first word lines, and each of the plurality of third word lines is coupled to one or more corresponding memory cells among a plurality of third memory cells respectively coupled to corresponding first pillars of the first pillar slice block, wherein the first decoding circuit system is further operable to: Concurrently activate the plurality of first word lines of the first word line board and the plurality of third word lines of the third word line board.

4. The memory device according to claim 3, wherein the first decoding circuitry includes or is coupled to a word line driver, and the word line driver is coupled to the first word line board and the third word line board.

5. The memory device according to claim 1, further comprising: A fourth word line board, which is addressable independently of the first word line board and includes a plurality of fourth word lines in the same plane as the plurality of first word lines, and each of the plurality of fourth word lines is coupled to one or more corresponding memory cells among a plurality of fourth memory cells respectively coupled to corresponding first pillars of the first pillar slice block, wherein each fourth word line is positioned between a pair of corresponding first word lines.

6. The memory device according to claim 1, wherein the first word line block includes a plurality of first word line boards stacked in a vertical direction and including the first word line board, and wherein each first word line extends in a horizontal direction and each first pillar extends in the vertical direction.

7. The memory device according to claim 6, wherein the first decoding circuitry is operable to activate one of the plurality of first word line boards for a corresponding access operation.

8. The memory device according to claim 1, further comprising: A second decoding circuit system, which is associated with the first pillar slice block and is operable to activate one or more first pillars among the plurality of first pillars, and the second decoding circuit system includes: Two first subsets, which are oriented in a first direction and are closer to opposite corresponding edges of the first pillar slice block; and A second subset, which is oriented in a second direction.

9. The memory device according to claim 8, wherein: The two first subsets are operable to activate access lines respectively extending in the second direction and respectively coupled to pillar selectors for corresponding columns of the first pillars; and The second subset is operable to activate access lines respectively extending in the first direction and respectively coupled to pillar selectors for corresponding rows of the first pillars.

10. The memory device according to claim 1, further comprising: A second decoding circuitry system, wherein at least a subset of the second decoding circuitry system is associated with the first pillar block and the second pillar block, and wherein at least the subset of the second decoding circuitry system is operable to activate one or more of the plurality of first pillars and one or more of the plurality of second pillars.

11. The memory device according to claim 1, further comprising: A second decoding circuitry system, which is associated with the first pillar block and is operable to activate one or more of the plurality of first pillars, the second decoding circuitry system including a first pillar decoder and a second pillar decoder; A plurality of pillar column lines, each of which is associated with a corresponding column of the first pillar and is operable to be activated by the first pillar decoder; A plurality of pillar row lines, each of which is associated with a corresponding row of the first pillar and is operable to be activated by the second pillar decoder; And A plurality of pillar selectors, each pillar selector being operable to be activated by a corresponding pillar column line to couple a corresponding first pillar of the plurality of first pillars to a corresponding pillar row line of the plurality of pillar row lines.

12. The memory device according to claim 11, further comprising: A plurality of sense amplifiers, which are positioned below the plurality of first memory cells and are associated with the first pillar block, the plurality of sense amplifiers being operable to read one or more corresponding logic values from one or more of the plurality of first memory cells, wherein the number of the plurality of sense amplifiers is equal to the number of the plurality of pillar row lines.

13. The memory device according to claim 1, wherein the first pillar block and the second pillar block have a first length in a first direction and a second length different from the first length in a second direction.

14. The memory device according to claim 1, wherein the first decoding circuit system includes a plurality of word line drivers, and each of the plurality of word line drivers includes a corresponding n-type transistor and a corresponding p-type transistor.

15. The memory device according to claim 1, wherein the first decoding circuit system includes a plurality of word line drivers, and each of the plurality of word line drivers includes two or more corresponding n-type transistors.

16. A memory device, comprising: A first word line block, which includes a first word line board including a plurality of first word lines, each of the plurality of first word lines being coupled to one or more corresponding memory cells of the plurality of first memory cells; A first pillar block, which includes a plurality of first pillars associated with the first word line block and each being coupled to one or more corresponding first memory cells of the plurality of first memory cells; A second word line block, which includes a second word line board including a plurality of second word lines, each of the plurality of second word lines being coupled to one or more corresponding memory cells of the plurality of second memory cells; A second pillar block, which includes a plurality of second pillars associated with the second word line block and each being coupled to one or more corresponding second memory cells of the plurality of second memory cells; A first decoding circuitry system, which is associated with the first word line block and the second word line block; A second decoding circuitry system, which is associated with the first pillar block; A third decoding circuitry system, which is associated with the second pillar block; and A controller, which is operable to cause the memory device: To apply a first voltage to the first word line board using the first decoding circuitry system; To apply a second voltage to the second word line board using the first decoding circuitry system; To apply a third voltage to a first pillar of the plurality of first pillars included in the first pillar block, the first pillar being coupled to a first memory cell of the plurality of first memory cells, wherein the first memory cell is operable to be accessed at least in part based on applying the first voltage to the first word line board and applying the third voltage to the first pillar; And Apply a fourth voltage to a second one of the plurality of second pillars included in the second pillar stack using the third decoding circuit system, the second pillar being coupled to a second memory cell of the plurality of second memory cells, wherein the second memory cell is operable to access based at least in part on applying the second voltage to the second word line board and applying the fourth voltage to the second pillar.

17. The memory device according to claim 16, wherein the first decoding circuit system is positioned below the plurality of first memory cells and the plurality of second memory cells, and wherein the first decoding circuit system is aligned with corresponding edges of the first pillar block and the second pillar block.

18. The memory device according to claim 16, further comprising: A third word line stack including a third word line board including a plurality of third word lines in a same plane as the plurality of first word lines, each third word line of the plurality of third word lines being coupled to one or more respective memory cells of a plurality of third memory cells each coupled to a respective first pillar of the first pillar stack, wherein the controller is further operable to cause the memory device to: Apply the first voltage to the first word line board and the third word line board concurrently using the first decoding circuit system, wherein the first word line board and the third word line board share a word line driver included in or coupled to the first decoding circuit system.

19. The memory device according to claim 16, further comprising: A fourth word line board addressable independently of the first word line board and including a plurality of fourth word lines in a same plane as the plurality of first word lines, each word line of the plurality of fourth word lines being coupled to one or more respective memory cells of a plurality of fourth memory cells each coupled to a respective first pillar of the first pillar stack, wherein each fourth word line is positioned between a pair of corresponding first word lines, and wherein the controller is further operable to cause the memory device to: Apply the first voltage to the fourth word line board independently of the first word line board using the first decoding circuit system, wherein the first word line board and the fourth word line board are coupled to different word line decoders of the first decoding circuit system.

20. The memory device according to claim 16, wherein the first word line block includes a plurality of first word line plates stacked in a vertical direction and including the first word line plate, wherein each first word line extends in a horizontal direction and each first pillar extends in the vertical direction, and wherein the controller is further operable to cause the memory device to: Apply the first voltage to one of the plurality of first word line plates for a corresponding access operation.

21. The memory device according to claim 16, wherein the second decoding circuitry includes a first pillar decoder and a second pillar decoder, and the controller is further operable to cause the memory device to: Apply the third voltage to a pillar row line associated with the first pillar using the first pillar decoder; and Apply a fifth voltage to a pillar column line associated with the first pillar using the second pillar decoder, wherein a pillar selector for the first pillar is operable to couple the first pillar to the pillar row line at least in part based on applying the fifth voltage to the pillar column line, and wherein applying the third voltage to the first pillar is at least in part based on coupling the first pillar to the pillar row line.

22. The memory device according to claim 16, wherein the third decoding circuitry includes a third pillar decoder and a fourth pillar decoder, and the controller is further operable to cause the memory device to: Apply the fourth voltage to a pillar row line associated with the second pillar using the third pillar decoder; and Apply a fifth voltage to a pillar column line associated with the second pillar using the fourth pillar decoder, wherein a pillar selector for the second pillar is operable to couple the second pillar to the pillar row line at least in part based on applying the fifth voltage to the pillar column line, and wherein applying the fourth voltage to the second pillar is at least in part based on coupling the second pillar to the pillar row line.

23. A memory device, comprising: A first word line stack including a plurality of first word line boards stacked in a vertical direction, each first word line board of the plurality of first word line boards including a respective plurality of first word lines each coupled to one or more respective memory cells of a plurality of first memory cells; A second word line stack including a plurality of second word line boards stacked in the vertical direction, each second word line board of the plurality of second word line boards including a respective plurality of second word lines each coupled to one or more respective memory cells of a plurality of second memory cells, wherein each second word line board is positioned in a same plane as a corresponding first word line board; A first pillar stack including a plurality of first pillars associated with the first word line stack and the second word line stack, each first pillar being coupled to a respective subset of first memory cells within the plurality of first memory cells or a respective subset of second memory cells within the plurality of second memory cells; A third word line slice block, which includes a plurality of third word line plates stacked in the vertical direction, each of the plurality of third word line plates including a corresponding plurality of third word lines respectively coupled to one or more corresponding memory cells among a plurality of third memory cells, wherein each third word line plate is located in the same plane as a corresponding first word line plate; A second pillar slice block, which includes a plurality of second pillars associated with the third word line slice block, each second pillar being coupled to a corresponding subset of the third memory cells of the plurality of third memory cells; and A first decoding circuit system, which is associated with the first pillar slice block and the second pillar slice block, the first decoding circuit system being located below the plurality of first memory cells, the plurality of second memory cells, and the plurality of third memory cells, wherein the first decoding circuit system is operable to activate a first word line plate among the plurality of first word line plates, a second word line plate among the plurality of second word line plates, and a third word line plate among the plurality of third word line plates, and wherein the first decoding circuit system is aligned with a corresponding edge of the first pillar slice block and a corresponding edge of the second pillar slice block.

24. The memory device according to claim 23, wherein the first decoding circuitry is further operable to: Concurrently activate the corresponding plurality of first word lines of the first word line board and the corresponding plurality of second word lines of the second word line board, wherein the first word line board and the second word line board share a word line driver included in or coupled to the first decoding circuitry.

25. The memory device according to claim 23, further comprising: A plurality of fourth word line plates, which are addressable independently of the plurality of first word line plates and each located in the same plane as a corresponding first word line plate, each fourth word line plate including a corresponding plurality of fourth word lines respectively coupled to one or more corresponding memory cells among a plurality of fourth memory cells respectively coupled to corresponding first pillars of the first pillar slice block, wherein each fourth word line is located between a pair of corresponding first word lines.

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