Digital integrated circuit timing monitoring method based on graph convolutional neural network

Abstract

This invention relates to the field of deep learning technology, and more particularly to a method for timing monitoring of digital integrated circuits based on graph convolutional neural networks. The method includes: determining multiple candidate monitoring nodes in a target circuit and their connection relationships; determining feature information of the target circuit based on device attribute information of the multiple candidate monitoring nodes; inputting the feature information of the target circuit and the connection relationships of the multiple candidate monitoring nodes into a trained target graph convolutional neural network model, so that the graph convolutional neural network model outputs judgment results for multiple candidate monitoring nodes; the judgment results include a first judgment result indicating that a node is a monitoring node and a second judgment result indicating that a node is not a monitoring node; determining at least one valid monitoring node from the multiple candidate monitoring nodes based on the judgment results output by the graph convolutional neural network model; and performing timing monitoring on the target circuit based on the at least one monitoring node.

Description

Technical Field

[0001] This application relates to the field of deep learning technology, and in particular to a method for timing monitoring of digital integrated circuits based on graph convolutional neural networks. Background Technology

[0002] With the continuous development of integrated circuit manufacturing processes, process dimensions are constantly shrinking, while chip integration density and operating frequencies are continuously increasing, making timing analysis and verification of chip designs increasingly important. Existing technologies often employ methods based on static timing analysis and path activation rates to select timing monitoring points. Taking static timing analysis as an example, this method obtains all critical paths by performing static timing analysis on the circuit netlist and selects the terminal triggers of a subset of the longest paths for monitoring. However, this method suffers from problems such as excessive monitoring quantity, high area power consumption cost, and long monitoring point selection time. Therefore, reducing area power consumption cost and shortening the monitoring point selection time are urgent problems to be solved. Summary of the Invention

[0003] In view of this, this application provides a digital integrated circuit timing monitoring method based on graph convolutional neural networks, which can effectively reduce the selection time of monitoring points and the power consumption of the surface base.

[0004] In a first aspect, embodiments of the present invention provide a method for timing monitoring of digital integrated circuits based on graph convolutional neural networks, comprising:

[0005] Determine multiple candidate monitoring nodes in the target circuit and the connection relationships of the multiple candidate monitoring nodes;

[0006] The characteristic information of the target circuit is determined based on the device attribute information of the multiple candidate monitoring nodes;

[0007] The feature information of the target circuit and the connection relationship of the multiple candidate monitoring nodes are input into the trained target graph convolutional neural network model, so that the graph convolutional neural network model outputs the determination results of multiple candidate monitoring nodes; the determination results include a first determination result that is a monitoring node and a second determination result that is not a monitoring node;

[0008] Based on the determination result output by the graph convolutional neural network model, at least one valid monitoring node is determined from the plurality of candidate monitoring nodes;

[0009] Timing monitoring of the target circuit is performed based on the at least one monitoring node.

[0010] In one possible implementation, determining multiple candidate monitoring nodes in the target circuit includes:

[0011] Obtain the circuit netlist data of the target circuit;

[0012] Based on the circuit netlist data, a corresponding circuit netlist diagram is generated using standard cells and ports as nodes.

[0013] The nodes in the circuit netlist diagram are identified as the candidate monitoring nodes.

[0014] In one possible implementation, the connection relationship between the candidate monitoring nodes is an adjacency matrix, and the steps for determining the connection relationship between the multiple candidate monitoring nodes include:

[0015] The connection relationships of each node are determined based on the circuit connection relationships of the target circuit;

[0016] The connection relationships of the multiple candidate monitoring nodes are determined based on the connection relationships of each node.

[0017] The adjacency matrix is ​​generated based on the connection relationships of the multiple candidate monitoring nodes.

[0018] In one possible implementation, determining the feature information of the target circuit based on the device attribute information of the plurality of candidate monitoring nodes includes:

[0019] Determine all device attribute information of the candidate monitoring node based on the process library corresponding to the target circuit;

[0020] Select at least one device attribute from the device attribute information of the candidate monitoring nodes as the target device attribute information;

[0021] The characteristic information of the target circuit is determined based on the target device attribute information corresponding to each candidate monitoring node.

[0022] In one possible implementation, the feature information of the target circuit is a feature matrix, and the step of determining the feature information of the target circuit based on the target device attribute information corresponding to each candidate monitoring node includes:

[0023] The node vector of the corresponding candidate monitoring node is determined based on the target device attribute information;

[0024] The feature matrix of the target circuit is constructed based on the node vectors of the candidate monitoring nodes.

[0025] In one possible implementation, the training process of the target graph convolutional neural network model includes:

[0026] Obtain a training dataset; the training dataset includes feature data of each node in the training circuit, connection relationships of each node, and label data of each node; wherein the label data includes: first label data of monitoring nodes, and second label data of non-monitoring nodes;

[0027] The initial graph convolutional neural network model is iteratively trained based on the training dataset so that the initial graph convolutional neural network model can learn the node features of different labeled data;

[0028] When the loss function of the initial graph convolutional neural network model is detected to meet the preset conditions, the training is determined to be complete, and the target convolutional neural network model is obtained.

[0029] In one possible implementation, the feature data is a feature matrix, the connection relationship is an adjacency matrix, and the steps for obtaining the feature data of each node and the connection relationship of each node include:

[0030] The standard cells and ports in the training circuit are used as nodes to generate the circuit netlist diagram of the training circuit.

[0031] Determine the connection relationships of each node based on the circuit netlist diagram;

[0032] The adjacency matrix of the training circuit is generated based on the connection relationship of each node, and the feature matrix of the training circuit is generated based on the device attribute information of each node.

[0033] In one possible implementation, the steps for obtaining the label data of each node include:

[0034] Static timing analysis is performed on the training circuit to obtain the critical path in the training circuit;

[0035] The training circuit is dynamically simulated to determine the effective activation path from the critical path;

[0036] Multiple valid monitoring points are determined based on the effective activation path;

[0037] The label data of the node corresponding to the effective monitoring point in the circuit netlist diagram is determined as the first label data, and the label data of the remaining nodes is determined as the second label data.

[0038] In one possible implementation, the target graph convolutional neural network model is composed of multiple stacked graph convolutional layers. The input of the first graph convolutional layer is the feature matrix of each node, the adjacency matrix of each node, and the label data of each node. The data of the other graph convolutional layers besides the first graph convolutional layer are the outputs of the previous graph convolutional layer.

[0039] The last graph convolutional layer in the plurality of graph convolutional layers is connected to the algorithm layer; the algorithm layer constructs a hypersphere based on the node data output by the last graph convolutional layer based on the target anomaly detection algorithm and calculates the Euclidean distance between each node and the center of the hypersphere;

[0040] The output of the algorithm layer is connected to the input of the classifier. The classifier determines abnormal node data from the data of each node based on the Euclidean distance corresponding to each node and the radius of the hypersphere, and removes the abnormal node data.

[0041] Secondly, embodiments of the present invention provide a digital integrated circuit timing monitoring device based on a graph convolutional neural network, comprising:

[0042] A node determination module is used to determine multiple candidate monitoring nodes in the target circuit and the connection relationships of the multiple candidate monitoring nodes.

[0043] The feature information determination module is used to determine the feature information of the target circuit based on the device attribute information of the multiple candidate monitoring nodes;

[0044] The monitoring node prediction module is used to input the feature information of the target circuit and the connection relationship of the multiple candidate monitoring nodes into the trained target graph convolutional neural network model, so that the graph convolutional neural network model outputs the determination results of multiple candidate monitoring nodes; the determination results include a first determination result that is a monitoring node and a second determination result that is not a monitoring node;

[0045] The monitoring node determination module is used to determine at least one monitoring node from the plurality of candidate monitoring nodes based on the determination result output by the graph convolutional neural network model.

[0046] A timing monitoring module is used to perform timing monitoring on the target circuit based on the at least one monitoring node.

[0047] Thirdly, embodiments of the present invention provide an electronic device, comprising:

[0048] At least one processor; and

[0049] At least one memory communicatively connected to the processor, wherein:

[0050] The memory stores program instructions that can be executed by the processor, and the processor can execute the method described in the first aspect by calling the program instructions.

[0051] Fourthly, embodiments of the present invention provide a computer-readable storage medium storing computer instructions that cause the computer to perform the method described in the first aspect.

[0052] In this embodiment of the invention, the selection of monitoring nodes is accelerated by combining a graph convolutional neural network model, which can improve the efficiency of circuit timing monitoring while ensuring accuracy. Attached Figure Description

[0053] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 A flowchart of a circuit timing monitoring method provided in an embodiment of the present invention;

[0055] Figure 2 A schematic diagram of gate-level circuit conversion provided in an embodiment of the present invention;

[0056] Figure 3 A schematic diagram of an adjacency matrix provided in an embodiment of the present invention;

[0057] Figure 4 A schematic diagram of a feature matrix provided in an embodiment of the present invention;

[0058] Figures 5-a to 5-c A schematic diagram illustrating the generation process of a circuit netlist diagram provided in an embodiment of the present invention;

[0059] Figure 6 A flowchart of a graph convolutional neural network model training method provided in an embodiment of the present invention;

[0060] Figure 7 This is a schematic diagram illustrating the principle of graph convolution operation provided in an embodiment of the present invention;

[0061] Figure 8 This is a schematic diagram of a graph convolution structure provided in an embodiment of the present invention;

[0062] Figures 9-a to 9-b A schematic diagram of another adjacency matrix provided in an embodiment of the present invention;

[0063] Figures 10-a to 10-b This is a schematic diagram illustrating the principle of an anomaly detection algorithm provided in an embodiment of the present invention;

[0064] Figure 11This is a schematic diagram of a circuit synthesis result provided in an embodiment of the present invention.

[0065] Figure 12 A schematic diagram of a timing report provided in an embodiment of the present invention;

[0066] Figure 13 A schematic diagram illustrating an activation rate statistical result provided in an embodiment of the present invention;

[0067] Figure 14 This is a training effect diagram of a graph convolutional neural network model provided in an embodiment of the present invention;

[0068] Figure 15 A schematic diagram illustrating the accuracy of a graph convolutional neural network model during inference, provided in an embodiment of the present invention;

[0069] Figure 16 This is a schematic diagram of the analysis results output by a graph convolutional neural network, provided in an embodiment of the present invention.

[0070] Figure 17 This is a schematic diagram of the structure of a circuit timing monitoring device provided in an embodiment of the present invention;

[0071] Figure 18 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0072] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0073] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0074] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0075] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0076] In this embodiment of the invention, the time required to select monitoring points is reduced by combining a graph convolutional neural network model with the selection of monitoring points. Figure 1 A flowchart of a circuit timing monitoring method provided in an embodiment of the present invention is shown below. Figure 1 As shown, the method processing steps include:

[0077] Step 101: Determine multiple candidate monitoring nodes in the target circuit and their connection relationships. The target circuit can be implemented as a digital or analog circuit. When determining candidate monitoring nodes from the target circuit, it can first be converted into a gate-level circuit.

[0078] Specifically, the netlist data of the target circuit is obtained by loading its netlist file. The netlist file is generated by Electronic Design Automation (EDA) synthesis tools. Based on the technology library files used for synthesis, the target circuit is transformed from a system-level circuit into a gate-level representation, specifying the model numbers of all standard cells and the connections between them. The file format is Verilog, and its syntax follows the requirements of the hardware description language Verilog HDL. Afterwards, the corresponding netlist diagram can be generated based on the netlist data, using standard cells and ports as nodes. Figure 2 This is a schematic diagram of a gate-level circuit conversion provided in an embodiment of the present invention. For example... Figure 2 As shown in the diagram, Figure (a) on the left is a gate-level circuit diagram. The target circuit is transformed into a gate-level circuit using appropriate tools or algorithms. The circuit netlist data corresponding to this gate-level circuit, obtained from the circuit netlist file, is the... Figure 2 As shown in Figure (b) above. Finally, the nodes in the circuit netlist diagram (i.e., all standard cells and ports) can be identified as candidate monitoring nodes.

[0079] The connection relationships of each candidate monitoring node can be expressed as an adjacency matrix. First, the connection relationships of each node in the circuit netlist are determined based on the circuit connections of the target circuit. Then, the connection relationships of multiple candidate monitoring nodes are determined based on the connection relationships of each node. Since monitoring nodes are essentially the nodes in the circuit netlist, the connection relationships of each monitoring node are the same as the connection relationships of each node in the circuit netlist. Finally, the corresponding adjacency matrix can be generated based on the connection relationships of multiple candidate monitoring nodes. Figure 2 Taking the gate-level circuit shown as an example, the adjacency matrix obtained based on the connection relationship between each standard cell and the port is as follows: Figure 3 As shown in the image. Figure 3The adjacency matrix shown is a 7×7 matrix. Blank spaces in the adjacency matrix represent values ​​of 0.

[0080] Step 102: Determine the feature information of the target circuit based on the device attribute information of multiple candidate monitoring nodes. Specifically, all device attribute information of the candidate monitoring nodes can be determined based on the technology library corresponding to the target circuit. This technology library is the technology library corresponding to the circuit netlist file mentioned above. Then, at least one device attribute can be selected from the device attribute information of the candidate monitoring nodes as the target device attribute information. Finally, the feature information of the target circuit is determined based on the target device attribute information corresponding to each candidate monitoring node. The device attribute information includes the resistance, capacitance, drive capability, functional type, and unit type of electrical components.

[0081] In a specific example, since the feature information obtained in step 102 cannot be directly input into the target graph convolutional neural network model, it needs to be converted into a data format that the target graph convolutional neural network can receive and recognize. Optionally, the feature data can be implemented in the form of a feature matrix, which allows the node vectors of the corresponding candidate monitoring nodes to be determined based on the target device data information. Then, the feature matrix of the target circuit is constructed based on the node vectors of the candidate monitoring nodes. Figure 2 Taking the gate-level circuit shown as an example, the node vector corresponding to each node is generated based on the target device attribute information of each node (standard cell and port), and the feature matrix of the target circuit is constructed based on the node vector. Figure 4 This is a method provided by the embodiments of the present invention. Figure 2 The diagram shows the characteristic matrix corresponding to the gate-level circuit. Determined through a technology library. Figure 2 The node vector for each node is determined by the device attribute information of each node (standard component and port). Then, based on the obtained node vectors, the following steps are performed: Figure 4 The 7×n characteristic matrix shown.

[0082] Step 103: Input the feature information of the target circuit and the connection relationships of multiple candidate monitoring nodes into the trained target graph convolutional neural network model, so that the graph convolutional neural network model outputs the judgment results of multiple candidate monitoring nodes; the judgment results include a first judgment result that it is a monitoring node and a second judgment result that it is not a monitoring node. The graph convolutional neural network model performs feature extraction based on the input feature information (feature matrix) and connection relationships (adjacency matrix) of the target circuit. For each node in the same convolutional layer of the graph convolutional neural network model, the feature chronology of its neighboring nodes is aggregated to calculate the features of the neighboring nodes. The feature representation of the current node is updated based on the aggregated neighboring node features and the current node's own features, thereby updating the model parameters. Finally, the target graph convolutional neural network model outputs the judgment results of each candidate monitoring node.

[0083] Step 104: Based on the judgment result output by the graph convolutional neural network model, determine at least one valid monitoring node from multiple candidate monitoring nodes. The candidate monitoring node whose judgment result is the first judgment result can be determined as the valid monitoring node.

[0084] Step 105: Perform timing monitoring on the target circuit based on at least one monitoring node. This can be achieved by inserting or replacing existing flip-flops at a determined effective monitoring node to obtain a monitoring signal. The timing of the target circuit is then monitored by analyzing the monitoring signal.

[0085] In some embodiments, to achieve rapid diagram creation, regular expression matching is used to add all circuit elements as nodes (including ports, standard cells, and nets) when creating the circuit netlist diagram. This is because it aims to capture node and connection information in a single traversal, as multiple traversals are time-consuming. After the traversal is complete, since net variables only represent electrical connections in the circuit and contain less information as nodes, and deleting them reduces the number of nodes and simplifies the diagram, only standard cells and ports are added as nodes. At the same time, nets need to be deleted while maintaining their original connections.

[0086] The specific steps for generating the circuit netlist diagram in the above steps are as follows: Figures 5-a to 5-c As shown. Figure 5-a This is a schematic diagram of a circuit netlist file provided in an embodiment of the present invention. Due to the requirements of the Verilog HDL syntax specification, circuit ports are listed at the beginning of the file. The instantiation statements of standard cells contain the electrical connections and corresponding pins of the standard cells. Therefore, specific text can be located using text traversal and regular expression matching, making it convenient to add nodes and edges based on the text. Figure 5-a As shown, the text conforms to Verilog HDL syntax and follows certain patterns, such as fixed periods and brackets. Therefore, these patterns can be easily used for regular expression matching. By traversing the target circuit's netlist file, all standard cells and ports (i.e.,...) can be identified. Figure 5-a (The area enclosed by the rectangle in the middle) uses standard units and ports as nodes, and defines the electrical connections between standard units and ports as edges to complete the node addition. The result is as follows: Figure 5-b As shown in the diagram. Deleting and reconnecting nodes after traversal can reduce graph construction time. Because... Figure 5-b The wire mesh n2950 shown serves to connect standard units U3371 and U3370. Therefore, n2950 needs to be removed to directly connect U3370 and U3371. Figure 5-bThe dotted lines in the diagram are removed to simplify the connection relationships, while U3371 and U3370 are retained. The final result is... Figure 5-c The circuit netlist diagram is shown below. The corresponding adjacency matrix can be obtained from this circuit netlist diagram.

[0087] In some embodiments, data preprocessing is required before inputting the feature information of the target circuit and the connection relationships of multiple candidate monitoring nodes into the trained target graph convolutional network to increase data reliability. Specifically, the feature information can be encoded according to the functions of all standard units and ports under the current process, and used as the initial vector of the node. Each standard unit in the process library has attributes such as logical function and driving capability. These attributes are extracted from the file and encoded as the initial vector of the node, using one-hot encoding. For example, the standard unit INVD3LVT has a driving capability of 3, a function type of 6, and a unit type of 0. Then the initial vector of this standard unit is (3,6,0), and the encoded result is: node U3365 embedding. The standard unit IOA21D1LVT has a driving capability of 1, a function type of 28, and a unit type of 0. Then the initial vector of this standard unit is (1,28,0), and the encoded result is: node U3368 embedding.

[0088] At this point, the node identifiers are vectors, with different positions representing different attributes and varying numerical values. Therefore, they need to be normalized or otherwise standardized to control the data scale within a reasonable range. Optionally, this can be achieved using a formula... Normalization is then performed. Based on the normalized node vectors, the feature matrix of the target circuit is obtained. The normalization process for the adjacency matrix of the target circuit is the same as that for the feature matrix, and will not be repeated here.

[0089] In this embodiment of the invention, the graph convolutional neural network model has also been improved. Figure 6 This is a flowchart illustrating a graph convolutional neural network model training method provided in an embodiment of the present invention. Figure 6 As shown, the training process of a graph convolutional neural network includes:

[0090] Step 601: Obtain the training dataset. The training dataset includes the feature data of each node in the training circuit, the connection relationships of each node, and the label data of each node. The label data includes: first label data for monitoring nodes and second label data for nodes that are not monitoring nodes. The feature data of each node can be implemented as feature vectors, and the feature matrix of the training circuit is obtained through the feature vectors of each node. The connection relationships of each node can be implemented as adjacency matrices. The feature matrix and adjacency matrix are obtained as follows: A circuit netlist diagram of the training circuit is generated using standard cells and ports in the training circuit as nodes. The connection relationships of each node are determined based on the circuit netlist diagram. The adjacency matrix of the training circuit is generated based on the connection relationships of each node, and the feature matrix of the training circuit is generated based on the device attribute information of each node. Optionally, directly using these node representations as input to the model will negatively impact the model's learning. Therefore, before inputting the feature matrix and adjacency matrix as training data into the initial graph convolutional neural network model, they need to be encoded and normalized. The specific processing steps are the same as those performed on the feature matrix and adjacency matrix of the target circuit in the above steps, and will not be repeated here.

[0091] In machine learning, the label data for each node represents the results of training samples. In this invention, the label data indicates whether each node is a monitoring node. For example, the label data for a monitoring node is 1, and the label data for a non-monitoring node is -1.

[0092] Step 602 involves iteratively training the initial graph convolutional neural network model based on the training dataset, enabling it to learn the node features of data with different labels. When training the initial graph convolutional neural network model, mainstream deep learning frameworks such as PyTorch, Caffe, and CNTK can be selected. Python facilitates data processing and model training, and a dedicated graph neural network framework can be used to quickly build the model, improving implementation efficiency.

[0093] The basic principle of graph convolution operations is to update its own information by aggregating information from neighboring nodes. Figure 7 This is a schematic diagram illustrating the principle of graph convolution operation provided in an embodiment of the present invention. For example... Figure 7 As shown, the circuit netlist graph of the input training circuit has 5 nodes, and the feature extraction is completed after two layers of graph convolution operation. Figure 8 This is a schematic diagram of a graph convolution structure provided in an embodiment of the present invention. Figure 8As shown, the graph convolutional layer (NodeConv) is based on the GATv2 model with residual connections and drop mechanism. It uses a multi-head attention mechanism to perform multiple operations on neighboring nodes during the aggregation process and calculate the average value to update the node message graph.

[0094] Let represent the set of adjacent nodes of node v, where k represents the current layer, k-1 represents the previous layer, W represents the network parameters, and α represents the attention coefficient.

[0095] A typical model has multiple graph convolutional layers, designed to enhance its expressive power. Given a graph including its node feature matrix and adjacency matrix, for each node, the graph convolutional layers obtain a hidden representation by aggregating feature information from its neighborhood. By stacking multiple layers, the final hidden representation of each node can receive information from more distant nodes, thus enabling graph convolutional neural networks to efficiently learn node representations. Residual connections, after aggregating neighboring nodes, add the new node representation to the original representation and update the node representation again. Their purpose is to prevent the vanishing gradient problem caused by excessively deep model layers and long derivative chains during parameter updates. This is because long derivative chains and the multiplication mechanism of partial derivatives can easily cause a rapid decrease in the magnitude of partial derivatives. Adding residual connections avoids this situation and also reduces model complexity, thereby reducing overfitting.

[0096] Step 603: When the loss function of the initial graph convolutional neural network model meets the preset conditions, the training is considered complete, and the target convolutional neural network model is obtained. The preset conditions can be implemented as loss function convergence. The error between the predicted result and the known result is calculated using the loss function, and optimization methods such as gradient descent are used to reduce the error, i.e., the loss function converges. If the loss function converges, it means that the model can accurately predict the monitoring nodes based on the input.

[0097] In some embodiments, the steps for acquiring label data for each node in the training circuit include: performing static timing analysis on the training circuit to obtain the critical path in the training circuit; performing dynamic simulation on the training circuit to determine the effective activation path from the critical path; then determining multiple effective monitoring points based on the effective activation path; finally, determining the label data of the node corresponding to the effective monitoring point in the circuit netlist as the first label data, and determining the label data of the remaining nodes as the second label data. The static timing analysis process is used to calculate the delay of each path in the circuit netlist and obtain the critical path; the dynamic simulation process is used to eliminate paths inactive in the critical path; by analyzing the timing report, critical paths containing input / output ports are further eliminated; and the end triggers of the remaining critical paths are selected as monitoring nodes to obtain a set of monitoring nodes. The set of monitoring points is preprocessed to obtain the aforementioned label data.

[0098] In some embodiments, data augmentation can be used to amplify the data in order to effectively utilize the sample data. Data augmentation can prevent the neural network from learning irrelevant features, thereby further improving the performance of the neural network. Specifically, new data different from the original data can be obtained by shuffling the order of the nodes and simultaneously shuffling the adjacency matrix. For example, the circuit netlist diagram of the training circuit has 5 nodes, namely nodes 1, 2, 3, 4, and 5. Their order is 1, 2, 3, 4, 5. Its adjacency matrix is ​​as follows. Figure 9-a As shown in the diagram. Then, the order of nodes 1 and 5 is swapped. The resulting adjacency matrix is ​​shown below. Figure 9-b As shown in the image.

[0099] After the training circuit is synthesized into a circuit netlist, one characteristic is that it has a large number of combinational units and a small proportion of temporal units. Since the selected temporal monitoring nodes are temporal units, data imbalance is inevitable. In practical applications, especially in classification problems, the proportion of samples with different labels in the dataset is likely to be imbalanced. In this case, predicting only the majority class can achieve fairly high accuracy, but it cannot capture the minority class. Therefore, if the algorithm is directly used for classification training, the training effect will be poor, and the model needs further optimization. Based on this, this embodiment of the invention introduces a deep semi-supervised anomaly detection (Deep SAD) algorithm to optimize the model.

[0100] Specifically, the target graph convolutional neural network model consists of multiple stacked graph convolutional layers. The input to the first graph convolutional layer is the feature matrix, adjacency matrix, and label data of each node. The data of each graph convolutional layer other than the first graph convolutional layer is the output of the previous graph convolutional layer. The last graph convolutional layer is connected to the algorithm layer. The algorithm layer, based on the target anomaly detection algorithm (i.e., the Deep SAD algorithm), constructs a hypersphere based on the node data output by the last graph convolutional layer and calculates the Euclidean distance between each node and the center of the hypersphere.

[0101] The output of the algorithm layer is connected to the input of the classifier. The classifier identifies and removes outlier nodes from the data based on the Euclidean distance of each node and the radius of the hypersphere. The Euclidean distance from all nodes to the center of the hypersphere serves as the evaluation score for each node. The scores are calculated for each sample, and a threshold is then used for classification. The theory behind the Deep SAD algorithm is that after obtaining the high-dimensional embedding representation of the nodes, a hypersphere is constructed to ensure that normal sample points fall inside the sphere, while outlier samples fall outside. Figure 10-a and Figure 10-bThis is a schematic diagram illustrating the principle of an anomaly detection algorithm provided in an embodiment of the present invention. Figure 10-a As shown, before classification by the anomaly detection algorithm, normal points (solid black dots) and anomaly points (hollow star shapes) are evenly distributed. After processing by the anomaly detection algorithm, normal points fall inside the circle, and anomaly points fall outside the circle. The center c and radius R can be calculated based on the average value of the node representation and the Euclidean distance from the anomaly point to the center of the circle.

[0102] Most anomaly detection is an unsupervised learning task, which can lead to the inability to apply labeled data to model parameter updates. To address this issue, this invention modifies the Deep SAD algorithm. The Deep SAD algorithm uses the labeled data as the exponent of the Euclidean distance between sample points, with a discrete value of 1 or -1. The value for minority class sample points is -1, and the reciprocal of their Euclidean distance is taken. That is, when the data is from the majority class, the Euclidean distance is not processed, ultimately making majority class samples closer to the hypersphere center c (smaller Euclidean distance), while minority class samples are farther from the hypersphere center (smaller reciprocal of Euclidean distance).

[0103] For the loss function, it can be expressed by the formula... We obtain h. (K) This represents the Kth layer, which is the last hidden layer, where c represents the center of the hypersphere, and W... (k) It is a learnable parameter, the exponential part. It refers to the true label of the data. This represents the L2 norm operation. The first term in the formula is the average Euclidean distance from all points to the center of the hypersphere, and the second term is the regularization term for the model parameters. The radius R of the hypersphere does not participate in the backpropagation of the model; it is only used for classifier classification. Nodes with an Euclidean distance less than the radius are considered normal samples, while nodes with an Euclidean distance greater than the radius are considered outlier points.

[0104] After obtaining the loss function, the goal of model learning is to find suitable parameters that minimize the value of the loss function. The process of solving this problem is called optimization, and optionally, optimizers such as Adam, SDG, LookAhead, and Lion can be used. Through multiple iterations of training, the model parameters are optimized to improve the accuracy of the model's selection results.

[0105] Adjustments made to the Deep SAD algorithm:

[0106] Each circuit generates a circuit netlist. Since the purpose of this embodiment is to predict monitoring nodes in new circuits, the training data includes multiple circuits, resulting in multiple circuit netlists. Although nodes are similar, different circuit netlists can be considered independent. Training needs to iterate through multiple circuit netlists, so calculating the radius requires averaging the radii of all circuit netlists. The radius of a single circuit netlist can be obtained from the minimum Euclidean distance of outliers, a problem the original Deep SAD algorithm did not need to consider. The original Deep SAD algorithm only provided a method for calculating evaluation scores, without explicitly specifying the classification threshold, i.e., the radius.

[0107] The hypersphere's center is calculated using the average value of the node representations after convergence in the previous training round, and the training model remains a graph convolutional neural network. Since the original Deep SAD algorithm was applied to a CNN network, the center can be obtained using a pre-trained autoencoder, avoiding the complex connections and multiple circuit netlists involved.

[0108] The original algorithm obtains the sample representation based on a CNN network, while the Deep SAD algorithm in this embodiment of the invention takes the representation obtained from a graph convolutional neural network as its input. The original Deep SAD algorithm is a semi-supervised learning method, and the adjusted loss function removes the part related to unlabeled data, making it closer to supervised learning.

[0109] After training, the model can predict unknown circuits and obtain predicted label data. Combined with the circuit netlist file of the unknown circuit, the name of the monitoring node trigger can be obtained for subsequent replacement of the standard unit. In machine learning, the logic of the monitoring node selection method learned by the model is contained in the model's parameters. To apply it to the actual selection process, the model and its parameters need to be saved as local files. Once the local files are ready, a Python script can be used to call the file, loading the model and its parameters for real-time use. At this point, the model and its parameters are independent of the model's training and testing processes. Afterwards, the script can be run externally using a command line to construct the circuit netlist, initialize features, load the model, and perform inference, realizing a circuit timing monitoring method based on a graph convolutional neural network model.

[0110] In a specific example, the complete execution process of the above method can be as follows:

[0111] First, the training circuit is synthesized to obtain the circuit netlist data. The training circuit used can be a collection of reference circuit designs commonly used in scientific research, such as ISCAS89 and ITC99, or it may include some open-source hardware designs. Figure 11 This invention provides a circuit synthesis result according to an embodiment of the invention. Figure 11The circuit synthesis result shown is a partial synthesis result of the S38584 circuit. To obtain the tag data, it is necessary to first analyze the circuit netlist data and select the monitoring nodes using existing EDA tools.

[0112] After circuit synthesis, the netlist files for all circuits are obtained. Then, to obtain tag data, static timing analysis is performed using a 65nm process. After timing analysis, the setup time check results are saved to a text file. To facilitate subsequent program analysis, the timing report file only records the start and end points of the path, not the delays of specific standard cells along the path. Figure 12 This is a schematic diagram of a timing report provided in an embodiment of the present invention. Figure 12 The image shown is the timing report obtained by running the PT tool.

[0113] Different timing analysis strategies employed during the establishment of the training dataset will result in different logics learned by the model. Taking the simultaneous use of static timing analysis and circuit simulation as an example, PT timing analysis and VCS simulation are used, and the activation status of specific paths is further considered based on the simulation results to eliminate invalid monitoring nodes, finally obtaining the monitoring node set. Figure 13 The diagram shows some activation rate statistics and the principles behind generating label data.

[0114] Next, a circuit netlist is constructed to obtain the circuit netlist diagram. This leads to the adjacency matrix, and data processing is performed on the monitoring node set to obtain tag data. Then, these tags are encoded according to the functions of all standard units under the current process, serving as the initial characteristic representation of each standard unit. To effectively utilize the data, data augmentation is employed to amplify it.

[0115] After the training dataset is built, the model code is implemented using the graph convolutional neural network framework, and the initial graph convolutional neural network model is used to train the data. Figure 14 This image shows the training effect of a graph convolutional neural network model provided in an embodiment of the present invention. Figure 14 The decrease in the value of the loss function shown indicates that the model has been adequately trained. Figure 15 The accuracy of the graph convolutional neural network model during inference is shown. Figure 15 As shown in the figure, the accuracy rate is gradually increasing and tending to stabilize, indicating that the model can effectively select monitoring nodes.

[0116] Once training is complete, the trained graph convolutional neural network model can be used to predict monitoring nodes in unknown circuits. Figure 16 This paper presents an analysis of the output of a graph convolutional neural network. For example... Figure 16 As shown, the graph convolutional neural network is applied in a command-based manner.

[0117] Corresponding to the above-described timing circuit monitoring method, this embodiment of the invention provides a circuit timing monitoring device. Figure 17 This is a schematic diagram of a circuit timing monitoring device provided in an embodiment of the present invention. Figure 17 As shown, the circuit timing monitoring device includes: a node determination module 1701, a feature information determination module 1702, a monitoring node prediction module 1703, a monitoring node determination module 1704, and a timing monitoring module 1705.

[0118] The node determination module 1701 is used to determine multiple candidate monitoring nodes in the target circuit and the connection relationship of the multiple candidate monitoring nodes.

[0119] The feature information determination module 1702 is used to determine the feature information of the target circuit based on the device attribute information of the plurality of candidate monitoring nodes;

[0120] The monitoring node prediction module 1703 is used to input the feature information of the target circuit and the connection relationship of the multiple candidate monitoring nodes into the trained target graph convolutional neural network model, so that the graph convolutional neural network model outputs the determination results of multiple candidate monitoring nodes; the determination results include a first determination result that is a monitoring node and a second determination result that is not a monitoring node.

[0121] The monitoring node determination module 1704 is used to determine at least one monitoring node from the plurality of candidate monitoring nodes based on the determination result output by the graph convolutional neural network model.

[0122] The timing monitoring module 1705 is used to perform timing monitoring on the target circuit based on the at least one monitoring node.

[0123] Figure 18 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention, such as... Figure 18 As shown, the aforementioned electronic device may include at least one processor and at least one memory communicatively connected to the processor, wherein the memory stores program instructions executable by the processor, and the processor can execute this specification by calling the program instructions. Figures 1 to 16 The circuit timing monitoring method provided in the illustrated embodiment.

[0124] like Figure 18 As shown, the electronic device is represented in the form of a general-purpose computing device. The components of the electronic device may include, but are not limited to: one or more processors 1810, communication interface 1820 and memory 1830, and a communication bus 1840 connecting different system components (including memory 1830, communication interface 1820 and processor 1810).

[0125] The communication bus 1840 represents one or more of several bus architectures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any of the various bus architectures. Examples of these architectures include, but are not limited to, the Industry Standard Architecture (ISA) bus, the Micro Channel Architecture (MAC) bus, the Enhanced ISA bus, the Video Electronics Standards Association (VESA) local bus, and the Peripheral Component Interconnect (PCI) bus.

[0126] Electronic devices typically include a variety of computer-readable media. These media can be any available media that can be accessed by the electronic device, including volatile and non-volatile media, and removable and non-removable media.

[0127] Memory 1830 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) and / or cache memory. The electronic device may further include other removable / non-removable, volatile / non-volatile computer system storage media. Memory 1830 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of the embodiments described herein.

[0128] A program / utility having a set (at least one) of program modules may be stored in memory 1830. Such program modules include—but are not limited to—an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment. The program modules typically perform the functions and / or methods described in the embodiments of this specification.

[0129] Processor 1810 executes various functional applications and data processing by running programs stored in memory 1830, such as implementing the functions described in this specification. Figures 1 to 16 The circuit timing monitoring method provided in the illustrated embodiment.

[0130] This specification provides a computer-readable storage medium storing computer instructions that cause a computer to execute this specification. Figures 1 to 16The circuit timing monitoring method provided in the illustrated embodiment.

[0131] The aforementioned computer-readable storage medium may be any combination of one or more computer-readable media. A computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), or flash memory, optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in connection with an instruction execution system, apparatus, or device.

[0132] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.

[0133] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this specification. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0134] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this specification, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0135] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this specification includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which the embodiments of this specification pertain.

[0136] Depending on the context, the word "if" as used here can be interpreted as "when," "when," "in response to determination," or "in response to detection." Similarly, depending on the context, the phrase "if determination" or "if detection (of the stated condition or event)" can be interpreted as "when determination," "in response to determination," "when detection (of the stated condition or event)," or "in response to detection (of the stated condition or event)."

[0137] It should be noted that the devices involved in the embodiments of this specification may include, but are not limited to, personal computers (hereinafter referred to as PCs), personal digital assistants (hereinafter referred to as PDAs), wireless handheld devices, tablet computers, mobile phones, MP3 displays, MP4 displays, etc.

[0138] In the several embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0139] Furthermore, the functional units in the various embodiments of this specification can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in a combination of hardware and software functional units.

[0140] The integrated units implemented as software functional units described above can be stored in a computer-readable storage medium. These software functional units, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, a connector, or a network device, etc.) or a processor to execute some steps of the methods described in the various embodiments of this specification. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0141] The above description is merely a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of protection of this specification.

[0142] The same or similar parts between the various embodiments in this specification can be referred to mutually. In particular, the device embodiments and terminal embodiments are basically similar to the method embodiments, so the description is relatively simple, and the relevant parts can be referred to the description in the method embodiments.

Claims

1. A method for timing monitoring of digital integrated circuits based on graph convolutional neural networks, characterized in that, include: Determine multiple candidate monitoring nodes in the target circuit and the connection relationships of the multiple candidate monitoring nodes; The characteristic information of the target circuit is determined based on the device attribute information of the multiple candidate monitoring nodes; The feature information of the target circuit and the connection relationship of the multiple candidate monitoring nodes are input into the trained target graph convolutional neural network model, so that the graph convolutional neural network model outputs the determination results of multiple candidate monitoring nodes; the determination results include a first determination result that is a monitoring node and a second determination result that is not a monitoring node; Based on the determination result output by the graph convolutional neural network model, at least one valid monitoring node is determined from the plurality of candidate monitoring nodes; Timing monitoring of the target circuit is performed based on at least one effective monitoring node; The training dataset used during training of the target graph convolutional neural network model includes feature data of each node in the training circuit, connection relationships between each node, and label data of each node. The steps for obtaining the label data of each node include: Static timing analysis is performed on the training circuit to obtain the critical path in the training circuit; The training circuit is dynamically simulated to determine the effective activation path from the critical path; Multiple valid monitoring points are determined based on the effective activation path; The label data of the node corresponding to the effective monitoring point in the circuit netlist diagram of the training circuit is determined as the first label data, and the label data of the remaining nodes is determined as the second label data.

2. The method according to claim 1, characterized in that, The determination of multiple candidate monitoring nodes in the target circuit includes: Obtain the circuit netlist data of the target circuit; Based on the circuit netlist data, a corresponding circuit netlist diagram is generated using standard cells and ports as nodes. The nodes in the circuit netlist diagram are identified as the candidate monitoring nodes.

3. The method according to claim 1, characterized in that, The connection relationships between the candidate monitoring nodes are formed by an adjacency matrix. The steps for determining the connection relationships between the multiple candidate monitoring nodes include: The connection relationships of each node are determined based on the circuit connection relationships of the target circuit; The connection relationships of the multiple candidate monitoring nodes are determined based on the connection relationships of each node. The adjacency matrix is ​​generated based on the connection relationships of the multiple candidate monitoring nodes.

4. The method according to claim 1, characterized in that, The determination of the characteristic information of the target circuit based on the device attribute information of the multiple candidate monitoring nodes includes: Determine all device attribute information of the candidate monitoring node based on the process library corresponding to the target circuit; Select at least one device attribute from the device attribute information of the candidate monitoring nodes as the target device attribute information; The characteristic information of the target circuit is determined based on the target device attribute information corresponding to each candidate monitoring node.

5. The method according to claim 4, characterized in that, The feature information of the target circuit is a feature matrix. Determining the feature information of the target circuit based on the target device attribute information corresponding to each candidate monitoring node includes: The node vector of the corresponding candidate monitoring node is determined based on the target device attribute information; The feature matrix of the target circuit is constructed based on the node vectors of the candidate monitoring nodes.

6. The method according to claim 1, characterized in that, The training process of the target graph convolutional neural network model includes: Obtain the training dataset; wherein the label data includes: first label data that is a monitoring node, and second label data that is not a monitoring node; The initial graph convolutional neural network model is iteratively trained based on the training dataset so that the initial graph convolutional neural network model can learn the node features of different labeled data; When the loss function of the initial graph convolutional neural network model is detected to meet the preset conditions, the training is determined to be complete, and the target graph convolutional neural network model is obtained.

7. The method according to claim 6, characterized in that, The feature data is a feature matrix, the connection relationship is an adjacency matrix, and the steps for obtaining the feature data of each node and the connection relationship of each node include: The standard cells and ports in the training circuit are used as nodes to generate the circuit netlist diagram of the training circuit. Determine the connection relationships of each node based on the circuit netlist diagram; The adjacency matrix of the training circuit is generated based on the connection relationship of each node, and the feature matrix of the training circuit is generated based on the device attribute information of each node.

8. The method according to claim 6, characterized in that, The target graph convolutional neural network model is composed of multiple stacked graph convolutional layers. The input of the first graph convolutional layer is the feature matrix of each node, the adjacency matrix of each node, and the label data of each node. The data of the other graph convolutional layers are the outputs of the previous graph convolutional layer. The last graph convolutional layer in the plurality of graph convolutional layers is connected to the algorithm layer; the algorithm layer constructs a hypersphere based on the node data output by the last graph convolutional layer based on the target anomaly detection algorithm and calculates the Euclidean distance between each node and the center of the hypersphere; The output of the algorithm layer is connected to the input of the classifier. The classifier determines abnormal node data from the data of each node based on the Euclidean distance corresponding to each node and the radius of the hypersphere, and removes the abnormal node data.

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