LDO circuit and chip with fast response and adjustable transient response

Abstract

The application provides an LDO circuit and chip with fast response and adjustable transient response, comprising: an error amplifier EA0, a power transistor MP0, a low-gain stage module, a compensation capacitor selector, a digital control resistance voltage division array, and a transient enhancement circuit; the compensation capacitor selector is used for providing a capacitor with a corresponding capacitance value for an output end of the error amplifier EA0 and a drain of the power transistor MP0 according to a first external control signal; the digital control resistance voltage division array is used for controlling a resistance value of a feedback resistor in the LDO circuit according to a second external control signal, so as to generate a corresponding output voltage; and the transient enhancement circuit is used for adjusting a gate voltage of the power transistor MP0 according to a feedback voltage between the error amplifier EA0 and the digital control resistance voltage division array, and the circuit has the advantages of simple structure, fast response, programmable output voltage, and flexible adjustment of transient response.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of electronic circuits, and particularly relates to an LDO circuit with fast response and adjustable transient response and a chip. BACKGROUND

[0002] In recent years, with the rapid development of various portable electronic devices, consumer electronics and automotive electronics, simply relying on board-level design cannot meet the development of integrated circuits towards small size, high density and low power consumption, so a system on chip (SoC) with higher integration is proposed. However, the higher the integration of the integrated circuit, the more power the system on chip consumes. In order to reduce the power consumption of the system on chip, the system on chip is usually given a working time sequence and a working mode.

[0003] Among them, the working time sequence can make the circuit module that does not need to work temporarily stop working, thereby saving the chip power consumption; the working mode can make the same circuit module consume different power consumption when realizing different performances. In order to save the power consumption of each module in the chip in different working modes, it is necessary to manage the power supply of each module of the chip, that is, the power supply voltages required by different circuit modules in different working modes are different, and the power supply voltages required by the same circuit module when realizing different performances are also different.

[0004] The traditional low dropout regulator (LDO) circuit can only output one stable power supply voltage. In order to output different power supply voltages for the same circuit module or different modules, the prior art usually adopts the technical scheme of configuring multiple traditional LDO circuits to work respectively. However, configuring multiple traditional LDO circuits will occupy a large area, thereby increasing the cost of the chip. In addition, when different power supply voltages are output for the same circuit module, it is necessary to re-establish the steady state of the circuit. The technical scheme of the prior art for realizing the output of different power supply voltages through the working switching of multiple traditional LDO circuits cannot guarantee the speed of the transient response, and even the problem of slow transient response may occur, which seriously affects the working time sequence and performance of other circuit modules. Therefore, an LDO with programmable output voltage can be used to generate the required different power supply voltages, but different output voltages will change the loop bandwidth of the LDO, and the change of the loop bandwidth of the LDO will affect the speed of its transient response, so it is necessary to solve the influence of different output voltages of the LDO on its bandwidth and transient response speed. SUMMARY

[0005] In order to solve the above problems in the prior art, the application provides an LDO circuit and chip with fast response and adjustable transient response.

[0006] In a first aspect, the application provides an LDO circuit with fast response and adjustable transient response, comprising:

[0007] an error amplifier EA0, a power transistor MP0, a low-gain stage module, a compensation capacitor selector, a digital control resistance dividing array, and a transient enhancement circuit.

[0008] The negative input end of the error amplifier EA0 is connected to a voltage Vref, the positive input end is connected to a first end of the digital control resistance dividing array and a first end of the transient enhancement circuit respectively, the power supply end is connected to a voltage Vin, and the output end is connected to a second end of the low-gain stage module and a first end of the compensation capacitor selector respectively.

[0009] The first end of the low-gain stage module is connected to an input signal Vb1, the third end is connected to ground, the fourth end is connected to a gate of the power transistor MP0 and a fifth end of the transient enhancement circuit respectively, and the fifth end is connected to the power supply Vin.

[0010] The source of the power transistor MP0 is connected to the power supply Vin, and the drain is connected to a second end of the compensation capacitor selector and a fourth end of the digital control resistance dividing array respectively.

[0011] The third end of the compensation capacitor selector is connected to a first external control signal.

[0012] The third end of the digital control resistance dividing array is connected to a second external control signal, and the second end is connected to ground.

[0013] The second end of the transient enhancement circuit is connected to a voltage Vref1, the third end is connected to an input signal Vb2, the fourth end is connected to ground, and the sixth end is connected to the power supply Vin.

[0014] The compensation capacitor selector is used to provide a capacitor with a corresponding capacitance value for the output end of the error amplifier EA0 and the drain of the power transistor MP0 according to the first external control signal.

[0015] The digital control resistance dividing array is used to control the resistance value of a feedback resistor in the LDO circuit according to the second external control signal, so as to generate a corresponding output voltage.

[0016] The transient enhancement circuit is used to adjust the gate voltage of the power transistor MP0 according to the feedback voltage between the error amplifier EA0 and the digital control resistance dividing array.

[0017] Optionally, the transient enhancement circuit comprises:

[0018] an error amplifier EA1, a discharging circuit, and a charging circuit.

[0019] The positive input end of the error amplifier EA1 is the first end of the transient enhancement circuit, the negative input end is the second end of the transient enhancement circuit, the negative output end is respectively connected with the first end of the discharging circuit and the first end of the charging circuit, and the positive output end is respectively connected with the second end of the discharging circuit and the second end of the charging circuit;

[0020] The third end of the discharging circuit is the third end of the transient enhancement circuit, and the fourth end is grounded.

[0021] The third end of the charging circuit is the third end of the transient enhancement circuit, the fourth end is grounded, the fifth end is the fifth end of the transient enhancement circuit, and the sixth end is the sixth end of the transient enhancement circuit.

[0022] The discharging circuit is used for pulling down the gate voltage of the power tube MP0.

[0023] The charging circuit is used for pulling up the gate voltage of the power tube MP0.

[0024] Optionally, the discharging circuit comprises:

[0025] The PMOS tubes MP3 and MP4 and the NMOS tubes MN1, MN2 and MN3.

[0026] The gate of the MN1 is connected with the gate of the MN2, the source is grounded, and the drain is respectively connected with the drain and the gate of the MP3 and the gate of the MP4.

[0027] The source of the MP3 is the second end of the discharging circuit.

[0028] The source of the MP4 is the first end of the discharging circuit, and the drain is respectively connected with the gate of the MN3 and the drain of the MN2.

[0029] The drain of the MN3 is the fifth end of the discharging circuit, and the source is grounded.

[0030] The source of the MN2 is grounded.

[0031] Optionally, the charging circuit comprises:

[0032] The PMOS tubes MP5, MP6, MP7 and MP8 and the NMOS tubes MN4, MN5 and MN6.

[0033] The gate of the MN4 is connected with the gate of the MN5, the source is grounded, and the drain is respectively connected with the drain and the gate of the MP5 and the gate of the MP6.

[0034] The source of the MN5 is grounded, and the drain is respectively connected with the gate of the MN6 and the drain of the MP6.

[0035] The source of the MN6 is grounded, and the drain is respectively connected with the drain and the gate of the MP7 and the gate of the MP8.

[0036] The source of the MP7 is the sixth terminal of the charging circuit;

[0037] The drain of the MP8 is the fifth terminal of the charging circuit, and the source is connected to the source of the MP7;

[0038] The source of the MP6 is the second terminal of the charging circuit;

[0039] The source of the MP5 is the first terminal of the charging circuit.

[0040] Optionally, the low-gain stage module comprises:

[0041] PMOS transistors MP1 and MP2;

[0042] The gate of the MP1 is the first terminal of the low-gain stage module, the source is the fifth terminal of the low-gain stage module, and the drain is the fourth terminal of the low-gain stage module;

[0043] The gate of the MP2 is the second terminal of the low-gain stage module, the source is connected to the drain of the MP1, and the drain is connected to the ground.

[0044] Optionally, the compensation capacitor selector comprises:

[0045] A first multi-control signal generating unit and a capacitor selection unit;

[0046] The input terminal of the first multi-control signal generating unit is connected to the first external control signal, and the output terminal is connected to the control terminal of the capacitor selection unit;

[0047] The first input / output terminal of the capacitor selection unit is connected to the output terminal of the error amplifier EA0, and the second input / output terminal is connected to the drain of the power transistor MP0;

[0048] The first multi-control signal generating unit is configured to generate and output a plurality of first internal control signals according to the first external control signal, and transmit the plurality of first internal control signals to the capacitor selection unit;

[0049] The capacitor selection unit is configured to provide a capacitor with a corresponding capacitance between the output terminal of the error amplifier EA0 and the drain of the power transistor MP0 according to the plurality of first internal control signals.

[0050] Optionally, the first multi-control signal generating unit comprises a 3-8 decoder U1 and a plurality of NOT gates F0, F1, F2, F3, F4, F5, F6, and F7;

[0051] The capacitor selection unit comprises capacitors C0, C1, C2, C3, C4, C5, C6, and C7, and switches S0, S1, S2, S3, S4, S5, S6, and S7;

[0052] The 1st-8th output terminals of the 3-8 decoder U1 are respectively connected to the input terminals of the NOT gates F0-F7.

[0053] The input end of the NOT gate F0-F7 is connected with the forward control end of the switch S0-S7 respectively;

[0054] The output end of the NOT gate F0-F7 is connected with the reverse control end of the switch S0-S7 respectively;

[0055] The first input and output end of the switch S0-S7 is connected with the second end of the capacitor C0-C7 respectively;

[0056] The second input and output end of the switch S0-S7 is connected with the output end of the error amplifier EA0;

[0057] The first end of the capacitor C0 is connected with the drain of the power tube MP0, the capacitors C0-C7 are connected in series, and the second end of the capacitor C0 is connected with the first end of the capacitor C1.

[0058] Optionally, the digital control resistance voltage dividing array comprises:

[0059] The second multi-path control signal generating unit and the resistance voltage dividing selection unit;

[0060] The input end of the second multi-path control signal generating unit is connected with the second external control signal, and the output end is connected with the control end of the resistance voltage dividing selection unit;

[0061] The first end of the resistance voltage dividing selection unit is connected with the drain of the power tube MP0, the second end is connected with the positive input end of the error amplifier EA0, and the third end is connected with the ground;

[0062] The second multi-path control signal generating unit is used for generating and outputting a plurality of second internal control signals according to the second external control signal, and transmitting the plurality of second internal control signals to the resistance voltage dividing selection unit;

[0063] The resistance voltage dividing selection unit is used for forming different resistance voltage dividing circuits according to the plurality of second internal control signals, so as to change the resistance value of the feedback resistance in the LDO circuit to generate different output voltages.

[0064] Optionally, the second multi-path control signal generating unit comprises a 3-8 decoder U2;

[0065] The resistance voltage dividing selection unit comprises resistors R1, R2, R3, R4, R5, R6, R7, R8, R9 and R10, and NMOS tube switches T0, T1, T2, T3, T4, T5, T6 and T7;

[0066] The 1st-8th output ends of the 3-8 decoder U2 are connected with the gate of the NMOS tube switches T0-T7 respectively;

[0067] The drain of the NMOS tube switches T0-T7 is connected with the first end of the resistors R1-R8 respectively.

[0068] The source of each of the NMOS transistor switches T0-T7 is connected to the first end of the resistor R9.

[0069] The resistors R1-R10 are connected in series, and the second end of the resistor R1 is connected to the first end of the resistor R2.

[0070] The first end of the resistor R1 is connected to the drain of the power transistor MP0.

[0071] The second end of the resistor R9 is connected to the positive input terminal of the error amplifier EA0.

[0072] The second end of the resistor R10 is connected to the ground.

[0073] In a second aspect, the present application further provides an LDO chip with fast response and adjustable transient response, comprising any of the LDO circuits with fast response and adjustable transient response provided in the first aspect and the optional modes thereof.

[0074] The present application has the following advantages:

[0075] The LDO circuit and chip with fast response and adjustable transient response provided by the present application comprise: an error amplifier EA0, a power transistor MP0, a low-gain stage module, a compensation capacitor selector, a digital control resistance divider array, and a transient enhancement circuit; the negative input terminal of the error amplifier EA0 is connected to a voltage Vref, the positive input terminal is connected to the first end of the digital control resistance divider array and the first end of the transient enhancement circuit respectively, the power supply terminal is connected to a voltage Vin, and the output terminal is connected to the second end of the low-gain stage module and the first end of the compensation capacitor selector respectively; the first end of the low-gain stage module is connected to an input signal Vb1, the third end is connected to the ground, the fourth end is connected to the gate of the power transistor MP0 and the fifth end of the transient enhancement circuit respectively, and the fifth end is connected to the power supply Vin; the source of the power transistor MP0 is connected to the power supply Vin, and the drain is connected to the second end of the compensation capacitor selector and the fourth end of the digital control resistance divider array respectively; the third end of the compensation capacitor selector is connected to a first external control signal; the third end of the digital control resistance divider array is connected to a second external control signal respectively, and the second end is connected to the ground; the second end of the transient enhancement circuit is connected to a voltage Vref1, the third end is connected to an input signal Vb2, the fourth end is connected to the ground, and the sixth end is connected to the power supply Vin; the compensation capacitor selector is used to provide a capacitor with a corresponding capacitance value for the output terminal of the error amplifier EA0 and the drain of the power transistor MP0 according to the first external control signal; the digital control resistance divider array is used to control the resistance value of the feedback resistor in the LDO circuit according to the second external control signal, so as to generate a corresponding output voltage; and the transient enhancement circuit is used to adjust the gate voltage of the power transistor MP0 according to the feedback voltage between the error amplifier EA0 and the digital control resistance divider array. The circuit structure is simple, the response is fast, the output voltage is programmable, and the transient response can be flexibly adjusted.

[0076] The application will be described in further detail below with reference to the drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0077] Figure 1 A structure schematic diagram of a conventional LDO circuit provided by the application;

[0078] Figure 2 A structure schematic diagram of an LDO circuit with fast response and adjustable transient response provided by the application;

[0079] Figure 3 A structure schematic diagram of a compensation capacitor selector provided by the application;

[0080] Figure 4 A structure schematic diagram of a digital control resistance dividing array provided by the application. DETAILED DESCRIPTION

[0081] The application will be described in further detail below with reference to the drawings and embodiments.

[0082] It is particularly important for the flexibility of the LDO to generate different power supply voltages required by each module in the LDO generation chip with adjustable output voltage and to realize the design of adjustable transient response speed of the LDO for different output voltages on the premise of ensuring fast response of the LDO. Figure 1 A structure schematic diagram of a conventional LDO circuit, in which Figure 1 In the LDO structure, the expression of the LDO output voltage Vout is:

[0083]

[0084] In which, A is the loop gain, F is the feedback coefficient, and the expression of F is:

[0085]

[0086] When FA tends to infinity, the expression of the relationship between the output voltage and the reference voltage is:

[0087]

[0088] Therefore, by adjusting the values of Rf1 and Rf2, the required output voltage can be obtained.

[0089] In actual situations, since the loop gain of the error amplifier cannot be infinite, there will be errors in the output voltage. In order to reduce the errors, the gain of the loop needs to be improved.

[0090] Secondly, since the conventional LDO has an off-chip load capacitor CL , which generally contains two high impedance nodes in the loop, respectively at the output of the LDO and at the output of the error amplifier. According to the stability criterion, in order to ensure the stability of the system loop, only one pole is allowed to appear in the loop bandwidth, so the LDO needs to be loop compensated to make the system stable. Usually, the equivalent series resistance (ESR) of the output off-chip load capacitor is used to form a left half plane zero point to offset the non-main pole generated at the output of the error amplifier, so that there is only one pole in the loop bandwidth of the LDO, thereby ensuring the loop stability. However, the resistance R ESR and the capacitor will also form a pole. It is easy to know that the zero and pole positions of the LDO are respectively:

[0091]

[0092]

[0093]

[0094]

[0095] wherein P1 is a main pole in the loop, P2 and P3 are respectively a first non-main pole and a second non-main pole, Z1 is a zero point, R OUT is an output resistance of the LDO, C L is a load capacitor, R OA is an output resistance of the error amplifier, C GP is a total capacitance at the gate terminal of the power tube, R ESR is an equivalent series resistance of the load capacitor C L , C b is a bypass capacitor, and From the above analysis, when the values of the feedback resistances Rf1 and Rf2 are changed, although different output voltages can be obtained, the position of the main pole is also changed, and the position of the pole is also related to the capacitance values at each node.

[0096] The transient response performance reflects the ability of the LDO circuit to respond to load mutations or power supply voltage mutations. In actual situations, the working voltage of the LDO chip is generally stable, but the load often changes. When the load changes, the peak value ΔV MAX of the output voltage change is:

[0097]

[0098] wherein I LOAD,MAX represents the maximum load current of the LDO circuit, C O is the output capacitance of the circuit, and C bis a bypass parasitic capacitance, and Δt is the closed-loop response time of the LDO circuit, and its expression is:

[0099]

[0100] wherein BW is the -3dB bandwidth of the loop, C GP is the total capacitance of the gate of the power transistor MP, and ΔV is the voltage variation on C GP , and I SR is the slew rate current.

[0101] From the above analysis, it can be seen that increasing the bandwidth and the slew rate of the loop or reducing the total capacitance of the gate of the power adjustment transistor MP can improve the transient response performance and reduce the output voltage peak.

[0102] From the above overall analysis, it can be seen that when the LDO outputs different output voltages, the zero-pole of the system will change due to the change of the feedback resistance, thereby affecting the bandwidth of the loop, and the change of the bandwidth will affect the performance of the transient response. In order to ensure that the loop bandwidth and the transient response remain unchanged under different output voltages, the present application proposes an LDO circuit with fast response and adjustable transient response on the basis of the traditional LDO circuit structure. The circuit increases a low-gain stage module, a compensation capacitor selector, a transient enhancement circuit and a digital control resistance divider array on the basis of the traditional LDO. The low-gain stage module provides certain driving capability and signal isolation; the compensation capacitor selector controls the capacitance value across the output end of the error amplifier and the output end of the traditional LDO circuit through digital logic, thereby compensating the frequency point and adjusting the loop bandwidth and the transient response time; the transient enhancement circuit is used to realize the fast transient response of the system; and the digital control resistance divider array controls the resistance value of the feedback resistance in the traditional LDO circuit through digital logic, thereby generating different output voltages. The structure finally realizes an LDO circuit with programmable output voltage, fast response and adjustable transient response.

[0103] Figure 2 A structure diagram of the LDO circuit with fast response and adjustable transient response provided by the present application is shown in FIG. 1, which comprises: Figure 2

[0104] an error amplifier EA0, a power transistor MP0, a low-gain stage module, a compensation capacitor selector, a digital control resistance divider array, and a transient enhancement circuit.

[0105] The negative input end of the error amplifier EA0 is connected with a voltage Vref, the positive input end is connected with the first end of the digital control resistance divider array and the first end of the transient enhancement circuit respectively, the power supply end is connected with a voltage Vin, and the output end is connected with the second end of the low-gain stage module and the first end of the compensation capacitor selector respectively.​

[0106] The first end of the low-gain stage module is connected with an input signal Vb1, the third end is connected with ground, and the fourth end is connected with the gate of the power transistor MP0 and the fifth end of the transient enhancement circuit respectively, and the fifth end is connected with a power supply Vin.

[0107] The source of the power transistor MP0 is connected with the power supply Vin, and the drain is connected with the second end of the compensation capacitor selector and the fourth end of the digital control resistance voltage dividing array respectively.

[0108] The third end of the compensation capacitor selector is connected with a first external control signal.

[0109] The third end of the digital control resistance voltage dividing array is connected with a second external control signal, and the second end is connected with ground.

[0110] The second end of the transient enhancement circuit is connected with a voltage Vref1, the third end is connected with an input signal Vb2, the fourth end is connected with ground, and the sixth end is connected with the power supply Vin.

[0111] The compensation capacitor selector is used for providing a capacitor with a corresponding capacitance value for the output end of the error amplifier EA0 and the drain of the power transistor MP0 according to the first external control signal.

[0112] The digital control resistance voltage dividing array is used for controlling the resistance value of the feedback resistance in the LDO circuit according to the second external control signal, so that the LDO circuit generates a corresponding output voltage Vout. OUT .

[0113] The transient enhancement circuit is used for adjusting the gate voltage of the power transistor MP0 according to the feedback voltage VFB between the error amplifier EA0 and the digital control resistance voltage dividing array.

[0114] The error amplifier EA0 outputs an error voltage to the low-gain stage circuit by comparing and amplifying the difference between the input reference voltage Vref and the feedback voltage VFB through a feedback system. The structure of the error amplifier is not limited in the present application, and can be determined by those skilled in the art according to business needs. The structure can be a traditional two-stage operational amplifier structure or a folded common-source common-gate operational amplifier structure, etc. The operational amplifier commonly used in the error amplifier has the characteristics of high open-loop gain, fast transient response, high common-mode rejection ratio, etc.

[0115] Optionally, referring to Figure 2 , the transient enhancement circuit comprises:

[0116] The error amplifier EA1, the discharging circuit and the charging circuit.

[0117] The positive input end of the error amplifier EA1 is the first end of the transient enhancement circuit, the negative input end is the second end of the transient enhancement circuit, the negative output end is connected with the first end of the discharging circuit and the first end of the charging circuit respectively, and the positive output end is connected with the second end of the discharging circuit and the second end of the charging circuit respectively.

[0118] The third end of the discharging circuit is the third end of the transient enhancement circuit, and the fourth end is grounded.

[0119] The third end of the charging circuit is the third end of the transient enhancement circuit, the fourth end is grounded, the fifth end is the fifth end of the transient enhancement circuit, and the sixth end is the sixth end of the transient enhancement circuit.

[0120] The discharging circuit is used for pulling down the gate voltage of the power tube MP0.

[0121] The charging circuit is used for pulling up the gate voltage of the power tube MP0.

[0122] Optionally, referring to Figure 2 , the discharging circuit comprises:

[0123] The PMOS tubes MP3 and MP4 and the NMOS tubes MN1, MN2 and MN3.

[0124] The gate of the MN1 is connected with the gate of the MN2, the source is grounded, and the drain is connected with the drain and the gate of the MP3 and the gate of the MP4 respectively.

[0125] The source of the MP3 is the second end of the discharging circuit.

[0126] The source of the MP4 is the first end of the discharging circuit, and the drain is connected with the gate of the MN3 and the drain of the MN2 respectively.

[0127] The drain of the MN3 is the fifth end of the discharging circuit, and the source is grounded.

[0128] The source of the MN2 is grounded.

[0129] Optionally, referring to Figure 2 , the charging circuit comprises:

[0130] The PMOS tubes MP5, MP6, MP7 and MP8 and the NMOS tubes MN4, MN5 and MN6.

[0131] The gate of the MN4 is connected with the gate of the MN5, the source is grounded, and the drain is connected with the drain and the gate of the MP5 and the gate of the MP6 respectively.

[0132] The source of the MN5 is grounded, and the drain is connected with the gate of the MN6 and the drain of the MP6 respectively.

[0133] The source of the MN6 is grounded, and the drain is connected to the drain and gate of the MP7 and the gate of the MP8 respectively.

[0134] The source of the MP7 is the sixth terminal of the charging circuit.

[0135] The drain of the MP8 is the fifth terminal of the charging circuit, and the source is connected to the source of the MP7.

[0136] The source of the MP6 is the second terminal of the charging circuit.

[0137] The source of the MP5 is the first terminal of the charging circuit.

[0138] The transient enhancement circuit rapidly adjusts the voltage of the VG according to the change of the LDO load current, first samples the feedback voltage VFB when the load current changes, amplifies the difference between the voltage and the reference voltage Vref1 through the error amplifier EA1, and then converts the amplified voltage signal into pull-up or pull-down current of the gate of the adjusting tube MP0, so as to rapidly establish the gate potential.

[0139] Taking the change of the output load current of the LDO from light load to heavy load as an example, the change will cause the VFB voltage to drop, so that the voltage of the reverse output end of the error amplifier EA1 rises and the voltage of the same direction output end decreases, so that the gate voltage of the MN3 tube rapidly increases and the gate voltage of the MN6 tube rapidly decreases, so that the MN3 tube is turned on and the MN6 tube is turned off, and the discharge circuit for controlling the gate VG of the power tube in the circuit starts to work, the pull-down current of the MN3 tube rapidly increases, the gate potential of the adjusting tube MP rapidly decreases, the drop voltage of the output voltage is effectively reduced, the output voltage of the LDO rapidly tends to be stable, and the function of the rapid response of the LDO circuit is realized.

[0140] Optionally, referring to Figure 2 , the low-gain stage circuit comprises:

[0141] The PMOS tubes MP1 and MP2.

[0142] The gate of the MP1 is the first terminal of the low-gain stage circuit, the source is the fifth terminal of the low-gain stage circuit, and the drain is the fourth terminal of the low-gain stage circuit.

[0143] The gate of the MP2 is the second terminal of the low-gain stage circuit, the source is connected to the drain of the MP1, and the drain is grounded.

[0144] The source follower composed of the PMOS tubes MP1 and MP2 is the low-gain stage circuit, which can provide a certain driving capability for the circuit and play a role in signal isolation.

[0145] Optionally, the compensation capacitor selector comprises:

[0146] The first multiplexing control signal generating unit and the capacitor selecting unit.

[0147] The input end of the first multipath control signal generating unit is connected with the first external control signal, and the output end is connected with the control end of the capacitor selection unit.

[0148] The first input-output end of the capacitor selection unit is connected with the output end of the error amplifier EA0, and the second input-output end is connected with the drain of the power tube MP0.

[0149] The first multipath control signal generating unit is used for generating and outputting a plurality of first internal control signals according to the first external control signal, and transmitting the plurality of first internal control signals to the capacitor selection unit.

[0150] The capacitor selection unit is used for providing a capacitor with a corresponding capacitance between the output end of the error amplifier EA0 and the drain of the power tube MP0 according to the plurality of first internal control signals.

[0151] Optionally, the compensation capacitor selector can also be realized by an integrated capacitor selection chip, which can realize the selection of the capacitance.

[0152] Figure 3 A structural schematic diagram of the compensation capacitor selector is provided.

[0153] Optionally, referring to Figure 3 The first multipath control signal generating unit comprises a 3-8 decoder U1 and a plurality of NOT gates F0, F1, F2, F3, F4, F5, F6 and F7.

[0154] The capacitor selection unit comprises capacitors C0, C1, C2, C3, C4, C5, C6 and C7, and switches S0, S1, S2, S3, S4, S5, S6 and S7.

[0155] The 1st-8th output ends of the 3-8 decoder U1 are respectively connected with the input ends of the NOT gates F0-F7, and the 1st-8th output ends of the 3-8 decoder U1 are respectively connected with the positive control ends of the switches S0-S7.

[0156] The 1st-8th output ends of the 3-8 decoder U1 respectively output signals M0, M1, M2, M3, M4, M5, M6 and M7.

[0157] The output ends of the NOT gates F0-F7 are respectively connected with the reverse control ends of the switches S0-S7.

[0158] The output ends of the NOT gates F0-F7 respectively output signals NM0, NM1, NM2, NM3, NM4, NM5, NM6 and NM7.

[0159] The first input-output ends of the switches S0-S7 are respectively connected with the second ends of the capacitors C0-C7.

[0160] The second input and output ends of the switches S0-S7 are connected with the output end of the error amplifier EA0.

[0161] The first end of the capacitor C0 is connected with the drain of the power transistor MP0, the capacitors C0-C7 are connected in series, and the second end of the capacitor C0 is connected with the first end of the capacitor C1.

[0162] Optionally, the switches S0-S7 are transmission gate switches.

[0163] It can be understood that the first multipath control signal generating unit can also be implemented by other ways, for example, a 2-4 decoder, a 4-16 decoder, etc., which can generate multipath control signals. At the same time, the capacitor selection unit should also be adjusted according to the specific implementation mode of the first multipath control signal generating unit.

[0164] The 3-8 decoder U1 inputs B0-B2 three-bit binary codes, outputs M0-M7 eight-way output signals, and generates corresponding NM0-NM7 control signals through inverters, and then uses the M0-M7 and NM0-NM7 signals to control the on-off state of the transmission gate switches S0-S7, thereby controlling the capacitance value of the compensation capacitor connected between the output end of the error amplifier and the output voltage V OUT The size of the compensation capacitor is used to adjust the frequency point of the system, and finally realizes the functions of adjustable-3dB bandwidth and transient response of the loop.

[0165] Since the change of the feedback resistance value will cause the change of the output resistance, the zero-pole in the system will move, thereby affecting the-3dB bandwidth and the transient response of the loop. Through the compensation capacitor selector provided by the application, different capacitance values of the compensation capacitor can be selected through digital logic control to compensate the frequency point in the system, so as to adjust the position of the zero-pole, realize the adjustment of the-3dB bandwidth of the loop under different output voltages, and finally realize the adjustment of the transient response time. The-3dB bandwidth and the transient response time under different output voltages can also be kept unchanged by changing the compensation capacitor.

[0166] Optionally, the digital control resistance voltage division array comprises:

[0167] The second multipath control signal generating unit and the voltage division resistance selection unit.

[0168] The input end of the second multipath control signal generating unit is connected with the second external control signal, and the output end is connected with the control end of the voltage division resistance selection unit.

[0169] The first end of the voltage division resistance selection unit is connected with the drain of the power transistor MP0, the second end is connected with the positive input end of the error amplifier EA0, and the third end is connected with the ground.

[0170] The second multipath control signal generating unit is configured to generate and output a plurality of second internal control signals according to a second external control signal, and transmit the plurality of second internal control signals to the voltage dividing resistor selecting unit.

[0171] The voltage dividing resistor selecting unit is configured to form different voltage dividing circuits according to the plurality of second internal control signals, so as to generate different output voltages V OUT .

[0172] Optionally, the digital control resistor voltage dividing array can also be implemented in other manners, which can generate different output voltages by changing the resistance values.

[0173] Figure 4 A structure diagram of the digital control resistor voltage dividing array is provided.

[0174] Optionally, referring to Figure 4 The second multipath control signal generating unit comprises a 3-8 decoder U2.

[0175] The voltage dividing resistor selecting unit comprises resistors R1, R2, R3, R4, R5, R6, R7, R8, R9 and R10, and NMOS transistors T0, T1, T2, T3, T4, T5, T6 and T7.

[0176] The first to eighth output terminals of the 3-8 decoder U2 are respectively connected to the gate electrodes of the NMOS transistors T0-T7.

[0177] The first to eighth output terminals of the 3-8 decoder U2 respectively output signals X0, X1, X2, X3, X4, X5, X6 and X7.

[0178] The drain electrodes of the NMOS transistors T0-T7 are respectively connected to the first ends of the resistors R1-R8.

[0179] The source electrodes of the NMOS transistors T0-T7 are all connected to the first end of the resistor R9.

[0180] The resistors R1-R10 are connected in series, and the second end of the resistor R1 is connected to the first end of the resistor R2.

[0181] The first end of the resistor R1 is connected to the drain electrode of the power transistor MP0.

[0182] The second end of the resistor R9 is connected to the positive input terminal of the error amplifier EA0.

[0183] The second end of the resistor R10 is connected to the ground.

[0184] 3-8 decoder U2 inputs A0-A2 three-bit binary code, and outputs eight control signals X0-X7, then through eight control signals X0-X7, the on-off state of eight NMOS tubes is controlled respectively, and then the resistance value in the feedback loop is controlled, so that the LDO generates different output voltages, and the function of programmable output voltage is realized.

[0185] It can be understood that the second multipath control signal generating unit can also be implemented in other ways, such as a 2-4 decoder, a 4-16 decoder, etc., which can generate multipath control signals. At the same time, the voltage dividing resistor selection unit should also be adjusted accordingly according to the specific implementation mode of the second multipath control signal generating unit.

[0186] The application also provides an LDO chip with fast response and adjustable transient response, comprising any of the above LDO circuits with fast response and adjustable transient response.

[0187] The terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0188] The above is a further detailed description of the application in combination with specific preferred embodiments, and the specific implementation of the application cannot be limited to these descriptions. For ordinary skilled persons in the technical field to which the application belongs, a number of simple deductions or substitutions can be made without departing from the concept of the application, and all of them should be regarded as falling within the protection scope of the application.

Claims

1. An LDO circuit having fast response and adjustable transient response, characterized in that, The application relates to an LDO circuit, comprising: an error amplifier EA0, a power transistor MP0, a low-gain stage module, a compensation capacitor selector, a digital control resistance voltage divider array and a transient enhancement circuit; a negative input terminal of the error amplifier EA0 is connected with a voltage Vref, a positive input terminal is connected with a first terminal of the digital control resistance voltage divider array and a first terminal of the transient enhancement circuit respectively, a power supply terminal is connected with a voltage Vin, and an output terminal is connected with a second terminal of the low-gain stage module and a first terminal of the compensation capacitor selector respectively; a first terminal of the low-gain stage module is connected with an input signal Vb1, a third terminal is connected with ground, a fourth terminal is connected with a gate of the power transistor MP0 and a fifth terminal of the transient enhancement circuit respectively, and a fifth terminal is connected with a power supply Vin; a source of the power transistor MP0 is connected with the power supply Vin, and a drain is connected with a second terminal of the compensation capacitor selector and a fourth terminal of the digital control resistance voltage divider array respectively; a third terminal of the compensation capacitor selector is connected with a first external control signal; third terminals of the digital control resistance voltage divider array are connected with second external control signals respectively, and a second terminal is connected with ground; a second terminal of the transient enhancement circuit is connected with a voltage Vref1, a third terminal is connected with an input signal Vb2, a fourth terminal is connected with ground, and a sixth terminal is connected with the power supply Vin; the compensation capacitor selector is used for providing a capacitor with a corresponding capacitance value for an output terminal of the error amplifier EA0 and a drain of the power transistor MP0 according to the first external control signal; the digital control resistance voltage divider array is used for controlling a resistance value of a feedback resistance in the LDO circuit according to the second external control signal, so as to generate a corresponding output voltage; the transient enhancement circuit is used for adjusting a gate voltage of the power transistor MP0 according to a feedback voltage between the error amplifier EA0 and the digital control resistance voltage divider array.

2. The circuit of claim 1, wherein, The transient enhancement circuit comprises an error amplifier EA1, a discharging circuit and a charging circuit. a positive input terminal of the error amplifier EA1 is a first terminal of the transient enhancement circuit, a negative input terminal is a second terminal of the transient enhancement circuit, a negative output terminal is connected with a first terminal of the discharging circuit and a first terminal of the charging circuit respectively, and a positive output terminal is connected with a second terminal of the discharging circuit and a second terminal of the charging circuit respectively; a third terminal of the discharging circuit is a third terminal of the transient enhancement circuit, and a fourth terminal is connected with ground; a third terminal of the charging circuit is a third terminal of the transient enhancement circuit, a fourth terminal is connected with ground, a fifth terminal is a fifth terminal of the transient enhancement circuit, and a sixth terminal is a sixth terminal of the transient enhancement circuit; the discharging circuit is used for pulling down a gate voltage of the power transistor MP0; the charging circuit is used for pulling up the gate voltage of the power transistor MP0.

3. The circuit of claim 2, wherein, The discharging circuit comprises PMOS transistors MP3 and MP4 and NMOS transistors MN1, MN2 and MN3. a gate of MN1 is a third terminal of the discharging circuit and is connected with a gate of MN2, a source is connected with ground, and a drain is connected with a drain and a gate of MP3 and a gate of MP4 respectively; a source of MP3 is a second terminal of the discharging circuit. The source of the MP4 is the first end of the discharging circuit, and the drain is connected to the gate of MN3 and the drain of MN2 respectively; The drain of MN3 is the fifth end of the discharging circuit, and the source is grounded; The source of MN2 is grounded.

4. A circuit according to claim 2 or 3, characterised in that, The charging circuit comprises PMOS tubes MP5, MP6, MP7, MP8 and NMOS tubes MN4, MN5, MN6; The gate of MN4 is the third end of the charging circuit and is connected to the gate of MN5, the source is grounded, and the drain is connected to the drain and gate of MP5 and the gate of MP6 respectively; The source of MN5 is grounded, and the drain is connected to the gate of MN6 and the drain of MP6 respectively; The source of MN6 is grounded, and the drain is connected to the drain and gate of MP7 and the gate of MP8 respectively; The source of MP7 is the sixth end of the charging circuit; The drain of MP8 is the fifth end of the charging circuit, and the source is connected to the source of MP7; The source of MP6 is the second end of the charging circuit; The source of MP5 is the first end of the charging circuit.

5. The circuit of claim 1, wherein, The low-gain stage module comprises PMOS tubes MP1 and MP2; The gate of MP1 is the first end of the low-gain stage module, the source is the fifth end of the low-gain stage module, and the drain is the fourth end of the low-gain stage module; The gate of MP2 is the second end of the low-gain stage module, the source is connected to the drain of MP1, and the drain is grounded.

6. The circuit of claim 5, wherein, The compensation capacitor selector comprises a first multi-control signal generation unit and a capacitor selection unit; The input end of the first multi-control signal generation unit is connected to the first external control signal, and the output end is connected to the control end of the capacitor selection unit; The first input and output end of the capacitor selection unit is connected to the output end of the error amplifier EA0, and the second input and output end is connected to the drain of the power tube MP0; The first multi-control signal generation unit is configured to generate and output a plurality of first internal control signals according to the first external control signal, and transmit the plurality of first internal control signals to the capacitor selection unit; The capacitor selection unit is configured to provide a capacitor with a corresponding capacitance between the output end of the error amplifier EA0 and the drain of the power tube MP0 according to the plurality of first internal control signals.

7. The circuit of claim 6, wherein, The first multi-control signal generation unit comprises a 3-8 decoder U1 and NAND gates F0, F1, F2, F3, F4, F5, F6, and F7; The capacitor selection unit comprises capacitors C0, C1, C2, C3, C4, C5, C6, and C7, and switches S0, S1, S2, S3, S4, S5, S6, and S7; The 1st-8th output ends of the 3-8 decoder U1 are respectively connected to the input ends of the NAND gates F0-F7; The input ends of the NAND gates F0-F7 are respectively connected to the forward control ends of the switches S0-S7; The output ends of the NAND gates F0-F7 are respectively connected to the reverse control ends of the switches S0-S7; The first input and output ends of the switches S0-S7 are respectively connected to the second ends of the capacitors C0-C7; The second input and output ends of the switches S0-S7 are all connected to the output end of the error amplifier EA0; The first end of the capacitor C0 is connected with the drain of the power transistor MP0, the capacitors C0-C7 are connected in series, and the second end of the capacitor C0 is connected with the first end of the capacitor C1.

8. The circuit of claim 5 or 6, wherein, The digital control resistance voltage dividing array comprises a second multipath control signal generation unit and a voltage dividing resistance selection unit. The input end of the second multipath control signal generation unit is connected with the second external control signal, and the output end is connected with the control end of the voltage dividing resistance selection unit. The first end of the voltage dividing resistance selection unit is connected with the drain of the power transistor MP0, the second end is connected with the positive input end of the error amplifier EA0, and the third end is connected with the ground. The second multipath control signal generation unit is configured to generate and output a plurality of second internal control signals according to the second external control signal, and transmit the plurality of second internal control signals to the voltage dividing resistance selection unit. The voltage dividing resistance selection unit is configured to form different voltage dividing circuits according to the plurality of second internal control signals, so as to change the resistance value of the feedback resistance in the LDO circuit to generate different output voltages.

9. The circuit of claim 8, wherein, The second multipath control signal generation unit comprises a 3-8 decoder U2. The voltage dividing resistance selection unit comprises resistors R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, and NMOS transistor switches T0, T1, T2, T3, T4, T5, T6, T7. The 1st-8th output ends of the 3-8 decoder U2 are respectively connected with the gates of the NMOS transistor switches T0-T7. The drains of the NMOS transistor switches T0-T7 are respectively connected with the first ends of the resistors R1-R8. The sources of the NMOS transistor switches T0-T7 are all connected with the first end of the resistor R9. The resistors R1-R10 are connected in series, and the second end of the resistor R1 is connected with the first end of the resistor R2. The first end of the resistor R1 is connected with the drain of the power transistor MP0. The second end of the resistor R9 is connected with the positive input end of the error amplifier EA0. The second end of the resistor R10 is connected with the ground.

10. An LDO chip with fast response and adjustable transient response, characterized in that, The LDO circuit with fast response and adjustable transient response comprises the LDO circuit with fast response and adjustable transient response according to any one of claims 1-9.

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