A method for preparing a light-emitting element and a light-emitting element

Abstract

The present invention provides a method for preparing a light-emitting element, wherein a Ni / Al metal layer structure is evaporated on the surface of a P-type semiconductor layer to form a Ni / Al reflective electrode; a Ni / Au metal layer structure is evaporated on the surface of the P-type semiconductor layer and above the Ni / Al reflective electrode to form a Ni / Au ohmic contact electrode, so as to form a separated P-surface electrode structure. Among them, Ni / Au is used as an ohmic contact electrode, and Ni / Al is used as a reflective electrode structure. Compared with conventional Ni / Au reflective electrodes, this new P-surface reflective electrode has a higher reflectivity; compared with conventional Ni / Al reflective electrodes, this new P-surface reflective electrode has better ohmic contact performance. The present invention proposes a separated P-surface electrode structure, wherein separated Ni / Al is used as a reflective metal layer to improve light reflectivity, and covered Ni / Au is used as an ohmic contact metal to reduce contact barriers. By adopting this separated P-surface electrode structure, the above-mentioned ohmic contact barrier and reflectivity performance can be effectively balanced, thereby improving the luminous efficiency of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a light-emitting element and the light-emitting element. Background Art

[0002] Ultraviolet LED (UV LED) is mainly used in biomedicine, anti-counterfeiting identification, purification (water, air, etc.), computer data storage and military, etc. Moreover, with the development of technology, new applications will continue to emerge to replace the original technology and products, and UV LED has a broad market application prospect.

[0003] At present, the main problems of UV flip-chip LED chips are low P-side current injection efficiency and low P-side light reflectivity. The main reason for the low P-side current injection efficiency is that the general metal work function is lower than that of P-type GaN, and it is impossible to form an ohmic contact electrode. Therefore, high-work-function Ni / Au electrodes are generally used as P-side contact electrodes. After high-temperature annealing, the contact barrier can be effectively reduced. But at the same time, the Ni / Au contact electrode has a very low reflectivity for ultraviolet light, which has a great impact on the LED light extraction efficiency. On the other hand, for the problem of low P-side reflectivity, among common metals, Al metal has a relatively high reflectivity for ultraviolet light. Therefore, Al metal is generally used as the P-side reflective electrode, but the Al metal work function is low. Although a thin layer of Ni metal is added, Al is easily oxidized after annealing and Al will migrate to the GaN surface, resulting in its contact barrier still being very high, affecting the voltage of the LED. The problems of high contact barrier and low reflectivity cannot be solved at the same time. Summary of the invention

[0004] The main purpose of the present invention is to provide a method for preparing a light-emitting element and a light-emitting element, aiming to improve the defects in the prior art. To achieve the above purpose, the present invention provides a method for preparing a light-emitting element, comprising the following steps:

[0005] A buffer layer, an N-type semiconductor layer, a quantum well layer, and a P-type semiconductor layer are sequentially grown on the substrate;

[0006] Etching through the P-type semiconductor layer and the quantum well layer to form a groove;

[0007] Preparing an N-type electrode at the groove;

[0008] Vapor depositing a Ni / Al metal layer structure on the surface of the P-type semiconductor layer to form a Ni / Al reflective electrode;

[0009] Vapor depositing a Ni / Au metal layer structure on the surface of the P-type semiconductor layer and above the Ni / Al reflective electrode to form a Ni / Au ohmic contact electrode;

[0010] Vapor depositing a layer of protective metal on the Ni / Au ohmic contact electrode and the N-type electrode;

[0011] depositing a first passivation layer over the epitaxial region;

[0012] Vapor depositing a layer of sidewall reflective metal structure on the first passivation layer;

[0013] coating a second passivation layer over the epitaxial region;

[0014] A metal pad is formed on the etching area of ​​the second passivation layer by evaporation.

[0015] Optionally, preparing an N-type electrode at the groove comprises the following steps:

[0016] Perform photolithography on the wafer and expose the area outside the N-type electrode;

[0017] The wafer is baked, and after baking, the photoresist above the N-type electrode area is dissolved using a developer;

[0018] After development, the photoresist with the pattern is subjected to plasma bombardment;

[0019] First, evaporate or magnetron sputter the N electrode metal, and then perform stripping and degumming operations;

[0020] The patterned N-electrode metal is annealed.

[0021] Optionally, the step of evaporating a Ni / Al metal layer structure on the surface of the P-type semiconductor layer to form a Ni / Al reflective electrode includes:

[0022] Performing photolithography on the wafer and exposing the area outside the Ni / Al metal layer;

[0023] The wafer is baked, and after baking, a developer is used to dissolve the photoresist above the Ni / Al metal layer area;

[0024] After development, the photoresist with the pattern is subjected to plasma bombardment;

[0025] First, evaporate or magnetron sputter the Ni / Al metal layer, and then perform the stripping and degumming operation.

[0026] Optionally, the step of evaporating a Ni / Au metal layer structure on the surface of the P-type semiconductor layer and above the Ni / Al reflective electrode to form a Ni / Au ohmic contact electrode includes:

[0027] Performing photolithography on the wafer and exposing the area outside the Ni / Au metal layer;

[0028] The wafer is baked, and after baking, the photoresist above the Ni / Au metal layer area is dissolved using a developer;

[0029] After development, the photoresist with the pattern is subjected to plasma bombardment;

[0030] First, evaporate or magnetron sputter the Ni / Au metal layer, and then perform stripping and degumming operations;

[0031] The patterned Ni / Al metal layer and the Ni / Au metal layer are annealed.

[0032] Optionally, the step of evaporating a layer of protective metal on the Ni / Au ohmic contact electrode and the N-type electrode comprises:

[0033] Performing photolithography on the wafer and exposing the area outside the protective metal;

[0034] The wafer is baked, and after baking, a developer is used to dissolve the photoresist above the protective metal area;

[0035] After development, the photoresist with the pattern is subjected to plasma bombardment;

[0036] First, evaporate or magnetron sputter the protective metal, and then perform the stripping and degumming operation.

[0037] Optionally, the step of plating a first passivation layer above the epitaxial region comprises:

[0038] Depositing a passivation film on the wafer and photolithography the wafer;

[0039] Exposing the protective electrode area that needs to be exposed;

[0040] Use a developer to dissolve the photoresist above the protective electrode area to be exposed, and perform hard baking after development;

[0041] Etching the passivation film on the protective electrode area to be exposed;

[0042] The wafer is subjected to a debonding operation so that the required passivation layer structure with patterns is retained to form the first passivation layer.

[0043] Optionally, the step of evaporating a layer of sidewall reflective metal structure on the first passivation layer includes:

[0044] Performing a photolithography process on the wafer and exposing the area outside the sidewall reflective metal structure;

[0045] The wafer is baked, and after baking, a developer is used to dissolve the photoresist above the sidewall reflective metal structure area;

[0046] After development, the photoresist with the pattern is subjected to plasma bombardment;

[0047] First, evaporate or magnetron sputter the side wall reflective metal structure, and then perform the stripping and degumming operation.

[0048] Optionally, the step of coating a second passivation layer on the epitaxial region comprises:

[0049] Apply a layer of adhesion promoter on the wafer, and then deposit a layer of passivation film on the wafer;

[0050] Exposing the protective electrode area that needs to be exposed;

[0051] Use a developer to dissolve the photoresist above the protective electrode area to be exposed, and perform hard baking after development;

[0052] Etching the passivation film on the protective electrode area to be exposed;

[0053] The wafer is stripped so that the required patterned passivation layer structure is retained to form the second passivation layer.

[0054] Optionally, the step of forming a metal pad by evaporation above the etching area of ​​the second passivation layer includes:

[0055] Performing photolithography on the wafer and exposing the area outside the metal pad;

[0056] The wafer is baked, and after baking, the photoresist above the metal pad area is dissolved using a developer;

[0057] After development, the photoresist with the pattern is subjected to plasma bombardment;

[0058] First, evaporate the metal pad, and then perform the stripping and debonding operation.

[0059] In addition, to achieve the above-mentioned purpose, the present invention also proposes a light-emitting element, including a substrate, a buffer layer, an N-type semiconductor layer, a quantum well layer, a P-type electron blocking layer, and a P-type semiconductor layer, wherein a separated P-surface reflective electrode structure is formed on the P-type semiconductor layer, and the P-surface reflective electrode structure includes a Ni / Au ohmic contact electrode and a plurality of Ni / Al reflective electrodes, wherein the plurality of Ni / Al reflective electrodes are distributed at intervals on the P-type semiconductor layer, and the Ni / Au ohmic contact electrode is arranged on the P-type semiconductor layer and wraps the Ni / Al reflective electrode.

[0060] In the technical solution provided by the present invention, a Ni / Al reflective electrode is formed by evaporating a Ni / Al metal layer structure on the surface of a P-type semiconductor layer; a Ni / Au metal layer structure is evaporated on the surface of the P-type semiconductor layer and above the Ni / Al reflective electrode to form a Ni / Au ohmic contact electrode, and then a layer of protective metal is evaporated above the Ni / Au ohmic contact electrode and the N-type electrode to form a separated P-surface electrode structure. Among them, Ni / Au is used as an ohmic contact electrode and Ni / Al is used as a reflective electrode structure. Compared with conventional Ni / Au reflective electrodes, this new P-surface reflective electrode has a higher reflectivity; compared with Ni / Al reflective electrodes, this new P-surface reflective electrode has better ohmic contact performance; and the overall comprehensive performance is better.

[0061] The present invention proposes a separated P-surface electrode structure, wherein separated Ni / Al is used as a reflective metal layer to improve light reflectivity, and covered Ni / Au is used as an ohmic contact metal to reduce the contact barrier. The separated P-surface electrode structure can effectively balance the above-mentioned ohmic contact barrier and reflectivity performance, thereby improving the luminous efficiency of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0063] Figure 1 A schematic diagram of the overall structure of an embodiment of a light emitting element provided by the present invention;

[0064] Figure 2 for Figure 1 A schematic diagram of the structure of the N-type electrode of the light-emitting element;

[0065] Figure 3 for Figure 1 Schematic diagram of the structure of the Ni / Al reflective electrode of the light-emitting element;

[0066] Figure 4 for Figure 1 Schematic diagram of the structure of the Ni / Au ohmic contact electrode of the light-emitting element;

[0067] Figure 5 for Figure 1 A schematic diagram of the structure of the protective metal of the light-emitting element;

[0068] Figure 6 for Figure 1 A schematic structural diagram of the first passivation layer of the light-emitting element;

[0069] Figure 7 for Figure 1 A schematic diagram of the structure of the side wall reflective metal structure of the light emitting element;

[0070] Figure 8 for Figure 1 A schematic structural diagram of the second passivation layer of the light-emitting element;

[0071] Fig. 9 This is a comparison chart of the reflectivity of Ni / Al and Ni / Au.

[0072] Description of Figure Numbers:

[0073] Label name Label name 01 Light-emitting components 11 First passivation layer 1 Substrate 12 Side wall reflective metal structure 2 Buffer layer 13 Second passivation layer 3 N-type semiconductor layer 14 Pads 4 Quantum Well Layer 5 P-type electron blocking layer 6 P-type semiconductor layer 7 N-type electrode 8 Ni / Al reflective electrode 9 Ni / Au ohmic contact electrode 10 Protecting Metal

[0074] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0075] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings. The technical solution in the present invention is clearly and completely described. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0076] Below, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of embodiments of the present invention. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of concepts of the present invention.

[0077] The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0078] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification, and should not be interpreted in an idealized or overly rigid manner.

[0079] In the case of using expressions such as "at least one of A, B, and C, etc.", it should generally be interpreted in accordance with the meaning of the expression generally understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.). In the case of using expressions such as "at least one of A, B, or C, etc.", it should generally be interpreted in accordance with the meaning of the expression generally understood by those skilled in the art (for example, "a system having at least one of A, B, or C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0080] It should be noted that if a directional indication is involved in the embodiment of the present invention, the directional indication is only used to explain the relative position relationship, movement status, etc. between the components in a certain specific posture. If the specific posture changes, the directional indication will also change accordingly.

[0081] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the meaning of "and / or" appearing in the full text includes three parallel schemes. Taking "A and / or B" as an example, it includes scheme A, or scheme B, or a scheme that satisfies both A and B. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary technicians in this field to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0082] In the description of the present invention, it should be noted that the terms "upper", "lower", "top", "bottom", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present invention.

[0083] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0084] Furthermore, in the description of the present invention, unless otherwise specified, “plurality”, “multiple roots”, and “multiple groups” mean two or more.

[0085] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0086] At present, the main problems of UV flip-chip LED chips are low P-side current injection efficiency and low P-side light reflectivity. The main reason for the low P-side current injection efficiency is that the general metal work function is lower than that of P-type GaN, and it is impossible to form an ohmic contact electrode. Therefore, high-work-function Ni / Au electrodes are generally used as P-side contact electrodes. After high-temperature annealing, the contact barrier can be effectively reduced. But at the same time, the Ni / Au contact electrode has a very low reflectivity for ultraviolet light, which has a great impact on the LED light extraction efficiency. On the other hand, for the problem of low P-side reflectivity, among common metals, Al metal has a relatively high reflectivity for ultraviolet light. Therefore, Al metal is generally used as the P-side reflective electrode, but the Al metal work function is low. Although a thin layer of Ni metal is added, Al is easily oxidized after annealing and Al will migrate to the GaN surface, resulting in its contact barrier still being very high, affecting the voltage of the LED. The problems of high contact barrier and low reflectivity cannot be solved at the same time.

[0087] Therefore, the present invention proposes a separated P-side electrode structure, wherein separated Ni / Al is used as a reflective metal layer to improve light reflectivity, and covered Ni / Au is used as an ohmic contact metal to reduce the contact barrier. The use of this separated P-side electrode structure can effectively balance the above-mentioned ohmic contact barrier and reflectivity performance, thereby improving the luminous efficiency of the device.

[0088] See also Figure 1-Figure 8 The present invention provides a method for preparing a light-emitting element and a light-emitting element 01. The method for preparing the light-emitting element 01 comprises the following steps:

[0089] Step S10: growing a buffer layer 2 , an N-type semiconductor layer 3 , a quantum well layer 4 , and a P-type semiconductor layer 6 in sequence on the substrate 1 .

[0090] Step S20: etching through the P-type semiconductor layer 6 and the quantum well layer 4 to form a groove.

[0091] Step S30: preparing an N-type electrode 7 at the groove.

[0092] Step S40 : evaporating a Ni / Al metal layer structure on the surface of the P-type semiconductor layer 6 to form a Ni / Al reflective electrode 8 .

[0093] Step S50 : evaporating a Ni / Au metal layer structure on the surface of the P-type semiconductor layer and above the Ni / Al reflective electrode to form a Ni / Au ohmic contact electrode 9 .

[0094] Step S60 : vapor-depositing a layer of protective metal 10 on the Ni / Au ohmic contact electrode 9 and the N-type electrode 7 .

[0095] Step S70: plating a first passivation layer 11 on the epitaxial region.

[0096] Step S80: evaporating a layer of sidewall reflective metal structure 12 on the first passivation layer.

[0097] Step S90: depositing a second passivation layer 13 on the epitaxial region.

[0098] Step S100: forming a metal pad 14 on the etched area of ​​the second passivation layer 13 by evaporation.

[0099] In this embodiment, the substrate material of the semiconductor device is also called the substrate material, and the epitaxial layers are all grown on the substrate material. There are many types of LED substrate materials, which can be sapphire, gallium nitride (GaN), silicon (Si) or silicon carbide (SiC). In this embodiment, a sapphire substrate is used, which has the advantages of good chemical stability, no absorption of visible light, and good light transmittance. A buffer layer and a light-emitting structure are grown on a sapphire substrate by metal organic chemical vapor deposition technology (Metal Organic Chemical VaporDeposition). The light-emitting structure includes a buffer layer 2, an N-type semiconductor layer 3, a quantum well layer 4, a P-type electron blocking layer 5, and a P-type semiconductor layer 6, which are sequentially formed on a substrate 1. The buffer layer can be aluminum nitride (AlN) or aluminum gallium nitride (AlGaN).

[0100] See also Figure 2The P-type semiconductor layer 6 (P-GaN), the P-type electron blocking layer 5 (P-AlGaN) and the quantum well layer 4 are etched to obtain a groove (MESA), which exposes the N-AlGaN layer in order to prepare an N-type electrode 7 thereon. Figure 2 The etching process uses inductively coupled plasma (ICP) etching, the etching gas is chlorine (Cl2), carbon tetrafluoride (CF4) or a mixed gas thereof, the pressure is 1 to 1000 mTorr, and the upper and lower radio frequency (RF) powers are 1 to 1000W.

[0101] See also Figure 2 , magnetron sputtering or electron beam (E-Beam) is used to evaporate the N-type electrode 7 on the N-AlGaN surface, and its electrode structure is a Ti / Al / Ti / Au metal layer. The Ti metal work function in the N-type electrode junction 7 is low and has good adhesion, which is relatively advantageous in the N-type ohmic contact. To ensure a sufficiently high transmittance, its thickness is generally controlled at 1nm to 10nm. The reflectivity of the Al metal in the N-type electrode 7 is as high as 92%. As the N-face reflective metal, the thickness is 50nm to 200nm. The Ti / Au capping layer in the N-type electrode 7 can prevent the Al metal from being oxidized during the annealing process of the N-type electrode 7 and the subsequent etching process; the magnetron sputtering conditions are power 10W to 1000W, the gas used is argon (Ar2), and the pressure is 1mTorr to 1000mTorr. The electron beam (E-Beam) evaporation conditions are power 1W to 50W and pressure 1mTorr to 10mTorr.

[0102] The purpose of annealing the N-type electrode 7 is to form a good ohmic contact between the N-type electrode 7 and the N-AlGaN. The annealing process of the N-type electrode 7 is to use RTA or a furnace tube to anneal for 1 to 10 minutes at 800°C to 950°C and 1 to 1000 mTorr of nitrogen atmosphere. The purpose of using pure nitrogen is to prevent the Al metal in the N-type electrode 7 from being oxidized, resulting in poor ohmic contact performance.

[0103] See also Figure 3 , on the surface of P-GaN, a Ni / Al metal layer structure is deposited on the P-type gallium nitride position above the epitaxial wafer by magnetron sputtering or electron beam (E-Beam) evaporation, and a periodic array structure is formed through photolithography, with a width of 10um to 60um, an interval of 5um to 20um, and generally 2 to 10 cycles. Figure 3As shown, the metal structure is used as a Ni / Al reflective electrode 8. The Ni thickness of the Ni / Al reflective electrode 8 is 1nm to 5nm, and its function is to form an ohmic contact with P-GaN during the annealing process. The Al thickness is 10nm to 200nm, and its function is to reflect the metal layer. The reflectivity of the Ni / Al reflective electrode 8 of this structure reaches more than 80%, which is much higher than the Ni / Au reflective electrode under the same thickness condition. The magnetron sputtering conditions are power 10W to 1000W, the gas used is argon, and the pressure is 1mTorr to 1000mTorr. The electron beam (E-Beam) evaporation conditions are power 1W to 50W and pressure 1mTorr to 10mTorr.

[0104] See also Figure 4 , a Ni / Au metal layer structure is deposited on the surface of P-GaN and above the Ni / Al reflective electrode 8 by magnetron sputtering or electron beam (E-Beam). The metal structure, as the Ni / Au ohmic contact electrode 9, should cover the entire Ni / Al reflective electrode 8 and protect the Ni / Al reflective electrode 8 during the annealing process to prevent the Al metal in the Ni / Al reflective electrode 8 from being oxidized. Figure 4 As shown, in the Ni / Au ohmic contact electrode 9 structure, the Ni thickness is 1nm to 10nm, and its work function is 5eV, the Au thickness is 10nm to 200nm, and its work function is 5.25eV, so Ni / Au has a higher work function as a whole, and after annealing, it can form a good ohmic contact with P-GaN. The magnetron sputtering conditions are a power of 10W to 1000W, the gas used is argon, and the pressure is 1mTorr to 1000mTorr. The electron beam (E-Beam) evaporation conditions are a power of 1W to 50W and a pressure of 1mTorr to 10mTorr. In addition, some metals can be added above the P-surface reflective electrode and the P-surface ohmic contact electrode to improve the stability of the electrode structure, such as Ti, Pt, Cr, Cu, etc. and their alloys.

[0105] The Ni / Au ohmic contact electrode 9 is annealed to form a good ohmic contact between the Ni / Au ohmic contact electrode 9 and P-GaN. The Ni / Au ohmic contact electrode 9 is annealed using RTA or a furnace tube at 400°C to 650°C, an atmosphere pressure of 1 to 1000 mTo, an annealing atmosphere of a nitrogen and oxygen mixed gas, and an annealing time of 1 to 10 minutes. Nitrogen is added during the annealing process to prevent the Al layer metal in the Ni / Al reflective electrode 8 from being oxidized.

[0106] See also Figure 5 , a protective metal layer 10 is continuously evaporated on the Ni / Au ohmic contact electrode 9 and the Ni / Al reflective electrode 8, such as Figure 5As shown, the protective metal 10 can be Ti / Pt, the evaporation power is 1W~50W, the Ti metal is used as an adhesion layer, and its thickness is 1~10nm, the Pt metal has poor chemical activity and can be used as a barrier layer, and its thickness is 10nm~400nm. The purpose of the protective layer metal 10 is to protect the underlying Ni / Au ohmic contact electrode 9 and Ni / Al reflective electrode 8 to prevent them from being etched or oxidized during the subsequent passivation layer etching process.

[0107] See also Figure 6 A first passivation layer 11 (PV1) is deposited on the entire epitaxial region by PECVD (plasma enhanced chemical vapor deposition) or ALD (atomic layer deposition). The first passivation layer 11 (PV1) can be SiO2, SiN x , Al2O3 or a mixed structure thereof, with a thickness of 2000 angstroms to 10000 angstroms. The purpose of the passivation layer is to isolate the P electrode and the N electrode to prevent the direct interconnection of the PN electrodes from causing chip failure. The PECVD process conditions are SiH4 flow rate 50sccm to 200sccm, N2O flow rate 5sccm to 100sccm, chamber pressure 1mTorr to 100mTorr, and RF power 1W to 100W. After the photolithography process, the passivation layer above the Ni / Al reflective electrode and the N-type reflective electrode is etched away by dry etching or wet etching. The dry etching uses ICP or RIE (reactive plasma etching), the etching gas is CF4, the pressure is 1 to 1000mTorr, and the upper and lower RF powers are 1 to 1000W; the wet process uses BOE solution (49% HF aqueous solution: 40% NH4F = 6:1), in which HF is used as an etching solution, NH4F is used as a buffer, and the etching rate is 6nm / s. In order to ensure that there is no passivation layer residue at the bottom during the etching process, it is necessary to over-etch by 20% to 40%. After the etching is completed, the desired patterned passivation layer structure can be obtained by removing the glue.

[0108] See also Figure 7 A sidewall reflective metal structure 12 is deposited on the first passivation 11 to reflect the light emitted from the MESA sidewall back to the N region to improve the light extraction efficiency of the chip. The sidewall reflective metal structure is Ti / Al / Ti / Pt. Figure 7 As shown, Ti metal is used as an adhesion layer with a thickness of 1nm to 10nm, which can effectively prevent the metal from easily falling off on the dielectric film. Al metal is used as a reflective metal with a reflectivity of more than 80%, which can effectively reflect the light emitted from the MESA side wall. Pt metal is used as a barrier layer to prevent etching or oxidation of the underlying metal during the subsequent passivation layer etching process. The evaporation process conditions are power 1W to 50W and vacuum pressure 1mTorr to 100mTorr.

[0109] See also Figure 8A second passivation layer 13 (PV2) is deposited on the entire epitaxial region by PECVD (plasma enhanced chemical vapor deposition) or ALD (atomic layer deposition). The second passivation layer 13 can be SiO2, SiN x , Al2O3 or a mixed structure thereof, with a thickness of 5000 angstroms to 15000 angstroms, and the process conditions are the same as above. The purpose of the second passivation layer 13 is to isolate the PN pads to prevent the PN pads from interconnecting and causing chip failure. After the second passivation layer is plated, the second passivation layer 13 above the PN electrode is etched away by photolithography and etching processes, and the etching process conditions are the same as the above wet etching process. After the etching is completed, the glue is removed to obtain a patterned second passivation layer 13 structure.

[0110] A metal pad 14 is formed by evaporation above the etching area of ​​the second passivation layer 13. The metal pad 14 is an AuSn alloy pad. Its purpose is to facilitate chip wire bonding or electrode welding, and to introduce external current into the chip. At the same time, the large pad helps the chip to dissipate heat and improve the chip's optoelectronic performance and reliability. The mass ratio of Au to Sn in the AuSn evaporation target is 82:18; the evaporation power is 10W to 50W, and the vacuum pressure is 1mTorr to 100mTorr.

[0111] The present invention adopts a separated P-surface electrode structure, in which Ni / Au is used as an ohmic contact electrode and Ni / Al is used as a reflective electrode structure. Compared with the single Ni / Au and Ni / Al electrode structures, its comprehensive performance is better. Fig. 9 As shown, near 280nm, the reflectivity of Ni(1nm) / Au(100nm) is only 20%, while the reflectivity of Ni(1nm) / Al(100nm) reaches 80%. Therefore, compared with the traditional Ni / Au electrode, the Ni / Al reflective electrode has a higher light extraction efficiency for the flip-chip UV LED chip.

[0112] Furthermore, in this embodiment, step S30 includes the following steps:

[0113] Step S301: photolithography is performed on the wafer, and the area outside the N-type electrode 7 is exposed.

[0114] Step S302: baking the wafer, and after baking, using a developer to dissolve the photoresist above the N-type electrode 7 region.

[0115] Step S303: after development, the photoresist with the pattern is subjected to plasma bombardment.

[0116] Step S304: first evaporate or magnetron sputter the N-electrode metal, and then perform a stripping and debonding operation.

[0117] Step S305: performing annealing on the patterned N-electrode metal.

[0118] In this embodiment, the first step is to use a negative photoresist to perform a photolithography process on the entire wafer, the thickness of the photoresist is 1 to 3um, the exposure dose is in the range of 100mJ to 300mJ, and the area outside the required N-type electrode 7 area is exposed; the second step is to perform a development process, bake before development, bake at 90℃ to 130℃, so that the photoresist cross-linking reaction is more sufficient, and the standing wave effect is suppressed at the same time, and the photoresist above the N-type electrode 7 area is dissolved with a developer after baking; the third step is to bombard the photoresist with patterns with O2 plasma after development to avoid incomplete development and deformation of the photoresist. The fourth step is to evaporate or magnetron sputter the N electrode metal. In comparison, the sputtered metal has a higher flatness than the evaporated metal, which is beneficial to the N-side reflection, and the sputtering process is recommended. The fifth step is to perform a stripping and de-bonding operation on the N-electrode metal that has been evaporated or sputtered, so that the required N-electrode metal with a pattern can be retained; the sixth step is to perform a high-temperature annealing operation on the patterned N-electrode metal, the temperature is 800℃~900℃, the gas is a mixed gas of N2 and O2, and the time is 30s~300s.

[0119] Further, in this embodiment, step S40 includes the following steps:

[0120] Step S401: performing photolithography on the wafer and exposing the area outside the Ni / Al metal layer.

[0121] Step S402: baking the wafer, and after baking, using a developer to dissolve the photoresist above the Ni / Al metal layer area.

[0122] Step S403: after development, the photoresist with the pattern is subjected to plasma bombardment.

[0123] Step S403: First, evaporate or magnetron sputter a Ni / Al metal layer, and then perform a stripping and debonding operation.

[0124] In this embodiment, the first step is to use a negative photoresist to perform a photolithography process on the entire wafer, the thickness of the photoresist is 1 to 3um, the exposure dose is in the range of 100mJ to 300mJ, and the area outside the Ni / Al reflective metal area is exposed; the second step is to perform a development process, bake before development, bake at 90℃ to 130℃, and use a developer to dissolve the photoresist above the required Ni / Al reflective metal area after baking; the third step is to bombard the photoresist with patterns with O2 plasma after development. The fourth step is to evaporate or magnetron sputter the Ni / Al metal layer. It is recommended to use a sputtering process to improve the reflectivity of the Ni / Al reflective metal surface. The fifth step is to strip and remove the Ni / Al reflective metal area that has been evaporated or sputtered, so that the required Ni / Al reflective metal with patterns can be retained.

[0125] Further, in this embodiment, step S50 includes the following steps:

[0126] Step S501: performing photolithography on the wafer and exposing the area outside the Ni / Au metal layer.

[0127] Step S502: baking the wafer, and after baking, using a developer to dissolve the photoresist above the Ni / Au metal layer area.

[0128] Step S503: after development, the photoresist with the pattern is subjected to plasma bombardment.

[0129] Step S504: performing annealing on the patterned Ni / Al metal layer and the Ni / Au metal layer.

[0130] In this embodiment, the first step is to use a negative photoresist to perform a photolithography process on the entire wafer, the thickness of the photoresist is 1 to 3um, the exposure dose is in the range of 100mJ to 300mJ, and the area outside the required Ni / Au metal area is exposed. It should be noted that the Ni / Au metal area needs to cover the entire Ni / Al reflective electrode area; the second step is to perform a development process, bake before development, bake at 90℃ to 130℃, and use a developer to dissolve the photoresist above the required Ni / Au metal area after baking; the third step is to bombard the photoresist with patterns with O2 plasma after development. The fourth step is to evaporate or magnetron sputter the Ni / Au metal structure. It is recommended to use a sputtering process to improve the reflectivity of the P surface. The fifth step is to perform a stripping and de-bonding operation on the Ni / Au metal structure that has been evaporated or sputtered, so that the required Ni / Au metal with a pattern can be retained; the sixth step is to perform a high-temperature annealing operation on the patterned Ni / Al reflective metal and Ni / Au metal, the temperature is 500℃~650℃, the gas is a mixture of N2 and O2, and the time is 200s~600s.

[0131] Further, in this embodiment, step S60 includes the following steps:

[0132] Step S601 : performing photolithography on the wafer and exposing the area outside the protective metal 10 .

[0133] Step S602: baking the wafer, and after baking, using a developer to dissolve the photoresist above the protective metal 10 area.

[0134] Step S603: after development, the photoresist with the pattern is subjected to plasma bombardment.

[0135] Step S604: first evaporate or magnetron sputter the protective metal 10, and then perform a stripping and debonding operation.

[0136] In this embodiment, the first step is to use a negative photoresist to perform a photolithography process on the entire wafer, the thickness of the photoresist is 1 to 3um, the exposure dose is in the range of 100mJ to 300mJ, and the area outside the required protective metal 10 area is exposed. Note that the protective metal 10 area must cover the entire Ni / Au ohmic contact electrode 9 area and the Ni / Al reflective electrode 8 area; the second step is to perform a development process, bake before development, bake at 90℃ to 130℃, and use a developer to dissolve the photoresist above the required Ni / Au ohmic contact electrode 9 area and the Ni / Al reflective electrode 8 area after baking; the third step is to bombard the photoresist with a pattern with O2 plasma after development. The fourth step is to evaporate or magnetron sputter the protective metal 10, and the protective layer metal 10 structure can be Ti / Ni or Ti / Pt and its laminated structure. The fifth step is to strip and remove the protective metal structure completed by evaporation or sputtering, so that the required protective metal 10 structure with a pattern can be retained.

[0137] Further, in this embodiment, step S70 includes the following steps:

[0138] Step S701: depositing a passivation film on the wafer and performing photolithography on the wafer.

[0139] Step S702: exposing the protective electrode area to be exposed.

[0140] Step S703: using a developer to dissolve the photoresist above the protective electrode area to be exposed, and performing hard baking after development.

[0141] Step S704: etching the passivation film on the protective electrode region to be exposed.

[0142] Step S705 : performing a resist stripping operation on the wafer so that the required patterned passivation layer structure is retained to form the first passivation layer 11 .

[0143] In this embodiment, the first step is to deposit a first passivation layer 11 on the entire wafer using PECVD (plasma enhanced chemical vapor deposition) or ALD (atomic layer deposition). The first passivation layer 11 is SiO2, SiN x , Al2O3 or a combination thereof, with a thickness in the range of 0.1 to 2 microns. SiN is recommended xOr Al2O3, the film is more dense and the passivation protection effect is better. The second step is to use positive photoresist to perform photolithography on the entire wafer. Due to the poor adhesion between the passivation layer and the photoresist, a layer of HDMS viscosity enhancer with a thickness of less than 1 to 10 nm is applied before coating; the third step is to select a photoresist thickness of 2 to 5um and an exposure dose of 100mJ to 300mJ according to the actual dry etching selection ratio, and expose the required exposed protection electrode area; the fourth step is to perform the development process, and use the developer to dissolve the photoresist above the required exposed protection electrode area; the fifth step is to perform hard baking after development to evaporate the solvent to prevent the photoresist from deforming. The sixth step is to use a dry etching process to etch the passivation layer above the required exposed protection electrode area. The etching gas selects strong oxidizing gases such as CF4 or BCl2, and the etching power is in the range of 100 to 2000W. In order to ensure that there is no passivation layer above the required exposed protection electrode area, the etching process generally adopts over-etching, and the over-etching ratio is 10% to 50%. In the sixth step, the wafer after etching is stripped so that the required patterned passivation layer structure can be retained.

[0144] Further, in this embodiment, step S80 includes the following steps:

[0145] Step S801: performing a photolithography process on the wafer, and exposing the area outside the sidewall reflective metal structure 12 .

[0146] Step S802: baking the wafer, and after baking, using a developer to dissolve the photoresist above the sidewall reflective metal structure 12 area.

[0147] Step S803: After development, the photoresist with the pattern is subjected to plasma bombardment.

[0148] Step S804: first evaporate or magnetron sputter the sidewall reflective metal structure 12, and then perform a stripping and debonding operation.

[0149] In this embodiment, the first step is to use a negative photoresist to perform a photolithography process on the entire wafer, the thickness of the photoresist is 1 to 3um, the exposure dose is in the range of 100mJ to 300mJ, and the area outside the desired sidewall reflective metal structure 12 is exposed; the second step is to perform a development process, bake before development, bake at 90℃ to 130℃, and use a developer to dissolve the photoresist above the desired sidewall reflective metal structure area after baking; the third step is to perform O2 plasma bombardment on the photoresist with patterns after development. The fourth step is to evaporate or magnetron sputter the sidewall reflective metal structure 12. The fifth step is to perform a stripping and degumming operation on the sidewall reflective metal structure 12 that has been evaporated or sputtered, so that the desired sidewall reflective metal structure 12 with patterns can be retained.

[0150] Further, in this embodiment, step S90 includes the following steps:

[0151] Step S901: coating a layer of adhesion promoter on the wafer, and then depositing a layer of passivation film on the wafer.

[0152] Step S902: exposing the protective electrode area to be exposed.

[0153] Step S903: using a developer to dissolve the photoresist on the protective electrode area to be exposed, and performing hard baking after development.

[0154] Step S904: etching the passivation film on the protective electrode region to be exposed.

[0155] Step S905 : performing a resist stripping operation on the wafer so that the desired patterned passivation layer structure is retained to form the second passivation layer 13 .

[0156] In this embodiment, in the first step, a second passivation layer 13 is deposited on the entire wafer using PECVD (plasma enhanced chemical vapor deposition) or ALD (atomic layer deposition). The second passivation layer 13 is SiO2, SiN x , Al2O3 or a combination thereof, with a thickness in the range of 0.1 to 2 microns. SiN is recommended x Or Al2O3. The second step is to apply a layer of HDMS viscosity enhancer with a thickness of less than 1 to 10 nm before applying the glue; the third step is to select a photoresist thickness of 2 to 5 um and an exposure dose of 100 mJ to 300 mJ according to the actual dry etching selection ratio, and expose the protective electrode area to be exposed; the fourth step is to perform a development process, using a developer to dissolve the photoresist above the protective electrode area to be exposed; the fifth step is to perform hard baking after development. The sixth step is to use a dry etching process to etch the passivation layer above the protective electrode area to be exposed. The etching gas is a strong oxidizing gas such as CF4 or BCl2, and the etching power is in the range of 100 to 2000 W. The over-etching ratio is 10% to 50%. The sixth step is to remove the glue from the wafer after etching, so that the required passivation layer structure with patterns can be retained.

[0157] Further, in this embodiment, step S100 includes the following steps:

[0158] Step S101 : performing photolithography on the wafer and exposing the area outside the metal pad 14 .

[0159] Step S102: baking the wafer, and after baking, using a developer to dissolve the photoresist above the metal pad 14 area.

[0160] Step S103: after development, the photoresist with the pattern is subjected to plasma bombardment.

[0161] Step S104: first evaporate the metal pad 14, and then perform a stripping and debonding operation.

[0162] In this embodiment, the first step is to use a negative photoresist to perform a photolithography process on the entire wafer, the thickness of the photoresist is 5um to 8um, the exposure dose is in the range of 200mJ to 400mJ, and the area outside the desired metal pad 14 structure area is exposed; the second step is to perform a development process, bake before development, bake at 90℃ to 130℃, and use a developer to dissolve the photoresist above the desired metal pad structure area after baking; the third step is to perform O2 plasma bombardment on the patterned photoresist after development. The fourth step is to evaporate the metal pad 14, and the metal pad 14 structure is AuSn alloy or Ti, Pt, Au, Sn and a combination thereof. The fifth step is to perform a stripping and degumming operation on the evaporated metal pad 14 structure, so that the desired metal pad 14 with a pattern can be retained.

[0163] In addition, to achieve the above-mentioned purpose, the present invention also proposes a light-emitting element 01, comprising a substrate 1, a buffer layer 2, an N-type semiconductor layer 3, a quantum well layer 4, a P-type electron blocking layer 5, and a P-type semiconductor layer 6, wherein a separated P-surface reflective electrode structure is formed on the P-type semiconductor layer 6, and the P-surface reflective electrode structure comprises a Ni / Au ohmic contact electrode 9 and a plurality of Ni / Al reflective electrodes 8, wherein the plurality of Ni / Al reflective electrodes 8 are distributed at intervals on the P-type semiconductor layer 6, and the Ni / Au ohmic contact electrode 9 is arranged on the P-type semiconductor layer 6 and wraps the Ni / Al reflective electrode 8.

[0164] In this embodiment, a Ni / Al metal layer structure is deposited on the surface of P-GaN by magnetron sputtering or electron beam (E-Beam), and a periodic array structure is formed by photolithography, with a width of 10um to 60um, an interval of 5um to 20um, and generally 2 to 10 periods. Figure 1 As shown, the metal structure is used as a Ni / Al reflective electrode 8. The Ni thickness of the Ni / Al reflective electrode 8 is 1nm to 5nm, and its function is to form an ohmic contact with P-GaN during the annealing process. The Al thickness is 10nm to 200nm, and its function is to reflect the metal layer. The reflectivity of the Ni / Al reflective electrode 8 of this structure reaches more than 80%, which is much higher than the Ni / Au reflective electrode under the same thickness condition. The magnetron sputtering conditions are power 10W to 1000W, the gas used is argon, and the pressure is 1mTorr to 1000mTorr. The electron beam (E-Beam) evaporation conditions are power 1W to 50W and pressure 1mTorr to 10mTorr.

[0165] A Ni / Au metal layer structure is deposited on the surface of P-GaN and above the Ni / Al reflective electrode 8 by magnetron sputtering or electron beam (E-Beam). The metal structure as the Ni / Au ohmic contact electrode 9 should cover the entire Ni / Al reflective electrode 8, and is used to protect the Ni / Al reflective electrode 8 during the annealing process to prevent the Al metal in the Ni / Al reflective electrode 8 from being oxidized. In the Ni / Au ohmic contact electrode 9 structure, the Ni thickness is 1nm to 10nm, and its work function reaches 5eV, and the Au thickness is 10nm to 200nm, and its work function reaches 5.25eV. Therefore, Ni / Au has a higher work function as a whole, and after annealing, it can form a good ohmic contact with P-GaN. The magnetron sputtering conditions are power 10W to 1000W, the gas used is argon, and the pressure is 1mTorr to 1000mTorr. The electron beam (E-Beam) evaporation conditions are power 1W to 50W, and pressure 1mTorr to 10mTorr.

[0166] In the technical solution provided by the present invention, a Ni / Al metal layer structure is evaporated on the surface of the P-type semiconductor layer to form a Ni / Al reflective electrode 8; a Ni / Au metal layer structure is evaporated on the surface of the P-type semiconductor layer and above the Ni / Al reflective electrode to form a Ni / Au ohmic contact electrode 9, and then a layer of protective metal 10 is evaporated above the Ni / Au ohmic contact electrode 9 and the N-type electrode 7 to form a separated P-surface electrode structure. Among them, Ni / Au is used as an ohmic contact electrode and Ni / Al is used as a reflective electrode structure. Compared with conventional Ni / Au reflective electrodes, this new P-surface reflective electrode has a higher reflectivity; compared with Ni / Al reflective electrodes, this new P-surface reflective electrode has better ohmic contact performance; and the overall comprehensive performance is better.

[0167] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some of the technical features therein by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. The specific embodiments described above further describe the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not used to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a light-emitting element, characterized in that: The steps include: A buffer layer, an N-type semiconductor layer, a quantum well layer, and a P-type semiconductor layer are sequentially grown on the substrate; Etching through the P-type semiconductor layer and the quantum well layer to form a groove; Preparing an N-type electrode at the groove; Vapor depositing a Ni / Al metal layer structure on the surface of the P-type semiconductor layer, and making it present a periodic array structure through a photolithography process, so as to form a Ni / Al reflective electrode; Vapor depositing a Ni / Au metal layer structure on the surface of the P-type semiconductor layer and above the Ni / Al reflective electrode to form a Ni / Au ohmic contact electrode covering the Ni / Al reflective electrode, and annealing the Ni / Au ohmic contact electrode, wherein the annealing temperature is 400° C. to 650° C., and the annealing atmosphere is a mixture of nitrogen and oxygen; Vapor-depositing a layer of protective metal covering the Ni / Al reflective electrode and the Ni / Au ohmic contact electrode on the Ni / Au ohmic contact electrode and the N-type electrode; depositing a first passivation layer over the epitaxial region; Vapor depositing a layer of sidewall reflective metal structure on the first passivation layer; coating a second passivation layer over the epitaxial region; A metal pad is formed on the etching area of ​​the second passivation layer by evaporation.

2. The method for preparing a light-emitting element according to claim 1, wherein: Preparing an N-type electrode at the groove comprises the following steps: Perform photolithography on the wafer and expose the area outside the N-type electrode; The wafer is baked, and after baking, the photoresist above the N-type electrode area is dissolved using a developer; After development, the photoresist with the pattern is subjected to plasma bombardment; First, evaporate or magnetron sputter the N electrode metal, and then perform stripping and degumming operations; The patterned N-electrode metal is annealed.

3. The method for preparing a light-emitting element according to claim 1, wherein: The step of evaporating a Ni / Al metal layer structure on the surface of the P-type semiconductor layer to form a Ni / Al reflective electrode comprises: Performing photolithography on the wafer and exposing the area outside the Ni / Al metal layer; The wafer is baked, and after baking, the photoresist above the Ni / Al metal layer area is dissolved using a developer; After development, the photoresist with the pattern is subjected to plasma bombardment; First, evaporate or magnetron sputter the Ni / Al metal layer, and then perform the stripping and degumming operation.

4. The method for preparing a light-emitting element according to claim 3, characterized in that: The step of evaporating a Ni / Au metal layer structure on the surface of the P-type semiconductor layer and above the Ni / Al reflective electrode to form a Ni / Au ohmic contact electrode comprises: Performing photolithography on the wafer and exposing the area outside the Ni / Au metal layer; The wafer is baked, and after baking, the photoresist above the Ni / Au metal layer area is dissolved using a developer; After development, the photoresist with the pattern is subjected to plasma bombardment; First, evaporate or magnetron sputter the Ni / Au metal layer, and then perform the stripping and degumming operation.

5. The method for preparing a light-emitting element according to claim 1, wherein: The step of evaporating a layer of protective metal on the Ni / Au ohmic contact electrode and the N-type electrode comprises: Performing photolithography on the wafer and exposing the area outside the protective metal; The wafer is baked, and after baking, a developer is used to dissolve the photoresist above the protective metal area; After development, the photoresist with the pattern is subjected to plasma bombardment; First, evaporate or magnetron sputter the protective metal, and then perform the stripping and degumming operation.

6. The method for preparing a light-emitting element according to claim 1, wherein: The step of plating a first passivation layer over the epitaxial region comprises: Depositing a passivation film on the wafer and photolithography the wafer; Exposing the protective electrode area that needs to be exposed; Use a developer to dissolve the photoresist above the protective electrode area to be exposed, and perform hard baking after development; Etching the passivation film on the protective electrode area to be exposed; The wafer is subjected to a debonding operation so that the required passivation layer structure with patterns is retained to form the first passivation layer.

7. The method for preparing a light-emitting element according to claim 1, wherein: The step of evaporating a layer of sidewall reflective metal structure on the first passivation layer comprises: Performing a photolithography process on the wafer and exposing the area outside the sidewall reflective metal structure; The wafer is baked, and after baking, a developer is used to dissolve the photoresist above the sidewall reflective metal structure area; After development, the photoresist with the pattern is subjected to plasma bombardment; First, evaporate or magnetron sputter the side wall reflective metal structure, and then perform the stripping and degumming operation.

8. The method for preparing a light-emitting element according to claim 1, wherein: The step of coating a second passivation layer over the epitaxial region comprises: Apply a layer of adhesion promoter on the wafer, and then deposit a layer of passivation film on the wafer; Exposing the protective electrode area that needs to be exposed; Use a developer to dissolve the photoresist above the protective electrode area to be exposed, and perform hard baking after development; Etching the passivation film on the protective electrode area to be exposed; The wafer is stripped so that the required patterned passivation layer structure is retained to form the second passivation layer.

9. The method for preparing a light-emitting element according to claim 1, wherein: The step of forming a metal pad by evaporation above the etching area of ​​the second passivation layer comprises: Performing photolithography on the wafer and exposing the area outside the metal pad; The wafer is baked, and after baking, the photoresist above the metal pad area is dissolved using a developer; After development, the photoresist with the pattern is subjected to plasma bombardment; First, evaporate the metal pad, and then perform the stripping and debonding operation.

10. A light emitting element, comprising a substrate, a buffer layer, an N-type semiconductor layer, a quantum well layer, a P-type electron blocking layer, and a P-type semiconductor layer, characterized in that: A separate P-surface reflective electrode structure is formed on the P-type semiconductor layer, and the P-surface reflective electrode structure includes a Ni / Au ohmic contact electrode and a plurality of Ni / Al reflective electrodes, and the plurality of Ni / Al reflective electrodes are spaced apart on the P-type semiconductor layer, and the Ni / Au ohmic contact electrode is arranged on the P-type semiconductor layer and wraps the Ni / Al reflective electrode, and the light-emitting element is prepared by the method for preparing a light-emitting element according to any one of claims 1 to 9.

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