一种基于高层次综合的QC-LDPC编码器
By designing a QC-LDPC encoder based on high-level synthesis, and utilizing the cyclic shift characteristics and pipeline structure of the generator matrix, the hardware design was optimized, solving the problem of low hardware efficiency in existing technologies. This resulted in high-efficiency encoding rates and resource utilization, meeting the performance requirements of high-speed channels for holographic storage.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUAZHONG UNIV OF SCI & TECH
- Filing Date
- 2023-10-20
- Publication Date
- 2026-07-17
AI Technical Summary
Existing HLS-based QC-LDPC decoders suffer from low hardware efficiency in RTL implementations, failing to meet the high-performance encoding and decoding requirements of high-speed holographic storage channels. Furthermore, general-purpose CPU encoding and decoding are inefficient and result in significant resource waste.
Design a QC-LDPC encoder based on high-level synthesis. It adopts a data input module, an encoding calculation module, and a data output module. It utilizes the cyclic shift characteristics of the generator matrix and performs parallel encoding through sub-matrix encoding units. Combined with pipeline structure and kernel-level module partitioning, it optimizes hardware design and encoding rate.
It reduces hardware consumption, increases encoding rate, solves the problem of low hardware efficiency, achieves high-efficiency encoding rate and resource utilization, and meets the performance requirements of high-speed holographic storage channels.
Smart Images
Figure CN117375633B_ABST