Monoclinic adc device and image sensor, analog-to-digital conversion method

Abstract

A kind of single ADC device and image sensor and analog-digital conversion method.The single ADC device first comparator;Second comparator, for comparing the voltage of the second input signal with the voltage of the ramp signal, obtain clock adjustment signal;And counter, adapted to start counting with the counting clock signal, from the voltage of the ramp signal begins to drop time, until the count stop signal occurs flip, to obtain the digital signal corresponding to the first input signal;The voltage of the second input signal is the sum of the voltage of the first input signal and the preset voltage;Counter, for recovering the low bit counting clock signal of the counter in the counting time and when the clock adjustment signal is the second logic value, until the end of counting time, turn off the low bit counting clock signal of the counter in other time.Such scheme can reduce the power consumption of single ADC device.

Description

Technical Field

[0001] This invention relates to the field of image sensor technology, specifically to a single-slope ADC device, an image sensor, and an analog-to-digital conversion method. Background Technology

[0002] Complementary metal-oxide-semiconductor (CMOS) image sensors are a typical type of solid-state imaging sensor. They have advantages such as high integration, low power consumption, and low cost, and are widely used in the field of image acquisition.

[0003] In CMOS image sensors, due to factors such as manufacturing process and temperature, there is a certain degree of mismatch between the transistors in each column of pixels. Under the same lighting conditions, this mismatch causes deviations in the output values ​​of the pixels, and this deviation forms the fixed pattern noise (FPN) within the pixel. Fixed pattern noise is one of the main factors leading to image quality degradation.

[0004] Correlated Double Sampling (CDS) technology can eliminate fixed-pattern noise within a pixel by subtracting the pixel reset voltage Vrst from the exposure signal voltage Vsig to reduce FPN. In a CMOS image sensor, the analog value obtained by subtracting the exposure signal voltage from the pixel reset voltage is used as the pixel output and transmitted to an analog-to-digital converter (ADC). The ADC performs analog-to-digital conversion on the pixel output to obtain the digital result of CDS.

[0005] Currently, single-slope ADC devices are frequently used in CMOS image sensors to perform analog-to-digital conversion on pixel outputs. Single-slope ADC devices have a simple structure; each device requires only one comparator and one counter, occupying a small area. Furthermore, all columns of pixels share a single slope signal, resulting in better inter-column consistency.

[0006] However, existing single-slope ADC devices have high power consumption, resulting in high overall power consumption for CMOS image sensors. Summary of the Invention

[0007] The problem this invention aims to solve is to reduce the power consumption of a single-slope ADC device.

[0008] To address the above problems, embodiments of the present invention provide a monoclinic ADC device, the monoclinic ADC device comprising:

[0009] A first comparator includes a first input terminal and a second input terminal; wherein, the first input terminal of the first comparator is adapted to receive a first input signal, and the second input terminal of the first comparator is adapted to receive a ramp signal; the first comparator is used to compare the voltage of the first input signal with the voltage of the ramp signal to obtain a counting stop signal;

[0010] The second comparator includes a first input terminal and a second input terminal; wherein, the first input terminal of the second comparator is adapted to receive a second input signal, and the second input terminal of the second comparator is adapted to receive the ramp signal; the second comparator is used to compare the voltage of the second input signal with the voltage of the ramp signal to obtain a clock adjustment signal;

[0011] And a counter, connected to the first comparator and the second comparator, adapted to start counting from the moment when the voltage of the ramp signal begins to fall using a counting clock signal, until the counting stop signal flips, so as to obtain the digital signal corresponding to the first input signal;

[0012] Wherein, the voltage of the second input signal is the sum of the voltage of the first input signal and the preset voltage; the counting clock signal includes: a low-order counting clock signal and a high-order counting clock signal; the counter is used to restore the low-order counting clock signal of the counter during the counting time and when the clock adjustment signal is the second logic value, until the counting time ends, and to turn off the low-order counting clock signal of the counter during other times.

[0013] Optionally, the single-slope ADC device further includes: a voltage adjustment circuit connected to the first input terminal of the second comparator and the output terminal of the first input signal, for increasing the voltage of the first input signal by a preset voltage before inputting it to the first input terminal of the second comparator.

[0014] Optionally, the voltage adjustment circuit includes: a first capacitor, one end of which is connected to the output terminal of the first input signal, and the other end of which is connected to a preset voltage output terminal.

[0015] Optionally, during the counting time of the counter and when the clock adjustment signal is low, the low-order counting clock signal of the counter is restored until the counting time ends.

[0016] Optionally, the counter includes:

[0017] The TDC clock generation module is used to generate the low-order counting clock signal and the high-order counting clock signal.

[0018] Optionally, the low-order counting clock signal includes at least one high-speed clock signal.

[0019] Optionally, the low-order counting clock signal includes: three high-speed clock signals of a first frequency and a low-speed clock signal of a second frequency, wherein the first frequency is twice the second frequency.

[0020] Optionally, the monoclinic ADC device further includes:

[0021] A ramp signal generation circuit, connected to the first comparator and the second comparator, is adapted to generate the ramp signal.

[0022] This invention also provides an image sensor, which includes any of the above-described monoclinic ADC devices.

[0023] This invention also provides an analog-to-digital conversion method, the method comprising:

[0024] The voltage of the voltage ramp signal of the first input signal is compared with the voltage of the second input signal to obtain the counting stop signal;

[0025] The voltage of the second input signal is compared with the voltage of the ramp signal to obtain the clock adjustment signal;

[0026] Using a counting clock signal, counting starts from the moment the voltage of the ramp signal begins to fall until the counting stop signal flips, so as to obtain the digital signal corresponding to the first input signal;

[0027] Wherein, the voltage of the second input signal is the sum of the voltage of the first input signal and the preset voltage; the counting clock signal includes: a low-order counting clock signal and a high-order counting clock signal; during the counting process, when the clock adjustment signal is at the second logic value within the counting time, the low-order counting clock signal is restored until the counting time ends, and the low-order counting clock signal is turned off at other times.

[0028] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0029] By employing the scheme of this invention, a second comparator is provided. This second comparator compares the voltage of the second input signal with the voltage of the ramp signal to obtain a clock adjustment signal. During the counting time and when the clock adjustment signal is at the second logic value, the counter can resume the low-order counting clock signal until the counting time ends. At other times, the low-order counting clock signal of the counter is turned off. Since the voltage of the second input signal is the sum of the voltage of the first input signal and a preset voltage, the logic flip of the clock adjustment signal can occur before the logic flip of the counting stop signal. Thus, the low-order counting clock signal can be turned off until the clock adjustment signal undergoes a logic flip, thereby reducing the power consumption of the counter while ensuring its normal operation, and consequently reducing the power consumption of the single-ramp ADC device. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of a monoclinic ADC device;

[0031] Figure 2 for Figure 1 Timing diagram of each signal in a single-slope ADC device;

[0032] Figure 3 This is a schematic diagram of a TDC multi-phase clock signal;

[0033] Figure 4 This is a schematic diagram of the structure of a single-slope ADC device according to an embodiment of the present invention;

[0034] Figure 5 yes Figure 4 Timing diagram of each signal in a single-slope ADC device;

[0035] Figure 6 This is a flowchart of an analog-to-digital conversion method according to an embodiment of the present invention. Detailed Implementation

[0036] Figure 1 This is a schematic diagram of a monoclinic ADC device. (Refer to...) Figure 1 The single-slope ADC device includes a comparator 11 and a counter 12. The comparator 11 has a first input terminal and a second output terminal. The first input terminal of the comparator 11 is connected to the bit line of the pixel and is used to receive the pixel output signal Vn. The second output terminal of the comparator 11 is used to receive the ramp signal Ramp. The output terminal of the comparator 11 is connected to the counter 12. The pixel output signal Vn can be an analog signal obtained by subtracting the exposure signal voltage from the pixel reset voltage.

[0037] Figure 2 for Figure 1 Timing diagram of each signal in a single-slope ADC device. (Refer to...) Figure 1 and Figure 2 Comparator 11 compares the voltage of the pixel output signal Vn with the voltage of the ramp signal Ramp, and obtains the comparison result signal Cmp_out. When the voltage of the ramp signal Ramp starts to approach the voltage of the pixel output signal Vn (as shown at times t1 and t3), counter 12 starts counting. When the voltage of the ramp signal Ramp exceeds the voltage of the pixel output signal Vn (as shown at times t2 and t4), the comparison result signal Cmp_out output by comparator 11 flips, and counter 12 stops counting.

[0038] Currently, counter 12 uses a Time-to-Digital Converter (TDC) multi-phase clock for counting. The TDC clock has 5 phases, and their phase relationships are as follows: Figure 3 As shown.

[0039] Specifically, refer to Figure 3 Clocks clk4 and clk5 have the same frequency, while clocks clk1 through clk3 have frequencies twice that of clk4 and clk5. Clocks clk1 through clk4 are the low-order counting clocks for the counter, and clock clk5 is the subsequent high-order counting clock. The high-order counting clock counts while the counting time is high, while the low-order counting clock counts only when the comparison result signal Cmp_out toggles.

[0040] However, in existing multi-phase clock counters, all five clock phases operate normally regardless of whether the counter is counting or not, resulting in high power consumption. This power consumption increases further in high-speed counters. Therefore, it is necessary to appropriately disable these clocks without affecting the normal operation of the counter.

[0041] To address this problem, the present invention provides a single-slope ADC device, which includes a second comparator that compares the voltage of the second input signal with the voltage of the ramp signal to obtain a clock adjustment signal. The counter can shut off the low-order counting clock signal based on the clock adjustment signal until the clock adjustment signal undergoes a logic flip, thereby reducing the power consumption of the counter while ensuring its normal operation, and thus reducing the power consumption of the single-slope ADC device.

[0042] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0043] Reference Figure 4This invention provides a single-slope ADC device, which may include: a first comparator 41, a second comparator 42, and a counter 43. Wherein:

[0044] The first comparator 41 includes a first input terminal and a second input terminal; wherein, the first input terminal of the first comparator 41 is adapted to receive a first input signal s1, and the second input terminal of the first comparator 41 is adapted to receive a ramp signal Ramp; the first comparator 41 is used to compare the voltage of the first input signal s1 with the voltage of the ramp signal Ramp to obtain a counting stop signal Cmp_out;

[0045] The second comparator 42 includes a first input terminal and a second input terminal; wherein, the first input terminal of the second comparator 42 is adapted to receive a second input signal s2, and the second input terminal of the second comparator 42 is adapted to receive the ramp signal Ramp; the second comparator 42 is used to compare the voltage of the second input signal s2 with the voltage of the ramp signal Ramp to obtain a clock adjustment signal Cmp_out_pre;

[0046] And a counter 43, connected to the first comparator 41 and the second comparator 42, is adapted to start counting from the moment when the voltage of the ramp signal Ramp begins to fall using a counting clock signal, until the counting stop signal Cmp_out flips, so as to obtain the digital signal corresponding to the first input signal s1;

[0047] Wherein, the voltage of the second input signal s2 is the sum of the voltage of the first input signal s1 and the preset voltage Vos; the counting clock signal includes: a low-order counting clock signal and a high-order counting clock signal; the counter 43 is used to restore the low-order counting clock signal of the counter 43 when the clock adjustment signal Cmp_out_pre is the second logic value during the counting time of the counter 43, until the counting time ends, and to turn off the low-order counting clock signal of the counter 43 during other times.

[0048] During the counting time, counter 43 only restores the low-order counting clock signal when the clock adjustment signal Cmp_out_pre is at the second logic value, and shuts down the low-order counting clock signal at other times, retaining only the high-order counting clock signal for high-order clock counting. Since the clock adjustment signal Cmp_out_pre is obtained by comparing the voltage of the second input signal s2 with the voltage of the ramp signal Ramp, and the voltage of the second input signal s2 is the sum of the voltage of the first input signal s1 and the preset voltage Vos, the logic flip of the clock adjustment signal Cmp_out_pre occurs before the logic flip of the counting stop signal Cmp_out. This allows the low-order counting clock signal to count normally when the counting stop signal Cmp_out flips, ensuring the normal operation of counter 43 while reducing its power consumption, thus reducing the power consumption of the single-ramp ADC device.

[0049] In a specific implementation, the first comparator 41 can be triggered to start working by the first comparator enable signal, enabling the first comparator 41 to compare the first input signal s1 with the ramp signal Ramp and output a counting stop signal Cmp_out. The moment the first comparator enable signal triggers the first comparator 41 to work is earlier than the moment the counter 43 starts counting. The counter 43 typically starts counting when the voltage of the ramp signal Ramp begins to decrease (e.g., when the voltage of the ramp signal Ramp begins to decrease). Figure 5 The counting starts at time t1. The counting begins when the voltage of the ramp signal Ramp equals the voltage of the first input signal s1 (e.g., at time t1). Figure 5 At time t2, the counting stop signal Cmp_out undergoes a logical flip, thereby stopping the counting.

[0050] In one embodiment, the first comparator 41 can output a high level for the counting stop signal Cmp_out when the voltage of the ramp signal Ramp is greater than the voltage of the first input signal s1, and vice versa.

[0051] In another embodiment, the first comparator 41 can output a counting stop signal Cmp_out at a low level when the voltage of the ramp signal Ramp is greater than the voltage of the first input signal s1, and conversely, output a counting stop signal Cmp_out at a high level when the voltage of the ramp signal Ramp is greater than the voltage of the first input signal s1.

[0052] In one embodiment of the present invention, the single-slope ADC device may further include a voltage adjustment circuit 44. The voltage adjustment circuit 44 may be connected to the first input terminal of the second comparator 42 and the output terminal of the first input signal s1, and is used to increase the voltage of the first input signal s1 by a preset voltage Vos before inputting it to the first input terminal of the second comparator 42.

[0053] In specific implementation, the voltage adjustment circuit 44 can use various methods to provide the second output signal s2 to the second comparator 42, as long as the voltage of the second input signal s2 is the sum of the voltage of the first input signal s1 and the preset voltage Vos.

[0054] In one embodiment of the present invention, the voltage adjustment circuit 44 may include a first capacitor C1, one end of which is connected to the output terminal of the first input signal s1, and the other end is connected to the output terminal of a preset voltage Vos. In this case, the second input signal s2 input to the first input terminal of the second comparator 42 is a signal obtained by adding the preset voltage Vos to the voltage of the first input signal s1.

[0055] In a specific implementation, the first input signal s1 can be a pixel output signal. In this case, the second input terminal of the second comparator 42 can be connected to the bit line of the pixel through the second capacitor C2. In this way, the analog signal output by the pixel after correlation double sampling, that is, the analog value after correlation double sampling, can form the second input signal s2 after adding a preset voltage Vos and output to the second comparator 42.

[0056] In a specific implementation, the second comparator 42 can be controlled to work by the second comparator enable signal, so that the second comparator can compare the second input signal s2 with the ramp signal Ramp and output the clock adjustment signal Cmp_out_pre.

[0057] Specifically, refer to Figure 5 The second comparator 42 can be configured to output a clock adjustment signal Cmp_out_pre high when the voltage of the second input signal s2 is greater than the voltage of the ramp signal Ramp, and to output a clock adjustment signal Cmp_out_pre low when the voltage of the second input signal s2 is equal to the voltage of the ramp signal Ramp (e.g., ...). Figure 5 Starting at time t5, the clock adjustment signal Cmp_out_pre is switched to low level.

[0058] In some embodiments, the second comparator 42 may be configured to output a low level clock adjustment signal Cmp_out_pre when the voltage of the second input signal s2 is greater than the voltage of the ramp signal Ramp, and to output a high level clock adjustment signal Cmp_out_pre when the voltage of the second input signal s2 is less than or equal to the voltage of the ramp signal Ramp.

[0059] It is understood that the specific setting of the clock adjustment signal Cmp_out_pre does not constitute a limitation of the present invention, as long as the logic flip of the clock adjustment signal Cmp_out_pre occurs before the counting stop signal Cmp_out.

[0060] In specific implementations, the value of the preset voltage Vos can be set as needed. The smaller the value of the preset voltage Vos, the closer the voltage of the second input signal s2 is to the voltage of the first input signal s1, the closer the logic flip times of the clock adjustment signal Cmp_out_pre and the counting stop signal Cmp_out are, and the lower the power consumption of the counter 43.

[0061] In specific implementation, the counting clock signal includes a low-order counting clock signal and a high-order counting clock signal. The low-order bits of the counting result can be determined based on the logic value of the low-order counting clock signal, while the high-order bits of the counting result can be determined based on the logic value of the high-order counting clock signal. The low-order counting clock signal may include at least one high-speed clock signal, i.e., a high-frequency clock signal, while the high-order counting clock signal is mostly a low-frequency clock signal.

[0062] In one embodiment of the present invention, the low-bit counting clock signal may include three high-speed clock signals of a first frequency and a low-speed clock signal of a second frequency, wherein the first frequency is twice the second frequency.

[0063] Specifically, refer to Figure 2 The low-order counting clock signal may include clocks clk1 to clk4, where clocks clk1 to clk3 have a higher frequency, twice that of clock clk4. Clocks clk1 to clk4 can count in parallel to obtain the lower four binary bits of the count value. Clock clk5 has the same frequency as clock clk4 and serves as the high-order counting clock signal, allowing for serial counting to obtain the higher binary bits of the count value. Subsequently, the lower four binary bits of the count value are added to the higher binary bits to obtain the final counting result.

[0064] In a specific implementation, the counter 43 is used to restore the low-order counting clock signal of the counter during the counting time and when the clock adjustment signal Cmp_out_pre is the second logic value, and to turn off the low-order counting clock signal at other times. The first logic value can be logic "1" and the second logic value can be logic "0", or the first logic value can be logic "0" and the second logic value can be logic "1".

[0065] In one embodiment of the present invention, the counter 43 may include a TDC clock generation module for generating the low-order counting clock signal and the high-order counting clock signal. Specifically, the TDC clock generation module can generate a multi-phase clock signal, with a portion of the clock signal serving as the low-order counting clock signal and the remaining portion serving as the high-order counting clock signal. The clock adjustment signal generated by the second comparator 42 can be directly sent to the TDC clock generation module to turn off or restore the low-order counting clock signal.

[0066] Taking the first logical value as logical "1" and the second logical value as logical "0" as an example, refer to... Figure 5 During this time, the counter 43 is used to restore the low-order counting clock signal of the counter 43 when the clock adjustment signal Cmp_out_pre is low during the counting time, until the counting time ends. At other times, the counter 43 turns off the low-order counting clock signal to reduce power consumption.

[0067] It should be noted that the time the clock adjustment signal Cmp_out_pre is low includes the moment when the clock adjustment signal Cmp_out_pre transitions from high to low. Before time t5, counter 43 disables the low-order counting clock signal. From time t5 to time t2, counter 43 restores the low-order counting clock signal. After the counting time ends, i.e., after time t2, counter 43 disables the low-order counting clock signal.

[0068] Combination Figure 2 and Figure 4 A preset voltage Vos is added to the voltage of the first input signal s1, causing the second comparator 42 to flip ahead of the first comparator 41. Before the second comparator 42 flips, three high-speed clocks and one low-speed clock (clk1~clk4) in the 5-phase clock are turned off, leaving only one low-speed clock (clk5) for counting the higher bits. Therefore, the power consumption of the counter is greatly reduced. When the second comparator 42 flips, the operation of clocks clk1~clk4 is resumed, so that clocks clk1~clk4 can count the lower bits when the counting stop signal Cmp_out flips.

[0069] In a specific implementation, the counter 43 may be equipped with a phase sampling module. This module samples the phases of clocks clk1 to clk5 to obtain corresponding binary values. The sampling results of clocks clk1 to clk4 are stored in a latch, and the sampling result of clock clk5 is also stored in a latch. The latch adds the sampling results of clocks clk1 to clk4 to the sampling result of clock clk5 to obtain the final counting result. This final counting result is the digital signal corresponding to the first input signal s1.

[0070] When the first input signal s1 is a pixel output signal, the final counting result is also the quantization result.

[0071] As can be seen from the above, by setting a second comparator to turn off the high-order counting clock signal, the power consumption of the counter can be reduced while the counter is working normally.

[0072] This invention also provides an image sensor, which may include the above-described monoclinic ADC device.

[0073] In a specific implementation, the image sensor can be a CMOS image sensor. The CMOS image sensor includes a pixel array and a column-parallel single-slope ADC device. Each column of pixels is connected to the same single-slope ADC device, thereby enabling CDS quantization by allowing all columns of pixels to share the same slope signal.

[0074] Reference Figure 6 This invention also provides an analog-to-digital conversion method, which may include:

[0075] Step 61: Compare the voltage of the voltage ramp signal of the first input signal to obtain the counting stop signal.

[0076] In a specific implementation, the first input signal can be a pixel output signal, whose voltage is an analog value obtained by subtracting the exposure signal voltage from the pixel reset voltage. A counting stop signal can be obtained by comparing the voltage of the voltage ramp signal of the first input signal. Based on this counting stop signal, it is determined whether to stop counting.

[0077] Step 62: Compare the voltage of the second input signal with the voltage of the ramp signal to obtain the clock adjustment signal.

[0078] In a specific implementation, the voltage of the second input signal is the sum of the voltage of the first input signal and a preset voltage. By comparing the voltage of the second input signal with the voltage of the ramp signal, the clock adjustment signal can be made to count ahead of the stop signal logic flip.

[0079] Step 63: Using a counting clock signal, start counting from the moment the voltage of the ramp signal begins to drop until the counting stop signal flips, so as to obtain the digital signal corresponding to the first input signal.

[0080] In a specific implementation, the counting clock signal includes a low-order counting clock signal and a high-order counting clock signal. During the counting process, when the clock adjustment signal is at the second logic value within the counting time, the low-order counting clock signal is restored until the counting time ends, and the low-order counting clock signal is turned off at other times.

[0081] For example, during the counting process, when the clock adjustment signal is low, the low-order counting clock signal of the counter is restored, and at other times the low-order counting clock signal can be turned off. In this way, when the low-order counting clock signal is turned off, only the high-order counting clock signal is retained for counting, while when the clock adjustment signal is low, both the low-order and high-order counting clock signals are used for counting, thereby reducing power consumption.

[0082] By employing the analog-to-digital conversion method in this embodiment of the invention, and using a clock adjustment signal to turn off the low-order counting clock signal, the power consumption required for counting can be reduced while counting is performed normally.

[0083] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A monoclinic ADC device, characterized in that, include: A first comparator includes a first input terminal and a second input terminal; wherein, the first input terminal of the first comparator is adapted to receive a first input signal, and the second input terminal of the first comparator is adapted to receive a ramp signal; the first comparator is used to compare the voltage of the first input signal with the voltage of the ramp signal to obtain a counting stop signal; The second comparator includes a first input terminal and a second input terminal; wherein, the first input terminal of the second comparator is adapted to receive a second input signal, and the second input terminal of the second comparator is adapted to receive the ramp signal; the second comparator is used to compare the voltage of the second input signal with the voltage of the ramp signal to obtain a clock adjustment signal; And a counter, connected to the first comparator and the second comparator, adapted to start counting from the moment when the voltage of the ramp signal begins to fall using a counting clock signal, until the counting stop signal flips, so as to obtain the digital signal corresponding to the first input signal; Wherein, the voltage of the second input signal is the sum of the voltage of the first input signal and the preset voltage; the counting clock signal includes: a low-order counting clock signal and a high-order counting clock signal; the counter is used to restore the low-order counting clock signal of the counter during the counting time and when the clock adjustment signal flips, until the counting time ends, and to turn off the low-order counting clock signal of the counter during other times.

2. The monoclinic ADC device as described in claim 1, characterized in that, Also includes: A voltage adjustment circuit is connected to the first input terminal of the second comparator and the output terminal of the first input signal, and is used to increase the voltage of the first input signal by a preset voltage before inputting it to the first input terminal of the second comparator.

3. The monoclinic ADC device as described in claim 2, characterized in that, The voltage adjustment circuit includes: a first capacitor, one end of which is connected to the output terminal of the first input signal, and the other end of which is connected to a preset voltage output terminal.

4. The monoclinic ADC device as described in claim 1, characterized in that, The counter is used to restore the low-order counting clock signal of the counter when the clock adjustment signal flips to a low level during the counting time of the counter, until the counting time ends.

5. The monoclinic ADC device as described in claim 1, characterized in that, The counter includes: The TDC clock generation module is used to generate the low-order counting clock signal and the high-order counting clock signal.

6. The monoclinic ADC device as described in claim 5, characterized in that, The low-order counting clock signal includes at least one high-speed clock signal.

7. The monoclinic ADC device as described in claim 6, characterized in that, The low-order counting clock signal includes: three high-speed clock signals of a first frequency and a low-speed clock signal of a second frequency, wherein the first frequency is twice the second frequency.

8. The monoclinic ADC device as described in claim 1, characterized in that, Also includes: A ramp signal generation circuit, connected to the first comparator and the second comparator, is adapted to generate the ramp signal.

9. An image sensor, characterized in that, include: The monoclinic ADC device according to any one of claims 1 to 8.

10. An analog-to-digital conversion method, characterized in that, include: The voltage of the first input signal is compared with the voltage of the ramp signal to obtain the counting stop signal; The voltage of the second input signal is compared with the voltage of the ramp signal to obtain the clock adjustment signal; Using a counting clock signal, counting starts from the moment the voltage of the ramp signal begins to fall until the counting stop signal flips, so as to obtain the digital signal corresponding to the first input signal; Wherein, the voltage of the second input signal is the sum of the voltage of the first input signal and the preset voltage; the counting clock signal includes: a low-order counting clock signal and a high-order counting clock signal; during the counting process, when the clock adjustment signal flips within the counting time, the low-order counting clock signal of the counter is restored until the counting time ends, and the low-order counting clock signal of the counter is turned off during other times.

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