Silicon-based OLED lateral turbulence partition structure and manufacturing method thereof

Abstract

The present application belongs to the technical field of silicon-based OLED, and discloses a silicon-based OLED transverse turbulence blocking structure and a manufacturing method thereof. The silicon-based OLED transverse turbulence blocking structure comprises a CMOS substrate (2), an anode pattern formed on the CMOS substrate (2), an inorganic material layer formed on the anode pattern, a planarized inorganic film layer (4), an inorganic material layer formed on the planarized inorganic film layer (4), a stack layer, an under cut structure, an organic light-emitting layer (3) formed on the under cut structure, a cathode layer (8) formed on the organic light-emitting layer (3), and the under cut structure blocks the organic light-emitting layer (3). The silicon-based OLED transverse turbulence blocking structure and the manufacturing method thereof have simple structure and steps, and can solve the problem of the display effect caused by the current interference phenomenon between the light-emitting units and the adjacent display units, and improve the display effect.

Description

Technical Field

[0001] This invention belongs to the technical field of the semiconductor display industry, and more specifically, it relates to a silicon-based OLED lateral turbulence barrier structure. This invention also relates to a method for manufacturing a silicon-based OLED lateral turbulence barrier structure. Background Technology

[0002] In the semiconductor display industry, Organic Light-Emitting Diode (OLED) is a type of display that has emerged in recent years, with silicon-based OLED being one example. Silicon-based OLEDs not only enable active pixel addressing but also allow for the fabrication of pixel driving circuits and other structures on silicon substrates, which helps reduce system size and achieve lightweight design. Silicon-based OLEDs are fabricated using mature Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuit technology, offering advantages such as small size, high resolution (Pixels Per Inch, PPI), and high refresh rate. They are widely used in near-eye displays for Virtual Reality (VR) and Augmented Reality (AR). In the manufacturing of semiconductor silicon-based OLEDs, under normal operating conditions, the R, G, and B units (R: RED, G: GREEN; B: BLUE) should emit light independently without interfering with each other. However, in actual product design, due to increasingly finer linewidths and spacing, current interference can occur between two light-emitting units. The occurrence of current interference can cause adjacent display units to light up intermittently, affecting the product's display effect.

[0003] Existing technology includes a method for preparing silicon-based OLEDs and a silicon-based OLED display module, with publication number "108321311A". This technology includes the following steps: S1, preparing several silicon-based masks with evaporated pixel patterns; S2, selecting silicon-based masks with corresponding pixel patterns; S3, aligning and bonding the silicon-based mask with the wafer, and evaporating the corresponding OLED functional layer film; S4, after the OLED functional layer film evaporation is completed, separating the silicon-based mask from the wafer using a separation technique; S5, repeating steps S2 to S4 to evaporate the remaining functional layer films for preparing the silicon-based OLED onto the wafer, thereby obtaining a silicon-based OLED substrate; S6, encapsulating the silicon-based OLED substrate from step S5, thus completing the preparation of the silicon-based OLED. The silicon-based OLED fabrication method and silicon-based OLED display module of the present invention reduce the use of the CF layer and the separate fabrication of white OLED, thereby increasing the brightness of the silicon-based OLED display module by four times, while also increasing the PPI of the silicon-based OLED and simplifying the silicon-based OLED fabrication process. However, this technology does not address the technical problems and solutions of this application. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a simple manufacturing method for a silicon-based OLED lateral turbulence isolation structure that solves the problem of current interference between light-emitting units causing adjacent display units to dim and affect the display effect, thereby improving the display effect.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0006] This invention relates to a method for manufacturing a silicon-based OLED lateral flow barrier structure. The manufacturing steps of the method are as follows:

[0007] S1. Obtain a CMOS substrate, then deposit an anode layer on the CMOS substrate, and form an anode pattern through coating, exposure, development, etching, and stripping.

[0008] S2. Deposit an inorganic material layer on the anode pattern. The thickness of the inorganic material layer is greater than or equal to that of the anode pattern. Through coating, exposure, development, etching, and stripping, a planarized inorganic film layer 4 is formed.

[0009] S3. On the planarized inorganic film layer, a first inorganic material layer, a second inorganic material layer, and a third inorganic material layer are deposited in one step to form a stack. Through coating, exposure, development, etching, and stripping, an undercut structure is formed. The undercut structure is in the non-pixel definition area.

[0010] S4. To form an undercut structure, the etching rate between each layer of the stack formed by the first inorganic material layer, the second inorganic material layer, and the third inorganic material layer is controlled, and materials with different etching rates are used to construct the first inorganic material layer, the second inorganic material layer, and the third inorganic material layer, respectively; wherein, the etching rate of the second inorganic material layer is greater than the etching rate of the first inorganic material layer and the third inorganic material layer; an asymmetric partition opening is provided on the stack formed by the first inorganic material layer, the second inorganic material layer, and the third inorganic material layer, and a groove is provided in the partition opening, the height of which is greater than or equal to the height difference between the charge generation layer and the first electrode;

[0011] After the S5. Undercut structure is formed, an organic light-emitting layer is deposited by vapor deposition. The undercut structure blocks the organic light-emitting layer, and finally, a cathode layer is deposited by vapor deposition.

[0012] After the undercut structure is formed, a hole injection layer, a hole transport layer, a light-emitting layer, and an electron transport layer are deposited in a vapor deposition machine to form an organic light-emitting layer, which is broken at the groove. After the organic light-emitting layer is deposited, a cathode layer is deposited to obtain a silicon-based OLED lateral turbulence barrier structure.

[0013] A CMOS driving circuit is fabricated on a silicon wafer substrate to form a CMOS substrate, which is then cleaned. After cleaning, the CMOS substrate is coated to form an anode layer. After the anode layer is formed, the CMOS substrate is subjected to photolithography equipment for cleaning, coating, exposure, development, and curing. Patterning is completed using a pH process, followed by dry etching. After etching, in-situ resist stripping (PR) is performed. After resist stripping, the CMOS substrate is cleaned to remove the polymer, finally yielding the anode pattern.

[0014] After cleaning the CMOS substrate, an inorganic material layer is deposited. The thickness of the inorganic material layer is greater than or equal to the thickness of the anode layer to ensure complete filling of the channels between the anodes. After the inorganic material layer is deposited, it is cleaned, coated, exposed, developed, and cured. The pH process completes the patterning, followed by dry etching. After etching, in-situ resist stripping and PR removal are performed. After resist stripping, the CMOS substrate is cleaned to remove the polymer, resulting in a planarized inorganic film layer.

[0015] Before coating, the planarized inorganic film layer is cleaned, then the first inorganic material layer is coated, then the second inorganic material layer is coated, then the third inorganic material layer is coated, and the above coating process is repeated to form a stack. The stack of inorganic material layers is then put into a photolithography device, and the pixel definition area is photolithographically etched using Mask1. Cleaning, coating, exposure, development and curing are then performed.

[0016] After the pH process is completed, the layer is patterned and then dry etched to remove the stack of the first, second, and third inorganic material layers of the pixel definition layer (PDL). After etching, in-situ resist stripping (PR) is performed. After in-situ resist stripping, the CMOS substrate is cleaned to remove the polymer. After the pixel definition area is etched, the third inorganic material layer of the undercut structure is patterned using Mask2, followed by cleaning, coating, exposure, development, and curing.

[0017] The PH process completes the patterning of the third inorganic material layer, and then the third inorganic material layer is dry etched away. The etching process formula for the third inorganic material layer adopts a high selectivity ratio, and the underloss of the underlying second inorganic material layer is ignored. After etching, in-situ resist stripping and PR are performed. After resist stripping, the CMOS substrate is cleaned to remove the polymer, and the third inorganic material layer is patterned.

[0018] After etching the third inorganic material layer of the undercut structure, Mask3 is used to pattern the second inorganic material layer of the undercut structure, followed by cleaning, coating, exposure, development, and curing. The pH process completes the patterning of the second inorganic material layer, and then dry etching removes the second inorganic material layer. The etching process formula for the second inorganic material layer uses a high selectivity ratio, ignoring the underloss of the underlying first inorganic material layer. After etching, in-situ resist stripping (PR) is performed. After in-situ resist stripping, the CMOS substrate is cleaned to remove the polymer, thus achieving the patterning of the second inorganic material layer.

[0019] After etching the second inorganic material layer of the undercut structure, the first inorganic material layer of the undercut structure is patterned using Mask4, followed by cleaning, coating, exposure, development, and curing. The patterning of the first inorganic material layer is completed using the pH process, and the first inorganic material layer is then dry-etched away. The etching process formula for the first inorganic material layer uses a high selectivity ratio, ignoring the under-loss of the underlying inorganic film layer. After etching, in-situ resist stripping (PR) is performed. After in-situ resist stripping, the CMOS substrate is cleaned to remove the polymer, thus achieving patterning of the first inorganic material layer, which completes the fabrication of the undercut structure of the PDL layer.

[0020] This invention also relates to a silicon-based OLED lateral turbulence isolation structure with a simple structure that solves the problem of current interference between light-emitting units causing adjacent display units to dim and affect the display effect, thereby improving the display effect.

[0021] The silicon-based OLED lateral turbulence barrier structure includes an anode layer, a CMOS substrate, an organic light-emitting layer, an inorganic film layer, a first inorganic material layer, a third inorganic material layer, a second inorganic material layer, and a cathode layer.

[0022] The working principle and beneficial effects of the technical solution adopted in this invention are as follows:

[0023] The silicon-based OLED lateral current-disrupting barrier structure and its manufacturing method described in this invention effectively isolate two sub-pixels and enhance resistance to current interference by improving the process flow, specifically by employing an asymmetric undercut process between sub-pixels. Through the structure and fabrication process of this invention, an asymmetric barrier opening is provided on the stacked structure, and a groove structure is provided within the barrier opening. The height of this groove structure is greater than or equal to the height difference between the charge generation layer and the first electrode, effectively isolating the charge generation layer between adjacent sub-pixels and avoiding crosstalk between them. Through structural and process improvements, the charge generation layer between adjacent sub-pixels is isolated, preventing crosstalk and thus improving the overall performance of the product. Attached Figure Description

[0024] The following is a brief explanation of the contents depicted in the accompanying drawings and the markings therein:

[0025] Figure 1 This is a schematic diagram of the structure of a CMOS substrate formed using the manufacturing method of the silicon-based OLED lateral turbulence barrier structure described in this invention;

[0026] Figure 2-1 This is a schematic diagram of the structure of the CMOS substrate anode layer when the silicon-based OLED lateral turbulence barrier structure is deposited using the manufacturing method of the silicon-based OLED lateral turbulence barrier structure described in this invention.

[0027] Figure 2-2 A schematic diagram of a CMOS substrate fed into a photolithography apparatus using the manufacturing method of the silicon-based OLED lateral turbulence barrier structure described in this invention.

[0028] Figure 2-2-1 This is a schematic diagram of the structure of a CMOS substrate after cleaning, coating, exposure, development, and curing following the manufacturing method of the silicon-based OLED lateral turbulence barrier structure described in this invention.

[0029] Figure 2-2-2A schematic diagram of the CMOS substrate patterned using the manufacturing method of the silicon-based OLED lateral turbulence barrier structure described in this invention.

[0030] Figure 2-3 This is a schematic diagram of the structure when forming an inorganic material layer on a CMOS substrate using the manufacturing method of the silicon-based OLED lateral turbulence barrier structure described in this invention.

[0031] Figure 2-3-1 This is a schematic diagram of the structure after cleaning, coating, exposure, development, and curing of the inorganic film layer of the CMOS substrate formed by the manufacturing method of the silicon-based OLED lateral turbulence barrier structure described in this invention.

[0032] Figure 2-3-2 This is a schematic diagram of the structure of the inorganic film layer obtained by forming a CMOS substrate using the manufacturing method of the silicon-based OLED lateral turbulence barrier structure described in this invention.

[0033] Figure 2-4 This is a schematic diagram of the structure when a CMOS substrate is formed by the manufacturing method of the silicon-based OLED lateral turbulence barrier structure described in this invention to obtain a stacked structure.

[0034] Figure 2-5 This is a schematic diagram of the structure of a CMOS substrate formed by the manufacturing method of the silicon-based OLED lateral turbulence barrier structure described in this invention, when the pixel definition area is photolithographically etched using Mask1.

[0035] Figure 2-5-1 This is a schematic diagram of the CMOS substrate cleaned to remove polymer using the manufacturing method of the silicon-based OLED lateral turbulence barrier structure described in this invention.

[0036] Figure 2-6-1 This is a schematic diagram of the structure of a CMOS substrate formed by the manufacturing method of the silicon-based OLED lateral turbulence barrier structure described in this invention, when the third inorganic material layer of the undercut structure is patterned using Mask2.

[0037] Figure 2-6-2 This is a schematic diagram of the CMOS substrate cleaned to remove polymer using the manufacturing method of the silicon-based OLED lateral turbulence barrier structure described in this invention.

[0038] Figure 2-7-1 This is a schematic diagram of the structure of a CMOS substrate formed by the manufacturing method of the silicon-based OLED lateral turbulence barrier structure described in this invention, when the second inorganic material layer of the undercut structure is patterned using Mask3.

[0039] Figure 2-7-2This is a schematic diagram of the CMOS substrate cleaned to remove polymer using the manufacturing method of the silicon-based OLED lateral turbulence barrier structure described in this invention.

[0040] Figure 2-8-1 This is a schematic diagram of the structure of a CMOS substrate formed by the manufacturing method of the silicon-based OLED lateral turbulence barrier structure described in this invention, when the first inorganic material layer of the undercut structure is patterned using Mask4.

[0041] Figure 2-8-2 This is a schematic diagram of the CMOS substrate cleaned to remove polymer using the manufacturing method of the silicon-based OLED lateral turbulence barrier structure described in this invention.

[0042] The labels in the attached diagram are as follows: 1. Anode layer; 2. CMOS substrate (CMOS Wafer); 3. Organic light-emitting layer (organic light-emitting material layer, organic light-emitting composite layer); 4. Inorganic film layer; 5. First inorganic material layer; 6. Third inorganic material layer; 7. Second inorganic material layer; 8. Cathode layer. Detailed Implementation

[0043] The following description, with reference to the accompanying drawings, provides a more detailed explanation of the specific embodiments of the present invention, including the shape and structure of each component, the relative positions and connections between the parts, the functions and working principles of each part:

[0044] As attached Figure 1 As shown, this invention relates to a method for manufacturing a silicon-based OLED lateral flow-disrupting barrier structure. The manufacturing steps of the method for manufacturing the silicon-based OLED lateral flow-disrupting barrier structure are as follows:

[0045] S1. Obtain a CMOS substrate 2, then deposit an anode layer 1 on the CMOS substrate 2. Through coating, exposure, development, etching, and stripping, an anode pattern is formed. S2. Deposit an inorganic material layer on the anode pattern. The thickness of the inorganic material layer is greater than or equal to that of the anode pattern. Through coating, exposure, development, etching, and stripping, a planarized inorganic film layer 4 is formed. S3. On the planarized inorganic film layer 4, a first inorganic material layer 5, a second inorganic material layer 7, and a third inorganic material layer 6 are deposited in a single vapor deposition to form a stack. Through coating, exposure, development, etching, and stripping, an undercut structure is formed. The undercut structure is located in the non-pixel definition area. S4. To form the undercut structure... The undercut structure involves controlling the etching rate between each layer of the stack formed by the first inorganic material layer 5, the second inorganic material layer 7, and the third inorganic material layer 6. Materials with different etching rates are used to construct the first inorganic material layer 5, the second inorganic material layer 7, and the third inorganic material layer 6, respectively. The etching rate of the second inorganic material layer 7 is greater than that of the first inorganic material layer 5 and the third inorganic material layer 6. An asymmetric partition opening is formed on the stack formed by the first inorganic material layer 5, the second inorganic material layer 7, and the third inorganic material layer 6, and a groove is formed within the partition opening. The height of the groove is greater than or equal to the height difference between the charge generation layer and the first electrode. After the undercut structure is formed, the organic light-emitting layer 3 is deposited by vapor deposition. The undercut structure isolates the organic light-emitting layer 3, and finally, the cathode layer 8 is formed by vapor deposition. This structure addresses the shortcomings of existing technologies by proposing an improved technical solution. By improving the process flow, i.e., using an asymmetric undercut process between sub-pixels, two sub-pixels can be effectively isolated, enhancing resistance to current interference. Through the structure and fabrication process of this invention, an asymmetric partition opening is set on the stacked structure, and a groove structure is set within the partition opening. The height of the groove structure is greater than or equal to the height difference between the charge generation layer and the first electrode, thereby effectively isolating the charge generation layers between adjacent sub-pixels and avoiding crosstalk between adjacent sub-pixels. Because the charge generation layers between adjacent sub-pixels are isolated through structural and process improvements, crosstalk between adjacent sub-pixels is avoided, improving the overall performance of the product. The manufacturing method of the silicon-based OLED lateral turbulence isolation structure described in this invention has simple steps, solves the problem of current interference between light-emitting units causing adjacent display units to dim and affecting the display effect, and improves the display effect.

[0046] After the undercut structure is formed, a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), and an electron transport layer (ETL) are deposited in an evaporation machine to form an organic light-emitting layer 3 (organic light-emitting composite layer and organic light-emitting material layer), and the organic light-emitting layer 3 is broken at the groove. After the organic light-emitting layer 3 is deposited, a cathode layer 8 is deposited to obtain a silicon-based OLED lateral turbulence barrier structure. The product structure obtained by the manufacturing method of the present invention is shown in the attached drawings of the specification. Figure 1 As shown.

[0047] A CMOS driving circuit is fabricated on a silicon wafer substrate to form a CMOS substrate 2. The CMOS substrate is then cleaned. After cleaning, the CMOS substrate is deposited using a metal sputtering machine to form an anode layer. After the anode layer is formed, the CMOS substrate is subjected to photolithography equipment for cleaning, coating, exposure, development, and curing. The pattern is completed using a pH process, and the substrate is then subjected to dry etching (etching). After etching, in-situ resist stripping (PR) is performed. After in-situ resist stripping, the CMOS substrate is cleaned using an STR (Solid State Removal) machine to remove the polymer, finally obtaining the anode pattern.

[0048] After the CMOS substrate 2 is cleaned in the STR equipment, it is then deposited with inorganic material in the chemical vapor deposition equipment. The thickness of the inorganic material layer of the anode pattern is greater than or equal to the coating thickness of the anode layer 1 to ensure that the channels between the anodes are completely filled. After the inorganic material coating is completed, it is put into the photolithography equipment for cleaning, coating, exposure, development and curing. The pH process completes the patterning, and it is put into the etching equipment for dry etching. After the etching is completed, the resist stripping PR is performed. After the resist stripping is completed, the CMOS substrate 2 is cleaned in the STR equipment to remove the polymer, thus obtaining the planarized inorganic film layer 4.

[0049] Before coating, the planarized inorganic film layer 4 is cleaned, and then the first inorganic material layer 5 is coated using a chemical vapor deposition equipment, followed by the second inorganic material layer 7, and then the third inorganic material layer 6. The above coating process is repeated to form a stack. The stack of inorganic material layers is then placed in a photolithography equipment, and the pixel definition area is photolithographically etched using Mask1. The process includes cleaning, coating, exposure, development, and curing.

[0050] After the PH process is completed, the substrate is patterned and then subjected to dry etching in an etching device to etch away the stack of the first inorganic material layer 5, the second inorganic material layer 7, and the third inorganic material layer 6 of the pixel definition area (PDL pixel definition layer). After etching, in-situ resist stripping (PR) is performed. After in-situ resist stripping, the CMOS substrate 2 is cleaned in an STR device to remove the polymer. After the pixel definition area is etched, the substrate is subjected to photolithography in a photolithography device, where the third inorganic material layer 6 of the undercut structure is patterned using Mask 2, followed by cleaning, coating, exposure, development, and curing.

[0051] The PH process completes the patterning of the third inorganic material layer 6, and then the substrate is sent to the Etch equipment for dry etching to remove the third inorganic material layer 6. The etching process formula for the third inorganic material layer 6 adopts a high selectivity ratio, ignoring the underloss of the underlying second inorganic material layer 7. After etching, in-situ resist stripping (PR) is performed. After resist stripping, the CMOS substrate 2 is sent to the STR equipment for cleaning to remove the polymer, thus realizing the patterning of the third inorganic material layer 6.

[0052] After the third inorganic material layer 6 of the undercut structure is etched, it enters the photolithography equipment and uses Mask3 to pattern the second inorganic material layer 7 of the undercut structure. This involves cleaning, coating, exposure, development, and curing. The pH process completes the patterning of the second inorganic material layer 7, and then it enters the Etch equipment for dry etching to remove the second inorganic material layer 7. The etching process for the second inorganic material layer 7 uses a high selectivity ratio, ignoring the under-loss of the underlying first inorganic material layer 5. After etching, in-situ resist stripping (PR) is performed. After in-situ resist stripping, the CMOS substrate 2 enters the STR equipment for cleaning to remove the polymer, thus achieving the patterning of the second inorganic material layer 7.

[0053] After etching the second inorganic material layer 7 of the undercut structure, the first inorganic material layer 5 of the undercut structure is patterned using Mask 4. It then enters the photolithography equipment for cleaning, coating, exposure, development, and curing. The first inorganic material layer 5 is patterned using a pH process, and then dry-etched away using an Etch device. The etching process for the first inorganic material layer 5 uses a high selectivity ratio, ignoring the under-loss of the underlying inorganic film layer 4. After etching, in-situ resist stripping (PR) is performed. After in-situ resist stripping, the CMOS substrate 2 is cleaned using an STR device to remove the polymer, achieving patterning of the first inorganic material layer 5, thus completing the undercut structure of the PDL layer.

[0054] This invention also relates to a silicon-based OLED lateral turbulence isolation structure with a simple structure that solves the problem of current interference between light-emitting units causing adjacent display units to dim and affect the display effect, thereby improving the display effect.

[0055] The silicon-based OLED lateral turbulence barrier structure includes an anode layer 1, a CMOS substrate 2, an organic light-emitting layer 3, an inorganic film layer 4, a first inorganic material layer 5, a third inorganic material layer 6, a second inorganic material layer 7, and a cathode layer 8.

[0056] Specific embodiments of the manufacturing method described in this invention are shown below:

[0057] Step 1: Fabricate CMOS driving circuits on a silicon substrate to form a CMOS substrate. Clean the CMOS wafer (CMOS substrate, wafer) to obtain the following... Figure 2-1 .

[0058] Step 2: As Figure 2-1 After cleaning, the CMOS substrate is subjected to a metal sputtering machine to deposit an anode layer. The result is as follows: Figure 2-2 .

[0059] Step 3: After coating, the film is placed in photolithography equipment for cleaning, coating, exposure, development, and curing. The result is as follows: Figure 2-2-1 .

[0060] Step 4: As Figure 2-2-1 The pH process completes the patterning, followed by dry etching in the etching equipment. After etching, in-situ photoresist stripping is performed. Following in-situ stripping, the wafer is cleaned in the STR (Stripping Equipment) system to remove polymer and achieve patterning, resulting in the desired product. Figure 2-2-2 .

[0061] Step 5: As Figure 2-2-2 After the CMOS substrate undergoes STR cleaning, it is then deposited with an inorganic material layer using a chemical vapor deposition (CVD) system to form inorganic film layer 4. The thickness of inorganic film layer 4 is not less than the thickness of anode layer 1, ensuring complete filling of the channels between the anodes. The result is as follows: Figure 2-3 .

[0062] Step 6: As Figure 2-3 After the inorganic film layer 4 is formed, the substrate is placed in a photolithography machine for cleaning, coating, exposure, development, and curing. The result is as follows: Figure 2-3-1 .

[0063] Step 7: As Figure 2-3-1 The patterning process is completed using the pH process, followed by dry etching in the etching equipment. After etching, in-situ photoresist stripping is performed. After in-situ photoresist stripping (dry stripping), the wafer is cleaned in the STR (Stripping Equipment) to remove the polymer, resulting in a planarized inorganic film layer 4, as shown. Figure 2-3-2 .

[0064] Step 8: As Figure 2-3-2 The planarized inorganic film layer 4 is pre-cleaned before chemical deposition, then a first inorganic material layer 5 is deposited using a chemical vapor deposition (CVD) system, followed by a second inorganic material layer 7. This deposition process is repeated until a single-pass deposition is achieved, forming a stack of inorganic material layers, as shown in the image. Figure 2-4 .

[0065] Step 9: As Figure 2-4 Inorganic material layer-by-layer structures are processed using photolithography equipment, with Mask1 used to lithographically define pixel areas. The process involves cleaning, coating, exposure, development, and curing. The result is as follows: Figure 2-5 .

[0066] Step 10: As Figure 2-5 After the pH process, the wafer is patterned and then subjected to dry etching to remove the inorganic material layers in the PDL pixel definition area. Following etching, in-situ photoresist stripping is performed. After in-situ photoresist stripping, the wafer is cleaned in an STR (Stripping Equipment) system to remove polymer, resulting in the desired product. Figure 2-5-1 .

[0067] Step 11: As Figure 2-5-1 After the PDL pixel definition layer is etched, it enters the photolithography equipment. Mask 2 is used to pattern the third inorganic material layer 6 of the undercut structure. The process involves cleaning, coating, exposure, development, and curing to obtain the desired result. Figure 2-6-1 .

[0068] Step 12: As Figure 2-6-1The PH process completes the patterning of the third inorganic material layer 6, which is then processed by dry etching in an Etch apparatus to remove it. The etching process for the third inorganic material layer 6 uses a high selectivity ratio, resulting in negligible underloss of the underlying second inorganic material layer 7. After etching, in-situ photoresist stripping is performed. Following in-situ photoresist stripping, the wafer is cleaned in an STR apparatus to remove polymer, achieving patterning. Figure 2-6-2 .

[0069] Step 13: As Figure 2-6-2 After etching the third inorganic material layer 6 in the PDL undercut region, the image is processed using a photolithography device. Mask 3 is used to pattern the second inorganic material layer 7 of the undercut structure. The process includes cleaning, coating, exposure, development, and curing to obtain the desired result. Figure 2-7-1 .

[0070] Step 14: As Figure 2-7-1 The PH process completes the patterning of the second inorganic material layer 7, which is then processed by dry etching in an Etch apparatus to remove it. The etching process for the second inorganic material layer 7 uses a high selectivity ratio, resulting in negligible underloss of the underlying first inorganic material layer 5. After etching, in-situ photoresist stripping is performed. Following in-situ photoresist stripping, the wafer is cleaned in an STR apparatus to remove polymer, achieving patterning. Figure 2-7-2 .

[0071] Step 15: As Figure 2-7-2 After etching the second inorganic material layer 7 of the PDL undercut structure, the pattern of the first inorganic material layer 5 undercut is performed using Mask 4. The material is then processed in a photolithography apparatus for cleaning, coating, exposure, development, and curing to obtain the desired result. Figure 2-8-1 .

[0072] Step 16: As Figure 2-8-1 The first inorganic material layer 5 is patterned using the PH process. Then, it is etched away using an Etch device. The etching process for the first inorganic material layer 5 employs a high selectivity ratio, resulting in negligible underloss for the underlying inorganic film layer 4. After etching, in-situ photoresist stripping is performed. Following in-situ photoresist stripping, the wafer is cleaned using an STR device to remove polymer and achieve patterning. Figure 2-8-2 .

[0073] By now, through Step 1 to Step 14, the Undercut (groove) structure of the PDL planarization layer has been completed.

[0074] Step 17: As Figure 2-8-2 After the PDL undercut is fabricated, organic light-emitting composite layers, including a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), and an electron transport layer (ETL), are deposited in an evaporation machine, and then broken at the PDL groove. The isolation effect depends on the groove structure; at least the HIL and HTL layers will break, and at most the ETL and EIL layers will break. After the organic light-emitting layers are deposited, the cathode is deposited, and the final product is as follows: Figure 1 The PDL undercut partition evaporation luminescent layer process is now complete.

[0075] The silicon-based OLED lateral current-disrupting barrier structure and its manufacturing method described in this invention effectively isolate two sub-pixels and enhance resistance to current interference by improving the process flow, specifically by employing an asymmetric undercut process between sub-pixels. Through the structure and fabrication process of this invention, an asymmetric barrier opening is provided on the stacked structure, and a groove structure is provided within the barrier opening. The height of this groove structure is greater than or equal to the height difference between the charge generation layer and the first electrode, effectively isolating the charge generation layer between adjacent sub-pixels and avoiding crosstalk between them. Through structural and process improvements, the charge generation layer between adjacent sub-pixels is isolated, preventing crosstalk and thus improving the overall performance of the product.

[0076] The present invention has been described above by way of example with reference to the accompanying drawings. Obviously, the specific implementation of the present invention is not limited to the above-described manner. Any improvements made by adopting the inventive concept and technical solution of the present invention, or the direct application of the inventive concept and technical solution of the present invention to other occasions without modification, are all within the protection scope of the present invention.

Claims

1. A method for manufacturing a silicon-based OLED lateral flow-disrupting barrier structure, characterized in that: The manufacturing steps of the method for manufacturing the silicon-based OLED lateral flow barrier structure are as follows: S1. Obtain a CMOS substrate (2), and then deposit an anode layer (1) on the CMOS substrate (2). Through coating, exposure, development, etching and stripping, an anode pattern is formed. S2. An inorganic material layer is deposited on the anode pattern. The thickness of the inorganic material layer is greater than or equal to that of the anode pattern. The inorganic material layer is planarized through coating, exposure, development, etching and stripping (4). S3. On the planarized inorganic film layer (4), a first inorganic material layer (5), a second inorganic material layer (7), and a third inorganic material layer (6) are deposited in one step to form a stack. Through coating, exposure, development, etching, and stripping, an undercut structure is formed. The undercut structure is in the non-pixel definition area. S4. To form an undercut structure, the etching rate between each layer of the stack formed by the first inorganic material layer (5), the second inorganic material layer (7), and the third inorganic material layer (6) is adjusted, and materials with different etching rates are used to form the first inorganic material layer (5), the second inorganic material layer (7), and the third inorganic material layer (6), respectively; wherein, the etching rate of the second inorganic material layer (7) is greater than the etching rate of the first inorganic material layer (5) and the third inorganic material layer (6); an asymmetric partition opening is provided on the stack formed by the first inorganic material layer (5), the second inorganic material layer (7), and the third inorganic material layer (6), and a groove is provided in the partition opening, the height of which is greater than or equal to the height difference between the charge generation layer and the first electrode; S5. After the undercut structure is formed, an organic light-emitting layer (3) is deposited by vapor deposition. The undercut structure blocks the organic light-emitting layer (3), and finally a cathode layer (8) is deposited by vapor deposition.

2. The manufacturing method of the silicon-based OLED lateral flow-disrupting barrier structure according to claim 1, characterized in that: After the undercut structure is formed, a hole injection layer, a hole transport layer, a light-emitting layer, and an electron transport layer are deposited in the evaporation machine to form an organic light-emitting layer (3), and the organic light-emitting layer (3) is broken at the groove. After the organic light-emitting layer (3) is deposited, a cathode layer (8) is deposited to obtain a silicon-based OLED lateral turbulence barrier structure.

3. The manufacturing method of the silicon-based OLED lateral flow-disrupting barrier structure according to claim 2, characterized in that: A CMOS driving circuit is fabricated on a silicon wafer substrate to form a CMOS substrate (2). The CMOS substrate (2) is then cleaned. After cleaning, the CMOS substrate (2) is coated to form an anode layer. After the CMOS substrate (2) is coated to form an anode layer (1), it is then subjected to photolithography equipment for cleaning, coating, exposure, development, and curing. The patterning is completed by the pH process, and dry etching is performed. After etching, in-situ resist stripping and PR are performed. After resist stripping, the CMOS substrate (2) is cleaned to remove the polymer, and finally the anode pattern is obtained.

4. The manufacturing method of the silicon-based OLED lateral flow-disrupting barrier structure according to claim 3, characterized in that: After cleaning the CMOS substrate (2), an inorganic material layer is deposited. The thickness of the inorganic material layer is greater than or equal to the coating thickness of the anode layer (1) to ensure that the channels between the anodes are completely filled. After the inorganic material layer is coated, it is cleaned, coated, exposed, developed and cured. The PH process completes the patterning and dry etching is performed. After etching, in-situ resist removal and PR stripping are performed. After resist removal, the CMOS substrate (2) is cleaned to remove the polymer, and a planarized inorganic film layer (4) is obtained.

5. The manufacturing method of the silicon-based OLED lateral flow-disrupting barrier structure according to claim 4, characterized in that: Before coating the planarized inorganic film layer (4), clean it, then coat the first inorganic material layer (5), then coat the second inorganic material layer (7), then coat the third inorganic material layer (6), repeat the above coating process to form a stack; use Mask1 to perform photolithography on the pixel definition area; perform cleaning, coating, exposure, development and curing.

6. The method for manufacturing the silicon-based OLED lateral flow-disrupting barrier structure according to claim 5, characterized in that: After the PH process is completed, the pattern is created and dry etching is performed to etch away the stack of the first inorganic material layer (5), the second inorganic material layer (7), and the third inorganic material layer (6) of the pixel definition area (PDL pixel definition layer). After etching, in-situ resist stripping and PR are performed. After in-situ resist stripping and PR are performed, the CMOS substrate (2) is cleaned to remove the polymer. After the pixel definition area is etched, the third inorganic material layer (6) of the undercut structure is patterned using Mask2, and then cleaned, coated, exposed, developed, and cured.

7. The method for manufacturing the silicon-based OLED lateral flow-disrupting barrier structure according to claim 6, characterized in that: The PH process completes the patterning of the third inorganic material layer (6), and the third inorganic material layer (6) is dry etched away. The process formula for etching the third inorganic material layer (6) adopts a high selectivity ratio, and the under loss of the lower second inorganic material layer (7) is ignored. After etching, in-situ resist stripping and PR removal are performed; after resist stripping, the CMOS substrate (2) is cleaned to remove the polymer and the third inorganic material layer (6) is patterned.

8. The method for manufacturing the silicon-based OLED lateral flow-disrupting barrier structure according to claim 7, characterized in that: After etching the third inorganic material layer (6) of the Undercut structure, Mask3 is used to pattern the second inorganic material layer (7) of the Undercut structure, followed by cleaning, coating, exposure, development, and curing. The PH process completes the patterning of the second inorganic material layer (7) and then the second inorganic material layer (7) is dry etched away. The process formula for etching the second inorganic material layer (7) adopts a high selectivity ratio, and the under loss of the first inorganic material layer (5) is ignored. After etching, in-situ resist removal and peeling (PR) are performed. After in-situ resist removal and peeling, the CMOS substrate (2) is cleaned to remove the polymer, and the second inorganic material layer (7) is patterned.

9. The method for manufacturing the silicon-based OLED lateral flow-disrupting barrier structure according to claim 8, characterized in that: After etching the second inorganic material layer (7) of the Undercut structure, Mask4 is used to pattern the first inorganic material layer (5) of the Undercut structure, followed by cleaning, coating, exposure, development, and curing. The first inorganic material layer (5) is patterned using the PH process, and then the first inorganic material layer (5) is etched away using dry etching. The etching process formula for the first inorganic material layer (5) adopts a high selectivity ratio, and the under loss of the underlying inorganic film layer (4) is ignored. After etching, in-situ resist removal and peeling (PR) are performed. After in-situ resist removal and peeling, the CMOS substrate (2) is cleaned to remove the polymer, thus realizing the patterning of the first inorganic material layer (5), which means that the undercut structure of the PDL layer is completed.

10. The silicon-based OLED lateral flow barrier structure manufactured by the manufacturing method of the silicon-based OLED lateral flow barrier structure according to claim 1, characterized in that: It includes an anode layer (1), a CMOS substrate (2), an organic light-emitting layer (3), an inorganic film layer (4), a first inorganic material layer (5), a third inorganic material layer (6), a second inorganic material layer (7), and a cathode layer (8).

Images