An impedance source type three-level inverter and modulation method thereof

Abstract

The present invention belongs to the field of power electronic converter control technology and proposes an impedance-source three-level inverter and a modulation method thereof. The impedance-source three-level inverter in the present invention includes a DC power supply, a boost network, a low-voltage stress three-level inverter, and a load. The low-voltage stress three-level inverter includes three-phase bridge arms, each of which includes a first power device with a collector connected to one end of the boost network, a second power device with a collector connected to an emitter of the first power device, a third power device with an emitter connected to an emitter of the second power device, and a fourth power device with a collector connected to an emitter of the second power device. Compared with traditional quasi-Z-source NPC three-level inverters and quasi-Z-source T-type three-level inverters, the number of high-voltage stress devices is reduced. The proposed modulation method uses only a single carrier signal, making it easy to implement digitally.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronic converter control, and in particular relates to an impedance source type three-level inverter and a modulation method thereof. Background Art

[0002] Impedance-source three-level inverters replace the DC / DC boost converter by adding a boost network to the front end of a traditional three-level inverter. This achieves both boost and inversion functions in a single-stage power conversion process while maintaining a multi-level waveform output. These inverters have found widespread application in fields such as solar photovoltaic power generation, fuel cells, and energy storage systems. Currently, commonly used impedance-source three-level circuit topologies include the quasi-Z-source neutral-point-clamped (NPC) three-level inverter, the quasi-Z-source T-type three-level inverter, the Z-source NPC three-level inverter, and the Z-source T-type three-level inverter. Quasi-Z-source NPC and T-type three-level inverters offer significant advantages, particularly due to their continuous input current.

[0003] The modulation method bridges the gap between the inverter control strategy and the main circuit, converting the control signal into a PWM drive signal for the power devices, which directly impacts system efficiency, stability, and reliability. Space Vector Modulation (SVM) offers advantages such as high DC voltage utilization and high output waveform quality, and has been widely used in impedance-source three-level inverter systems. However, traditional SVM methods involve sector determination, basic voltage vector selection, action time calculation, shoot-through state injection, switching sequence design, and PWM drive signal generation. Furthermore, these methods require complex trigonometric calculations, making digital implementation highly complex. Carrier-Based Modulation (CBM) offers an ideal solution, eliminating the need for complex computations and facilitating digital implementation.

[0004] The inventors discovered that the quasi-Z-source NPC three-level inverter circuit topology contains 12 power devices and six clamping diodes, resulting in high system costs. The quasi-Z-source T-type three-level inverter circuit topology contains only 12 power devices and eliminates the need for clamping diodes. However, the voltage stress of six of these power devices is high, equal to the output current amplitude of the boost network, resulting in still high system costs. Compared with traditional space vector modulation methods, carrier modulation methods are easier to implement digitally. However, most existing carrier modulation methods are designed for traditional three-level inverter systems. Therefore, research is urgently needed on impedance-source three-level inverter circuit topologies that exhibit low power device voltage stress and simplified carrier modulation methods. Summary of the Invention

[0005] To solve the above problems, the present invention proposes an impedance source three-level inverter and a modulation method thereof, which reduces the number of high voltage stress devices and thus reduces system costs. At the same time, the proposed modulation method only uses a single carrier signal, which facilitates digital implementation of a digital controller.

[0006] In order to achieve the above objectives, in a first aspect, the present invention provides an impedance source type three-level inverter, which adopts the following technical solution:

[0007] An impedance source three-level inverter comprises a DC power supply, a boost network connected to the DC power supply, a low voltage stress three-level inverter connected to the boost network, and a load connected to the low voltage stress three-level inverter;

[0008] The low-voltage stress type three-level inverter includes three-phase bridge arms, each phase bridge arm includes a first power device whose collector is connected to one end of the boost network, a second power device whose collector is connected to the emitter of the first power device, a third power device whose emitter is connected to the emitter of the second power device, and a fourth power device whose collector is connected to the emitter of the second power device, the emitter of the fourth power device is connected to the other end of the boost network, and the collector of the third power device is connected to the neutral point of the boost network; the low-voltage stress type three-level inverter is used to convert the direct current output by the boost network into alternating current, the voltage stress of the first power device is equal to the output voltage amplitude of the boost network, and the voltage stress of the second power device, the third power device and the fourth power device is equal to half the output voltage amplitude of the boost network.

[0009] Furthermore, the boost network includes a first inductor connected to one end of the DC power supply, a first diode connected to the first inductor, a second inductor connected to the first diode, a third inductor connected to the other end of the DC power supply, a second diode connected to the third inductor, and a fourth inductor connected to the second diode; the second inductor is connected to the first power device, and the fourth inductor is connected to the fourth power device.

[0010] Furthermore, a first capacitor is connected in parallel between the anode of the first diode and the end of the second inductor away from the first diode; a second capacitor and a third capacitor are connected between the cathode of the first diode and the anode of the second diode; and a fourth capacitor is connected in parallel between the cathode of the second diode and the end of the fourth inductor away from the second diode.

[0011] Furthermore, the positive output terminal of the boost network is connected to the first power device, and the negative output terminal of the boost network is connected to the fourth power device.

[0012] In order to achieve the above objectives, in a second aspect, the present invention further provides an impedance source type three-level inverter modulation method, which adopts the following technical solution:

[0013] A modulation method for an impedance source three-level inverter, using the impedance source three-level inverter as described in the first aspect, comprising:

[0014] Compare the size relationship of the three-phase original modulation waves and generate a flag bit;

[0015] Split the single modulation wave of each phase in the three-phase original modulation wave into dual modulation waves;

[0016] Obtaining the voltage across the capacitor in the boost network, calculating the difference and processing it through a proportional-integral controller to obtain a given value of the neutral current and update the modulation wave;

[0017] Determine the through state injection phase according to the generated flag bit and the updated modulation wave, and calculate the modulation wave used to inject the through state;

[0018] Modify the modulation wave used to inject the through state;

[0019] The modified modulation wave is compared with the single carrier wave to generate a driving signal; and the generated driving signal is used to control the operation of the impedance source type three-level inverter.

[0020] Furthermore, when the A-phase modulation wave is not less than the B-phase modulation wave, and the B-phase modulation wave is greater than the C-phase modulation wave, the flag is equal to 1; when the B-phase modulation wave is greater than the A-phase modulation wave, and the A-phase modulation wave is not less than the C-phase modulation wave, the flag is equal to 2; when the B-phase modulation wave is not less than the C-phase modulation wave, and the C-phase modulation wave is greater than the A-phase modulation wave, the flag is equal to 3; when the C-phase modulation wave is greater than the B-phase modulation wave, and the B-phase modulation wave is not less than the A-phase modulation wave, the flag is equal to 4; when the C-phase modulation wave is not less than the A-phase modulation wave, and the A-phase modulation wave is greater than the B-phase modulation wave, the flag is equal to 5; when the A-phase modulation wave is greater than the C-phase modulation wave, and the C-phase modulation wave is not less than the B-phase modulation wave, the flag is equal to 6.

[0021] Furthermore, when the flag bit is equal to 1, and two modulation waves in the modulation wave of phase B are respectively greater than zero and less than zero, the modulation wave of phase B is updated.

[0022] Furthermore, the voltages across the second capacitor and the third capacitor are obtained, the difference between the voltages across the second capacitor and the third capacitor is calculated, and the difference is input into a proportional-integral controller to obtain a given value of the neutral current.

[0023] Furthermore, when the flag bit is equal to 1, the direct-through state is injected into phase A and phase C; when the flag bit is equal to 2, the direct-through state is injected into phase B and phase C; when the flag bit is equal to 3, the direct-through state is injected into phase B and phase A; when the flag bit is equal to 4, the direct-through state is injected into phase C and phase A; when the flag bit is equal to 5, the direct-through state is injected into phase C and phase B; when the flag bit is equal to 6, the direct-through state is injected into phase A and phase B.

[0024] Furthermore, a modulated wave modified based on the updated modulated wave is compared with a single carrier to obtain a first component of the drive signal; a modulated wave modified based on the injected through state is compared with a single carrier to obtain a second component of the drive signal; and a logical OR operation is performed on the first component and the second component to obtain a final drive signal for the power device.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] The impedance source three-level inverter of the present invention can realize boost and inversion functions in a single-stage power conversion mode and maintain a multi-level output waveform;

[0027] For the impedance source three-level inverter of the present invention, the voltage stress of only one power device in each phase bridge arm is equal to the output voltage amplitude of the boost network, and the voltage stress of the other three power devices is equal to half of the output voltage amplitude of the boost network;

[0028] The method of the present invention can effectively control the midpoint voltage balance and is applicable to different power factor working conditions. The voltage fluctuation amplitude across each capacitor in the boost network is very small.

[0029] The method of the present invention adopts only a single carrier modulation method, and is easy to realize digitalization of a digital controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The drawings constituting a part of the specification of this embodiment are used to provide a further understanding of this embodiment. The schematic embodiments and descriptions of this embodiment are used to explain this embodiment and do not constitute an improper limitation on this embodiment.

[0031] Figure 1 This is a topology diagram of the impedance source three-level inverter circuit of the present invention;

[0032] Figure 2 is a control block diagram of the single carrier modulation method of the present invention;

[0033] Figure 3 A comparative logic diagram of a single carrier modulation method of the present invention;

[0034] 4( a ) and 4 ( b ) are steady-state operating waveforms of the impedance source type three-level inverter of the present invention with the output side connected to load 1 and in a non-boost operation mode;

[0035] 5( a ) and 5 ( b ) are steady-state operating waveforms of the impedance source type three-level inverter of the present invention with the output side connected to load 1 and in boost operation mode;

[0036] 6( a ) and 6 ( b ) are steady-state operating waveforms of the impedance source type three-level inverter of the present invention with the output side connected to a load 2 and in a non-boost operation mode;

[0037] 7( a ) and 7 ( b ) are steady-state operating waveforms of the impedance source type three-level inverter of the present invention with the output side connected to a load 2 and in a boost operation mode;

[0038] Figure 8 This is a dynamic operating waveform diagram of the impedance source type three-level inverter of the present invention when the output side is connected to load 1, the inverter is in non-boost operation mode, and the modulation index increases from 0.6 to 0.8;

[0039] Figure 9 This is a dynamic operating waveform diagram of the impedance source type three-level inverter of the present invention when the output side is connected to load 1, the voltage is in boost operation mode, and the modulation index increases from 0.6 to 0.8. DETAILED DESCRIPTION

[0040] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0041] It should be noted that the following detailed descriptions are exemplary and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present application belongs.

[0042] Example 1:

[0043] The quasi-Z-source NPC three-level inverter circuit topology contains 12 power devices and 6 clamping diodes, resulting in a relatively high system cost. The quasi-Z-source T-type three-level inverter circuit topology contains only 12 power devices and does not require clamping diodes. However, the voltage stress of the six power devices is relatively high, which is equal to the output current amplitude of the boost network, resulting in a still relatively high system cost.

[0044] In response to the above issues,

[0045] This embodiment provides an impedance source type three-level inverter (such as Figure 1 ) includes a DC power supply, a boost network connected to the DC power supply, a low voltage stress type three-level inverter connected to the boost network, and a load connected to the low voltage stress type three-level inverter;

[0046] The low-voltage stress three-level inverter includes three-phase bridge arms, each phase bridge arm includes a first power device whose collector is connected to one end of the boost network, a second power device whose collector is connected to the emitter of the first power device, a third power device whose emitter is connected to the emitter of the second power device, and a fourth power device whose collector is connected to the emitter of the second power device, the emitter of the fourth power device is connected to the other end of the boost network, and the collector of the third power device is connected to the neutral point of the boost network; compared with the traditional quasi-Z-source NPC three-level inverter and the quasi-Z-source T-type three-level inverter, the number of high-voltage stress devices is reduced and the system cost is reduced; the low-voltage stress three-level inverter is used to convert the direct current output of the boost network into alternating current, the voltage stress of the first power device is equal to the output voltage amplitude of the boost network, and the voltage stress of the second power device, the third power device and the fourth power device is equal to half the output voltage amplitude of the boost network.

[0047] Figure 1 The low voltage stress three-level inverter is used to convert the DC power output by the boost network into AC power. It includes three-phase bridge arms of phase A, phase B and phase C. Each phase bridge arm includes four power devices, which are respectively denoted as the first power device S j1 , the second power device S j2 , the third power device S j3 and the fourth power device S j4 Wherein, j = a, b, c; the first power device S j1 The emitter of the second power device S j2 The collector of the power device S j2 The emitter of the third power device S j3 The emitter and the fourth power device S j4 The collector of the first power device S j1 The collector of the boost network is connected to the output + terminal; the third power device S j3 The collector of the fourth power device S is connected to the neutral point O of the boost network; j4 The emitter is connected to the output-end of the boost network.

[0048] The boost network is used to increase the DC input voltage, and the boost network includes a DC power supply V in The first inductor L1 connected to one end, the first diode D1 connected to the first inductor L1, the second inductor L2 connected to the first diode D1, and the DC power supply V in The other end is connected to a third inductor L3, a second diode D2 connected to the third inductor L3, and a fourth inductor L4 connected to the second diode D2; the second inductor L4 is connected to the first power device Sj1 The fourth inductor L4 is connected to the fourth power device S j4 A first capacitor C1 is connected in parallel between the anode of the first diode D1 and the end of the second inductor L2 away from the first diode D1; a second capacitor C2 and a third capacitor C3 are connected between the cathode of the first diode D1 and the anode of the second diode D2; a fourth capacitor C4 is connected in parallel between the cathode of the second diode D2 and the end of the fourth inductor L4 away from the second diode D2. The positive output terminal of the boost network is connected to the first power device S j1 The negative output terminal of the boost network is connected to the fourth power device S j4 connect.

[0049] The switching states of the low voltage stress three-level inverter include non-shoot-through state and shoot-through state. Among them, there are three non-shoot-through states, which are marked as [P], [O] and [N]. When the switching state is [P], the output voltage of the bridge arm is +V dc / 2; when the switch state is [O], the bridge arm output voltage is 0; when the switch state is [N], the bridge arm output voltage is -V dc / 2. There are two shoot-through states: the upper shoot-through (UST) state and the lower shoot-through (LST) state, denoted as [U] and [L], respectively. The switching states and enabled power devices of the low-voltage stress three-level inverter are shown in Table 1.

[0050] Pulse width modulation is used to control the on and off of each power switch. It is understood that the power switch is an insulated-gate bipolar transistor (IGBT); the power switch can also be implemented using other types of transistors.

[0051] Table 1 Switching states and enabled power devices of low voltage stress three-level inverter

[0052]

[0053]

[0054] Example 2:

[0055] This embodiment provides an impedance source type three-level inverter modulation method, which uses the impedance source type three-level inverter described in Example 1, including:

[0056] Compare the size relationship of the three-phase original modulation waves and generate a flag bit;

[0057] Split the single modulation wave of each phase in the three-phase original modulation wave into dual modulation waves;

[0058] Obtaining the voltage across the capacitor in the boost network, calculating the difference and processing it through a proportional-integral controller to obtain a given value of the neutral current and update the modulation wave;

[0059] Determine the through state injection phase according to the generated flag bit and the updated modulation wave, and calculate the modulation wave used to inject the through state;

[0060] Modify the modulation wave used to inject the through state;

[0061] The modified modulation wave is compared with the single carrier wave to generate a driving signal; and the generated driving signal is used to control the operation of the impedance source type three-level inverter.

[0062] The method in this embodiment is a single carrier modulation method for an impedance source three-level inverter, such as Figure 2 As shown, the main steps of the method include modulation wave comparison and flag bit generation, dual modulation wave generation, midpoint voltage balance control, through state injection, dual modulation wave correction, single carrier generation and comparison logic; specifically:

[0063] S1. Modulation wave comparison and flag bit generation:

[0064] Using the carrier modulation method, the three-phase original modulation wave is expressed as:

[0065]

[0066] Among them, v a is the A-phase modulation wave, v b is the B-phase modulation wave, v c is the C-phase modulation wave, m is the modulation index; ω is the angular frequency; t is the time.

[0067] Compare the size relationship of the three-phase original modulation waves and generate a flag. Optionally, when the A-phase modulation wave is not less than the B-phase modulation wave, and the B-phase modulation wave is greater than the C-phase modulation wave, the flag is equal to 1; when the B-phase modulation wave is greater than the A-phase modulation wave, and the A-phase modulation wave is not less than the C-phase modulation wave, the flag is equal to 2; when the B-phase modulation wave is not less than the C-phase modulation wave, and the C-phase modulation wave is greater than the A-phase modulation wave, the flag is equal to 3; when the C-phase modulation wave is greater than the B-phase modulation wave, and the B-phase modulation wave is not less than the A-phase modulation wave, the flag is equal to 4; when the C-phase modulation wave is not less than the A-phase modulation wave, and the A-phase modulation wave is greater than the B-phase modulation wave, the flag is equal to 5; when the A-phase modulation wave is greater than the C-phase modulation wave, and the C-phase modulation wave is not less than the B-phase modulation wave, the flag is equal to 6; specifically, when v a ≥v b >v cWhen Flag=1; when v b >v a ≥v c When Flag=2; when v b ≥v c >v a When Flag=3; when v c >v b ≥v a When Flag=4; when v c ≥v a >v b When Flag=5; when v a >v c ≥v b , Flag=6.

[0068] S2. Dual modulation wave generation:

[0069] The single modulation wave (v j , j=a,b,c) is split into dual modulation waves (v jp and v jn ), which can be expressed as:

[0070]

[0071] When Flag = 1, the dual modulation waves of phase A, phase B, and phase C can be expressed as:

[0072]

[0073] When Flag takes other values, the dual modulation waves of phase A, phase B, and phase C can be calculated according to formula (2).

[0074] S3, midpoint voltage balance control:

[0075] The voltage across the second capacitor C2 and the third capacitor C3 in the sampling boost network are respectively recorded as the second capacitor voltage V C2 and the third capacitor voltage V C3 , calculate the second capacitor voltage V C2 and the third capacitor voltage V C3 The difference between the two is sent to the proportional-integral (PI) controller. The output of the PI controller is used as the given value of the neutral current and can be expressed as:

[0076]

[0077] Among them, k p，np and k i，np are the parameters of the PI controller.

[0078] Since the neutral current is only affected by the duty cycle of the [O] state, when Flag = 1, the PI controller causes the neutral current to change to:

[0079] i np =i b ·d comp (5)

[0080] Among them, d comp is the change in duty cycle of the [O] state under the action of the PI controller; i b is the B-phase output current.

[0081] Let the actual value of the neutral current be equal to its given value, and the compensation term d can be obtained. comp for:

[0082] d comp =i np,ref / i b (6)

[0083] When the B-phase modulation wave satisfies v bp >0 and v bn When η<0, the B-phase modulation wave is updated as formula (7), which can effectively control the midpoint voltage balance without changing the volt-second balance principle.

[0084]

[0085] For the updated B-phase dual modulation wave v bp1 and v bn1 , the following restrictions are required: 0 <v bp <1, and -1 <v bn <0, the compensation term d can be obtained comp The value range of is shown in formula (8).

[0086] max{2(v bp -1),2(-v bn -1)} <d c o mp <min{2v bp ,-2v bn}(8)

[0087] The modulation waves of phase A and phase C remain unchanged, see formula (9), to ensure the equivalence of the volt-second balance principle.

[0088]

[0089] When the flag takes other values, a similar method can be used to analyze and obtain the modulation wave v ap1 、v an1 、v bp1 、v bn1 、vcp1 and v cn1 , to achieve midpoint voltage balance control, no further details will be given.

[0090] S4, through state injection:

[0091] According to the flag bit generated in step S1, the through-state injection phase is determined and the modulation wave used to inject the through-state is calculated. When the flag bit is equal to 1, the through-state is injected into phases A and C; when the flag bit is equal to 2, the through-state is injected into phases B and C; when the flag bit is equal to 3, the through-state is injected into phases B and A; when the flag bit is equal to 4, the through-state is injected into phases C and A; when the flag bit is equal to 5, the through-state is injected into phases C and B; when the flag bit is equal to 6, the through-state is injected into phases A and B. The specific method is as follows:

[0092] When the flag is 1, the upper through state is injected into phase A and the lower through state is injected into phase C. The modulation wave for injecting the through state is calculated as follows: ap2 =v ap1 +d st , v an2 =v an1 , v bp2 =v bp1 , v bn2 =v bn1 , v cp2 =v cp1 , v cn2 =v cn1 -d st ;

[0093] When the flag is 2, the upper through state is injected into phase B and the lower through state is injected into phase C. The modulation wave for injecting the through state is calculated as follows: ap2 =v ap1 , v an2 =v an1 , v bp2 =v bp1 +d st , v bn2 =v bn1 , v cp2 =v cp1 , v cn2 =v cn1 -d st ;

[0094] When the flag is 3, the upper through state is injected into phase B and the lower through state is injected into phase A. The modulation wave for injecting the through state is calculated as follows: ap2 =v ap1 , v an2 =v an1 -dst , v bp2 =v bp1 +d st , v bn2 =v bn1 , v cp2 =v cp1 , v cn2 =v cn1 ;

[0095] When the flag is 4, the upper through state is injected into phase C and the lower through state is injected into phase A. The modulation wave for injecting the through state is calculated as follows: ap2 =v ap1 , v an2 =v an1 -d st , v bp2 =v bp1 , v bn2 =v bn1 , v cp2 =v cp1 +d st , v cn2 =v cn1 ;

[0096] When the flag is 5, the upper through state is injected into phase C and the lower through state is injected into phase B. The modulation wave for injecting the through state is calculated as follows: ap2 =v ap1 , v an2 =v an1 , v bp2 =v bp1 , v bn2 =v bn1 -d st , v cp2 =v cp1 +d st , v cn2 =v cn1 ;

[0097] When the flag is 6, the upper through state is injected into phase A and the lower through state is injected into phase B. The modulation wave for injecting the through state is calculated as follows: ap2 =v ap1 +d st , v an2 =v an1 , v bp2 =v bp1 , v bn2 =v bn1 -d st , v cp2 =v cp1 , v cn2 =vcn1 .

[0098] S5, dual modulation wave correction:

[0099] In order to facilitate the digital implementation of the digital controller of the method of the present invention, the modulated wave obtained in step S4 is further corrected. The correction method of the j-phase (j=a, b, c) modulated wave is shown in formula (10).

[0100]

[0101] Among them, m jp1 、m jn1 、m jp2 、m jp2 is the modulated wave after phase j (j=a, b, c) is updated.

[0102] S6, dual modulation wave and single carrier comparison logic:

[0103] The modulated wave m obtained in step S5 jp1 、m jn1 、m jp2 and m jp2 (j=a, b, c) is compared with a single carrier to generate a PWM drive signal.

[0104] The PWM drive signal generation principle block diagram of the method of this embodiment is as follows Figure 3 The modified modulation wave based on the updated modulation wave is compared with the single carrier to obtain the first component of the driving signal; the modified modulation wave based on the injected through state is compared with the single carrier to obtain the second component of the driving signal; the first component and the second component are logically ORed to obtain the final driving signal of the power device; specifically: m jp1 、m jn1 、m jp2 and m jp2 is the modulation wave of phase j (j=a, b, c), and Carrier is the carrier. jp1 and m jn1 Compare with the carrier wave to obtain the first component of the j-phase (j=a, b, c) power device drive signal; jp2 and m jn2 Comparing with the carrier, the second component of the j-phase (j=a, b, c) power device drive signal is obtained. The first component and the second component of each power device drive signal are logically ORed to obtain the final drive signal of each power device, which controls the operation of the impedance source three-level inverter. The detailed operation process is as follows: Figure 3 shown.

[0105] Figures 4(a) and 4(b) show the steady-state operating waveforms of the impedance source three-level inverter of this embodiment with load 1 connected to the output side and in non-boost operation mode. At this time, the DC input power supply voltage is 400V, the system modulation index and the through-duty cycle are set to 0.8 and 0 respectively, and the output side is connected to load 1, with a load resistance of 12Ω and an inductance of 6mH respectively. C1 、V C2 、V C3 and V C4 Represent the voltages across capacitors C1, C2, C3, and C4, respectively. V dc Represents the output voltage of the boost network, v ab Indicates the line voltage, i a 、i b and i c is the three-phase output current, V Sa1 、V Sa2 、V Sa3 and V Sa4 Represents the power device S a1 、S a2 、S a3 and S a4 Since the direct duty cycle is set to 0, the output voltage of the boost network is equal to the DC input power supply voltage (i.e., 400V). The line voltage is a five-level waveform, and the three-phase output current is a symmetrical sinusoidal waveform, thereby verifying the effectiveness of the impedance source three-level inverter and modulation method of the present invention. The voltages across capacitors C2 and C3 are equal, which illustrates the effectiveness of the midpoint balance control strategy. Power device S a1 The voltage stress is 400V (i.e. the output voltage amplitude of the boost network), and the power device S a2 、S a3 and S a4 The voltage stress is 200V (i.e. 1 / 2 of the output voltage amplitude of the boost network).

[0106] Figures 5(a) and 5(b) show the steady-state operating waveforms of the impedance source three-level inverter of this embodiment, with load 1 connected to the output side and in boost mode. At this point, the DC input power supply voltage is 300V, the system modulation index and the through duty cycle are set to 0.8 and 0.125, respectively. The output side is connected to load 1, with a load resistance of 12Ω and an inductance of 6mH, respectively. C1 、V C2 、V C3 and V C4 Represent the voltages across capacitors C1, C2, C3, and C4, respectively. V dc Represents the output voltage of the boost network, v ab Indicates the line voltage, i a 、i b and i cis the three-phase output current, V Sa1 、V Sa2 、V Sa3 and V Sa4 Represents the power device S a1 、S a2 、S a3 and S a4 The voltage stress of the boost network is shown. It can be seen that the output voltage of the boost network varies between 200V and 400V, with an amplitude of 400V, which is higher than the DC input power supply voltage, verifying the effectiveness of the boost function achieved by the present invention. In boost mode, the voltages across capacitors C2 and C3 remain equal, verifying the effectiveness of the midpoint balance control strategy.

[0107] Figures 6(a) and 6(b) show the steady-state operating waveforms of the impedance source three-level inverter of this embodiment with load 2 connected to the output side and in non-boost operation mode. At this time, the DC input power supply voltage is 400V, the system modulation index and the through-duty cycle are set to 0.8 and 0 respectively, and the output side is connected to load 2, with a load resistance of 12Ω and an inductance of 36mH respectively. C1 、V C2 、V C3 and V C4 Represent the voltages across capacitors C1, C2, C3, and C4, respectively. V dc Represents the output voltage of the boost network, v ab Indicates the line voltage, i a 、i b and i c is the three-phase output current, V Sa1 、V Sa2 、V Sa3 and V Sa4 Represents the power device S a1 、S a2 、S a3 and S a4 At this time, due to the large load inductance, the system power factor is lower than when load 1 is used. At this time, the output voltage amplitude of the boost network is 400V, which is equal to the DC input power supply voltage. Under low power factor conditions, the voltages across capacitors C2 and C3 remain equal, further verifying the effectiveness of the midpoint balance control method of the present invention. Power device S a1 The voltage stress of the boost network is the output voltage amplitude of the power device S a2 、S a3 and S a4 The voltage stress is 1 / 2 of the output voltage amplitude of the boost network.

[0108] Figures 7(a) and 7(b) show the steady-state operating waveforms of the impedance source three-level inverter of this embodiment with load 2 connected to the output side and in boost operation mode. At this time, the DC input power supply voltage is 300V, the system modulation index and the through-duty cycle are set to 0.8 and 0.125 respectively, and the output side is connected to load 2, with a load resistance of 12Ω and an inductance of 36mH respectively. C1 、V C2 、V C3 and V C4 Represent the voltages across capacitors C1, C2, C3, and C4, respectively. V dc Represents the output voltage of the boost network, v ab Indicates the line voltage, i a 、i b and i c is the three-phase output current, V Sa1 、V Sa2 、V Sa3 and V Sa4 Represents the power device S a1 、S a2 、S a3 and S a4 The voltage stress of the boost network is shown in Figure 2. It can be seen that the output voltage of the boost network is 400V, which is higher than the DC input power supply voltage, and the system can achieve normal boost function. The voltage across capacitors C2 and C3 remains equal, verifying the effectiveness of the midpoint balance control strategy.

[0109] When the output side of the impedance source type three-level inverter of the present invention is connected to a load 1 and the modulation index is increased from 0.65 to 0.8, the operating waveforms of the non-boost operation mode and the boost operation mode are respectively as follows: Figure 8 and Figure 9 As shown in the figure, the three-phase output current amplitude increases with increasing modulation index, and the waveform quality improves. During the dynamic process of step changes in modulation index, the three-phase current waveform amplitude increases steadily, thus verifying that the method of the present invention can ensure stable and reliable system operation under different modulation indexes.

[0110] The above description is merely a preferred embodiment of this embodiment and is not intended to limit this embodiment. Those skilled in the art will readily appreciate that this embodiment may be modified and varied in various ways. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this embodiment shall be within the scope of protection of this embodiment.

Claims

1. An impedance source three-level inverter, characterized in that: It includes a DC power supply, a boost network connected to the DC power supply, a low voltage stress type three-level inverter connected to the boost network, and a load connected to the low voltage stress type three-level inverter; The low-voltage stress type three-level inverter includes three-phase bridge arms, each phase bridge arm includes a first power device whose collector is connected to one end of the boost network, a second power device whose collector is connected to the emitter of the first power device, a third power device whose emitter is connected to the emitter of the second power device, and a fourth power device whose collector is connected to the emitter of the second power device, the emitter of the fourth power device is connected to the other end of the boost network, and the collector of the third power device is connected to the neutral point of the boost network; the low-voltage stress type three-level inverter is used to convert the direct current output by the boost network into alternating current, the voltage stress of the first power device is equal to the output voltage amplitude of the boost network, and the voltage stress of the second power device, the third power device and the fourth power device is equal to half the output voltage amplitude of the boost network; obtaining voltages across the second capacitor and the third capacitor, calculating a difference between the voltages across the second capacitor and the third capacitor, and inputting the difference into a proportional-integral controller to obtain a given value of the neutral current; When the flag bit is equal to 1, the A phase is injected into the upper direct-through state and the C phase is injected into the lower direct-through state; When the flag bit is equal to 2, the B phase is injected into the upper direct-through state and the C phase is injected into the lower direct-through state; When the flag bit is equal to 3, the B phase is injected into the upper direct-through state and the A phase is injected into the lower direct-through state; When the flag bit is equal to 4, the C phase is injected into the upper direct-through state and the A phase is injected into the lower direct-through state; When the flag bit is equal to 5, the C phase is injected into the upper direct-through state and the B phase is injected into the lower direct-through state; When the flag bit is equal to 6, the A phase is injected into the upper direct-through state and the B phase is injected into the lower direct-through state; The boost network includes a first inductor connected to one end of the DC power supply, a first diode connected to the first inductor, a second inductor connected to the first diode, a third inductor connected to the other end of the DC power supply, a second diode connected to the third inductor, and a fourth inductor connected to the second diode; the second inductor is connected to the first power device, and the fourth inductor is connected to the fourth power device; The positive output terminal of the boost network is connected to the first power device, and the negative output terminal of the boost network is connected to the fourth power device; The single modulation wave v of each phase in the three-phase original modulation wave j , j=a, b, c is split into dual modulation wave v jp and v jn , expressed as: When the flag bit is equal to 1, the dual modulation waves of phase A, phase B, and phase C are expressed as:

2. The impedance source three-level inverter according to claim 1, characterized in that: A first capacitor is connected in parallel between the anode of the first diode and the end of the second inductor away from the first diode; a second capacitor and a third capacitor are connected between the cathode of the first diode and the anode of the second diode; and a fourth capacitor is connected in parallel between the cathode of the second diode and the end of the fourth inductor away from the second diode.

3. A modulation method for an impedance source three-level inverter, characterized in that: The impedance source three-level inverter according to any one of claims 1 to 2 is used, comprising: Compare the size relationship of the three-phase original modulation waves and generate a flag bit; Split the single modulation wave of each phase in the three-phase original modulation wave into dual modulation waves; Obtaining the voltage across the capacitor in the boost network, calculating the difference and processing it through a proportional-integral controller to obtain a given value of the neutral current and update the modulation wave; Determine the through state injection phase according to the generated flag bit and the updated modulation wave, and calculate the modulation wave used to inject the through state; Modify the modulation wave used to inject the through state; The modified modulation wave is compared with the single carrier wave to generate a driving signal; and the generated driving signal is used to control the operation of the impedance source type three-level inverter.

4. The impedance source three-level inverter modulation method according to claim 3, wherein: When the A-phase modulation wave is not less than the B-phase modulation wave, and the B-phase modulation wave is greater than the C-phase modulation wave, the flag is equal to 1; when the B-phase modulation wave is greater than the A-phase modulation wave, and the A-phase modulation wave is not less than the C-phase modulation wave, the flag is equal to 2; when the B-phase modulation wave is not less than the C-phase modulation wave, and the C-phase modulation wave is greater than the A-phase modulation wave, the flag is equal to 3; When the C-phase modulation wave is greater than the B-phase modulation wave, and the B-phase modulation wave is not less than the A-phase modulation wave, the flag bit is equal to 4; When the C-phase modulation wave is not less than the A-phase modulation wave, and the A-phase modulation wave is greater than the B-phase modulation wave, the flag is equal to 5; when the A-phase modulation wave is greater than the C-phase modulation wave, and the C-phase modulation wave is not less than the B-phase modulation wave, the flag is equal to 6.

5. The impedance source three-level inverter modulation method according to claim 3, wherein: When the flag bit is equal to 1, and the two modulation waves in the modulation wave of phase B are respectively greater than zero and less than zero, the modulation wave of phase B is updated.

6. The impedance source three-level inverter modulation method according to claim 3, wherein: The modulated wave corrected based on the updated modulated wave is compared with the single carrier to obtain the first component of the driving signal; the modulated wave corrected based on the injected through state is compared with the single carrier to obtain the second component of the driving signal; the first component and the second component are logically ORed to obtain the final driving signal of the power device.

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