System starting method and device, storage medium and electronic device

Abstract

Embodiments of the present application provide a system starting method and device, a storage medium and an electronic device, wherein the system starting method comprises: in the case of detecting that a first system starts, determining whether the first system is a cold start; in the case of determining that the first system is a cold start, detecting a central processing unit by a memory self-checking algorithm to determine whether there is a bad core in the central processing unit, wherein the bad core is used to indicate a damaged slave processing unit in the central processing unit, the first system starts at the same time as a master processing unit in the central processing unit, and the first system is used to control the master processing unit; in the case of there being a bad core in the central processing unit, isolating the bad core in the central processing unit, and starting a second system and other slave processing units in the central processing unit, wherein the second system is used to control the master processing unit and the other slave processing units, and the other slave processing units are slave processing units in the central processing unit except the bad core.

Description

Technical Field

[0001] This application relates to the field of computers, and more specifically, to a system startup method and apparatus, a storage medium, and an electronic device. Background Technology

[0002] With the continuous development of the digital economy and science and technology, the market's use and reliance on servers is gradually increasing. Many manufacturers and companies use servers, coming from various fields such as finance, banking, telecommunications, aerospace, scientific research, and manufacturing. Many enterprises have high requirements for the continuous and reliable operation of servers, such as those in banking, internet, telecommunications, and healthcare. If a server experiences prolonged downtime or malfunctions, in addition to disrupting customer business, it may also lead to the backlog and loss of customer business data, triggering security issues and causing irreparable losses to the customer company.

[0003] Servers are multi-CPU, multi-core systems, typically with a single CPU containing dozens of CPU cores (processing units). After prolonged operation, one or more CPU cores may fail. The BIOS (Basic Input Output System) is a single-core, single-threaded system. When the BIOS boots, only one CPU core is running. Therefore, a bad CPU core usually has little impact on the BIOS. The CPU core running during BIOS boot is called the master core, and the others are called slave cores. After BIOS boot, it transfers control of the CPU to the OS (Operating System). The OS is a multi-core, multi-threaded system. During OS boot, the master core starts the other CPU slave cores in the system. If a bad CPU core exists, it may cause a bus error or other anomaly when it is restarted by the master core, leading to system crashes.

[0004] Regarding the technical problem in related technologies, where the OS (secondary operating system) boots the CPU from the core during startup, if there is a bad CPU core in the system, the booting of the bad core will cause bus errors or other abnormalities, leading to system crashes, no effective solution has yet been proposed. Summary of the Invention

[0005] This application provides a system startup method and apparatus, storage medium and electronic device to at least solve the problem in the related art where the OS (second system) starts the CPU from the core during startup. If there is a bad CPU core in the system, starting the bad core will cause bus errors or other abnormalities, resulting in the system hanging.

[0006] According to one embodiment of this application, a system startup method is provided, comprising: upon detecting the startup of a first system, determining whether the first system is a cold start, wherein the cold start indicates that the first system is starting for the first time after power-on; if the first system is determined to be a cold start, detecting the central processing unit (CPU) using a memory self-test algorithm to determine whether there is a bad core in the CPU, wherein the bad core indicates a damaged slave processing unit in the CPU, the first system and the main processing unit in the CPU start simultaneously, and the first system controls the main processing unit; if a bad core exists in the CPU, isolating the bad core in the CPU, and starting a second system and other slave processing units in the CPU, wherein the second system controls the main processing unit and the other slave processing units, the other slave processing units being slave processing units other than the bad core in the CPU.

[0007] In an exemplary embodiment, determining whether the first system is a cold start includes: reading a status value stored in the register of the first system; if the status value is determined to be a first value, determining that the first system is a cold start and updating the status value to a second value, wherein the first value is a default value of the status value; if the status value is determined to be not the first value, determining that the first system is not a cold start.

[0008] In an exemplary embodiment, the step of detecting the central processing unit (CPU) using a memory self-test algorithm to determine whether a bad core exists in the CPU includes: determining the detection object corresponding to the memory self-test algorithm, wherein the detection object includes the memory of a plurality of slave processing units; configuring parameter information of the memory self-test algorithm according to the detection object, wherein the parameter information includes: test mode and test time; generating a detection vector according to the specification parameters and address information of the detection object; executing the detection vector to detect the memory of the plurality of slave processing units; comparing and analyzing the detection results with preset detection results corresponding to the detection vector to obtain detection data; and parsing the detection data to determine whether a bad core exists in the CPU and to determine the numbering information of the bad core in the plurality of slave processing units.

[0009] In an exemplary embodiment, isolating the bad core in the central processing unit and starting the second system and other slave processing units in the central processing unit includes: storing the numbering information of the other slave processing units in startup configuration information, and sending the startup configuration information to the second system to instruct the second system to start according to the startup configuration information, wherein the startup configuration information is used by the second system to determine the slave processing unit to be started.

[0010] In an exemplary embodiment, before isolating the bad cores in the central processing unit and starting the second system and other slave processing units in the central processing unit, the method further includes: determining whether the number of bad cores exceeds a preset threshold; if the number of bad cores exceeds the preset threshold, prohibiting the second system and the other slave processing units from starting, and stopping the first system and the main processing unit from running; if the number of bad cores does not exceed the preset threshold, isolating the bad cores and starting the second system and the other slave processing units.

[0011] In an exemplary embodiment, after prohibiting the second system and the other slave processing units from starting up, and stopping the first system and the main processing unit from running, the method further includes: sending alarm information to a baseboard management controller to instruct the baseboard management controller to store the alarm information in a controller log, wherein the alarm information includes: the number of bad cores and the bad core number information; the controller log is used by a first object to view the alarm information.

[0012] In an exemplary embodiment, after isolating the bad core and starting the second system and the other slave processing units, the method further includes: displaying the bad core's identification number on a first page, and sending the identification number to the second system through the first system's management system to indicate to the first object that a bad core exists in the central processing unit.

[0013] According to another embodiment of this application, a system startup apparatus is provided, comprising: a determining module, configured to determine whether the first system is a cold start when a first system startup is detected, wherein the cold start indicates that the first system is starting for the first time after power-on; a detecting module, configured to detect the central processing unit (CPU) using a memory self-test algorithm when the first system is determined to be a cold start, to determine whether there is a bad core in the CPU, wherein the bad core indicates a damaged slave processing unit in the CPU, the first system and the main processing unit in the CPU start simultaneously, and the first system controls the main processing unit; and a startup module, configured to isolate the bad core in the CPU and start a second system and other slave processing units in the CPU when there is a bad core, wherein the second system controls the main processing unit and the other slave processing units, and the other slave processing units are slave processing units in the CPU other than the bad core.

[0014] According to yet another embodiment of this application, a computer-readable storage medium is also provided, wherein a computer program is stored therein, and the computer program is configured to perform the steps in any of the above method embodiments when it is run.

[0015] According to yet another embodiment of this application, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0016] This application addresses the issue that, upon detecting the startup of the first system (BIOS), a cold boot is first determined. If it is not a cold boot, bad core detection is unnecessary. If it is a cold boot, a memory self-test algorithm is used to check the CPU to determine if a bad core exists. If a bad core is identified, it is isolated, thus ensuring the normal operation of the second system. This solution resolves the problem in related technologies where the OS (second system) boots from the CPU core during startup. If a bad CPU core exists, booting from the bad core can cause bus errors or other anomalies, leading to system crashes. This avoids CPU crashes caused by bad cores, allowing customer machines to continue operating normally, improving the security, availability, and maintainability of the company's products, and significantly enhancing product quality. Attached Figure Description

[0017] Figure 1 This is a hardware structure block diagram of an AMD server according to an embodiment of the present application of a system startup method;

[0018] Figure 2 This is a flowchart of a system startup method according to an embodiment of this application;

[0019] Figure 3 This is a flowchart illustrating an optional system startup method according to an embodiment of this application;

[0020] Figure 4 This is a structural block diagram (a) of a system startup device according to an embodiment of this application;

[0021] Figure 5 This is a structural block diagram (II) of a system startup device according to an embodiment of this application. Detailed Implementation

[0022] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.

[0023] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0024] The methods and embodiments provided in this application can be executed on AMD servers or similar computing devices. Taking running on an AMD server as an example, Figure 1 This is a hardware structure block diagram of an AMD server according to an embodiment of the system startup method of this application. Figure 1 As shown, AMD servers can include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data are also shown. The AMD server may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the AMD server described above. For example, AMD servers may also include... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0025] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the system startup method in this embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thus implementing the above-described method. The memory 104 may include high-speed random access memory and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to AMD servers via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0026] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by the communication provider of the AMD server. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0027] This embodiment provides a system startup method. Figure 2 This is a flowchart of a system startup method according to an embodiment of this application, such as... Figure 2 As shown, the process includes the following steps:

[0028] Step S202: If the first system is detected to be starting, determine whether the first system is a cold start, wherein the cold start is used to indicate that the first system is starting for the first time after power-on;

[0029] It should be noted that a cold boot refers to the first boot of the BIOS (equivalent to the first system mentioned above) after power-on. After the BIOS has finished booting, performing a restart operation without powering on, which causes the BIOS to restart, does not constitute a cold boot.

[0030] Step S204: If it is determined that the first system is a cold start, the central processing unit is detected by a memory self-test algorithm to determine whether there is a bad core in the central processing unit. The bad core is used to indicate a damaged slave processing unit in the central processing unit. The first system and the main processing unit in the central processing unit start up at the same time, and the first system is used to control the main processing unit.

[0031] Step S206: If a bad core exists in the central processing unit, the bad core in the central processing unit is isolated, and a second system and other slave processing units in the central processing unit are started. The second system is used to control the main processing unit and the other slave processing units, which are slave processing units other than the bad core in the central processing unit.

[0032] Through the above steps, when the first system (BIOS) is detected to be booting, it is first determined whether it is a cold boot. If it is not a cold boot, bad core detection is not required. If it is a cold boot, the CPU is first detected by a memory self-test algorithm to determine whether a bad core exists. If a bad core is found in the CPU, it is isolated to ensure the normal operation of the second system. By adopting the above solution, the problem in related technologies where the OS (second system) boots from the CPU core during startup, and if a bad CPU core exists in the system, booting from the bad core will cause bus errors or other abnormalities, leading to system hang. This avoids the accident of CPU abnormal crash caused by a bad CPU core, allowing the customer's machine to continue to operate normally, improving the security, availability, and maintainability of the company's products, and greatly improving the quality of the products.

[0033] The entity performing the above steps can be an AMD server, but is not limited to this.

[0034] The execution order of steps S202 and S204 can be interchanged; that is, step S204 can be executed first, and then step S202 can be executed.

[0035] The following explains the technical terms that appear in this application:

[0036] SMBIOS: System Management BIOS, the BIOS management system;

[0037] MBIST: Memory Build Self Test.

[0038] BMC: Baseboard Management Controller;

[0039] RAM: Random Access Memory;

[0040] IPMI: Intelligent Platform Management Interface;

[0041] ACPI: Advanced Configuration and Power Management Interface.

[0042] In an exemplary embodiment, performing step S202 above: determining whether the first system is a cold start includes the following steps: reading the status value stored in the register of the first system; if the status value is determined to be a first value, determining that the first system is a cold start, and updating the status value to a second value, wherein the first value is the default value of the status value; if the status value is determined to be not the first value, determining that the first system is not a cold start.

[0043] The following method can be used to determine whether the first system is a cold start: First, read the status value stored in the register of the first system. The status value is the first value by default. That is, when the first system is powered off and then powered on again, the status value will be restored to the first value by default. If the current status value is the first value, it is determined that the first system is a cold start. Then, update the status value in the register to the second value. If the current status value is not the first value, it is determined that the first system is not a cold start.

[0044] It should be noted that if it is determined that the first system is not a cold boot, there is no need to perform bad core detection on the central processing unit to avoid wasting processing resources.

[0045] Through the above embodiments, when the first system starts, it is first determined whether it is a cold start, and bad core detection is only performed during cold starts, thereby reducing the frequency of bad core detection and thus reducing the waste of processing resources.

[0046] Optionally, step S204 above can be implemented through the following embodiments: the technical solution described in the step of detecting the central processing unit (CPU) using a memory self-test algorithm to determine whether a bad core exists in the CPU includes: determining the detection object corresponding to the memory self-test algorithm, wherein the detection object includes the memory of multiple slave processing units; configuring the parameter information of the memory self-test algorithm according to the detection object, wherein the parameter information includes: test mode and test time; generating a detection vector according to the specification parameters and address information of the detection object; executing the detection vector to detect the memory of the multiple slave processing units; comparing and analyzing the detection result with the preset detection result corresponding to the detection vector to obtain detection data; and parsing the detection data to determine whether a bad core exists in the CPU and to determine the number information of the bad core in the multiple slave processing units.

[0047] First, the target of the memory self-test algorithm is determined to be the memory of multiple slave processing units, i.e., the target to be tested is configured for the memory self-test algorithm. Then, the parameter information of the memory self-test algorithm is configured according to the testing requirements of the target, including at least the test mode and test time. Then, a test vector is generated according to the specification parameters and address information of the target, and the test vector is executed to completely test the memory of the multiple slave processing units. The test results are compared and analyzed with the preset test results corresponding to the test vector to obtain test data. The test data is parsed to determine whether there are bad cores in the central processing unit. If bad cores are found, their ID information can also be obtained.

[0048] Through the above embodiments, the memory self-test algorithm can quickly and accurately find bad cores in the central processing unit and deal with them in a timely manner to avoid abnormal OS crashes due to the presence of bad cores during operation, thus preventing greater losses to customers.

[0049] In an exemplary embodiment, step S206 above: isolating the bad core in the central processing unit and starting the second system and other slave processing units in the central processing unit can be implemented by: storing the numbering information of the other slave processing units in startup configuration information and sending the startup configuration information to the second system to instruct the second system to start according to the startup configuration information, wherein the startup configuration information is used by the second system to determine the slave processing unit to be started.

[0050] BIOS isolation of bad cores means that the BIOS does not record bad cores in the ACPI table (equivalent to the boot configuration information mentioned above). The ACPI table is a way for the BIOS to pass system information to the OS, and it contains all available CPU cores in the system. When the OS boots, it reads the ACPI table to get the number of CPU cores. Since bad cores are not recorded in the ACPI table, the OS is unaware of their existence and will not boot from them, thus avoiding abnormal CPU crashes caused by bad cores.

[0051] Through the above embodiments, when a bad core is detected in the central processing unit, the bad core is isolated, thereby preventing the OS from starting the bad core and causing the CPU to crash abnormally.

[0052] Optionally, before performing step S206 above: isolating the bad cores in the central processing unit and starting the second system and other slave processing units in the central processing unit, the method further includes: determining whether the number of bad cores exceeds a preset threshold; if the number of bad cores exceeds the preset threshold, prohibiting the second system and the other slave processing units from starting, and stopping the first system and the main processing unit from running; if the number of bad cores does not exceed the preset threshold, isolating the bad cores, and starting the second system and the other slave processing units.

[0053] When a bad core is detected in the central processing unit (CPU), the system first checks if the number of bad cores exceeds a preset threshold. If it does, even if the bad cores are isolated, the server's performance will be severely affected, and it may even disrupt the server's normal operation. Therefore, if the number of bad cores exceeds the preset threshold, the second system and other slave processing units are prevented from booting, and the BIOS is stopped. If the number of bad cores does not exceed the threshold, the bad cores can be isolated, thus ensuring the normal boot and operation of the OS.

[0054] Through the above embodiments, different countermeasures are taken according to the number of bad cores, thereby minimizing the impact of bad cores on system operation.

[0055] Based on the above steps, after prohibiting the second system and the other slave processing units from starting, and stopping the first system and the main processing unit from running, the method further includes: sending alarm information to the baseboard management controller to instruct the baseboard management controller to store the alarm information in the controller log, wherein the alarm information includes: the number of bad cores and the bad core number information; the controller log is used by the first object to view the alarm information.

[0056] If the number of bad CPU cores exceeds the allowable threshold, even isolating the bad cores will severely impact server performance, thus preventing further machine operation and halting BIOS operation. The BIOS will also issue a warning, displaying the number of bad CPU cores, the allowable bad core threshold, and the bad core ID on the monitor. Simultaneously, the BIOS can send alarm information to the BMC via IPMI commands. The BMC records the CPU bad core alarm information in its log (equivalent to the aforementioned baseboard management controller). Users can then view the CPU bad core information on the BMC web interface or by using commands to access the BMC log. IPMI is a protocol interface used for communication and data transfer between the BIOS and the BMC.

[0057] Based on the above steps, after isolating the bad core and starting the second system and the other processing units, the method further includes: displaying the bad core's identification number on a first page, and sending the identification number to the second system through the first system's management system to indicate to the first object that a bad core exists in the central processing unit.

[0058] After isolating the bad core and continuing to boot the second system and other processing units, the BIOS displays the bad core number of the CPU on the BIOS SETUP interface. At the same time, the bad core number of the CPU is transmitted to the OS through SMBIOS. Technicians or customers (equivalent to the first object mentioned above) can check whether there is a bad core in the CPU by viewing the BIOS SETUP interface or by using the dmidecode command to view SMBIO.

[0059] Through the above embodiments, when a customer's machine CPU has a bad core, it is only necessary to check the BIOS SETUP or the OS SMBIOS to confirm whether there is a bad CPU core. This avoids the need for multiple communications with the customer's personnel to confirm the problem, greatly improving the customer's experience with the company's products. It also avoids the complicated process of technicians going to the site for location and analysis, greatly saving the company's labor costs.

[0060] In one exemplary embodiment, this application provides an optional system startup method, including the following steps:

[0061] Step 1: The BIOS boots and determines if it's a cold boot. A cold boot refers to the first time the BIOS starts up after power-on. If the BIOS completes its boot process and then a reboot is performed without interrupting power, causing the BIOS to restart, this is not considered a cold boot.

[0062] Step 2: If the BIOS is cold-booted, it executes the CPU MBIST test program (equivalent to the memory self-test algorithm described above) and stores the test data in FLASH. If the BIOS is not cold-booted, it does not execute the CPU MBIST test program. MBIST is used to test the CPU core's RAM to determine if the CPU has a faulty core.

[0063] It should be noted that MBIST stands for Memory Built-in Self Test, a technology used to build test memories into integrated circuits to detect defects in the memory. The MBIST hardware module is integrated inside the CPU and can be enabled in the BIOS to specify the testing of specific RAM to determine if the RAM is damaged.

[0064] Step 3: The BIOS reads the CPU MBIST detection data from the FLASH and analyzes whether the CPU has bad cores;

[0065] Step 4: If the BIOS determines that there are no bad cores in the CPU, the BIOS will continue running until completion.

[0066] Step 5: If the BIOS detects bad cores in the CPU, it determines whether the number of bad cores exceeds the allowable threshold (equivalent to the preset threshold in the above embodiment). If it exceeds the allowable threshold, even isolating the bad cores will severely impact server performance and may even affect normal server operation. The BIOS issues an alert, displaying the number of bad cores, the allowable bad core threshold, and the bad core ID on the monitor. Simultaneously, the BIOS sends an alert to the BMC via IPMI commands. The BMC records the CPU bad core alert in its log. This information can then be viewed on the BMC web interface or by using commands to access the BMC log. IPMI is a protocol interface used for communication and data transfer between the BIOS and BMC. If the number of bad cores exceeds the threshold, the BIOS will not allow the machine to continue running and will subsequently stop operating.

[0067] Step 6: If the BIOS detects bad cores in the CPU and the number of bad cores does not exceed the allowable threshold, the BIOS isolates the bad cores. BIOS isolation of bad cores means that the BIOS does not record the bad cores in the ACPI table (equivalent to the boot configuration information mentioned above). The ACPI table is a way for the BIOS to pass system information to the OS, and it contains all available CPU cores in the system. When the OS boots, it reads the ACPI table to obtain the number of CPU cores. Since the bad cores are not recorded in the ACPI table, the OS is unaware of their existence and will not boot from them, thus preventing abnormal CPU crashes caused by bad cores. The BIOS then displays the bad core number on the BIOS SETUP interface (equivalent to the first page mentioned above) and simultaneously transmits the bad core number to the OS via SMBIOS. Technicians or customers can check whether the CPU has bad cores by viewing the BIOS SETUP interface or using the SMBIOS's dmidecode command.

[0068] Through the above embodiments, during a cold boot, the BIOS executes the CPU MBIST detection program. If bad cores are detected in the CPU, and the number of bad cores does not exceed the allowable threshold, the BIOS does not record the bad cores in the ACPI table. When the OS boots, it reads the number of CPU cores from the ACPI table. Since the bad cores are not recorded in the ACPI table, the OS is unaware of them, thus avoiding CPU crashes caused by booting with bad cores. Furthermore, the BIOS records the bad core number in the BIOS SETUP and transmits it to the OS via SMBIOS. The presence of bad cores can be checked by viewing the BIOS SETUP interface or using the dmidecode command in the SMBIO. When a customer's CPU experiences bad cores, only the BIOS SETUP or the OS's SMBIOS needs to be checked to confirm their existence. This avoids the need for multiple communications with customer personnel to confirm the problem, greatly improving the customer's experience with the company's products. It also avoids the tedious process of technicians going to the site for location and analysis, significantly saving the company's labor costs.

[0069] Optionally, this application also provides an optional system startup method, such as... Figure 3 As shown, it includes the following steps:

[0070] Step S301: BIOS startup;

[0071] Step S302: Determine if the BIOS is cold booted. If yes, proceed to step S303; otherwise, proceed to step S304.

[0072] Step S303: The BIOS executes the CPU MBIST test program and stores the test data in FLASH.

[0073] Step S304: The BIOS reads the CPU MBIST test data from the FLASH.

[0074] Step S305: The BIOS analyzes whether the CPU has a bad core. If so, proceed to step S306; otherwise, proceed to step S310.

[0075] Step S306: Determine whether the number of bad CPU cores exceeds the threshold. If not, proceed to step S307; otherwise, proceed to step S311.

[0076] Step S307: The BIOS performs CPU bad core isolation;

[0077] Step S308: The BIOS displays the bad core number on the SETUP interface;

[0078] Step S309: The BIOS transmits the bad core number to the OS via SMBIOS;

[0079] Step S310: BIOS continues booting until completion;

[0080] Step S311: The BIOS displays alarm information on the monitor and KVM, and sends alarm information to the BMC via IPMI;

[0081] Step S312: BIOS stops booting.

[0082] With the above solution, when the BIOS detects that a customer's machine has a bad CPU core and the number of bad cores does not exceed the allowable threshold, the BIOS will isolate the bad CPU cores, avoiding the accident of abnormal CPU crash caused by bad CPU cores. This allows the customer's machine to continue to operate normally, avoids interruption of customer business, minimizes customer business losses, improves the security, availability and maintainability of the company's products, and greatly improves the quality of the company's products.

[0083] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0084] This embodiment also provides a system startup device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0085] Figure 4 This is a structural block diagram of a system startup device according to an embodiment of this application, such as... Figure 4 As shown, the device includes

[0086] The determination module 42 is used to determine whether the first system is a cold start when the first system is detected to be starting, wherein the cold start is used to indicate that the first system is starting for the first time after power-on;

[0087] It should be noted that a cold boot refers to the first boot of the BIOS (equivalent to the first system mentioned above) after power-on. After the BIOS has finished booting, performing a restart operation without powering on, which causes the BIOS to restart, does not constitute a cold boot.

[0088] The detection module 44 is used to detect the central processing unit (CPU) through a memory self-test algorithm when it is determined that the first system is a cold start, so as to determine whether there is a bad core in the CPU. The bad core is used to indicate a damaged slave processing unit in the CPU. The first system and the main processing unit in the CPU start simultaneously, and the first system is used to control the main processing unit.

[0089] The startup module 46 is used to isolate the bad core in the central processing unit and start the second system and other slave processing units in the central processing unit when a bad core exists in the central processing unit. The second system is used to control the main processing unit and the other slave processing units, which are slave processing units other than the bad core in the central processing unit.

[0090] The aforementioned device, upon detecting the startup of the first system (BIOS), first determines whether it is a cold boot. If it is not a cold boot, bad core detection is unnecessary. If it is a cold boot, the CPU is first tested using a memory self-test algorithm to determine if a bad core exists. If a bad core is found in the CPU, it is isolated, thus ensuring the normal operation of the second system. This solution addresses the problem in related technologies where the OS (second system) boots from the CPU core during startup. If a bad CPU core exists, booting from the bad core can cause bus errors or other anomalies, leading to system crashes. This avoids CPU crashes caused by bad cores, allowing customer machines to continue operating normally, improving the security, availability, and maintainability of the company's products, and significantly enhancing product quality.

[0091] Optionally, the determining module 42 is further configured to read the status value stored in the register of the first system; if the status value is determined to be a first value, determine that the first system is a cold start and update the status value to a second value, wherein the first value is the default value of the status value; if the status value is determined to be not the first value, determine that the first system is not a cold start.

[0092] The following method can be used to determine whether the first system is a cold start: First, read the status value stored in the register of the first system. The status value is the first value by default. That is, when the first system is powered off and then powered on again, the status value will be restored to the first value by default. If the current status value is the first value, it is determined that the first system is a cold start. Then, update the status value in the register to the second value. If the current status value is not the first value, it is determined that the first system is not a cold start.

[0093] It should be noted that if it is determined that the first system is not a cold boot, there is no need to perform bad core detection on the central processing unit to avoid wasting processing resources.

[0094] Through the above embodiments, when the first system starts, it is first determined whether it is a cold start, and bad core detection is only performed during cold starts, thereby reducing the frequency of bad core detection and thus reducing the waste of processing resources.

[0095] Optionally, the detection module 44 is further configured to: determine the detection object corresponding to the memory self-test algorithm, wherein the detection object includes the memory of multiple slave processing units; configure the parameter information of the memory self-test algorithm according to the detection object, wherein the parameter information includes: test mode, test time; generate a detection vector according to the specification parameters and address information of the detection object; execute the detection vector to detect the memory of the multiple slave processing units; compare and analyze the detection result with the preset detection result corresponding to the detection vector to obtain detection data; and parse the detection data to determine whether there is a bad core in the central processing unit and to determine the number information of the bad core in the multiple slave processing units.

[0096] First, the target of the memory self-test algorithm is determined to be the memory of multiple slave processing units, i.e., the target to be tested is configured for the memory self-test algorithm. Then, the parameter information of the memory self-test algorithm is configured according to the testing requirements of the target, including at least the test mode and test time. Then, a test vector is generated according to the specification parameters and address information of the target, and the test vector is executed to completely test the memory of the multiple slave processing units. The test results are compared and analyzed with the preset test results corresponding to the test vector to obtain test data. The test data is parsed to determine whether there are bad cores in the central processing unit. If bad cores are found, their ID information can also be obtained.

[0097] Through the above embodiments, the memory self-test algorithm can quickly and accurately find bad cores in the central processing unit and deal with them in a timely manner to avoid abnormal OS crashes due to the presence of bad cores during operation, thus preventing greater losses to customers.

[0098] Optionally, the startup module 46 is further configured to store the numbering information of the other slave processing units into startup configuration information, and send the startup configuration information to the second system to instruct the second system to start according to the startup configuration information, wherein the startup configuration information is used by the second system to determine the slave processing unit to be started.

[0099] BIOS isolation of bad cores means that the BIOS does not record bad cores in the ACPI table (equivalent to the boot configuration information mentioned above). The ACPI table is a way for the BIOS to pass system information to the OS, and it contains all available CPU cores in the system. When the OS boots, it reads the ACPI table to get the number of CPU cores. Since bad cores are not recorded in the ACPI table, the OS is unaware of their existence and will not boot from them, thus avoiding abnormal CPU crashes caused by bad cores.

[0100] Through the above embodiments, when a bad core is detected in the central processing unit, the bad core is isolated, thereby preventing the OS from starting the bad core and causing the CPU to crash abnormally.

[0101] Optionally, the aforementioned determining module 42 is further configured to determine whether the number of bad cores exceeds a preset threshold; if the number of bad cores exceeds the preset threshold, the second system and the other slave processing units are prohibited from starting, and the first system and the main processing unit are stopped from running; if the number of bad cores does not exceed the preset threshold, the bad cores are isolated, and the second system and the other slave processing units are started.

[0102] When a bad core is detected in the central processing unit (CPU), the system first checks if the number of bad cores exceeds a preset threshold. If it does, even if the bad cores are isolated, the server's performance will be severely affected, and it may even disrupt the server's normal operation. Therefore, if the number of bad cores exceeds the preset threshold, the second system and other slave processing units are prevented from booting, and the BIOS is stopped. If the number of bad cores does not exceed the threshold, the bad cores can be isolated, thus ensuring the normal boot and operation of the OS.

[0103] Through the above embodiments, different countermeasures are taken according to the number of bad cores, thereby minimizing the impact of bad cores on system operation.

[0104] Optionally, the above-mentioned system startup device further includes a sending module 48, such as... Figure 5As shown, it is used to send alarm information to the baseboard management controller to instruct the baseboard management controller to store the alarm information in the controller log, wherein the alarm information includes: the number of bad cores and the bad core number information; the controller log is used by a first object to view the alarm information.

[0105] If the number of bad CPU cores exceeds the allowable threshold, even isolating the bad cores will severely impact server performance, thus preventing further machine operation and halting BIOS operation. The BIOS will also issue a warning, displaying the number of bad CPU cores, the allowable bad core threshold, and the bad core ID on the monitor. Simultaneously, the BIOS can send alarm information to the BMC via IPMI commands. The BMC records the CPU bad core alarm information in its log (equivalent to the aforementioned baseboard management controller). Users can then view the CPU bad core information on the BMC web interface or by using commands to access the BMC log. IPMI is a protocol interface used for communication and data transfer between the BIOS and the BMC.

[0106] Optionally, the sending module 48 is further configured to display the bad core number information on the first page, and to send the number information to the second system through the management system of the first system, so as to indicate to the first object that there is a bad core in the central processing unit.

[0107] After isolating the bad core and continuing to boot the second system and other processing units, the BIOS displays the bad core number of the CPU on the BIOS SETUP interface. At the same time, the bad core number of the CPU is transmitted to the OS through SMBIOS. Technicians or customers (equivalent to the first object mentioned above) can check whether there is a bad core in the CPU by viewing the BIOS SETUP interface or by using the dmidecode command to view SMBIO.

[0108] Through the above embodiments, when a customer's machine CPU has a bad core, it is only necessary to check the BIOS SETUP or the OS SMBIOS to confirm whether there is a bad CPU core. This avoids the need for multiple communications with the customer's personnel to confirm the problem, greatly improving the customer's experience with the company's products. It also avoids the complicated process of technicians going to the site for location and analysis, greatly saving the company's labor costs.

[0109] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0110] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when run.

[0111] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0112] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0113] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0114] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0115] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0116] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A system startup method, characterized in that, include: If the startup of the first system is detected, it is determined whether the first system is a cold start, wherein the cold start is used to indicate that the first system is starting for the first time after power-on; If the first system is determined to be a cold start, a memory self-test algorithm is used to detect the central processing unit to determine whether there is a bad core in the central processing unit. The bad core is used to indicate a damaged slave processing unit in the central processing unit. The first system and the main processing unit in the central processing unit are started simultaneously, and the first system is used to control the main processing unit. In the event of a bad core in the central processing unit, the bad core in the central processing unit is isolated, and a second system and other slave processing units in the central processing unit are started. The second system is used to control the main processing unit and the other slave processing units, which are slave processing units other than the bad core in the central processing unit. The step of using a memory self-test algorithm to detect the central processing unit (CPU) to determine whether there are bad cores in the CPU includes: The detection object corresponding to the memory self-test algorithm is determined, wherein the detection object includes the memory of multiple processing units; The parameter information of the memory self-test algorithm is configured according to the detection object, wherein the parameter information includes: test mode and test time; A detection vector is generated based on the specification parameters and address information of the object being detected; The detection vector is executed to detect the memory of the plurality of slave processing units; The detection results are compared and analyzed with the preset detection results corresponding to the detection vector to obtain detection data; The detection data is parsed to determine whether there is a bad core in the central processing unit, and to determine the numbering information of the bad core in the plurality of slave processing units.

2. The method according to claim 1, characterized in that, Determining whether the first system is undergoing a cold start includes: Read the status value stored in the register of the first system; If the state value is determined to be the first value, the first system is determined to be in a cold start state, and the state value is updated to the second value, wherein the first value is the default value of the state value; If the state value is determined to be different from the first value, then the first system is determined not to be a cold start.

3. The method according to claim 1, characterized in that, The step of isolating the faulty core in the central processing unit and starting the second system and other slave processing units in the central processing unit includes: The numbering information of the other slave processing units is stored in the startup configuration information, and the startup configuration information is sent to the second system to instruct the second system to start according to the startup configuration information, wherein the startup configuration information is used by the second system to determine the slave processing unit to be started.

4. The method according to claim 1, characterized in that, Before isolating the bad core in the central processing unit and starting the second system and other slave processing units in the central processing unit, the method further includes: Determine whether the number of bad cores exceeds a preset threshold; If the number of bad cores exceeds the preset threshold, the second system and the other slave processing units are prohibited from starting, and the first system and the main processing unit are stopped from running. If the number of bad cores is determined not to exceed the preset threshold, the bad cores are isolated, and the second system and the other slave processing units are started.

5. The method according to claim 4, characterized in that, After prohibiting the second system and the other slave processing units from starting up, and stopping the first system and the main processing unit from running, the method further includes: The alarm information is sent to the baseboard management controller to instruct the baseboard management controller to store the alarm information in the controller log. The alarm information includes: the number of bad cores and the bad core number information. The controller log is used by the first object to view the alarm information.

6. The method according to claim 4, characterized in that, After isolating the bad kernel and starting the second system and the other processing units, the method further includes: The faulty core's identification number is displayed on the first page, and the identification number is sent to the second system through the first system's management system to alert the first object that a faulty core exists in the central processing unit.

7. A system startup device, characterized in that, include: The determination module is used to determine whether the first system is a cold start when the first system is detected to be starting, wherein the cold start is used to indicate that the first system is starting for the first time after power-on; The detection module is used to detect the central processing unit (CPU) through a memory self-test algorithm when it is determined that the first system is a cold start, in order to determine whether there is a bad core in the CPU. The bad core is used to indicate a damaged slave processing unit in the CPU. The first system and the main processing unit in the CPU start simultaneously, and the first system is used to control the main processing unit. A startup module is used to isolate the bad core in the central processing unit (CPU) and start a second system and other slave processing units in the CPU when a bad core exists in the CPU. The second system is used to control the main processing unit and the other slave processing units, which are slave processing units other than the bad core in the CPU. The detection module is further configured to: determine the detection object corresponding to the memory self-test algorithm, wherein the detection object includes the memory of multiple slave processing units; configure the parameter information of the memory self-test algorithm according to the detection object, wherein the parameter information includes: test mode, test time; generate a detection vector according to the specification parameters and address information of the detection object; execute the detection vector to detect the memory of the multiple slave processing units; compare and analyze the detection result with the preset detection result corresponding to the detection vector to obtain detection data; and parse the detection data to determine whether there is a bad core in the central processing unit and to determine the number information of the bad core in the multiple slave processing units.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method described in any one of claims 1 to 6.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method described in any one of claims 1 to 6.

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