Quantum circuit mapping method, device and electronic device

Abstract

The present disclosure provides a quantum circuit mapping method, device and electronic device, which relates to the field of quantum computing technology, and specifically to the field of quantum circuit technology. The specific implementation scheme is: based on the arrangement structure information of quantum bits on the quantum chip, obtain the coupling graph and node index of the quantum chip; obtain the interaction graph of the first logical quantum circuit precompiled on the quantum chip; search for the first subgraph isomorphic to the interaction graph in the reduced search space of the coupling graph, and the reduced search space includes a node set in the coupling graph whose distance from the generation set does not exceed a specified distance; based on the node index, use the octagonal array structure of the coupling graph to perform a translation operation on the first subgraph on the coupling graph to match the generation set, and obtain a second subgraph; determine the first mapping scheme corresponding to each subgraph in the subgraph set; based on the fidelity of the physical quantum gate on the quantum chip, determine the target mapping scheme from the first mapping scheme corresponding to the subgraph set.

Description

Technical Field

[0001] The present disclosure relates to the field of quantum computing technology, in particular to the field of quantum circuit technology, and specifically to a quantum circuit mapping method, device and electronic device. Background Art

[0002] Quantum circuit mapping is an important problem in quantum computing and plays an important role in alleviating the impact of noise on quantum computing. It involves selecting a set of physical quantum bits in a quantum processor (also known as a quantum chip) to construct quantum gates to execute a given logical quantum circuit.

[0003] In essence, the quantum circuit mapping problem is about determining the mapping relationship between the quantum bits (or quantum gates) in the logical quantum circuit and the physical quantum bits (or quantum gates) in the quantum processor. Due to the limitations of existing micro-nano processing and measurement and control technologies, the performance of the quantum bits (or quantum gates) on the quantum processor varies.

[0004] Generally, quantum circuit mapping should avoid quantum bits and quantum gates with poor quality, and select appropriate quantum bits and quantum gates to execute quantum algorithms to reduce errors that may occur during the operation of quantum circuits and obtain high-fidelity computing results. Summary of the invention

[0005] The present disclosure provides a quantum circuit mapping method, device and electronic device.

[0006] According to a first aspect of the present disclosure, a quantum circuit mapping method is provided, comprising:

[0007] Based on the arrangement structure information of the quantum bits on the quantum chip, a coupling graph of the quantum chip and a node index of the coupling graph are obtained; and an interaction graph of a first logic quantum circuit precompiled onto the quantum chip is obtained; the arrangement structure information indicates that the quantum bits on the quantum chip are arranged in an octagonal array structure, and the node index indicates a mapping relationship between the node position coordinates of the quantum bits and the node labels;

[0008] searching for a first subgraph isomorphic to the interaction graph in a reduced search space of the coupling graph, the reduced search space comprising a set of nodes in the coupling graph whose distances to a spanning set do not exceed a specified distance, the specified distance being greater than or equal to a radius of the interaction graph, and the spanning set covering the coupling graph under a matching translation operation;

[0009] Based on the node index, using the octagonal array structure of the coupling graph, a translation operation matching the spanning set is performed on the first subgraph on the coupling graph to obtain a second subgraph isomorphic to the interaction graph;

[0010] Determine each subgraph in the subgraph collection Figure 1 a corresponding first mapping scheme, wherein the first mapping scheme is a mapping scheme from the first logic quantum circuit to the quantum chip, and the subgraph set includes the first subgraph and the second subgraph;

[0011] Based on the fidelity of the physical quantum gates on the quantum chip, a target mapping scheme from the first logical quantum circuit to the quantum chip is determined from the first mapping schemes corresponding to the subgraph set.

[0012] According to a second aspect of the present disclosure, a quantum circuit mapping device is provided, comprising:

[0013] An acquisition module is used to acquire a coupling graph of the quantum chip and a node index of the coupling graph based on the arrangement structure information of the quantum bits on the quantum chip; and to acquire an interaction graph of a first logic quantum circuit precompiled onto the quantum chip; the arrangement structure information indicates that the quantum bits on the quantum chip are arranged in an octagonal array structure, and the node index indicates a mapping relationship between the node position coordinates of the quantum bits and the node labels;

[0014] A search module, configured to search a first subgraph isomorphic to the interaction graph in a reduced search space of the coupling graph, the reduced search space comprising a set of nodes in the coupling graph whose distances from a generated set do not exceed a specified distance, the specified distance being greater than or equal to a radius of the interaction graph, and the generated set covering the coupling graph under a matching translation operation;

[0015] A translation operation module, configured to perform a translation operation on the first subgraph on the coupling graph that matches the generated set based on the node index and utilize the octagonal array structure of the coupling graph to obtain a second subgraph that is isomorphic to the interaction graph;

[0016] The first determination module is used to determine each subgraph in the subgraph set. Figure 1 a corresponding first mapping scheme, wherein the first mapping scheme is a mapping scheme from the first logic quantum circuit to the quantum chip, and the subgraph set includes the first subgraph and the second subgraph;

[0017] The second determination module is used to determine a target mapping scheme from the first logical quantum circuit to the quantum chip from the first mapping scheme corresponding to the subgraph set based on the fidelity of the physical quantum gate on the quantum chip.

[0018] According to a third aspect of the present disclosure, there is provided an electronic device, including:

[0019] at least one processor; and

[0020] a memory communicatively connected to at least one processor; wherein,

[0021] The memory stores instructions that can be executed by at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform any method in the first aspect.

[0022] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause a computer to execute any one of the methods in the first aspect.

[0023] According to a fifth aspect of the present disclosure, a computer program product is provided, comprising a computer program, which implements any one of the methods in the first aspect when executed by a processor.

[0024] The technology disclosed in the present invention solves the problem of relatively low mapping efficiency of quantum circuits on quantum chips with octagonal array structures in related technologies, and can improve the mapping efficiency of quantum circuits on quantum chips with octagonal array structures.

[0025] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure.

[0027] Figure 1 is a flowchart of a quantum circuit mapping method according to the first embodiment of the present disclosure;

[0028] Figure 2 Schematic diagram of the structure of a quantum chip with a coupling diagram of an octagonal array structure;

[0029] Figure 3 It is a schematic diagram of the node numbering of quantum bits;

[0030] Figure 4 It is a schematic diagram of the structure of an example of a logic quantum circuit;

[0031] Figure 5 It is a schematic diagram of the structure of an interaction diagram of an example logic quantum circuit;

[0032] Figure 6 is a schematic diagram of the structure of a coupling diagram of an example quantum chip;

[0033] Figure 7 It is a performance operation diagram of different subgraph matching schemes;

[0034] Figure 8 It is a performance operation diagram of different circuit mapping schemes;

[0035] Fig. 9 is a schematic structural diagram of a quantum circuit mapping device according to a second embodiment of the present disclosure;

[0036] Fig.10 is a schematic block diagram of an example electronic device for implementing an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0038] First embodiment

[0039] like Figure 1 As shown, the present disclosure provides a quantum circuit mapping method, comprising the following steps:

[0040] Step S101: Based on the arrangement structure information of the quantum bits on the quantum chip, a coupling graph of the quantum chip and a node index of the coupling graph are obtained; and an interaction graph of a first logic quantum circuit precompiled onto the quantum chip is obtained; the arrangement structure information indicates that the quantum bits on the quantum chip are arranged in an octagonal array structure, and the node index indicates a mapping relationship between the node position coordinates of the quantum bits and the node labels.

[0041] Among them, the coupling diagram is used to characterize the physical connection between quantum bits on the quantum chip, the coupling diagram is an octagonal array structure, and the interaction diagram is used to characterize the interaction between quantum bits involved in the execution process of the first logical quantum circuit.

[0042] In this embodiment, the quantum circuit mapping method relates to the field of quantum computing technology, and in particular to the field of quantum circuit technology. It can be widely used in quantum circuit mapping scenarios, and has important significance for the practical applications of quantum computing, such as code breaking, drug development, and machine learning. The quantum circuit mapping method of the disclosed embodiment can be performed by the quantum circuit mapping device of the disclosed embodiment. The quantum circuit mapping device of the disclosed embodiment can be configured in any electronic device to perform the quantum circuit mapping method of the disclosed embodiment.

[0043] Quantum computing is a new computing model that uses the characteristics of quantum mechanics to perform calculations. Unlike classical computing, quantum computing uses phenomena such as quantum superposition and entanglement of quantum bits (qubits), allowing more efficient calculations in some cases. In quantum computing, calculations are no longer based solely on the 0 and 1 of classical bits, but allow for a certain degree of superposition of 0 and 1 at the same time, as well as entanglement between different quantum bits.

[0044] These quantum properties allow the design of quantum algorithms that are more efficient than classical algorithms. For example, Shor's algorithm can speed up the factorization of large numbers, which helps in password cracking; quantum algorithms such as the HHL algorithm can speed up the solution of linear equations and have great application value in engineering practice.

[0045] Noise is a major challenge facing quantum computers, limiting their performance and reliability. Noise can come from many sources, including hardware processing defects, environmental interference, and crosstalk between quantum bits. In order to reduce the impact of noise on quantum computing, a variety of solutions have been proposed, including hardware technologies such as environmental isolation, and software technologies such as quantum error correction codes and quantum circuit mapping.

[0046] This embodiment is aimed at quantum circuit mapping in software to reduce noise during the operation of logical quantum circuits. Quantum circuit mapping is an important issue in quantum computing and plays an important role in alleviating the impact of noise on quantum computing. It involves selecting a set of physical quantum bits and quantum gates in a quantum processor (also known as a quantum chip) to execute a given quantum algorithm (i.e., a logical quantum circuit).

[0047] Essentially, the quantum circuit mapping problem is about determining the mapping relationship between the qubits (or quantum gates) in the logical quantum circuit and the physical qubits (or quantum gates) in the quantum processor. In particular, due to the limitations of existing micro-nano processing and measurement and control technologies, the performance of qubits (or quantum gates) on quantum processors varies. An ideal quantum circuit mapping should avoid qubits and quantum gates of poor quality, thereby reducing the errors that may occur during the operation of the quantum circuit.

[0048] Due to the complex entanglement and coupling between quantum bits, and the fact that actual quantum gate operations may be affected by noise and errors, mapping logical quantum circuits to physical quantum circuits is a complex optimization problem. This usually involves solving problems such as quantum bit connection restrictions, noise tolerance, and reordering and optimization of quantum gates.

[0049] Current quantum processors are susceptible to environmental noise during operation. Specifically, as the depth of the quantum circuit and the number of quantum gates increase, the fidelity of the quantum circuit decays exponentially, and the decrease in fidelity means that the probability of obtaining the correct result of the quantum computing operation decreases. Therefore, in order to achieve large-scale quantum computing, an effective error mitigation scheme must be used to suppress the decrease in the fidelity of the quantum circuit.

[0050] Quantum circuit mapping reduces the impact of noise during the operation of quantum circuits by selecting a set of high-quality quantum bits and quantum gates to run a given quantum algorithm. The use of appropriate quantum circuit mapping can significantly improve the fidelity of quantum algorithm operation. However, selecting a better quantum circuit mapping is itself an NP-hard problem, which means that searching for a better quantum circuit mapping is usually accompanied by a lot of computational overhead. Therefore, how to design an efficient quantum circuit mapping algorithm is a key problem that needs to be solved.

[0051] This embodiment is aimed at quantum chips with octagonal array structures that are widely used in quantum processors, and proposes an efficient quantum circuit mapping scheme for this type of quantum hardware. That is, by utilizing the structural characteristics of quantum chips, an efficient quantum circuit mapping scheme suitable for quantum chips with octagonal array structures is implemented.

[0052] The following is an explanation of the basic concepts related to quantum circuit mapping.

[0053] Quantum circuit: A qubit is the basic unit of quantum information and the quantum counterpart of a classical bit. A qubit can exist in a superposition of states or be entangled with other qubits, enabling powerful quantum computing. A quantum gate is an operation that acts on one or more qubits. Specifically, a quantum gate defines a specific evolution of a quantum state, which can be considered the basic building block of a quantum circuit, similar to a classical logic gate. A sequence of multiple quantum gates is called a quantum circuit. A quantum circuit essentially defines the evolution of an initial quantum state. By designing / programming a quantum circuit, any quantum algorithm can be implemented.

[0054] Quantum circuit interaction graph: A quantum circuit interaction graph is a graph representation of a quantum circuit. This is a structure consisting of a set of nodes and edges connecting some nodes. Specifically, given a quantum circuit, each quantum bit in the quantum circuit is represented by a node. For each two-qubit gate in the circuit, an edge is used to connect the nodes corresponding to the quantum bits acted on by the quantum gate. In this way, a graph is constructed. This graph is the interaction graph of the quantum circuit, which is used to represent the interaction between the quantum bits involved in the execution of the quantum circuit, or the connectivity between the logical quantum bits.

[0055] Quantum processor coupling graph: A quantum processor is a quantum chip. The coupling graph of a quantum hardware device represents the physical connection between the quantum bits used to implement a two-qubit gate. In other words, it shows which quantum bits can interact directly with each other, and these interactions are essential for performing the multi-qubit operations required for quantum computing. The structure of the coupling graph can significantly affect the functionality of a quantum processor. A dense (well-connected) coupling graph means that the quantum chip can effectively execute quantum algorithms and reduce noise interference. A sparse (poorly connected) coupling graph may pose challenges to the implementation of certain algorithms because it may require quantum bits that are not directly coupled to interact.

[0056] In particular, the coupling diagram of the octagonal array structure is one of the most commonly used coupling diagrams for quantum chips, and the connections between the quantum bits on the quantum chip with the coupling diagram of the octagonal array structure constitute an octagonal array. Figure 2 As shown, each node represents a quantum bit (qubit), and the lines between the nodes represent the coupling (coupler) between the quantum bits, that is, the connected quantum bits can interact with each other, wherein each quantum bit is connected to another three quantum bits, so the octagonal array structure has the characteristic of good quantum bit connectivity. In view of this, this embodiment is aimed at the quantum circuit mapping problem of the quantum chip with an octagonal array structure.

[0057] Quantum circuit compilation: Quantum circuit compilation refers to the process of converting advanced quantum algorithms or quantum gate operations into physical quantum gate sequences that can be executed on a specific hardware platform. The main goal of quantum circuit compilation is to optimize the sequence of quantum gate operations to minimize errors and noise in the calculation process, while converting quantum gates that are not supported by the hardware so that the quantum circuit meets the limitations of the hardware. The workflow of quantum circuit compilation is as follows:

[0058] 1. Determine the initial circuit mapping;

[0059] 2. Introduce SWAP gates to meet the qubit connection requirements (i.e. pre-compilation);

[0060] 3. Perform secondary mapping on the circuit to enhance fidelity (secondary quantum circuit mapping after circuit compilation); the secondary mapping of quantum circuits involves subgraph matching and quantum circuit mapping scoring;

[0061] 4. Convert the quantum gates in the circuit into hardware-native quantum gates;

[0062] 5. Optimize the circuit to minimize the total number of quantum gates;

[0063] 6. Output quantum circuit.

[0064] Among them, quantum circuit mapping is a sub-process of quantum circuit compilation, and in this embodiment, secondary quantum circuit mapping is performed on the pre-compiled quantum circuit, that is, the first logic quantum circuit is the logic quantum circuit obtained after pre-compilation. In an optional implementation, the original logic quantum circuit can be pre-compiled onto the quantum chip to obtain the pre-compiled first logic quantum circuit. In another optional implementation, a local area of ​​the quantum chip can be selected, and the original logic quantum circuit can be pre-compiled onto the local area of ​​the quantum chip to obtain the pre-compiled first logic quantum circuit. Correspondingly, based on the operation instructions of the first logic quantum circuit, the interaction diagram of the first logic quantum circuit can be obtained.

[0065] The coupling graph of the quantum chip can be obtained based on the arrangement structure information of the physical quantum bits in the quantum chip, wherein the arrangement structure information indicates that the quantum bits on the quantum chip are arranged in an octagonal array structure, and accordingly, its coupling graph is also an octagonal array structure. Based on the arrangement structure information, each quantum bit on the quantum chip can be obtained, and a node can be created for each quantum bit on the quantum chip to construct the coupling graph of the quantum chip.

[0066] The node index indicates the mapping relationship between the node position coordinates of the quantum bit and the node number, which can store the node position coordinates and node number of the quantum bit in a key-value manner. Among them, the node position coordinates can refer to the position of the node corresponding to the quantum bit on the coupling graph, which can be represented by two-dimensional coordinates or three-dimensional coordinates, which is not specifically limited here.

[0067] The node position coordinates of the quantum bits can be determined based on the relative position information between the quantum bits in the arrangement structure information of the quantum bits on the quantum chip. The node position coordinates of the quantum bits on the quantum chip can also be determined based on the relative position of the nodes corresponding to the quantum bits in the octagonal structure and the layout information of the octagonal structure arranged on the quantum chip, and the arrangement structure information includes the relative position and layout information, which is not specifically limited here.

[0068] The node label may be the number of the node corresponding to the quantum bit of the quantum chip, which may be determined based on the node position coordinates or may be pre-set, and is not specifically limited here.

[0069] The following describes in detail the logic of the quantum circuit quadratic mapping algorithm.

[0070] The first logical quantum circuit obtained by pre-compilation of the quantum circuit can be used as input. The goal is to identify the area on the quantum chip that is topologically equivalent to the input circuit (called an isomorphic subgraph) so that the circuit can be physically realized.

[0071] This involves solving the subgraph matching problem. After completing this step, a set of isomorphic subgraphs on the quantum chip can be obtained. Each subgraph corresponds to a mapping from logical qubits in the quantum circuit to actual physical qubits on the quantum hardware, which is called a feasible quantum circuit mapping scheme.

[0072] Then, for these feasible quantum circuit mapping schemes, the corresponding quantum circuit fidelity can be estimated, the feasible quantum circuit mappings can be ranked according to their scores, and the corresponding target mapping scheme can be selected based on the score ranking. In an optional implementation, the quantum circuit mapping with the highest score (the corresponding quantum circuit with the lowest error rate) can be selected as the output. In essence, the circuit mapping is optimized under the premise of meeting the hardware limitations of the quantum chip to minimize the probability of errors during the execution of the quantum circuit.

[0073] It is worth noting that the quantum circuit remapping involves searching for a set of physical qubits on the quantum hardware whose connectivity is equivalent to the connectivity between the logical bits in the input quantum circuit. Specifically, it is necessary to search for a subgraph in the coupling graph of the quantum chip that is isomorphic to the interaction graph of the quantum circuit. This problem is called the subgraph matching problem.

[0074] However, the subgraph matching problem is an NP-complete problem, which means that the quantum circuit remapping requires a relatively large computational overhead and has poor scalability. The relevant technology cannot handle the circuit mapping problem on large-scale quantum chips. In addition, the research and development of quantum computers has made significant progress in recent years. The latest quantum computers already have hundreds of qubits, and this number is expected to increase thousands of times in the next few years. In view of these developments, the relevant quantum circuit remapping schemes will be difficult to apply to recent quantum computers.

[0075] The purpose of this embodiment is to use the symmetry of the octagonal array structure of the quantum chip to accelerate the search process of circuit mapping, which has the advantage of significantly improving the search speed and realizing an efficient quantum circuit mapping scheme suitable for quantum chips with octagonal array structures. In addition, based on pre-compilation, the second mapping of the quantum circuit is used to obtain the target mapping scheme from the first logical quantum circuit to the quantum chip, which can optimize the mapping of the quantum circuit and improve the fidelity of the quantum circuit, thereby obtaining a high-fidelity quantum computing result.

[0076] Step S102: Search for a first subgraph isomorphic to the interaction graph in a reduced search space of the coupling graph, wherein the reduced search space includes a set of nodes in the coupling graph whose distance from the generation set does not exceed a specified distance, and the specified distance is greater than or equal to the radius of the interaction graph, and the generation set can cover the coupling graph under a matching translation operation.

[0077] The core problem of the quadratic mapping of quantum circuits is the subgraph matching problem. In the subgraph matching problem, given two graphs, usually called pattern graph G and target graph P, the goal is to find all subgraphs G′ in the target graph that are isomorphic to the pattern graph (i.e., have the same structure and connection mode). Indicates that graphs G′ and G are isomorphic.

[0078] A first subgraph isomorphic to the interaction graph may be searched in a reduced search space of the coupling graph. The reduced search space may be determined based on a spanning set, which includes a set of nodes in the coupling graph whose distances to the spanning set do not exceed a specified distance.

[0079] As long as the selected generation set can cover the entire target graph under the corresponding translation transformation, all isomorphic subgraphs can be searched based on the first subgraph under the translation transformation, and the logical correctness can be guaranteed.

[0080] The specified distance needs to be greater than or equal to the radius of the interaction graph, so that the first subgraph isomorphic to the interaction graph can be found in the reduced search space. The radius of the interaction graph can be the maximum step length from a node to the central node in the graph.

[0081] An existing or new subgraph search method may be used to search for a first subgraph isomorphic to the interaction graph in the reduced search space of the coupling graph, which is not specifically limited here.

[0082] In this step, by limiting the reduced search space of the coupling graph and searching for a subgraph isomorphic to the interaction graph in the reduced search space of the coupling graph, the scope of the subgraph search can be narrowed and the amount of computation of the subgraph search can be reduced.

[0083] Step S103: Based on the node index, the octagonal array structure of the coupling graph is used to perform a translation operation on the first subgraph on the coupling graph to match the generated set, so as to obtain a second subgraph isomorphic to the interaction graph.

[0084] In the field of quantum computing, symmetry plays a key role and provides a wide range of applications. It has been exploited to optimize resource usage efficiency in variational quantum eigensolvers, reduce error rates in quantum approximate optimization algorithms, efficiently design quantum error correction codes, and promote the development of quantum machine learning models.

[0085] A given logical quantum circuit can be mapped to a set of quantum bits and quantum gates on quantum hardware, so that the interaction graph of the quantum circuit and the coupling graph of the hardware are compatible, and the fidelity of the quantum circuit is high. In particular, the symmetry of the quantum chip structure can be used to significantly improve the efficiency of quantum circuit mapping.

[0086] In this step, when the first subgraph is obtained, the symmetry of the octagonal array structure of the coupling graph of the quantum chip can be used to simulate the movement of the first subgraph to various positions of the coupling graph by translation, and the node label of the subgraph after the movement is determined based on the node index to obtain the second subgraph, so that all subgraphs that are isomorphic to the interaction graph can be searched to form a subgraph set, and the search speed is very efficient.

[0087] Different generation sets have different translation modes. In order to enable the translation operation on the first subgraph to cover the entire target graph, the translation mode needs to correspond to the generation set.

[0088] In an optional embodiment, the translation operation of the first subgraph in the coupling graph can be simulated by software to obtain a second subgraph isomorphic to the interaction graph. In another optional embodiment, the symmetry of the octagonal array structure of the coupling graph can be used to construct an update range of the translation transformation of the node position coordinates of the first subgraph in the coupling graph, and based on the update range, the node position coordinates of the first subgraph are updated to obtain a second subgraph isomorphic to the interaction graph.

[0089] Step S104: Determine each subgraph in the subgraph set. Figure 1 A corresponding first mapping scheme, where the first mapping scheme is a mapping scheme from the first logic quantum circuit to the quantum chip, and the subgraph set includes the first subgraph and the second subgraph.

[0090] Each subgraph corresponds to a mapping from the interaction graph of the first logic quantum circuit to the quantum chip, and based on the pre-compilation, a mapping from the first logic quantum circuit to the quantum chip can be obtained. Accordingly, through the double mapping, all first mapping schemes from the first logic quantum circuit to the quantum chip can be obtained, and the first mapping scheme can be called a feasible quantum circuit mapping scheme.

[0091] Step S105: Based on the fidelity of the physical quantum gate on the quantum chip, determine a target mapping scheme from the first logical quantum circuit to the quantum chip from the first mapping scheme corresponding to the subgraph set.

[0092] In this step, the target fidelity of mapping the first logical quantum circuit to the physical quantum circuit on the quantum chip in each first mapping scheme can be obtained based on the fidelity of the physical quantum gate on the quantum chip. Based on the target fidelity, the first mapping schemes are sorted, and the first mapping scheme with the largest target fidelity can be selected as the target mapping scheme, or any first mapping scheme with a target fidelity greater than or equal to a specified threshold can be selected as the target mapping scheme.

[0093] In this embodiment, a secondary circuit mapping technology is used. After the circuit is precompiled, a first subgraph isomorphic to the interaction graph of the precompiled first logic quantum circuit by performing subgraph matching search in the reduced search space of the coupling graph determined based on the generation set, and then based on the node index, the first subgraph is translated on the coupling graph to match the generation set using the octagonal array structure of the coupling graph to obtain a second subgraph isomorphic to the interaction graph. Accordingly, all quantum circuit mappings can be searched through subgraph matching, and based on the fidelity of the physical quantum gates on the quantum chip, a target mapping scheme that makes the fidelity of the quantum circuit high is selected from all the first mapping schemes, which fully considers the difference in error rates of different physical quantum gates, optimizes the mapping of the quantum circuit, and improves the fidelity of the quantum circuit. Moreover, by effectively reducing the search space for subgraph matching and based on node indexing, by utilizing the structural characteristics of quantum hardware, that is, utilizing the symmetry of the octagonal array structure of the quantum chip to perform a translation transformation of the subgraph to search for other subgraphs, the subgraph search process of circuit mapping can be accelerated, and efficient translation transformation of a group of quantum bits can be achieved, which significantly simplifies the process of searching for quantum circuit mapping, has the advantage of significantly improving the search speed, and realizes an efficient quantum circuit mapping scheme suitable for quantum chips with octagonal array structures.

[0094] Accordingly, after the input circuit is precompiled onto the quantum chip to obtain the first logical quantum circuit and the target mapping scheme is determined, the first logical quantum circuit is mapped onto the quantum chip with an octagonal array structure according to the target mapping scheme, so as to actually run the input circuit on the quantum chip to perform actual quantum computing tasks, such as quantum communication, quantum computing protocols, and quantum key distribution protocols. Moreover, the accuracy of quantum algorithm operation on large quantum processors can be improved, making up for the shortcomings of current quantum computing that is easily affected by environmental noise, which is of great significance to the practical applications of quantum computing, such as code breaking, drug development, and machine learning.

[0095] Optionally, the step S101 specifically includes:

[0096] Creating a node for each quantum bit on the quantum chip to construct a coupling graph of the quantum chip;

[0097] Determining the node position coordinates of the quantum bits on the quantum chip based on the relative positions of the nodes corresponding to the quantum bits in the octagonal structure and the layout information of the octagonal structure arranged on the quantum chip, wherein the arrangement structure information includes the relative positions and layout information;

[0098] Determining the node number of the quantum bit on the quantum chip based on the node position coordinates;

[0099] A mapping relationship between the node position coordinates of the quantum bit and the node label is established to obtain the node index of the coupling graph.

[0100] In order to efficiently retrieve the quantum bits at a given position in the quantum chip, it is necessary to label these quantum bits and determine the node position coordinates of the node corresponding to each quantum bit.

[0101] Based on the arrangement structure information of the quantum bits on the quantum chip, the number of quantum bits on the quantum chip can be determined, and a node can be created for each quantum bit, and edges can be created between the nodes of two mutually coupled quantum bits, so that the coupling graph of the quantum chip can be constructed.

[0102] The node position coordinates of the quantum bits on the quantum chip can be determined based on the relative positions of the nodes corresponding to the quantum bits in the octagonal structure and the layout information of the octagonal structure arranged on the quantum chip. In an optional embodiment, the node position can be determined based on the relative positions of the nodes corresponding to the quantum bits in the octagonal structure and the layout information of the octagonal structure arranged on the quantum chip, thereby determining the node position coordinates.

[0103] Optionally, the node position coordinates include a first parameter, a second parameter and a third parameter, the first parameter indicates the row position of the octagonal structure to which the quantum bit corresponding node belongs, the second parameter indicates the column position of the octagonal structure to which the quantum bit corresponding node belongs, the third parameter indicates the relative position of the quantum bit corresponding node in the octagonal structure, the row position is less than or equal to the number of rows of the octagonal structures arranged on the quantum chip, the column position is less than or equal to the number of columns of the octagonal structures arranged on the quantum chip, and the layout information includes the number of rows and the number of columns.

[0104] That is, the node position coordinates of the quantum bit are determined based on the position of the octagonal structure to which the node belongs in the coupling graph and the relative position of the node in the octagonal structure to which it belongs. In this way, the node position coordinates of the quantum bit can be determined very efficiently.

[0105] Afterwards, the node number of the quantum bit on the quantum chip can be determined based on the node position coordinates. The node number can be calculated using the following formula:

[0106] node_index=(i×width+j)×8+k;

[0107] Among them, node_index is the node index, i is the first parameter, j is the second parameter, k is the third parameter, that is, the node position coordinates of the quantum bit are (i, j, k), and width is the number of columns.

[0108] In an optional implementation, the node numbering method of the quantum bit can be as follows: Figure 3 As shown in the figure, the quantum chip is composed of an octagonal array of 4 rows and 4 columns. Each vertex in the octagonal structure corresponds to a quantum bit. The vertex of the octagonal structure located at the lower left corner of the quantum chip (i.e., row 0 and column 0) can be numbered in a counterclockwise direction. Then, according to the periodicity (or translational symmetry) of the quantum chip, the numbering of the above quantum bits is extended to the entire chip.

[0109] The process of creating the coupling graph and node index of the qubit is as follows:

[0110] Input: the number of rows, height and columns, width of the octagonal structure in the coupling diagram of the octagonal array structure;

[0111] Output: coupling graph P of octagonal array structure, node index index (a dictionary storing the mapping from node position coordinates to node labels).

[0112] Step 1: Initialize the node list node_list and edge list edge_list to empty lists;

[0113] Step 2: Initialize the node index index to an empty dictionary;

[0114] Step 3: Loop through the row index i∈{0,1,...,height-1}: Loop through the column index j∈{0,1,...,width-1}: Loop through the relative position index k∈{0,1,...,7} of the node in the octagonal structure: Perform the following operations:

[0115] Operation a: Add a node to node_list and define the node position coordinates as (i, j, k);

[0116] Operation b: Calculate the node index node_index = (i×width+j)×8+k;

[0117] Operation c: Add the key-value pair {(i,j,k):node_index} to the node index index, where (i,j,k) is the node position coordinate;

[0118] Step 4: Add the edges between the nodes in the octagonal array to edge_list;

[0119] Step 5: Use a graph theory software package such as rustworkx or NetworkX to take the node_list and edge_list of the graph as input to create a coupling graph P of an octagonal array structure;

[0120] Step 6: Return the coupling graph P of the octagonal array structure and the node index index.

[0121] It should be noted that the row position indicates the row where the octagonal structure is located, and the row index indicates the number of the row position, which is numbered from 0, and its row index is less than the number of rows of the octagonal structure arranged on the quantum chip. The column position indicates the column where the octagonal structure is located, and the column index indicates the number of the column position, which is numbered from 0, and its column index is less than the number of columns of the octagonal structure arranged on the quantum chip.

[0122] Optionally, the generated set includes any of the following:

[0123] 8 nodes in any octagonal structure arranged in the coupling graph;

[0124] Six consecutive nodes in any octagonal structure arranged in the coupling graph.

[0125] Any of the above-mentioned groups of generation sets and corresponding translation transformations can satisfy the above-mentioned requirement of covering the complete coupling graph. In this way, the generation sets can be flexibly selected to construct the reduced search space of the coupling graph.

[0126] Optionally, in the case where the spanning set includes eight nodes in any octagonal structure arranged in the coupling graph, the translation operation matching the spanning set includes: translation in a horizontal direction and a vertical direction;

[0127] In the case where the generation set includes 6 consecutive nodes in any octagonal structure arranged in the coupling graph, the translation operation matching the generation set includes: translation along the horizontal direction, vertical direction and target diagonal direction, and the target diagonal direction is the vertical direction of the line connecting the other two nodes in the octagonal structure to which the generation set belongs except the 6 consecutive nodes.

[0128] The definition of translational symmetry is paired with the selection of the spanning set. In principle, as long as the selected spanning set can cover the entire coupling graph under the corresponding translation transformation, the correctness of the subgraph matching logic can be guaranteed.

[0129] You can choose to generate a set of 8 nodes of any octagonal structure, such as Figure 3 The octagonal structure composed of nodes 0 to 7 corresponds to the translation transformation along the horizontal and vertical directions. This set of generated sets and translation transformations satisfy the above conditions for covering the coupled graph.

[0130] Other combinations of generation sets and translation transformations may also be selected. For example, diagonal translation (node ​​5→node 0) may be added to the translation transformation. Accordingly, the generation set may be further reduced to a line graph consisting of nodes 2 to 7.

[0131] For the two different generation sets mentioned above, the number of translations performed during the subgraph matching process is the same, which is equal to the number of all subgraph isomorphic mappings. The difference is that if the translation along the diagonal is introduced into the translation transformation involved, the reduction of the generation set will lead to a reduction in the reduced search space, which means that the amount of computation required for subgraph matching in the reduced search space will be reduced. However, the amount of computation required for this step only accounts for a small part of the entire subgraph matching process, so it has little impact on the total running time.

[0132] In this way, after the corresponding generation set is selected, the sub-graph translation transformation can be performed according to the matching translation operation, thereby improving the flexibility of sub-graph matching.

[0133] Optionally, the step S103 specifically includes:

[0134] Based on the node labels of the first subgraph, retrieve the node position coordinates of the first subgraph in the node index;

[0135] Based on the layout information of the octagonal structure in the coupling graph and the node position coordinates of the first subgraph, determining the number of steps required for the first subgraph to be translated to the boundary of the coupling graph in units of octagonal structures according to the translation direction matched by the generation set;

[0136] Based on the number of steps required for translating the first subgraph to the boundary of the coupling graph, constructing an update range of the node position coordinates of the first subgraph during the movement on the coupling graph;

[0137] Based on the layout information of the octagonal structure in the coupling graph, the node labels of the first subgraph are updated within the update range to obtain a second subgraph isomorphic to the interaction graph.

[0138] During the translation process, the octagonal array structure of the coupling graph can be utilized, that is, based on the layout information of the octagonal structure in the coupling graph, the first subgraph can be translated in units of the octagonal structure, and based on the node position coordinates of the first subgraph and the layout information of the octagonal structure in the coupling graph, the number of steps required to translate the first subgraph to the boundary of the coupling graph can be determined.

[0139] Afterwards, based on the number of steps required for the first subgraph to be translated to the boundary of the coupling graph, the update range of the node position coordinates of the first subgraph during the movement on the coupling graph is constructed, and the node labels of the first subgraph are updated based on the update range. In this way, the symmetry of the octagonal array structure in the coupling graph can be utilized to efficiently realize subgraph matching search, thereby efficiently realizing quantum circuit mapping.

[0140] Optionally, when the generated set includes eight nodes in any octagonal structure arranged in the coupling graph, step S103 specifically includes:

[0141] Based on the node labels of the first subgraph, retrieve the node position coordinates of the first subgraph in the node index;

[0142] Based on the layout information of the octagonal structure in the coupling graph and the node position coordinates of the first subgraph, determining the number of steps required for the first subgraph to move horizontally and vertically to the boundary of the coupling graph in units of octagonal structures;

[0143] Based on the number of steps required for the first subgraph to move horizontally and vertically to the boundary of the coupling graph, construct an update range of the node position coordinates of the first subgraph during the movement on the coupling graph;

[0144] Based on the layout information of the octagonal structure in the coupling graph, the node labels of the first subgraph are updated within the update range to obtain a second subgraph isomorphic to the interaction graph.

[0145] In this way, subgraph matching search can be efficiently achieved by translating horizontally and vertically.

[0146] Optionally, in a case where the spanning set includes eight nodes in any octagonal structure arranged in the coupling graph, the translation direction matched by the spanning set includes horizontal and vertical directions, and the node labels of the first subgraph are updated within the update range based on the layout information of the octagonal structure in the coupling graph to obtain a second subgraph isomorphic to the interaction graph, including:

[0147] Increase the node numbers of the first subgraph by 8n; and increase the node numbers of the first subgraph by -8m×width to obtain the node numbers of the second subgraph;

[0148] Among them, n is a translation to the right of n steps in the coupling diagram, m is a translation downward of m steps in the coupling diagram, n and m are both within the update range, and width is the number of columns of the octagonal structure arranged on the quantum chip in the layout information.

[0149] In this way, the node labels of the first subgraph can be updated within the update range, thereby achieving subgraph matching search to obtain other subgraphs that are isomorphic to the interaction graph.

[0150] Optionally, the number of steps required for the first subgraph to move horizontally to the left to the boundary of the coupling graph is: a first target value, the first target value being the minimum value of the column position of the octagonal structure to which the node belongs in the position coordinates of each node of the first subgraph;

[0151] The number of steps required for the first subgraph to move horizontally to the right to the boundary of the coupling graph is: width-second target value-1, width is the number of columns of the octagonal structure arranged on the quantum chip in the layout information, and the second target value is the maximum value of the column position of the octagonal structure to which the node belongs in the position coordinates of each node of the first subgraph;

[0152] The number of steps required for the first subgraph to move vertically upward to the boundary of the coupling graph is: height-third target value-1, where height is the number of rows of the octagonal structure arranged on the quantum chip in the layout information, and the third target value is the maximum value of the row position of the octagonal structure to which the node belongs in the position coordinates of each node of the first subgraph;

[0153] The number of steps required for the first subgraph to move vertically downward to the boundary of the coupling graph is: a fourth target value, and the fourth target value is the minimum value of the row position of the octagonal structure to which the node belongs in the position coordinates of each node of the first subgraph.

[0154] In this way, the octagonal array structure of the coupling graph can be used to determine the number of steps required for translating the first subgraph to the boundary of the coupling graph.

[0155] Optionally, before step S102, the method further includes:

[0156] Determining an r-order neighborhood of the generated set, where r is the radius of the interaction graph;

[0157] The r-order neighborhood is determined as a reduced search space of the coupling graph.

[0158] Among them, the k-order neighborhood of a node subset S of graph P is defined as the set of all nodes whose distance from S does not exceed k, denoted as If all nodes of the subgraph G′ of graph P are in the neighborhood, In addition, Indicates that G′ is a subgraph of P.

[0159] Among them, the node subset S is the generated set, and the radius r of the interaction graph can be used as the limit of the neighborhood range. In this way, the determination of the reduced search space can be achieved and the complexity of the subgraph search can be reduced.

[0160] Since there may be more than one center of the interaction graph, optionally, the radius of the interaction graph is determined by:

[0161] Taking the node located in the central area of ​​the interaction graph as the target node, obtaining the maximum step length from the node in the interaction graph to the target node, and obtaining the target step length corresponding to the target node;

[0162] The step length with the shortest distance among the target step lengths corresponding to the target nodes in the central area is determined as the radius of the interaction graph.

[0163] In this way, determination of the radius of the interaction graph may be achieved.

[0164] The specific process of using the symmetry of the octagonal array structure to perform efficient subgraph matching based on node index is as follows:

[0165] Input: pattern graph G (i.e., the interaction graph of the first logic quantum circuit), coupling graph P of the octagonal array structure, node index index;

[0166] Output: All subgraphs in the coupled graph P that are isomorphic to G.

[0167] Step 1: locate an octagonal structure at the center of the coupling graph P of the octagonal array structure, and define the set of corresponding nodes as the generating set S of the coupling graph P;

[0168] Step 2: Calculate the radius r of the pattern graph G using a related algorithm (such as the algorithm built into the Python toolkit NetworkX).

[0169] Step 3: Calculate the r-order neighborhood of the generating set S As a reduced search space for subsequent subgraph matching;

[0170] Step 4: Find a subgraph isomorphic to the pattern graph G in the reduced search space Get a set of isomorphic subgraphs (i.e. the first subgraph);

[0171] Step 5: Initialize an empty list R;

[0172] Step 6: Traverse all node coordinates saved by index and determine the number of rows, height and columns, width of the coupling graph P;

[0173] Step 7: Reverse the key-value pairs of the dictionary index to obtain the dictionary index_reverse (i.e., the mapping from node numbers to node position coordinates);

[0174] Step 8: For G'∈R reduced To loop:

[0175] Step 8.1: Retrieve the coordinates of all nodes of G′ in the dictionary index_reverse and add them to the list coord_list;

[0176] Step 8.2: Calculate the number of steps required for G′ to move horizontally to the left to the boundary with P, n left= min{j:(i,j,k)∈coord_list}; Calculate the number of steps required for G′ to move horizontally to the right to the boundary with P, n right =width-max{j:(i,j,k)∈coord_list}-1; Calculate the number of steps required for G′ to move vertically upward to the boundary with P, recorded as m up = height-max{i:(i,j,k)∈coord_list}-1; Calculate the number of steps required for G′ to move vertically downward to the boundary with P, recorded as m down =min{i:(i,j,k)∈coord_list}; for n∈{-n left ,-n left +1,...,n right} for a loop: for m∈{-m up ,-m up +1,...,m down} for loop:

[0177] Step 8.3: Copy the graph G′ to G”; increase the node numbers of G” by 8n (i.e., shift right by n steps in the octagonal array graph); increase the node numbers of G” by -8m×width steps (i.e., shift downward by m steps in the octagonal array graph); add the shifted graph G” to R;

[0178] Step 9: Return a list R of isomorphic subgraphs as output.

[0179] It should be noted that in the above process, for example, when using Python to implement the algorithm, NumPy's vector operations can be used to accelerate the translation operations repeatedly performed in the nested loops. Specifically, all feasible translations (each translation is represented by a binary array) can be saved to a NumPy array moves (i.e., a two-dimensional array), and moves is added to the coordinates of each node position of the isomorphic subgraph G found in the reduced search space, thereby obtaining all translated isomorphic subgraphs.

[0180] Optionally, the step S101 further includes:

[0181] Selecting a local area in the area range of the quantum chip, wherein the number of physical quantum bits deployed in the local area is greater than or equal to the number of logical quantum bits of the second logical quantum circuit;

[0182] The second logic quantum circuit is precompiled onto the local region to obtain an interaction graph of the first logic quantum circuit.

[0183] In this embodiment, a local area of ​​the quantum chip can be selected to precompile the second logic quantum circuit, in which the physical quantum bits are connected to each other and can be any area, and the number of physical quantum bits deployed in the local area is greater than or equal to the number of logical quantum bits of the second logic quantum circuit. The second logic quantum circuit is a precompiled input circuit and is transformed into the first logic quantum circuit after precompilation.

[0184] A quantum circuit compiler can be used to precompile the input second logic quantum circuit to the selected local area to obtain the precompiled first logic quantum circuit and a mapping scheme from the first logic quantum circuit to the quantum chip.

[0185] For the original logic quantum circuit, that is, the second logic quantum circuit, after pre-compilation, it can be equivalently converted into the first logic quantum circuit. The running effect of the first logic quantum circuit on the quantum chip is consistent with the execution effect of the second logic quantum circuit. Therefore, through secondary mapping, the mapping of the original logic quantum circuit on the quantum chip can be realized.

[0186] In this implementation, by selecting a local area of ​​the quantum chip to precompile the second logic quantum circuit, the execution efficiency of the precompile can be improved, thereby further improving the mapping efficiency of the quantum circuit.

[0187] Optionally, the step S104 specifically includes:

[0188] Obtain a second mapping scheme from the first logic quantum circuit to the quantum chip, and obtain a third mapping scheme corresponding to each subgraph in the subgraph set, respectively, wherein the third mapping scheme is a mapping scheme from the interaction graph to the quantum chip;

[0189] The second mapping scheme is associated with each of the third mapping schemes to obtain a subgraph set for each subgraph. Figure 1 A corresponding first mapping scheme.

[0190] In this implementation, by associating the mapping schemes of the two mappings, all feasible quantum circuit mapping schemes from the first logic quantum circuit to the quantum chip can be obtained, thereby achieving determination of feasible quantum circuit mapping schemes.

[0191] The specific process of quantum circuit mapping is as follows:

[0192] Input: the second logic quantum circuit C, the coupling diagram P of the octagonal array structure of the quantum processor;

[0193] Output: Optimal mapping of quantum circuits

[0194] Step 1: Select a local area of ​​the quantum processor with an octagonal array structure;

[0195] Step 2: Use the quantum circuit compiler to precompile the input second logic quantum circuit C to the local area of ​​the selected quantum processor. The precompiled first logic quantum circuit is denoted as C′, and the quantum circuit mapping given by the precompilation is denoted as F pre ;

[0196] Step 3: Calculate the interaction graph G of the pre-compiled first logic quantum circuit C′;

[0197] Step 4: Use the symmetry of the octagonal array structure of the coupling graph to perform subgraph matching to search for all subgraphs in the coupling graph P of the quantum processor that are isomorphic to the interaction graph G. Each subgraph G j Corresponding to a mapping from G to P, denoted by F j ;

[0198] Step 5: Map the precompiled quantum circuit and the mapping F from G to P j To associate, All feasible first mapping schemes from the first logic quantum circuit to the quantum chip are obtained, where A connection symbol for two maps.

[0199] Step 6: Map all quantum circuits based on the fidelity of the physical quantum gates on the quantum chip Conduct ratings;

[0200] Step 7: Output the optimal mapping of the quantum circuit with the highest score

[0201] The computational time complexity of the quantum chip mapping of this embodiment increases linearly with the number of quantum bits in the quantum chip. Compared with the computational time complexity of the quantum chip mapping in the related art, which increases exponentially or at least polynomially with the number of quantum bits in the quantum chip, its operating efficiency is significantly improved.

[0202] Optionally, the step S105 specifically includes:

[0203] Based on the fidelity of the physical quantum gate on the quantum chip, obtaining the target fidelity of mapping the first logical quantum circuit to the physical quantum circuit on the quantum chip under each first mapping scheme;

[0204] A mapping scheme corresponding to a physical quantum circuit with the largest target fidelity is selected from the first mapping schemes corresponding to the subgraph set to obtain the target mapping scheme.

[0205] In this implementation, by selecting the mapping scheme corresponding to the physical quantum circuit with the highest target fidelity from the first mapping scheme corresponding to the subgraph set, the symmetry of the octagonal array structure can be used to efficiently search for feasible mappings of the quantum circuit, and the optimality of the quantum circuit mapping is guaranteed, thereby improving the fidelity of the quantum circuit.

[0206] In an optional implementation, the fidelity of each physical quantum gate under the first mapping scheme may be superimposed to obtain the fidelity of the quantum circuit.

[0207] Optionally, obtaining a target fidelity of mapping the first logical quantum circuit to a physical quantum circuit on the quantum chip under each first mapping scheme based on the fidelity of the physical quantum gate on the quantum chip includes:

[0208] Based on the fidelity of the physical quantum gate on the quantum chip, obtaining the fidelity of the physical quantum gate of the logical quantum gate in the first logical quantum circuit under each first mapping scheme;

[0209] For each first mapping scheme, the fidelity of each physical quantum gate corresponding to the first logical quantum circuit under the first mapping scheme is multiplied to obtain a target fidelity of the physical quantum circuit under the first mapping scheme.

[0210] In this implementation, by multiplying the fidelity of each physical quantum gate under the first mapping scheme, the target fidelity of the physical quantum circuit under the first mapping scheme is obtained, which can improve the fidelity accuracy and calculation speed of the quantum circuit.

[0211] Optionally, for each logical quantum gate, a mapping relationship of the logical quantum gate to a physical quantum gate under each first mapping scheme and the fidelity of the physical quantum gate are both stored and calculated in a vector form;

[0212] The step of multiplying the fidelity of each physical quantum gate corresponding to the first logical quantum circuit under the first mapping scheme for each first mapping scheme to obtain a target fidelity of the physical quantum circuit under the first mapping scheme includes:

[0213] The first vectors corresponding to the logic quantum gates in the first logic quantum circuit are multiplied by corresponding elements at the same position to obtain a target vector, wherein the target vector includes the target fidelity of the physical quantum circuit under each of the first mapping schemes, and the first vector is a vector of the fidelity of the physical quantum gate of the logic quantum gate under each of the first mapping schemes.

[0214] After finding a set of feasible quantum circuit mappings, it is necessary to evaluate these mappings and select the circuit mapping that maximizes the quantum circuit fidelity (minimizes the error rate). In this embodiment, a scheme for efficiently estimating the quantum circuit fidelity is proposed, which is based on vectorized acceleration and can simultaneously calculate the quantum circuit fidelity corresponding to a large number of quantum circuit mappings. Among them, vectors are represented by bold symbols. The specific process is as follows:

[0215] Input: the first logical quantum circuit, a set of quantum circuit mappings L to be scored, and a mapping V from quantum gates to fidelity;

[0216] Output: The first logical quantum circuit is mapped to the quantum circuit fidelity estimate S of the quantum chip.

[0217] Step 1: Convert the first logical quantum circuit into a quantum gate sequence (i.e., a list of quantum operation instructions) C list ;

[0218] Step 2: The logical quantum gate g in the first logical quantum circuit j ∈C list To loop:

[0219] Step 2.1: Retrieve the logical quantum gate g j The corresponding physical quantum gate g under the mapping of all first mapping schemes i =L(g j ), where g i is a vector containing multiple quantum gate indices;

[0220] Step 2.2: Retrieve the fidelity F corresponding to the physical quantum gate j =V(g i );

[0221] Step 3: Calculate the quantum circuit fidelity S = ∏ corresponding to the quantum circuit mapping j F j ,∏ j F j is the vector F j The product of corresponding elements in the same position;

[0222] Step 4: Return the calculated quantum circuit fidelity S.

[0223] In this way, the fidelity of the quantum circuit can be efficiently estimated, thereby efficiently determining the optimal mapping scheme for the quantum circuit.

[0224] The quantum circuit mapping method of this embodiment is described in detail with a specific example as follows.

[0225] You can enter Figure 4The logical quantum circuit shown in Figure 1, each horizontal line represents a quantum bit, denoted by (i∈{0,1,...,7}), the symbol on the horizontal line represents a quantum gate (i.e., logical operation), the symbol on the right end of the horizontal line represents the measurement of the quantum bit, and the quantum gate across multiple lines represents a two-qubit gate.

[0226] This quantum circuit can be precompiled using related modules such as Qiskit. It can be seen that the interaction diagram of this quantum circuit can be directly adapted to the coupling diagram of the quantum chip. Therefore, the precompilation process does not change the connectivity of the logical qubits in the quantum circuit.

[0227] like Figure 5 As shown, the interaction graph of the input quantum circuit is an octagonal structure graph, in which each quantum bit in the input quantum circuit corresponds to a node in the graph, and each two-qubit gate in the quantum circuit corresponds to an edge between nodes in the graph.

[0228] By calculating the graph radius r=4 of the interaction graph, the 4th-order neighborhood of the coupling graph generation set of the quantum processor can be defined as the reduced search space, and the generation set includes all nodes in an octagonal structure at the center of the coupling graph. Figure 6 This is a schematic diagram of the coupling diagram of an example quantum chip. Figure 6 As shown, each circular mark represents a node, that is, a physical quantum bit, and the edges between nodes represent the coupling connection between quantum bits. The nodes in the box 601 are a generation set of the coupling graph of the quantum chip, and the 4th-order neighborhood of the generation set is represented by the large circle 602. The subgraph formed by the nodes in the large circle 602 is defined as the reduced search space.

[0229] Figure 6 Each node of the octagonal structure represents a quantum bit, denoted by q i P (i is a natural number), each edge connecting the nodes represents a coupler between quantum bits, which provides hardware support for two-qubit gate operations.

[0230] In the reduced search space, we search for a subgraph that is isomorphic to the above interaction graph, i.e., an octagonal structure graph (i.e., an 8-node ring graph). There are 144 subgraph isomorphic mappings from the interaction graph to the reduced search space. For example, the following mapping. In which, the superscript L represents a logical bit, the superscript P represents a physical bit, and the subscript represents the number of the quantum bit, see Figure 4 and Figure 6 Number.

[0231]

[0232]

[0233]

[0234] For each isomorphic subgraph in the reduced search space, perform a horizontal and vertical translation until it intersects with the boundary of the quantum processor coupling graph. In particular, consider the case where each row and column of the quantum processor coupling graph contains 70 octagons, and the processor contains 8×70 2 = 39200 qubits. Through translation, 154576 subgraphs that are isomorphic to the quantum circuit interaction graph can be found in the coupling graph.

[0235] In order to test the efficiency of the subgraph matching, numerical experiments were performed on a MacBook Pro 2020 (subsequent experiments were also based on this computing platform). Experiments show that by using the subgraph matching of this embodiment, the search for all isomorphic subgraphs can be completed within 2 seconds. In comparison, the VF2 algorithm can be used to solve the problem, which takes 97 seconds, while VF2++ takes 95 seconds. In other words, the scheme in this embodiment, by utilizing the symmetry of the octagonal array structure, reduces the solution time of the subgraph matching problem (the core problem of secondary circuit mapping) by 97.9% compared to related schemes.

[0236] The isomorphic subgraphs searched during each subgraph matching process correspond to a feasible quantum circuit mapping. All these feasible circuit mappings need to be evaluated, and the mapping that maximizes the quantum circuit fidelity is selected as the output. To this end, a heuristic quantum circuit fidelity estimation function is used. This function multiplies the fidelity of all quantum gates in the quantum circuit as an estimate of the quantum circuit fidelity.

[0237] For example, suppose the quantum circuit mapping M is Figure 4 The 24 quantum gates contained in the quantum circuit Mapping to actual quantum gates on a quantum processor Further, suppose the fidelity of these actual quantum gates is F i P (i=1, 2, ..., 24) The quantum circuit mapping M is scored as follows according to the following formula (1).

[0238]

[0239] Using the vectorized accelerated circuit mapping scoring function, all searched quantum circuit mappings {M j}Perform this evaluation process to obtain the fidelity of all circuit mappings and store them in the form of a binary array S = {(M j ,Score(M j ))}.

[0240] We can traverse all quantum circuit mappings in S and search for the mapping M with the highest score (i.e., the highest fidelity) opt :=argmax j Score(M j ) and returns it as the target mapping scheme.

[0241] In order to demonstrate the scalability of the quantum circuit mapping scheme of this embodiment, this scheme can be used to Figure 4 The quantum circuit in is mapped onto a quantum chip with an octagonal array structure of l rows and l columns. In this process, the running time required for subgraph matching and complete circuit mapping proposed in this embodiment is tested respectively, and compared with related solutions.

[0242] Figure 4 The interaction graph of the quantum circuit in is an 8-node ring graph. Therefore, in the subgraph matching step, it is necessary to search for all isomorphic mappings from the 8-node ring graph to the quantum hardware coupling graph. The efficient subgraph matching scheme using the symmetry of the octagonal array structure, the VF2 scheme, and the VF2++ scheme of this embodiment are used to complete this task. The corresponding running times are shown in Figure 7 .

[0243] Figure 7 The horizontal axis in the middle represents the number of quantum bits in the quantum chip N = 8l 2 The vertical axis represents the time required to complete the subgraph isomorphic mapping search. The three curves, namely curve 701, curve 702 and curve 703, respectively represent the running time of the efficient subgraph matching scheme using the symmetry of the octagonal array structure, the VF2 scheme and the VF2++ scheme of this embodiment.

[0244] As the number of quantum bits in the quantum chip increases, the time required for the VF2 algorithm and the VF2++ algorithm to complete the subgraph matching task increases significantly, while the running time of the subgraph matching algorithm of this embodiment remains almost unchanged. In other words, when the number of bits in the quantum chip increases, the subgraph matching algorithm of this embodiment runs significantly faster than the traditional subgraph matching algorithms VF2 and VF2++. This shows that the subgraph matching algorithm of this embodiment has good scalability.

[0245] Considering the running time required for the complete circuit mapping scheme in this embodiment, the numerical experimental test is conducted for quantum chips of different sizes to find Figure 4 The running time required for the optimal mapping of the input quantum circuit shown. The quantum chip is set to an octagonal array structure with l rows and l columns, which is the same as the previous two numerical experiments. The experimental results are shown in Figure 8 .

[0246] Figure 8The horizontal axis in the middle represents the number of quantum bits in the quantum chip N = 8l 2 , the vertical axis represents the running time of the quantum circuit mapping scheme, and the two curves in the figure, namely curve 801 and curve 802, respectively represent the efficient circuit mapping scheme of this embodiment and other mapping schemes.

[0247] Figure 8 It shows that the time required for the quantum circuit mapping scheme of this embodiment to determine the optimal circuit mapping from a given quantum circuit to a quantum chip is significantly lower than that of other schemes. As the number of quantum bits in the quantum chip increases, the running time of other schemes increases significantly, while the running time of this scheme remains almost unchanged. This shows that the quantum circuit mapping scheme of this embodiment has a significant advantage in computational complexity compared to related schemes, and is particularly suitable for quantum circuit mapping of large-scale quantum chips.

[0248] Second embodiment

[0249] like Fig. 9 As shown, the present disclosure provides a quantum circuit mapping device 900, comprising:

[0250] An acquisition module 901 is used to acquire a coupling graph of the quantum chip and a node index of the coupling graph based on the arrangement structure information of the quantum bits on the quantum chip; and to acquire an interaction graph of a first logic quantum circuit precompiled onto the quantum chip; the arrangement structure information indicates that the quantum bits on the quantum chip are arranged in an octagonal array structure, and the node index indicates a mapping relationship between the node position coordinates of the quantum bits and the node labels;

[0251] A search module 902, configured to search a first subgraph isomorphic to the interaction graph in a reduced search space of the coupling graph, the reduced search space comprising a set of nodes in the coupling graph whose distances from a generated set do not exceed a specified distance, the specified distance being greater than or equal to a radius of the interaction graph, and the generated set covering the coupling graph under a matching translation operation;

[0252] A translation operation module 903 is used to perform a translation operation on the first subgraph on the coupling graph that matches the generated set based on the node index and utilize the octagonal array structure of the coupling graph to obtain a second subgraph that is isomorphic to the interaction graph;

[0253] The first determining module 904 is used to determine each subgraph in the subgraph set. Figure 1 a corresponding first mapping scheme, wherein the first mapping scheme is a mapping scheme from the first logic quantum circuit to the quantum chip, and the subgraph set includes the first subgraph and the second subgraph;

[0254] The second determination module 905 is used to determine a target mapping scheme from the first logical quantum circuit to the quantum chip from the first mapping scheme corresponding to the subgraph set based on the fidelity of the physical quantum gate on the quantum chip.

[0255] Optionally, the acquisition module 901 is specifically used to:

[0256] Creating a node for each quantum bit on the quantum chip to construct a coupling graph of the quantum chip;

[0257] Determining the node position coordinates of the quantum bits on the quantum chip based on the relative positions of the nodes corresponding to the quantum bits in the octagonal structure and the layout information of the octagonal structure arranged on the quantum chip, wherein the arrangement structure information includes the relative positions and layout information;

[0258] Determining the node number of the quantum bit on the quantum chip based on the node position coordinates;

[0259] A mapping relationship between the node position coordinates of the quantum bit and the node label is established to obtain the node index of the coupling graph.

[0260] Optionally, the node position coordinates include a first parameter, a second parameter, and a third parameter, the first parameter indicates a row position of an octagonal structure to which a quantum bit corresponding node belongs, the second parameter indicates a column position of an octagonal structure to which a quantum bit corresponding node belongs, the third parameter indicates a relative position of a quantum bit corresponding node in the octagonal structure, the row position is less than or equal to the number of rows of the octagonal structure arranged on the quantum chip, the column position is less than or equal to the number of columns of the octagonal structure arranged on the quantum chip, and the layout information includes the number of rows and the number of columns;

[0261] The node number is calculated by the following formula:

[0262] node_index=(i×width+j)×8+k;

[0263] Among them, node_index is the node index, i is the first parameter, j is the second parameter, k is the third parameter, and width is the number of columns.

[0264] Optionally, the generated set includes any of the following:

[0265] 8 nodes in any octagonal structure arranged in the coupling graph;

[0266] Six consecutive nodes in any octagonal structure arranged in the coupling graph.

[0267] Optionally, in the case where the spanning set includes eight nodes in any octagonal structure arranged in the coupling graph, the translation operation matching the spanning set includes: translation in a horizontal direction and a vertical direction;

[0268] In the case where the generation set includes 6 consecutive nodes in any octagonal structure arranged in the coupling graph, the translation operation matching the generation set includes: translation along the horizontal direction, vertical direction and target diagonal direction, and the target diagonal direction is the vertical direction of the line connecting the other two nodes in the octagonal structure to which the generation set belongs except the 6 consecutive nodes.

[0269] Optionally, the translation operation module 903 includes:

[0270] A retrieval unit, configured to retrieve the node position coordinates of the first subgraph from the node index based on the node labels of the first subgraph;

[0271] A first determining unit is used to determine the number of steps required for the first subgraph to be translated to the boundary of the coupling graph in units of octagonal structures according to the translation direction matched by the generation set based on the layout information of the octagonal structure in the coupling graph and the node position coordinates of the first subgraph;

[0272] A construction unit, configured to construct an update range of the node position coordinates of the first subgraph during the movement of the coupling graph based on the number of steps required for the first subgraph to be translated to the boundary of the coupling graph;

[0273] An updating unit is used to update the node labels of the first subgraph within the update range based on the layout information of the octagonal structure in the coupling graph to obtain a second subgraph isomorphic to the interaction graph.

[0274] Optionally, when the generated set includes 8 nodes in any octagonal structure arranged in the coupling graph, the translation direction matched by the generated set includes horizontal and vertical directions, and the updating unit is specifically configured to:

[0275] Increase the node numbers of the first subgraph by 8n; and increase the node numbers of the first subgraph by -8m×width to obtain the node numbers of the second subgraph;

[0276] Among them, n is a translation to the right of n steps in the coupling diagram, m is a translation downward of m steps in the coupling diagram, n and m are both within the update range, and width is the number of columns of the octagonal structure arranged on the quantum chip in the layout information.

[0277] Optionally, the number of steps required for the first subgraph to move horizontally to the left to the boundary of the coupling graph is: a first target value, the first target value being the minimum value of the column position of the octagonal structure to which the node belongs in the position coordinates of each node of the first subgraph;

[0278] The number of steps required for the first subgraph to move horizontally to the right to the boundary of the coupling graph is: width-second target value-1, width is the number of columns of the octagonal structure arranged on the quantum chip in the layout information, and the second target value is the maximum value of the column position of the octagonal structure to which the node belongs in the position coordinates of each node of the first subgraph;

[0279] The number of steps required for the first subgraph to move vertically upward to the boundary of the coupling graph is: height-third target value-1, where height is the number of rows of the octagonal structure arranged on the quantum chip in the layout information, and the third target value is the maximum value of the row position of the octagonal structure to which the node belongs in the position coordinates of each node of the first subgraph;

[0280] The number of steps required for the first subgraph to move vertically downward to the boundary of the coupling graph is: a fourth target value, and the fourth target value is the minimum value of the row position of the octagonal structure to which the node belongs in the position coordinates of each node of the first subgraph.

[0281] Optionally, the device further comprises:

[0282] A third determination module is used to determine the r-order neighborhood of the generated set, where r is the radius of the interaction graph;

[0283] The fourth determination module is used to determine the r-order neighborhood as the reduced search space of the coupling graph.

[0284] Optionally, the radius of the interaction graph is determined by:

[0285] Taking the node located in the central area of ​​the interaction graph as the target node, obtaining the maximum step length from the node in the interaction graph to the target node, and obtaining the target step length corresponding to the target node;

[0286] The step length with the shortest distance among the target step lengths corresponding to the target nodes in the central area is determined as the radius of the interaction graph.

[0287] Optionally, the first determining module 904 is specifically configured to:

[0288] Obtain a second mapping scheme from the first logic quantum circuit to the quantum chip, and obtain a third mapping scheme corresponding to each subgraph in the subgraph set, respectively, wherein the third mapping scheme is a mapping scheme from the interaction graph to the quantum chip;

[0289] The second mapping scheme is associated with each of the third mapping schemes to obtain a subgraph set for each subgraph. Figure 1 A corresponding first mapping scheme.

[0290] Optionally, the second determining module 905 includes:

[0291] A fidelity acquisition unit, configured to acquire, based on the fidelity of the physical quantum gate on the quantum chip, a target fidelity of mapping the first logical quantum circuit to the physical quantum circuit on the quantum chip under each first mapping scheme;

[0292] A selection unit is used to select a mapping scheme corresponding to a physical quantum circuit with the largest target fidelity from the first mapping schemes corresponding to the subgraph set to obtain the target mapping scheme.

[0293] Optionally, the fidelity acquisition unit is specifically used to:

[0294] Based on the fidelity of the physical quantum gate on the quantum chip, obtaining the fidelity of the physical quantum gate of the logical quantum gate in the first logical quantum circuit under each first mapping scheme;

[0295] For each first mapping scheme, the fidelity of each physical quantum gate corresponding to the first logical quantum circuit under the first mapping scheme is multiplied to obtain a target fidelity of the physical quantum circuit under the first mapping scheme.

[0296] Optionally, for each logical quantum gate, the mapping relationship of the logical quantum gate to the physical quantum gate under each first mapping scheme and the fidelity of the physical quantum gate are stored and calculated in vector form; the fidelity acquisition unit is specifically used to:

[0297] The first vectors corresponding to the logic quantum gates in the first logic quantum circuit are multiplied by corresponding elements at the same position to obtain a target vector, wherein the target vector includes the target fidelity of the physical quantum circuit under each of the first mapping schemes, and the first vector is a vector of the fidelity of the physical quantum gate of the logic quantum gate under each of the first mapping schemes.

[0298] Optionally, the acquisition module 901 is further used to:

[0299] Selecting a local area in the area range of the quantum chip, wherein the number of physical quantum bits deployed in the local area is greater than or equal to the number of logical quantum bits of the second logical quantum circuit;

[0300] The second logic quantum circuit is precompiled onto the local region to obtain an interaction graph of the first logic quantum circuit.

[0301] The quantum circuit mapping device 900 provided in the present disclosure can implement each process implemented by the quantum circuit mapping method embodiment and can achieve the same beneficial effects. To avoid repetition, it will not be described here.

[0302] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0303] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.

[0304] Fig.10 A schematic block diagram of an example electronic device that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0305] like Fig.10 As shown, the device 1000 includes a computing unit 1001, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 1002 or a computer program loaded from a storage unit 1008 into a random access memory (RAM) 1003. In the RAM 1003, various programs and data required for the operation of the device 1000 can also be stored. The computing unit 1001, the ROM 1002, and the RAM 1003 are connected to each other via a bus 1004. An input / output (I / O) interface 1005 is also connected to the bus 1004.

[0306] A number of components in the device 1000 are connected to the I / O interface 1005, including: an input unit 1006, such as a keyboard, a mouse, etc.; an output unit 1007, such as various types of displays, speakers, etc.; a storage unit 1008, such as a disk, an optical disk, etc.; and a communication unit 1009, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 1009 allows the device 1000 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0307] The computing unit 1001 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 1001 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 1001 performs the various methods and processes described above, such as the quantum circuit mapping method. For example, in some embodiments, the quantum circuit mapping method may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 1008. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 1000 via the ROM 1002 and / or the communication unit 1009. When the computer program is loaded into the RAM 1003 and executed by the computing unit 1001, one or more steps of the quantum circuit mapping method described above may be performed. Alternatively, in other embodiments, the computing unit 1001 may be configured to execute the quantum circuit mapping method in any other appropriate manner (for example, by means of firmware).

[0308] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0309] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0310] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0311] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0312] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0313] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0314] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0315] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A quantum circuit mapping method, comprising: Based on the arrangement structure information of the quantum bits on the quantum chip, obtaining a coupling graph of the quantum chip and a node index of the coupling graph; and obtaining an interaction graph of a first logic quantum circuit precompiled onto the quantum chip; the arrangement structure information indicates that the quantum bits on the quantum chip are arranged in an octagonal array structure, and the node index indicates a mapping relationship between the node position coordinates of the quantum bit and the node label; searching for a first subgraph isomorphic to the interaction graph in a reduced search space of the coupling graph, the reduced search space comprising a set of nodes in the coupling graph whose distances to a spanning set do not exceed a specified distance, the specified distance being greater than or equal to a radius of the interaction graph, and the spanning set covering the coupling graph under a matching translation operation; Based on the node index, using the octagonal array structure of the coupling graph, a translation operation matching the spanning set is performed on the first subgraph on the coupling graph to obtain a second subgraph isomorphic to the interaction graph; Determine a first mapping scheme that corresponds one-to-one to each subgraph in a subgraph set, where the first mapping scheme is a mapping scheme from the first logic quantum circuit to the quantum chip, and the subgraph set includes the first subgraph and the second subgraph; Based on the fidelity of the physical quantum gate on the quantum chip, determine a target mapping scheme from the first logical quantum circuit to the quantum chip from the first mapping scheme corresponding to the subgraph set; The generated set includes any of the following: 8 nodes in any octagonal structure arranged in the coupling graph; Six consecutive nodes in any octagonal structure arranged in the coupling graph.

2. The method according to claim 1, wherein: The step of obtaining a coupling graph of the quantum chip and a node index of the coupling graph based on the arrangement structure information of quantum bits on the quantum chip includes: Creating a node for each quantum bit on the quantum chip to construct a coupling graph of the quantum chip; Determining the node position coordinates of the quantum bits on the quantum chip based on the relative positions of the nodes corresponding to the quantum bits in the octagonal structure and the layout information of the octagonal structure arranged on the quantum chip, wherein the arrangement structure information includes the relative positions and layout information; Determining the node number of the quantum bit on the quantum chip based on the node position coordinates; A mapping relationship between the node position coordinates of the quantum bit and the node label is established to obtain the node index of the coupling graph.

3. The method according to claim 2, wherein: The node position coordinates include a first parameter, a second parameter, and a third parameter, wherein the first parameter indicates a row position of an octagonal structure to which a quantum bit corresponding node belongs, the second parameter indicates a column position of an octagonal structure to which a quantum bit corresponding node belongs, and the third parameter indicates a relative position of a quantum bit corresponding node in the octagonal structure, wherein the row position is less than or equal to the number of rows of the octagonal structure arranged on the quantum chip, the column position is less than or equal to the number of columns of the octagonal structure arranged on the quantum chip, and the layout information includes the number of rows and the number of columns; The node number is calculated by the following formula: node_index=(i×width+j)×8+k; Among them, node_index is the node index, i is the first parameter, j is the second parameter, k is the third parameter, and width is the number of columns.

4. The method according to claim 1, wherein: In the case where the spanning set includes eight nodes in any octagonal structure arranged in the coupling graph, the translation operation matching the spanning set includes: translation in the horizontal direction and the vertical direction; In the case where the generation set includes 6 consecutive nodes in any octagonal structure arranged in the coupling graph, the translation operation matching the generation set includes: translation along the horizontal direction, vertical direction and target diagonal direction, and the target diagonal direction is the vertical direction of the line connecting the other two nodes in the octagonal structure to which the generation set belongs except the 6 consecutive nodes.

5. The method according to claim 1, wherein: The method of performing a translation operation on the first subgraph on the coupling graph that matches the spanning set based on the node index and utilizing the octagonal array structure of the coupling graph to obtain a second subgraph that is isomorphic to the interaction graph includes: Based on the node labels of the first subgraph, retrieve the node position coordinates of the first subgraph in the node index; Based on the layout information of the octagonal structure in the coupling graph and the node position coordinates of the first subgraph, determining the number of steps required for the first subgraph to be translated to the boundary of the coupling graph in units of octagonal structures according to the translation direction matched by the generation set; Based on the number of steps required for translating the first subgraph to the boundary of the coupling graph, constructing an update range of the node position coordinates of the first subgraph during the movement on the coupling graph; Based on the layout information of the octagonal structure in the coupling graph, the node labels of the first subgraph are updated within the update range to obtain a second subgraph isomorphic to the interaction graph.

6. The method according to claim 5, wherein: In the case where the spanning set includes eight nodes in any octagonal structure arranged in the coupling graph, the translation direction matched by the spanning set includes horizontal and vertical directions, and the node labels of the first subgraph are updated within the update range based on the layout information of the octagonal structure in the coupling graph to obtain a second subgraph isomorphic to the interaction graph, including: Increase the node numbers of the first subgraph by 8n; and increase the node numbers of the first subgraph by -8m×width to obtain the node numbers of the second subgraph; Among them, n is a translation to the right of n steps in the coupling diagram, m is a translation downward of m steps in the coupling diagram, n and m are both within the update range, and width is the number of columns of the octagonal structure arranged on the quantum chip in the layout information.

7. The method according to claim 6, wherein: The number of steps required for the first subgraph to move horizontally to the left to the boundary of the coupling graph is: a first target value, where the first target value is the minimum value of the column position of the octagonal structure to which the node belongs in the position coordinates of each node of the first subgraph; The number of steps required for the first subgraph to move horizontally to the right to the boundary of the coupling graph is: width-second target value-1, width is the number of columns of the octagonal structure arranged on the quantum chip in the layout information, and the second target value is the maximum value of the column position of the octagonal structure to which the node belongs in the position coordinates of each node of the first subgraph; The number of steps required for the first subgraph to move vertically upward to the boundary of the coupling graph is: height-third target value-1, where height is the number of rows of the octagonal structure arranged on the quantum chip in the layout information, and the third target value is the maximum value of the row position of the octagonal structure to which the node belongs in the position coordinates of each node of the first subgraph; The number of steps required for the first subgraph to move vertically downward to the boundary of the coupling graph is: a fourth target value, and the fourth target value is the minimum value of the row position of the octagonal structure to which the node belongs in the position coordinates of each node of the first subgraph.

8. The method according to claim 1, before searching the first subgraph isomorphic to the interaction graph in the reduced search space of the coupling graph, further comprising: Determining an r-order neighborhood of the generated set, where r is the radius of the interaction graph; The r-order neighborhood is determined as a reduced search space of the coupling graph.

9. The method according to claim 1, wherein: The radius of the interaction map is determined by: Taking the node located in the central area of ​​the interaction graph as the target node, obtaining the maximum step length from the node in the interaction graph to the target node, and obtaining the target step length corresponding to the target node; The step length with the shortest distance among the target step lengths corresponding to the target nodes in the central area is determined as the radius of the interaction graph.

10. The method according to claim 1, wherein: The determining of a first mapping scheme in which each subgraph in the subgraph set corresponds to each other includes: Obtain a second mapping scheme from the first logic quantum circuit to the quantum chip, and obtain a third mapping scheme corresponding to each subgraph in the subgraph set, respectively, wherein the third mapping scheme is a mapping scheme from the interaction graph to the quantum chip; The second mapping scheme is associated with each of the third mapping schemes to obtain a first mapping scheme corresponding to each subgraph in the subgraph set.

11. The method according to claim 1, wherein: The step of determining a target mapping scheme from the first logical quantum circuit to the quantum chip from a first mapping scheme corresponding to the subgraph set based on the fidelity of the physical quantum gate on the quantum chip comprises: Based on the fidelity of the physical quantum gate on the quantum chip, obtaining the target fidelity of mapping the first logical quantum circuit to the physical quantum circuit on the quantum chip under each first mapping scheme; A mapping scheme corresponding to a physical quantum circuit with the largest target fidelity is selected from the first mapping schemes corresponding to the subgraph set to obtain the target mapping scheme.

12. The method according to claim 11, wherein: The obtaining, based on the fidelity of the physical quantum gate on the quantum chip, a target fidelity of mapping the first logical quantum circuit to the physical quantum circuit on the quantum chip under each first mapping scheme comprises: Based on the fidelity of the physical quantum gate on the quantum chip, obtaining the fidelity of the physical quantum gate of the logical quantum gate in the first logical quantum circuit under each first mapping scheme; For each first mapping scheme, the fidelity of each physical quantum gate corresponding to the first logical quantum circuit under the first mapping scheme is multiplied to obtain a target fidelity of the physical quantum circuit under the first mapping scheme.

13. The method according to claim 12, wherein: For each logical quantum gate, the mapping relationship of the logical quantum gate to the physical quantum gate under each first mapping scheme and the fidelity of the physical quantum gate are stored and calculated in vector form; The step of multiplying the fidelity of each physical quantum gate corresponding to the first logical quantum circuit under the first mapping scheme for each first mapping scheme to obtain a target fidelity of the physical quantum circuit under the first mapping scheme includes: The first vectors corresponding to the logic quantum gates in the first logic quantum circuit are multiplied by corresponding elements at the same position to obtain a target vector, wherein the target vector includes the target fidelity of the physical quantum circuit under each of the first mapping schemes, and the first vector is a vector of the fidelity of the physical quantum gate of the logic quantum gate under each of the first mapping schemes.

14. The method according to claim 1, wherein: The obtaining of the interaction graph of the first logic quantum circuit precompiled onto the quantum chip comprises: Selecting a local area in the area range of the quantum chip, wherein the number of physical quantum bits deployed in the local area is greater than or equal to the number of logical quantum bits of the second logical quantum circuit; The second logic quantum circuit is precompiled onto the local region to obtain an interaction graph of the first logic quantum circuit.

15. A quantum circuit mapping device, comprising: An acquisition module, used to acquire a coupling graph of the quantum chip and a node index of the coupling graph based on the arrangement structure information of the quantum bits on the quantum chip; and obtaining an interaction graph of a first logic quantum circuit precompiled onto the quantum chip; the arrangement structure information indicates that the quantum bits on the quantum chip are arranged in an octagonal array structure, and the node index indicates a mapping relationship between the node position coordinates of the quantum bit and the node label; A search module, configured to search a first subgraph isomorphic to the interaction graph in a reduced search space of the coupling graph, the reduced search space comprising a set of nodes in the coupling graph whose distances from a generated set do not exceed a specified distance, the specified distance being greater than or equal to a radius of the interaction graph, and the generated set covering the coupling graph under a matching translation operation; A translation operation module, configured to perform a translation operation on the first subgraph on the coupling graph that matches the generated set based on the node index and utilize the octagonal array structure of the coupling graph to obtain a second subgraph that is isomorphic to the interaction graph; A first determining module is used to determine a first mapping scheme corresponding one-to-one to each subgraph in a subgraph set, wherein the first mapping scheme is a mapping scheme from the first logic quantum circuit to the quantum chip, and the subgraph set includes the first subgraph and the second subgraph; A second determination module is used to determine a target mapping scheme from the first logic quantum circuit to the quantum chip from the first mapping scheme corresponding to the subgraph set based on the fidelity of the physical quantum gate on the quantum chip; The generated set includes any of the following: 8 nodes in any octagonal structure arranged in the coupling graph; Six consecutive nodes in any octagonal structure arranged in the coupling graph.

16. The device according to claim 15, wherein: The acquisition module is specifically used for: Creating a node for each quantum bit on the quantum chip to construct a coupling graph of the quantum chip; Determining the node position coordinates of the quantum bits on the quantum chip based on the relative positions of the nodes corresponding to the quantum bits in the octagonal structure and the layout information of the octagonal structure arranged on the quantum chip, wherein the arrangement structure information includes the relative positions and layout information; Determining the node number of the quantum bit on the quantum chip based on the node position coordinates; A mapping relationship between the node position coordinates of the quantum bit and the node label is established to obtain the node index of the coupling graph.

17. The device according to claim 16, wherein: The node position coordinates include a first parameter, a second parameter, and a third parameter, wherein the first parameter indicates a row position of an octagonal structure to which a quantum bit corresponding node belongs, the second parameter indicates a column position of an octagonal structure to which a quantum bit corresponding node belongs, and the third parameter indicates a relative position of a quantum bit corresponding node in the octagonal structure, wherein the row position is less than or equal to the number of rows of the octagonal structure arranged on the quantum chip, the column position is less than or equal to the number of columns of the octagonal structure arranged on the quantum chip, and the layout information includes the number of rows and the number of columns; The node number is calculated by the following formula: node_index=(i×width+j)×8+k; Among them, node_index is the node index, i is the first parameter, j is the second parameter, k is the third parameter, and width is the number of columns.

18. The device according to claim 15, wherein: In the case where the spanning set includes eight nodes in any octagonal structure arranged in the coupling graph, the translation operation matching the spanning set includes: translation in the horizontal direction and the vertical direction; In the case where the generation set includes 6 consecutive nodes in any octagonal structure arranged in the coupling graph, the translation operation matching the generation set includes: translation along the horizontal direction, vertical direction and target diagonal direction, and the target diagonal direction is the vertical direction of the line connecting the other two nodes in the octagonal structure to which the generation set belongs except the 6 consecutive nodes.

19. The device according to claim 15, wherein: The translation operation module includes: A retrieval unit, configured to retrieve the node position coordinates of the first subgraph from the node index based on the node labels of the first subgraph; A first determining unit is used to determine the number of steps required for the first subgraph to be translated to the boundary of the coupling graph in units of octagonal structures according to the translation direction matched by the generation set based on the layout information of the octagonal structure in the coupling graph and the node position coordinates of the first subgraph; A construction unit, configured to construct an update range of the node position coordinates of the first subgraph during the movement of the coupling graph based on the number of steps required for the first subgraph to be translated to the boundary of the coupling graph; An updating unit is used to update the node labels of the first subgraph within the update range based on the layout information of the octagonal structure in the coupling graph to obtain a second subgraph isomorphic to the interaction graph.

20. The device according to claim 19, wherein In the case where the generated set includes 8 nodes in any octagonal structure arranged in the coupling graph, the translation direction matched by the generated set includes horizontal and vertical directions, and the updating unit is specifically configured to: Increase the node numbers of the first subgraph by 8n; and increase the node numbers of the first subgraph by -8m×width to obtain the node numbers of the second subgraph; Among them, n is a translation to the right of n steps in the coupling diagram, m is a translation downward of m steps in the coupling diagram, n and m are both within the update range, and width is the number of columns of the octagonal structure arranged on the quantum chip in the layout information.

21. The device according to claim 20, wherein: The number of steps required for the first subgraph to move horizontally to the left to the boundary of the coupling graph is: a first target value, where the first target value is the minimum value of the column position of the octagonal structure to which the node belongs in the position coordinates of each node of the first subgraph; The number of steps required for the first subgraph to move horizontally to the right to the boundary of the coupling graph is: width-second target value-1, width is the number of columns of the octagonal structure arranged on the quantum chip in the layout information, and the second target value is the maximum value of the column position of the octagonal structure to which the node belongs in the position coordinates of each node of the first subgraph; The number of steps required for the first subgraph to move vertically upward to the boundary of the coupling graph is: height-third target value-1, where height is the number of rows of the octagonal structure arranged on the quantum chip in the layout information, and the third target value is the maximum value of the row position of the octagonal structure to which the node belongs in the position coordinates of each node of the first subgraph; The number of steps required for the first subgraph to move vertically downward to the boundary of the coupling graph is: a fourth target value, and the fourth target value is the minimum value of the row position of the octagonal structure to which the node belongs in the position coordinates of each node of the first subgraph.

22. The apparatus according to claim 15, further comprising: A third determination module is used to determine the r-order neighborhood of the generated set, where r is the radius of the interaction graph; The fourth determination module is used to determine the r-order neighborhood as the reduced search space of the coupling graph.

23. The device according to claim 15, wherein: The radius of the interaction map is determined by: Taking the node located in the central area of ​​the interaction graph as the target node, obtaining the maximum step length from the node in the interaction graph to the target node, and obtaining the target step length corresponding to the target node; The step length with the shortest distance among the target step lengths corresponding to the target nodes in the central area is determined as the radius of the interaction graph.

24. The device according to claim 15, wherein: The first determining module is specifically configured to: Obtain a second mapping scheme from the first logic quantum circuit to the quantum chip, and obtain a third mapping scheme corresponding to each subgraph in the subgraph set, respectively, wherein the third mapping scheme is a mapping scheme from the interaction graph to the quantum chip; The second mapping scheme is associated with each of the third mapping schemes to obtain a first mapping scheme corresponding to each subgraph in the subgraph set.

25. The device according to claim 15, wherein: The second determining module comprises: A fidelity acquisition unit, configured to acquire, based on the fidelity of the physical quantum gate on the quantum chip, a target fidelity of mapping the first logical quantum circuit to the physical quantum circuit on the quantum chip under each first mapping scheme; A selection unit is used to select a mapping scheme corresponding to a physical quantum circuit with the largest target fidelity from the first mapping schemes corresponding to the subgraph set to obtain the target mapping scheme.

26. The device according to claim 25, wherein The fidelity acquisition unit is specifically used for: Based on the fidelity of the physical quantum gate on the quantum chip, obtaining the fidelity of the physical quantum gate of the logical quantum gate in the first logical quantum circuit under each first mapping scheme; For each first mapping scheme, the fidelity of each physical quantum gate corresponding to the first logical quantum circuit under the first mapping scheme is multiplied to obtain a target fidelity of the physical quantum circuit under the first mapping scheme.

27. The device according to claim 26, wherein: For each logical quantum gate, the mapping relationship of the logical quantum gate to the physical quantum gate under each first mapping scheme and the fidelity of the physical quantum gate are stored and calculated in vector form; the fidelity acquisition unit is specifically used to: The first vectors corresponding to the logic quantum gates in the first logic quantum circuit are multiplied by corresponding elements at the same position to obtain a target vector, wherein the target vector includes the target fidelity of the physical quantum circuit under each of the first mapping schemes, and the first vector is a vector of the fidelity of the physical quantum gate of the logic quantum gate under each of the first mapping schemes.

28. The device according to claim 15, wherein: The acquisition module is further used for: Selecting a local area in the area range of the quantum chip, wherein the number of physical quantum bits deployed in the local area is greater than or equal to the number of logical quantum bits of the second logical quantum circuit; The second logic quantum circuit is precompiled onto the local region to obtain an interaction graph of the first logic quantum circuit.

29. An electronic device comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 14.

30. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1-14.

31. A computer program product comprising a computer program, which, when executed by a processor, implements the method according to any one of claims 1 to 14.

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