Gate drive circuit

Abstract

A gate drive circuit is provided. The gate drive circuit includes a plurality of output circuits and a noise resistance control circuit. An Nth stage output circuit includes a scan circuit, an output transistor, and a noise resistance circuit. The scan circuit precharges a bias node of the Nth stage output circuit in response to an (N-a)th stage gate drive signal. The output transistor outputs an Nth stage gate drive signal in response to a bias value of the bias node. The noise resistance circuit removes noise at the bias node in response to a low voltage level of the Nth stage gate drive signal. The noise resistance control circuit controls operations of the noise resistance circuits of the plurality of output circuits.

Description

Technical Field

[0001] This invention relates to a gate drive circuit, and more particularly to a gate drive circuit having a low layout area. Background Technology

[0002] Currently, the design of display panels in electronic devices is increasingly trending towards narrow bezels. From a design perspective, reducing the number of components (e.g., transistors) in the gate drive circuit of the display panel and decreasing the distance between components are primary design goals. Generally, reducing the distance between components increases the risk of interference from neighboring components, thus generating noise. Therefore, incorporating noise suppression mechanisms in the gate drive circuit is necessary. However, noise suppression control mechanisms increase the layout area. How to further reduce the layout area of ​​the gate drive circuit with noise suppression circuitry and improve the driving capability of the gate drive circuit in low-temperature environments is one of the key research focuses for those skilled in the art. Summary of the Invention

[0003] This invention provides a gate drive circuit with a low layout area.

[0004] The gate drive circuit of the present invention includes multiple output circuits and a noise suppression control circuit. The multiple output circuits each provide different gate drive signals. The Nth-stage output circuit among the multiple output circuits includes a scanning circuit, an output transistor, and a noise suppression circuit. The scanning circuit responds to the (Na)th-stage gate drive signal to pre-charge the bias node of the Nth-stage output circuit. The output transistor is coupled to the bias node and the output terminal of the Nth-stage output circuit. The output transistor responds to the bias value of the bias node to output the Nth-stage gate drive signal from the output terminal. The noise suppression circuit is coupled to the bias node and the output terminal. The noise suppression circuit responds to the low voltage level of the Nth-stage gate drive signal to remove noise located at the bias node. The noise suppression control circuit is coupled to the multiple noise suppression circuits of the multiple output circuits. The noise suppression control circuit responds to the (Na)th-stage gate drive signal and the (N+b)th-stage gate drive signal to control the multiple noise suppression circuits. a and b are positive integers. N is a positive integer greater than a.

[0005] Based on the above, the noise suppression control circuit of the present invention can serve as the core of noise suppression control for controlling the plurality of noise suppression circuits. The plurality of noise suppression circuits in the gate drive circuit require only a single noise suppression control circuit for control. This results in a low layout area for the gate drive circuit. Furthermore, the noise suppression circuit uses the low voltage level of the Nth-stage gate drive signal to remove noise located at the bias node. This reduces the load on the bias node. The bias value at the bias node can be more easily raised to a high bias value.

[0006] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of the gate drive circuit according to the first embodiment of the present invention.

[0008] Figure 2 This is a schematic diagram of a gate driving circuit according to a second embodiment of the present invention.

[0009] Figure 3 It is based on Figure 2 The diagram shows the noise reduction control circuit.

[0010] Figure 4 This is an operation timing diagram of a gate drive circuit according to an embodiment of the present invention.

[0011] Figure 5 This is a schematic diagram of a gate driving device according to an embodiment of the present invention.

[0012] Explanation of reference numerals in the attached figures

[0013] 110(N)~110(N+3), 210(N)~210(N+7): Output circuit

[0014] 111(N), 111(N+1), 111(N+2), 111(N+3), 211(N), 211(N+1), 211(N+2), 211(N+3): Scanning circuit

[0015] 112(N), 112(N+1), 112(N+2), 112(N+3), 212(N), 212(N+1), 212(N+2), 212(N+3): Noise suppression circuit

[0016] 120, 220, 220-1, 220-2: Noise suppression control circuit

[0017] 20: Gate driving device

[0018] 200-1, 200-2: Gate drive circuit

[0019] 213(N), 213(N+1), 213(N+2), 213(N+3): Reset circuit

[0020] 221: Control Unit

[0021] 222: Discharge control signal generator

[0022] A(N), A(N+1), A(N+2), A(N+3): Bias nodes

[0023] CLK1~CLK4: Frequency signals

[0024] D2U: Negative scan signal

[0025] ECK, EXCK: External frequency

[0026] G(N-4): Gate drive signal of the (N-4)th stage

[0027] G(N-3): Gate drive signal of the (N-3)th stage

[0028] G(N-2): Gate drive signal of the (N-2)th stage

[0029] G(N-1): Gate drive signal of the (N-1)th stage

[0030] G(Na): Gate drive signal of level (Na)

[0031] G(N): Gate drive signal of the Nth stage

[0032] G(N+1): Gate drive signal of the (N+1)th stage

[0033] G(N+1-a): Gate drive signal of the (N+1-a)th stage

[0034] G(N+2): Gate drive signal of the (N+2)th stage

[0035] G(N+2-a): Gate drive signal of the (N+2-a)th stage

[0036] G(N+3): Gate drive signal of the (N+3)th stage

[0037] G(N+3-a): Gate drive signal of the (N+3-a)th stage

[0038] G(N+4): Gate drive signal of the (N+4)th stage

[0039] G(N+5): Gate drive signal of the (N+5)th stage

[0040] G(N+6): Gate drive signal of the (N+6)th stage

[0041] G(N+7): Gate drive signal of the (N+7)th stage

[0042] G(N+8): Gate drive signal of the (N+8)th stage

[0043] G(N+9): Gate drive signal of the (N+9)th stage

[0044] G(N+10): Gate drive signal of the (N+10)th stage

[0045] G(N+11): Gate drive signal of the (N+11th)th stage

[0046] G(N+b): Gate drive signal of the (N+b)th stage

[0047] M11, M12, M21, M22, M31, M32, M41, M42: Scanning transistors

[0048] M13~M16, M23~M26, M33~M36, M43~M46: Noise-resistant transistors

[0049] M17, M27, M37, M47: Reset transistor

[0050] MC1~MC6: Control transistors

[0051] MH1~MH3: Transistors

[0052] MO(N), MO(N+1), MO(N+2), MO(N+3): output transistor

[0053] MP1~MP6: Pull-down transistors

[0054] NX: Control Node

[0055] RST: Reset signal

[0056] SQN, SQNX: Discharge control signals

[0057] SX: Indicator signal

[0058] T1~T4: Time interval

[0059] U2D: Forward Scan Signal

[0060] VDD: High reference voltage

[0061] VSS: Low reference voltage Detailed Implementation

[0062] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component symbols are used in the drawings and description to denote the same or similar parts.

[0063] Please refer to Figure 1 , Figure 1This is a schematic diagram of a gate driving circuit according to a first embodiment of the present invention. In this embodiment, the gate driving circuit may be at least a portion of a gate driving device. The gate driving circuit may be a single gate driving unit. In this embodiment, the gate driving circuit includes output circuits 110(N) to 110(N+3) and noise reduction control circuit 120. Output circuits 110(N) to 110(N+3) respectively provide different gate driving signals. For example, output circuit 110(N) provides the Nth level gate driving signal G(N). Output circuit 110(N+1) provides the (N+1)th level gate driving signal G(N+1). Output circuit 110(N+2) provides the (N+2)th level gate driving signal G(N+2). Output circuit 110(N+3) provides the (N+3)th level gate driving signal G(N+3).

[0064] In this embodiment, the output circuit 110(N) includes a scanning circuit 111(N), an output transistor MO(N), and a noise suppression circuit 112(N). The scanning circuit 111(N) precharges the bias node A(N) of the output circuit 110(N) in response to the (Na)th stage gate drive signal G(Na). a is a positive integer. N is a positive integer greater than a. The output transistor MO(N) is coupled to the bias node A(N) and the output terminal of the output circuit 110(N). The output transistor MO(N) outputs the Nth stage gate drive signal G(N) from the output terminal of the output circuit 110(N) in response to the bias value of the bias node A(N). In this embodiment, the output transistor MO(N) is an N-type transistor, such as an N-type thin-film transistor (this invention is not limited thereto). The first terminal of the output transistor MO(N) is coupled to the frequency signal CLK1. The second terminal of the output transistor MO(N) serves as the output terminal of the output circuit 110(N). The control terminal of the output transistor MO(N) is coupled to the bias node A(N). After the bias node A(N) is pre-charged, the bias value of the bias node A(N) is a high bias value. Therefore, the output transistor MO(N) will be turned on in response to the high bias value at the bias node A(N), and will use the frequency signal CLK1 as the Nth stage gate drive signal G(N).

[0065] In this embodiment, the noise suppression circuit 112(N) is coupled to the bias node A(N) and the output terminal of the output circuit 110(N). The noise suppression circuit 112(N) responds to the low voltage level of the Nth stage gate drive signal G(N) to remove noise located at the bias node A(N).

[0066] It is worth mentioning that the noise suppression circuit 112(N) removes noise at bias node A(N) by utilizing the low voltage level of the Nth-stage gate drive signal G(N), rather than by utilizing the low bias voltage of bias node A(N). This significantly reduces the load on bias node A(N), making it easier to raise the bias voltage at bias node A(N) to a higher value.

[0067] In this embodiment, the output circuit 110(N+1) includes a scanning circuit 111(N+1), an output transistor MO(N+1), and a noise suppression circuit 112(N+1). The scanning circuit 111(N+1) responds to the (N+1-a)th stage gate drive signal G(N+1-a) to precharge the bias node A(N+1) of the output circuit 110(N+1). The output transistor MO(N+1) responds to the bias value of the bias node A(N+1) to output the (N+1)th stage gate drive signal G(N+1) from the output terminal of the output circuit 110(N+1). The output transistor MO(N+1) is turned on in response to the high bias value at bias node A(N+1), and uses the frequency signal CLK2 as the gate drive signal G(N+1) for the (N+1)th stage. Noise suppression circuit 112(N+1) is coupled to the output of bias node A(N+1) and the output of output circuit 110(N+1). Noise suppression circuit 112(N+1) responds to the low voltage level of the gate drive signal G(N+1) for the (N+1)th stage to remove noise at bias node A(N+1).

[0068] In this embodiment, the output circuit 110(N+2) includes a scanning circuit 111(N+2), an output transistor MO(N+2), and a noise suppression circuit 112(N+2). The scanning circuit 111(N+2) responds to the (N+2-a)th stage gate drive signal G(N+2-a) to precharge the bias node A(N+2) of the output circuit 110(N+2). The output transistor MO(N+2) responds to the bias value of the bias node A(N+2) to output the (N+2)th stage gate drive signal G(N+2) from the output terminal of the output circuit 110(N+2). The output transistor MO(N+2) is turned on in response to the high bias value at bias node A(N+2), and uses the frequency signal CLK3 as the gate drive signal G(N+2) for the (N+2)th stage. Noise suppression circuit 112(N+2) is coupled to the output of bias node A(N+2) and the output of output circuit 110(N+2). Noise suppression circuit 112(N+2) responds to the low voltage level of the gate drive signal G(N+2) for the (N+2)th stage to remove noise at bias node A(N+2).

[0069] In this embodiment, the output circuit 110(N+3) includes a scanning circuit 111(N+3), an output transistor MO(N+3), and a noise suppression circuit 112(N+3). The scanning circuit 111(N+3) responds to the (N+3-a)th stage gate drive signal G(N+3-a) to precharge the bias node A(N+3) of the output circuit 110(N+3). The output transistor MO(N+3) responds to the bias value of the bias node A(N+3) to output the (N+3)th stage gate drive signal G(N+3) from the output terminal of the output circuit 110(N+3). The output transistor MO(N+3) is turned on in response to the high bias voltage at bias node A(N+3), and uses the frequency signal CLK4 as the gate drive signal G(N+3) for the (N+3)th stage. Noise suppression circuit 112(N+3) is coupled to the output of bias node A(N+3) and the output of output circuit 110(N+3). Noise suppression circuit 112(N+3) responds to the low voltage level of the gate drive signal G(N+3) for the (N+3)th stage to remove noise at bias node A(N+3).

[0070] It is worth mentioning that the scanning circuit 111(N) precharges the bias node A(N). The scanning circuit 111(N+1) precharges the bias node A(N+1) in response to the (N+1-a)th stage gate drive signal G(N+1), and so on. In other words, the bias nodes A(N) to A(N+3) are precharged by different corresponding scanning circuits. Therefore, the positive pulses of the Nth stage gate drive signal G(N) to the (N+3)th stage gate drive signal G(N+3) are equivalent to each other. The waveforms of the positive pulses of the Nth stage gate drive signal G(N) to the (N+3)th stage gate drive signal G(N+3) are approximately the same.

[0071] In this embodiment, the noise suppression control circuit 120 is coupled to the noise suppression circuits 112(N) to 112(N+3). The noise suppression control circuit 120 controls the operation of the noise suppression circuits 112(N) to 112(N+3) in response to the (Na)th stage gate drive signal G(Na) and the (N+b)th stage gate drive signal G(N+b). Here, b is a positive integer. It is worth noting that the noise suppression control circuit 120 can serve as the core of the noise suppression control for the noise suppression circuits 112(N) to 112(N+3). This results in a low layout area for the gate drive circuit.

[0072] For ease of explanation, this embodiment uses four output circuits 110(N) to 110(N+3) as an example. a is, for example, equal to 4. b is, for example, equal to 7. However, the number of output circuits in this invention is not limited to this. The number of output circuits in this invention can be multiple.

[0073] Please refer to Figure 2 , Figure 2 This is a schematic diagram of a gate driving circuit according to a second embodiment of the present invention. In this embodiment, the gate driving circuit includes output circuits 210(N) to 210(N+3) and noise reduction control circuit 220.

[0074] In this embodiment, the output circuit 210(N) includes a scanning circuit 211(N), an output transistor MO(N), and a noise reduction circuit 212(N). The configuration of the output transistor MO(N) has been clearly described in the first embodiment and will not be repeated here.

[0075] In this embodiment, the scanning circuit 211(N) includes scanning transistors M11 and M12. The first terminal of scanning transistor M11 receives a positive scan signal U2D. The second terminal of scanning transistor M11 is coupled to a bias node A(N). The control terminal of scanning transistor M11 receives a (N-4)th stage gate drive signal G(N-4). The first terminal of scanning transistor M12 is coupled to a bias node A(N). The second terminal of scanning transistor M12 receives a negative scan signal D2U. The control terminal of scanning transistor M12 receives a (N+4)th stage gate drive signal G(N+4). In this embodiment, when the positive scan signal U2D is at a high voltage level and the negative scan signal D2U is at a low voltage level, the gate drive circuit enters the positive scan mode. The scanning circuit 211(N) precharges the bias node A(N) in response to the positive pulse of the (N-4)th stage gate drive signal G(N-4), and pulls down the bias value at the bias node A(N) in response to the positive pulse of the (N+4)th stage gate drive signal G(N+4). On the other hand, when the positive scan signal U2D is at a low voltage level and the negative scan signal D2U is at a high voltage level, the gate drive circuit enters a negative scan mode. The scanning circuit 211(N) precharges the bias node A(N) in response to the positive pulse of the (N+4)th stage gate drive signal G(N+4), and pulls down the bias value at the bias node A(N) in response to the positive pulse of the (N-4)th stage gate drive signal G(N-4). The scanning transistors M11 and M12 are N-type transistors, such as N-type thin-film transistors (this invention is not limited thereto).

[0076] In this embodiment, the noise suppression circuit 212(N) includes noise suppression transistors M13 and M14. The first terminal of noise suppression transistor M13 is coupled to the bias node A(N). The second terminal of noise suppression transistor M13 receives the Nth-stage gate drive signal G(N). The control terminal of noise suppression transistor M13 receives a discharge control signal SQN. The first terminal of noise suppression transistor M14 is coupled to the bias node A(N). The second terminal of noise suppression transistor M14 receives the Nth-stage gate drive signal G(N). The control terminal of noise suppression transistor M14 receives a discharge control signal SQNX. In this embodiment, during the period when the noise suppression circuit 212(N) is disabled, the discharge control signals SQN and SQNX are at a first voltage level. During the noise suppression operation performed by the noise suppression circuit 212(N), the discharge control signals SQN and SQNX are complementary to each other.

[0077] In this embodiment, noise-suppressing transistors M13 and M14 are N-type transistors, such as N-type thin-film transistors (this invention is not limited thereto). The first voltage level is a low voltage level. The noise-suppressing control circuit 220 uses a discharge control signal SQN with a low voltage level to turn off noise-suppressing transistor M13, and uses a discharge control signal SQNX with a low voltage level to turn off noise-suppressing transistor M14. Therefore, the noise-suppressing circuit 212(N) is disabled. On the other hand, the noise-suppressing control circuit 220 uses complementary discharge control signals SQN and SQNX to alternately turn on noise-suppressing transistors M13 and M14. For example, the discharge control signal SQN is a high voltage level. The discharge control signal SQNX is a low voltage level, which is different from each other. In addition, the discharge control signals SQN and SQNX also transition based on a preset time. The preset time is, for example, at least one frame time, but this invention is not limited thereto. Therefore, the noise suppression circuit 212(N) responds to the low voltage level of the Nth stage gate drive signal G(N) to remove noise located at the bias node A(N).

[0078] In this embodiment, the noise suppression circuit 212(N) further includes noise suppression transistors M15 and M16. The first terminal of noise suppression transistor M15 is coupled to the output terminal of output circuit 210(N). The second terminal of noise suppression transistor M15 is coupled to the low reference voltage VSS. The control terminal of noise suppression transistor M15 receives a discharge control signal SQN. The first terminal of noise suppression transistor M16 is coupled to the output terminal of output circuit 210(N). The second terminal of noise suppression transistor M16 is coupled to the low reference voltage VSS. The control terminal of noise suppression transistor M16 receives a discharge control signal SQNX. The noise suppression control circuit 220 uses the complementary discharge control signals SQN and SQNX to alternately turn on noise suppression transistors M15 and M16. Therefore, the noise suppression circuit can also remove noise located at the output terminal of output circuit 210(N).

[0079] It should be noted that during the noise suppression operation, noise suppression transistors M13 and M14 are turned on alternately. Therefore, noise suppression transistors M13 and M14 can take turns resting (or being deactivated). During the noise suppression operation, noise suppression transistors M15 and M16 are turned on alternately. Therefore, noise suppression transistors M15 and M16 can take turns resting. In this way, the lifespan of the noise suppression circuit 212(N) can be extended.

[0080] In this embodiment, the output circuit 210(N) further includes a reset circuit 213(N). The reset circuit 213(N) is coupled to the bias node A(N). The reset circuit 213(N) responds to the reset signal RST to reset the bias value at the bias node A(N). The reset circuit 213(N) includes a reset transistor M17. A first terminal of the reset transistor M17 is coupled to the bias node A(N). A second terminal of the reset transistor M17 is coupled to the low reference voltage VSS. The control terminal of the reset transistor M17 receives the reset signal RST.

[0081] In this embodiment, the output circuit 210(N+1) includes a scanning circuit 211(N+1), an output transistor MO(N+1), a noise reduction circuit 212(N+1), and a reset circuit 213(N+1). The configuration of the output transistor MO(N+1) has been clearly described in the first embodiment and will not be repeated here.

[0082] In this embodiment, the scanning circuit 211(N+1) includes scanning transistors M21 and M22. The first terminal of scanning transistor M21 receives a positive scan signal U2D. The second terminal of scanning transistor M21 is coupled to bias node A(N+1). The control terminal of scanning transistor M21 receives the (N-3)th stage gate drive signal G(N-3). The first terminal of scanning transistor M22 is coupled to bias node A(N+1). The second terminal of scanning transistor M22 receives a negative scan signal D2U. The control terminal of scanning transistor M22 receives the (N+5)th stage gate drive signal G(N+5). In this embodiment, when the positive scan signal U2D is at a high voltage level and the negative scan signal D2U is at a low voltage level, the scanning circuit 211(N+1) responds to the positive pulse of the (N-3)th stage gate drive signal G(N-3) to precharge the bias node A(N+1), and responds to the positive pulse of the (N+5)th stage gate drive signal G(N+5) to pull down the bias value at the bias node A(N+1). On the other hand, when the positive scan signal U2D is at a low voltage level and the negative scan signal D2U is at a high voltage level, the scanning circuit 211(N+1) responds to the positive pulse of the (N+5)th stage gate drive signal G(N+5) to precharge the bias node A(N+1), and responds to the positive pulse of the (N-3)th stage gate drive signal G(N-3) to pull down the bias value at the bias node A(N+1). Scanning transistors M21 and M22 are N-type transistors, such as N-type thin-film transistors (this invention is not limited thereto).

[0083] In this embodiment, the noise suppression circuit 212(N+1) includes noise suppression transistors M23 to M26. The first terminal of noise suppression transistor M23 is coupled to the bias node A(N+1). The second terminal of noise suppression transistor M23 receives the (N+1)th stage gate drive signal G(N+1). The control terminal of noise suppression transistor M23 receives the discharge control signal SQN. The first terminal of noise suppression transistor M24 is coupled to the bias node A(N+1). The second terminal of noise suppression transistor M24 receives the (N+1)th stage gate drive signal G(N+1). The control terminal of noise suppression transistor M24 receives the discharge control signal SQNX. The first terminal of noise suppression transistor M25 is coupled to the output terminal of output circuit 210(N+1). The second terminal of noise suppression transistor M25 is coupled to the low reference voltage VSS. The control terminal of noise suppression transistor M25 receives the discharge control signal SQN. The first terminal of noise suppression transistor M26 is coupled to the output terminal of output circuit 210(N+1). The second terminal of the noise suppression transistor M26 is coupled to the low reference voltage VSS. The control terminal of the noise suppression transistor M26 receives the discharge control signal SQNX.

[0084] In this embodiment, noise-suppressing transistors M23 to M26 are N-type transistors, such as N-type thin-film transistors (this invention is not limited thereto). The first voltage level is a low voltage level. The noise-suppressing control circuit 220 uses a discharge control signal SQN with a low voltage level to turn off noise-suppressing transistors M23 and M25, and uses a discharge control signal SQNX with a low voltage level to turn off noise-suppressing transistors M24 and M26. Therefore, the noise-suppressing circuit 212 (N+1) is disabled. On the other hand, the noise-suppressing control circuit 220 uses complementary discharge control signals SQN and SQNX to alternately turn on noise-suppressing transistors M23 to M26 to remove noise located at bias node A (N+1) and noise located at the output terminal of output circuit 210 (N+1).

[0085] Reset circuit 213 (N+1) is coupled to bias node A (N+1). Reset circuit 213 (N+1) responds to the reset signal RST to reset the bias value at bias node A (N+1). Reset circuit 213 (N+1) includes reset transistor M27. A first terminal of reset transistor M27 is coupled to bias node A (N+1). A second terminal of reset transistor M27 is coupled to the low reference voltage VSS. The control terminal of reset transistor M27 receives the reset signal RST.

[0086] In this embodiment, the output circuit 210(N+2) includes a scanning circuit 211(N+2), an output transistor MO(N+2), a noise reduction circuit 212(N+2), and a reset circuit 213(N+2). The configuration of the output transistor MO(N+2) has been clearly described in the first embodiment and will not be repeated here.

[0087] In this embodiment, the scanning circuit 211(N+2) includes scanning transistors M31 and M32. The first terminal of scanning transistor M31 receives a positive scan signal U2D. The second terminal of scanning transistor M31 is coupled to bias node A(N+2). The control terminal of scanning transistor M31 receives the (N-2)th stage gate drive signal G(N-2). The first terminal of scanning transistor M32 is coupled to bias node A(N+2). The second terminal of scanning transistor M32 receives a negative scan signal D2U. The control terminal of scanning transistor M32 receives the (N+6)th stage gate drive signal G(N+6). In this embodiment, when the positive scan signal U2D is at a high voltage level and the negative scan signal D2U is at a low voltage level, the scanning circuit 211(N+2) responds to the positive pulse of the (N-2)th stage gate drive signal G(N-2) to precharge the bias node A(N+2), and responds to the positive pulse of the (N+6)th stage gate drive signal G(N+6) to pull down the bias value at the bias node A(N+2). On the other hand, when the positive scan signal U2D is at a low voltage level and the negative scan signal D2U is at a high voltage level, the scanning circuit 211(N+2) responds to the positive pulse of the (N+6)th stage gate drive signal G(N+6) to precharge the bias node A(N+2), and responds to the positive pulse of the (N-2)th stage gate drive signal G(N-2) to pull down the bias value at the bias node A(N+2). Scanning transistors M31 and M32 are N-type transistors, such as N-type thin-film transistors (this invention is not limited thereto).

[0088] In this embodiment, the noise suppression circuit 212(N+2) includes noise suppression transistors M33 to M36. The first terminal of noise suppression transistor M33 is coupled to the bias node A(N+2). The second terminal of noise suppression transistor M33 receives the (N+2)th stage gate drive signal G(N+2). The control terminal of noise suppression transistor M33 receives the discharge control signal SQN. The first terminal of noise suppression transistor M34 is coupled to the bias node A(N+2). The second terminal of noise suppression transistor M34 receives the (N+2)th stage gate drive signal G(N+2). The control terminal of noise suppression transistor M34 receives the discharge control signal SQNX. The first terminal of noise suppression transistor M35 is coupled to the output terminal of output circuit 210(N+2). The second terminal of noise suppression transistor M35 is coupled to the low reference voltage VSS. The control terminal of noise suppression transistor M35 receives the discharge control signal SQN. The first terminal of noise suppression transistor M36 is coupled to the output terminal of output circuit 210(N+2). The second terminal of the noise suppression transistor M36 is coupled to the low reference voltage VSS. The control terminal of the noise suppression transistor M36 receives the discharge control signal SQNX.

[0089] In this embodiment, noise-suppressing transistors M33 to M36 are N-type transistors, such as N-type thin-film transistors (this invention is not limited thereto). The first voltage level is a low voltage level. The noise-suppressing control circuit 220 uses a discharge control signal SQN with a low voltage level to turn off noise-suppressing transistors M33 and M35, and uses a discharge control signal SQNX with a low voltage level to turn off noise-suppressing transistors M34 and M36. Therefore, the noise-suppressing circuit 212 (N+2) is disabled. On the other hand, the noise-suppressing control circuit 220 uses complementary discharge control signals SQN and SQNX to alternately turn on noise-suppressing transistors M33 to M36 to remove noise located at bias node A (N+2) and noise located at the output terminal of output circuit 210 (N+2).

[0090] Reset circuit 213 (N+2) is coupled to bias node A (N+2). Reset circuit 213 (N+2) responds to the reset signal RST to reset the bias value at bias node A (N+2). Reset circuit 213 (N+2) includes reset transistor M37. A first terminal of reset transistor M37 is coupled to bias node A (N+2). A second terminal of reset transistor M37 is coupled to the low reference voltage VSS. The control terminal of reset transistor M37 receives the reset signal RST.

[0091] In this embodiment, the output circuit 210(N+3) includes a scanning circuit 211(N+3), an output transistor MO(N+3), a noise reduction circuit 212(N+3), and a reset circuit 213(N+3). The configuration of the output transistor MO(N+3) has been clearly described in the first embodiment and will not be repeated here.

[0092] In this embodiment, the scanning circuit 211(N+3) includes scanning transistors M41 and M42. The first terminal of scanning transistor M41 receives a positive scan signal U2D. The second terminal of scanning transistor M41 is coupled to bias node A(N+3). The control terminal of scanning transistor M41 receives the (N-1)th stage gate drive signal G(N-1). The first terminal of scanning transistor M42 is coupled to bias node A(N+3). The second terminal of scanning transistor M42 receives a negative scan signal D2U. The control terminal of scanning transistor M42 receives the (N+7)th stage gate drive signal G(N+7). In this embodiment, when the positive scan signal U2D is at a high voltage level and the negative scan signal D2U is at a low voltage level, the scanning circuit 211(N+3) responds to the positive pulse of the (N-1)th stage gate drive signal G(N-1) to precharge the bias node A(N+3), and responds to the positive pulse of the (N+7)th stage gate drive signal G(N+7) to pull down the bias value at the bias node A(N+3). On the other hand, when the positive scan signal U2D is at a low voltage level and the negative scan signal D2U is at a high voltage level, the scanning circuit 211(N+3) responds to the positive pulse of the (N+7)th stage gate drive signal G(N+7) to precharge the bias node A(N+3), and responds to the positive pulse of the (N-1)th stage gate drive signal G(N-1) to pull down the bias value at the bias node A(N+3). The scanning transistors M41 and M42 are N-type transistors, such as N-type thin-film transistors (this invention is not limited thereto).

[0093] In this embodiment, the noise suppression circuit 212(N+3) includes noise suppression transistors M43 to M46. The first terminal of noise suppression transistor M43 is coupled to the bias node A(N+3). The second terminal of noise suppression transistor M43 receives the (N+3)th stage gate drive signal G(N+3). The control terminal of noise suppression transistor M43 receives the discharge control signal SQN. The first terminal of noise suppression transistor M44 is coupled to the bias node A(N+3). The second terminal of noise suppression transistor M44 receives the (N+3)th stage gate drive signal G(N+3). The control terminal of noise suppression transistor M44 receives the discharge control signal SQNX. The first terminal of noise suppression transistor M45 is coupled to the output terminal of output circuit 210(N+3). The second terminal of noise suppression transistor M45 is coupled to the low reference voltage VSS. The control terminal of noise suppression transistor M45 receives the discharge control signal SQN. The first terminal of noise suppression transistor M46 is coupled to the output terminal of output circuit 210(N+3). The second terminal of the noise suppression transistor M46 is coupled to the low reference voltage VSS. The control terminal of the noise suppression transistor M46 receives the discharge control signal SQNX.

[0094] In this embodiment, noise suppression transistors M43 to M46 are N-type transistors, such as N-type thin-film transistors (this invention is not limited thereto). The first voltage level is a low voltage level. The noise suppression control circuit 220 uses a discharge control signal SQN with a low voltage level to turn off noise suppression transistors M43 and M45, and uses a discharge control signal SQNX with a low voltage level to turn off noise suppression transistors M44 and M46. Therefore, the noise suppression circuit 212 (N+3) is disabled. On the other hand, the noise suppression control circuit 220 uses complementary discharge control signals SQN and SQNX to alternately turn on noise suppression transistors M43 to M46 to remove noise located at bias node A (N+2) and noise located at the output terminal of output circuit 210 (N+3).

[0095] Reset circuit 213 (N+3) is coupled to bias node A (N+3). Reset circuit 213 (N+3) responds to the reset signal RST to reset the bias value at bias node A (N+3). Reset circuit 213 (N+3) includes reset transistor M47. A first terminal of reset transistor M47 is coupled to bias node A (N+3). A second terminal of reset transistor M47 is coupled to the low reference voltage VSS. The control terminal of reset transistor M47 receives the reset signal RST.

[0096] The reset circuits 213(N) to 213(N+3) are N-type transistors, such as N-type thin-film transistors (this invention is not limited thereto).

[0097] Please refer to Figure 3 , Figure 3 It is based on Figure 2 The diagram illustrates a noise suppression control circuit. In this embodiment, the noise suppression control circuit 220 includes a control unit 221 and a discharge control signal generator 222. The control unit 221 responds to one of the (N-4)th stage gate drive signal G(N-4) and the (N+7)th stage gate drive signal G(N+7) to provide an indication signal SX having a first voltage level (e.g., a low voltage level). The control unit 221 responds to the other of the (N-4)th stage gate drive signal G(N-4) and the (N+7)th stage gate drive signal G(N+7) to provide an indication signal SX having a second voltage level (e.g., a high voltage level). The discharge control signal generator 222 is coupled to the control unit 221. The discharge control signal generator 222 responds to the second voltage level of the indication signal SX to maintain the discharge control signals SQN and SQNX at the first voltage level. The discharge control signal generator 222 responds to the first voltage level of the indicator signal SX to make the voltage levels of the discharge control signal SQN and the discharge control signal SQNX complementary to each other.

[0098] In this embodiment, the control unit 221 includes control transistors MC1 and MC2, and pull-down transistors MP1 and MP2. The first terminal of control transistor MC1 is coupled to the positive scan signal U2D. The second terminal of control transistor MC1 is coupled to the control node NX. The control terminal of control transistor MC1 receives the (Na)th stage gate drive signal G(Na). In this embodiment, 'a' is taken as 4. The control node NX is used to output the indicator signal SX. The first terminal of control transistor MC2 is coupled to the negative scan signal D2U. The second terminal of control transistor MC2 is coupled to the control node NX. The control terminal of control transistor MC2 receives the (N+b)th stage gate drive signal G(N+b). In this embodiment, 'b' is taken as 7. The first terminal of pull-down transistor MP1 is coupled to the control node NX. The second terminal of pull-down transistor MP1 is coupled to the low reference voltage VSS. The control terminal of pull-down transistor MP1 receives the discharge control signal SQN. The first terminal of pull-down transistor MP2 is coupled to the control node NX. The second terminal of pull-down transistor MP2 is coupled to the low reference voltage VSS. The control terminal of pull-down transistor MP2 receives the discharge control signal SQNX.

[0099] The discharge control signal generator 222 includes control transistors MC3 to MC6 and pull-down transistors MP3 to MP6. The first terminal and control terminal of control transistor MC3 receive an external frequency ECK. The first terminal of control transistor MC4 receives the external frequency ECK. The second terminal of control transistor MC4 is used to output a discharge control signal SQN. The control terminal of control transistor MC4 is coupled to the second terminal of control transistor MC3. The first terminal of pull-down transistor MP3 is coupled to the second terminal of control transistor MC3. The second terminal of pull-down transistor MP3 is coupled to a low reference voltage VSS. The control terminal of pull-down transistor MP3 is coupled to a control node NX. The first terminal of pull-down transistor MP4 is coupled to the second terminal of control transistor MC4. The second terminal of pull-down transistor MP4 is coupled to a low reference voltage VSS. The control terminal of pull-down transistor MP4 is coupled to a control node NX.

[0100] The first terminal and control terminal of control transistor MC5 receive the external frequency EXCK. The first terminal of control transistor MC6 receives the external frequency EXCK. The second terminal of control transistor MC6 is used to output the second discharge control signal. The control terminal of control transistor MC6 is coupled to the second terminal of control transistor MC5. The first terminal of pull-down transistor MP5 is coupled to the second terminal of control transistor MC5. The second terminal of pull-down transistor MP5 is coupled to the low reference voltage VSS. The control terminal of pull-down transistor MP5 is coupled to the control node NX. The first terminal of pull-down transistor MP6 is coupled to the second terminal of control transistor MC6. The second terminal of pull-down transistor MP6 is coupled to the low reference voltage VSS. The control terminal of pull-down transistor MP6 is coupled to the control node NX.

[0101] The voltage levels of the external frequencies ECK and EXCK are complementary to each other and transition between states based on a preset time. The preset time is, for example, at least one frame, but the invention is not limited thereto.

[0102] In this embodiment, when the control unit 221 provides an indication signal SX with a high voltage level, the pull-down transistors MP3 to MP6 of the discharge control signal generator 222 are turned on. Therefore, the discharge control signals SQN and SQNX are at a low voltage level. In addition, to ensure that the high voltage level at the control node NX can be maintained, the control unit 221 also includes transistors MH1 to MH3, and uses transistors MH1 to MH3 to maintain the high voltage level at the control node NX. In this embodiment, the first terminal of transistor MH1 is coupled to the high reference voltage VDD. The second terminal of transistor MH1 is coupled to the control node NX. The control terminal of transistor MH1 receives the (N-1)th stage gate drive signal G(N-1). The first terminal of transistor MH2 is coupled to the high reference voltage VDD. The second terminal of transistor MH2 is coupled to the control node NX. The control terminal of transistor MH2 receives the (N+2)th stage gate drive signal G(N+2). The first terminal of transistor MH3 is coupled to the high reference voltage VDD. The second terminal of transistor MH3 is coupled to the control node NX. The control terminal of transistor MH3 receives the (N+4)th stage gate drive signal G(N+4).

[0103] It should be understood that, based on the charge retention capability of the control node NX, at least one of transistors MH1 to MH3 can be omitted.

[0104] In this embodiment, when the control unit 221 provides an indication signal SX with a low voltage level, the pull-down transistors MP3 to MP6 of the discharge control signal generator 222 are turned off. Therefore, the discharge control signal SQN is generated based on the external frequency ECK. The discharge control signal SQNX is generated based on the external frequency EXCK. Therefore, the voltage levels of the discharge control signals SQN and SQNX are complementary and transition based on a preset time. The pull-down transistors MP1 and MP2 are turned off alternately. Therefore, the indication signal SX is maintained at a low voltage level.

[0105] In this embodiment, the control transistors MC1 to MC6, the pull-down transistors MP1 to MP6, and the transistors MH1 to MH3 are all N-type transistors, such as N-type thin-film transistors (this invention is not limited thereto).

[0106] Please also refer to Figure 2 , Figure 3 as well as Figure 4 , Figure 4This is an operation timing diagram of a gate drive circuit according to an embodiment of the present invention. Figure 4 The timing diagram of the output circuit 210(N) and the noise suppression control circuit 220 is shown. In this embodiment, the positive scan signal U2D is at a high voltage level. The negative scan signal D2U is at a low voltage level. During time interval T1, the control transistor MC1 is turned on in response to the positive pulse of the (N-4)th stage gate drive signal G(N-4). The control unit 221 uses the positive scan signal U2D to charge the control node NX. Therefore, the control unit 221 provides an indication signal SX with a high voltage level at the beginning of time interval T1. The pull-down transistors MP3 to MP6 of the discharge control signal generator 222 are turned on. Therefore, the discharge control signals SQN and SQNX have low voltage levels. The output circuits 210(N) to 210(N+3) stop noise suppression operation.

[0107] During time interval T1, the scanning transistor M11 is turned on in response to the positive pulse of the (N-4)th stage gate drive signal G(N-4). Therefore, the scanning circuit 211(N) precharges the bias value at the bias node A(N) using the positive scan signal U2D. Consequently, the output transistor MO(N) is turned on.

[0108] Similarly, during time interval T1, the bias voltage of bias node A(N+1) is pre-charged in response to the gate drive signal G(N-3) of stage (N-3). The bias voltage of bias node A(N+2) is pre-charged in response to the gate drive signal G(N-2) of stage (N-2). The bias voltage of bias node A(N+3) is pre-charged in response to the gate drive signal G(N-1) of stage (N-1). Therefore, the output transistors MO(N+1) to MO(N+3) are turned on sequentially.

[0109] During time interval T2, the frequency signal CLK1 has a positive pulse. Therefore, the Nth-stage gate drive signal G(N) also has a positive pulse. There is a parasitic capacitance between the control terminal and the second terminal of the output transistor MO(N). Based on the capacitive coupling of the parasitic capacitance, the bias value of the bias node A(N) will be coupled to a higher bias value in response to the positive pulse of the Nth-stage gate drive signal G(N).

[0110] During time interval T3, the frequency signal CLK1 does not have a positive pulse. Therefore, the Nth-stage gate drive signal G(N) also does not have a positive pulse. Next, the scan transistor M12 is turned on in response to the (N+4)th-stage gate drive signal G(N+4). Therefore, the scan circuit 211(N) uses the negative scan signal D2U to pull down the bias voltage at the bias node A(N) to a low voltage level. Therefore, the output transistor MO(N) is turned off. Similarly, during time interval T3, the output transistors MO(N+1) to MO(N+3) are turned off sequentially.

[0111] Furthermore, the transistors MH1 to MH3, which are turned on, are used to maintain a high voltage level at the control node NX. Therefore, the indicator signal SX remains at a high voltage level during the time interval T1 to T3.

[0112] During time interval T4, control transistor MC2 is turned on in response to the positive pulse of the (N+7)th stage gate drive signal G(N+7). Transistor MH3 is turned off. Control unit 221 uses the negative sweep signal D2U to pull down the high voltage level at control node NX to a low voltage level. Therefore, control unit 221 provides an indication signal SX with a low voltage level at the beginning of time interval T4. The pull-down transistors MP3 to MP6 of discharge control signal generator 222 are turned off. Therefore, the voltage levels of discharge control signals SQN and SQNX begin to complement each other. For example, at the current frame time, discharge control signal SQN has a high voltage level, while discharge control signal SQNX has a low voltage level. Output circuits 210(N) to 210(N+3) begin full-time noise suppression operation.

[0113] During the time interval T5, the output circuit 210(N)~210(N+3) continuously performs noise suppression operation.

[0114] Please refer to Figure 5 , Figure 5 This is a schematic diagram of a gate driving device according to an embodiment of the present invention. In this embodiment, the gate driving device 20 includes a plurality of gate driving circuits. For ease of explanation, only gate driving circuits 200-1 and 200-2 are used as examples in this embodiment.

[0115] The gate drive circuit 200-1 includes output circuits 210(N) to 210(N+3) and a noise suppression control circuit 220-1. Output circuit 210(N) provides the Nth stage gate drive signal G(N). Output circuit 210(N+1) provides the (N+1)th stage gate drive signal G(N+1). Output circuit 210(N+2) provides the (N+2)th stage gate drive signal G(N+2). Output circuit 210(N+3) provides the (N+3)th stage gate drive signal G(N+3). Embodiments of output circuits 210(N) to 210(N+3) have been described previously. Figure 2 The embodiments are clearly illustrated and will not be repeated here. The noise reduction control circuit 220-1 can be composed of... Figure 3 The implementation of the noise reduction control circuit 220 is carried out by the noise reduction control circuit 220, so the implementation method of the noise reduction control circuit 220-1 will not be repeated here.

[0116] The gate drive circuit 200-2 includes output circuits 210(N+4) to 210(N+7) and noise suppression control circuit 220-2. Output circuit 210(N+4) receives frequency signal CLK1, positive scan signal U2D, negative scan signal D2U, reset signal RST, low reference voltage VSS, the Nth stage gate drive signal G(N), and the (N+8)th stage gate drive signal G(N+8). Output circuit 210(N+4) provides the (N+4)th stage gate drive signal G(N+4).

[0117] Output circuit 210(N+5) receives frequency signal CLK2, positive scan signal U2D, negative scan signal D2U, reset signal RST, low reference voltage VSS, (N+1)th stage gate drive signal G(N+1), and (N+9)th stage gate drive signal G(N+9). Output circuit 210(N+5) provides the (N+5)th stage gate drive signal G(N+5).

[0118] Output circuit 210(N+6) receives frequency signal CLK3, positive scan signal U2D, negative scan signal D2U, reset signal RST, low reference voltage VSS, (N+2)th stage gate drive signal G(N+2), and (N+10)th stage gate drive signal G(N+10). Output circuit 210(N+6) provides the (N+6)th stage gate drive signal G(N+6).

[0119] Output circuit 210(N+7) receives frequency signal CLK4, positive scan signal U2D, negative scan signal D2U, reset signal RST, low reference voltage VSS, (N+3)th stage gate drive signal G(N+3), and (N+11)th stage gate drive signal G(N+11). Output circuit 210(N+7) provides the (N+7)th stage gate drive signal G(N+7).

[0120] In this embodiment, the noise reduction control circuit 220-2 is used as the control core for the noise reduction operation of the output circuits 210(N) to 210(N+3).

[0121] In summary, the noise suppression control circuit of the present invention can control the noise suppression operation of the plurality of noise suppression circuits. The plurality of noise suppression circuits of the gate drive circuit only require a single noise suppression control circuit for control. As a result, the gate drive circuit has a low layout area. Furthermore, the noise suppression circuit uses the low voltage level of the Nth stage gate drive signal to remove noise located at the bias node. This reduces the load on the bias node. The bias value at the bias node can be more easily raised to a high bias value.

[0122] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A gate drive circuit characterized by comprising: The gate driving circuit comprises: a plurality of output circuits respectively providing different gate driving signals, wherein an Nth-stage output circuit among the plurality of output circuits comprises: a scan circuit configured to pre-charge a bias node of the Nth-stage output circuit in response to an (N-a)th-stage gate driving signal; an output transistor coupled to the bias node and an output terminal of the Nth-stage output circuit, configured to output an Nth-stage gate driving signal from the output terminal in response to a bias value of the bias node; and a noise-removing circuit coupled to the bias node and the output terminal, configured to remove noise at the bias node in response to a low voltage level of the Nth-stage gate driving signal; and a noise-removing control circuit coupled to a plurality of noise-removing circuits of the plurality of output circuits, configured to control the plurality of noise-removing circuits in response to the (N-a)th-stage gate driving signal and an (N+b)th-stage gate driving signal, wherein a and b are positive integers respectively, and N is a positive integer greater than a.

2. The gate drive circuit according to claim 1, characterized by The scan circuit comprises: a first scan transistor having a first end receiving a positive scan signal, a second end coupled to the bias node, and a control end receiving the (N-a)th-stage gate driving signal; and a second scan transistor having a first end coupled to the bias node, a second end receiving a negative scan signal, and a control end receiving an (N+a)th-stage gate driving signal.

3. The gate driving circuit of claim 2, wherein: when the positive scan signal is at a high voltage level and the negative scan signal is at a low voltage level, the scan circuit pre-charges the bias node in response to a positive pulse of the (N-a)th-stage gate driving signal, and pulls down the bias value at the bias node in response to a positive pulse of the (N+a)th-stage gate driving signal, and when the positive scan signal is at a low voltage level and the negative scan signal is at a high voltage level, the scan circuit pre-charges the bias node in response to a positive pulse of the (N+a)th-stage gate driving signal, and pulls down the bias value at the bias node in response to a positive pulse of the (N-a)th-stage gate driving signal.

4. The gate drive circuit according to claim 1, characterized by The noise-removing circuit comprises: a first noise-removing transistor having a first end coupled to the bias node, a second end receiving the Nth-stage gate driving signal, and a control end receiving a first discharge control signal; and a second noise-removing transistor having a first end coupled to the bias node, a second end receiving the Nth-stage gate driving signal, and a control end receiving a second discharge control signal.

5. The gate driving circuit of claim 4, wherein: during a period when the noise-removing circuit is disabled, the first discharge control signal and the second discharge control signal are at a first voltage level, and during a period when the noise-removing circuit is enabled, the first discharge control signal is at a second voltage level and the second discharge control signal is at a third voltage level. The first discharge control signal and the second discharge control signal are complementary to each other during the anti-noise circuit performs the anti-noise operation.

6. The gate drive circuit according to claim 4, characterized by The anti-noise circuit further comprises: a third anti-noise transistor, a first end of the third anti-noise transistor is coupled to the output terminal, a second end of the third anti-noise transistor is coupled to a low reference voltage, and a control end of the third anti-noise transistor receives the first discharge control signal; and a fourth anti-noise transistor, a first end of the fourth anti-noise transistor is coupled to the output terminal, a second end of the fourth anti-noise transistor is coupled to a low reference voltage, and a control end of the fourth anti-noise transistor receives the second discharge control signal.

7. The gate drive circuit according to claim 4, characterized by The anti-noise control circuit comprises: a control unit, configured to provide an indication signal with a first voltage level in response to one of the (N-a)th gate driving signal and the (N+b)th gate driving signal, and to provide the indication signal with a second voltage level in response to the other of the (N-a)th gate driving signal and the (N+b)th gate driving signal; and a discharge control signal generator, coupled to the control unit, configured to maintain the first discharge control signal and the second discharge control signal at the first voltage level in response to the second voltage level of the indication signal, and to make the voltage level of the first discharge control signal and the voltage level of the second discharge control signal complementary to each other in response to the first voltage level of the indication signal.

8. The gate drive circuit according to claim 7, characterized by The control unit comprises: a first control transistor, a first end of the first control transistor is coupled to a positive scan signal, a second end of the first control transistor is coupled to a control node, and a control end of the first control transistor receives the (N-a)th gate driving signal, wherein the control node is used to output the indication signal; a second control transistor, a first end of the second control transistor is coupled to a negative scan signal, a second end of the second control transistor is coupled to the control node, and a control end of the second control transistor receives the (N+b)th gate driving signal; a first pull-down transistor, a first end of the first pull-down transistor is coupled to the control node, a second end of the first pull-down transistor is coupled to a low reference voltage, and a control end of the first pull-down transistor receives the first discharge control signal; and a second pull-down transistor, a first end of the second pull-down transistor is coupled to the control node, a second end of the second pull-down transistor is coupled to the low reference voltage, and a control end of the second pull-down transistor receives the second discharge control signal.

9. The gate drive circuit according to claim 8, characterized in that The discharge control signal generator comprises: a third control transistor, a first end of the third control transistor and a control end of the third control transistor receive a first external frequency; a fourth control transistor, a first end of the fourth control transistor receives the first external frequency, a second end of the fourth control transistor is used to output the first discharge control signal, and a control end of the fourth control transistor is coupled to a second end of the third control transistor; and a fifth control transistor, a first end of the fifth control transistor receives the first external frequency, a second end of the fifth control transistor is used to output the second discharge control signal, and a control end of the fifth control transistor is coupled to a second end of the fourth control transistor. a third pull-down transistor, a first end of the third pull-down transistor is coupled to a second end of the third control transistor, a second end of the third pull-down transistor is coupled to the low reference voltage, and a control end of the third pull-down transistor is coupled to the control node; a fourth pull-down transistor, a first end of the fourth pull-down transistor is coupled to a second end of the fourth control transistor, a second end of the fourth pull-down transistor is coupled to the low reference voltage, and a control end of the fourth pull-down transistor is coupled to the control node; a fifth control transistor, a first end of the fifth control transistor and a control end of the fifth control transistor receive a second external frequency; a sixth control transistor, a first end of the sixth control transistor receives the second external frequency, a second end of the sixth control transistor is used to output the second discharge control signal, and a control end of the sixth control transistor is coupled to a second end of the fifth control transistor; a fifth pull-down transistor, a first end of the fifth pull-down transistor is coupled to a second end of the fifth control transistor, a second end of the fifth pull-down transistor is coupled to the low reference voltage, and a control end of the fifth pull-down transistor is coupled to the control node; and a sixth pull-down transistor, a first end of the sixth pull-down transistor is coupled to a second end of the sixth control transistor, a second end of the sixth pull-down transistor is coupled to the low reference voltage, and a control end of the sixth pull-down transistor is coupled to the control node.

10. The gate drive circuit according to claim 1, characterized by the Nth stage output circuit further includes: a reset circuit, coupled to the bias node, configured to reset a bias value at the bias node in response to a reset signal.

Images