Display panel and display device

Abstract

The present invention discloses a display panel and a display device. The display panel includes a driving component, a multiplexing circuit, a connection line, and a plurality of pixel units; the driving component is disposed in a bonding area and includes a first output unit; the multiplexing circuit is disposed in a circuit area and includes a first circuit unit; the connection line is connected between the driving component and the multiplexing circuit and includes a first connection line connected between the first circuit unit and the first output unit; the plurality of pixel units are disposed in a display area and are connected to the multiplexing circuit; wherein, the first connection line includes a winding segment distributed in the display area. The present invention can improve the resolution of the display panel, reduce the wiring space outside the display area, and reduce the frame width of the display panel so as to implement a narrow-frame display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and in particular, to a display panel and a display device. Background Art

[0002] An organic light-emitting diode (OLED) display panel has many advantages such as self-luminescence, low driving voltage, high luminous efficiency, short response time, high clarity and contrast, and can achieve flexible display and large-area full-color display, and is recognized by the industry as the most promising display panel.

[0003] Currently, in the related art, the technology of laying out fan-out lines in the display area (fanout in AA, FIAA) is to wind the fanout traces from the AA area and connect them to the data lines, thereby reducing the area of the lower border occupied by the fanout traces. However, when the number of data lines is large, the number of fanout traces corresponding to the connected data lines is also large, resulting in the need for more space in the AA area for winding the fanout traces, making it difficult to meet the requirements of high resolution. Summary of the Invention

[0004] Embodiments of the present invention provide a display panel and a display device, which can reduce the wiring space of the first connection line outside the display area and reduce the border width of the display panel.

[0005] Embodiments of the present invention provide a display panel, the display panel includes a display area, a bonding area, and a circuit area located between the display area and the bonding area;

[0006] The display panel further includes:

[0007] a driving component, disposed in the bonding area and including a first output unit;

[0008] a multiplexing circuit, disposed in the circuit area and including a first circuit unit;

[0009] a connection line, connected between the driving component and the multiplexing circuit, and including a first connection line connected between the first circuit unit and the first output unit;

[0010] a plurality of pixel units, disposed in the display area and connected to the multiplexing circuit;

[0011] wherein, the first connection line includes a winding segment distributed in the display area.

[0012] In one embodiment of the present invention, the first connecting line also includes a first line segment extending from the binding area to the circuit area and connected to the first output unit, and a second line segment extending from the boundary of the display area to the circuit area and connected to the first circuit unit, and the winding segment is connected between the first line segment and the second line segment.

[0013] In one embodiment of the present invention, the first line segment and the second line segment both extend along a first direction, and the first direction is the direction from the binding area to the display area. The first line segment and the second line segment are staggered along the first direction, and the winding segment is distributed in a bent shape in the display area.

[0014] In an embodiment of the present invention, the first output unit and the first circuit unit are staggered along the first direction.

[0015] In one embodiment of the present invention, the multiplexing circuit includes a plurality of second circuit units, the plurality of first circuit units and the plurality of second circuit units are arranged along a second direction, the second direction intersects the first direction, the driving component includes a plurality of second output units, the plurality of first output units and the plurality of second output units are arranged along the second direction, and the connecting line further includes a plurality of second connecting lines;

[0016] The second connecting line extends along the first direction and is connected between the second circuit unit and the second output unit.

[0017] In one embodiment of the present invention, the connecting wire includes a plurality of first connecting wires, and the plurality of winding segments of the plurality of first connecting wires do not intersect with each other.

[0018] In one embodiment of the present invention, the connecting wire includes at least one winding group, one winding group includes a plurality of winding segments, and within one winding group, the plurality of winding segments are nested one by one.

[0019] In one embodiment of the present invention, the length of the binding area along the second direction is smaller than the length of the circuit area along the second direction, and the circuit area includes a first sub-area and a second sub-area, the second sub-area and the binding area are aligned along the first direction, and the first sub-area is connected to the second sub-area along the second direction;

[0020] The plurality of first circuit units are distributed in the first sub-area, and the second circuit units are distributed in the second sub-area.

[0021] In an embodiment of the present invention, the multiple second output units include edge second output units located at the end of the driving component, and the first output unit connected to the first circuit unit on the side far from the second sub-region is on the side away from the edge second output unit of the first output unit connected to the first circuit unit on the side close to the second sub-region.

[0022] In an embodiment of the present invention, within the driving component, among the multiple second output units close to the edge second output unit, there is one first output unit spaced between two adjacent second output units, and among the multiple second output units far from the edge second output unit, the multiple second output units are arranged adjacent to each other.

[0023] In an embodiment of the present invention, the length of the winding segment of the first connection line connected to the first circuit unit on the side far from the second sub-region is greater than the length of the winding segment of the first connection line connected to the first circuit unit on the side close to the second sub-region.

[0024] In an embodiment of the present invention, the second circuit unit and the second output unit are arranged in alignment along the first direction.

[0025] In an embodiment of the present invention, the multiple pixel units include multiple pixel unit groups arranged along the second direction, and each pixel unit group includes multiple pixel units arranged along the first direction;

[0026] Wherein, one pixel unit group is arranged in alignment with one first circuit unit or one second circuit unit along the first direction.

[0027] In an embodiment of the present invention, the display panel further includes multiple data line groups, one data line group is connected to one pixel unit group, the data line group includes at least two data lines extending along the first direction, and the data lines are connected to the pixel units in the corresponding pixel unit group;

[0028] Wherein, one data line group is connected to the corresponding one first circuit unit or one second circuit unit along the first direction.

[0029] In an embodiment of the present invention, the display panel includes a substrate and a thin film transistor layer disposed on the substrate, the first circuit unit includes multiple first multiplexing thin film transistors located in the thin film transistor layer, and the second circuit unit includes multiple second multiplexing thin film transistors located in the thin film transistor layer;

[0030] Among them, one of the first connection lines is connected to the sources of a plurality of the first multiplexed thin film transistors, one data line is connected to the drain of one of the first multiplexed thin film transistors, one of the second connection lines is connected to the sources of a plurality of the second multiplexed thin film transistors, and one data line is connected to the drain of one of the second multiplexed thin film transistors.

[0031] In an embodiment of the present invention, the display panel further includes a conductive layer disposed on a side of the thin film transistor layer away from the substrate, and a light emitting device layer disposed on a side of the conductive layer away from the thin film transistor layer;

[0032] Among them, the conductive layer includes the first line segment, the second line segment, and the winding line segment.

[0033] In an embodiment of the present invention, the first line segment partially overlaps with the second circuit unit, and the second line segment extends from the boundary of the display area to the first circuit unit and is connected to the source of the first multiplexed thin film transistor.

[0034] According to the above object of the present invention, an embodiment of the present invention further provides a display device, and the display device includes the display panel.

[0035] Advantages of the present invention: In the present invention, a first connection line is provided between the first circuit unit and the first output unit, so that signals in the driving component are transmitted to the display area through the multiplexing circuit. Furthermore, the number of the first connection lines can be reduced compared with the data lines in the related art, and by providing a winding line segment in the first connection line, the first circuit unit can be arranged at a preset position according to actual needs. Furthermore, the winding of the fanout trace in the related art can be replaced by the winding line segment of the first connection line between the multiplexing circuit and the driving component in the present invention, which can reduce the number of windings, increase the available space in the display area, and is beneficial to improving the resolution of the display panel; further, the winding line segment in the first connection line is located in the display area, avoiding the winding line segment occupying the space of the circuit area, thereby reducing the wiring space outside the display area, and further reducing the frame width of the display panel, and a narrow bezel display panel can be realized. Description of the Drawings

[0036] The following will make the technical solutions and other beneficial effects of the present invention obvious by describing the specific embodiments of the present invention in detail with reference to the drawings.

[0037] Figure 1 It is a schematic diagram of a partial planar distribution structure of a display panel provided by an embodiment of the present invention;

[0038] Figure 2 It is a schematic diagram of another partial planar distribution structure of a display panel provided by an embodiment of the present invention;

[0039] Figure 3 A schematic diagram of a circuit structure of a first circuit unit and a second circuit unit provided by an embodiment of the present invention;

[0040] Figure 4 A schematic diagram of a circuit structure of a second circuit unit provided by an embodiment of the present invention;

[0041] Figure 5 Another schematic diagram of a partial planar distribution structure of a display panel provided by an embodiment of the present invention;

[0042] Figure 6 A schematic diagram of a planar distribution structure of a display panel provided by an embodiment of the present invention. Detailed implementation manners

[0043] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present invention.

[0044] The following disclosure provides many different implementation manners or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, components and settings of specific examples are described below. Of course, they are only examples and are not intended to limit the present invention. In addition, the present invention may repeat reference numerals and / or reference letters in different examples. Such repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between various implementation manners and / or settings discussed. In addition, the present invention provides examples of various specific processes and materials, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0045] An embodiment of the present invention provides a display panel. Please refer to Figure 1 and Figure 2 , the display panel includes a display area 101, a bonding area 1022, and a circuit area 1021 located between the display area 101 and the bonding area 1022.

[0046] Further, the display panel further includes a driving component 10, a multiplexing circuit 20, connection lines, and a plurality of pixel units 40; the driving component 10 is disposed in the bonding region 1022 and includes a first output unit 11; the multiplexing circuit 20 is disposed in the circuit region 1021 and includes a first circuit unit 21; the connection lines are connected between the driving component 10 and the multiplexing circuit 20 and include a first connection line 31 connected between the first circuit unit 21 and the first output unit 11; the plurality of pixel units 40 are disposed in the display region 101 and are connected to the plurality of multiplexing circuits 20.

[0047] Wherein, the first connection line 31 includes a winding segment 313 distributed in the display region 101.

[0048] During the implementation and application process, in the embodiment of the present invention, the first connection line 31 is disposed between the first circuit unit 21 and the first output unit 11, so that the signals in the driving component 10 are transmitted to the display region 101 through the multiplexing circuit 20. Furthermore, the number of the first connection lines 31 can be reduced compared with the data lines in the related art, and by disposing the winding segment 313 in the first connection line 31, the first circuit unit 21 can be arranged according to a preset position. Furthermore, the winding of the fanout trace in the related art can be replaced by the winding segment 313 of the first connection line 31 between the multiplexing circuit 20 and the driving component 10 in the embodiment of the present invention, the number of windings can be reduced, the available space in the display region 101 can be increased, which is beneficial to improving the resolution of the display panel; further, the winding segment 313 in the first connection line 31 is located in the display region 101, avoiding the winding segment 313 occupying the space of the circuit region 1021, and thus the wiring space outside the display region 101 can be reduced, and further the frame width of the display panel can be reduced, and a narrow-bezel display panel can be realized.

[0049] Specifically, please continue to refer to Figure 1 and Figure 2 , the display panel provided by the embodiment of the present invention includes a display region 101 and a non-display region 102 adjacent to the display region 101, and the non-display region 102 can be disposed around the display region 101; and the non-display region 102 can include a bonding region 1022 located on at least one side of the display region 101 and a circuit region 1021 located between the bonding region 1022 and the display region 101.

[0050] Further, the display panel further includes a plurality of pixel units 40 disposed in the display region 101, a driving component 10 disposed in the bonding region 1022, a multiplexing circuit 20 disposed in the circuit region 1021, and a plurality of connection lines.

[0051] Among them, a plurality of pixel units 40 are arranged in an array along a first direction M and a second direction N, and the first direction M is the direction from the bonding area 1022 to the display area 101, and the second direction N intersects the first direction M.

[0052] In one embodiment, the first direction M is perpendicular to the second direction N.

[0053] The plurality of pixel units 40 can be divided into a plurality of pixel unit groups arranged along the second direction N, and each pixel unit group includes a plurality of pixel units 40 arranged along the first direction M, that is, each pixel unit group includes a column of pixel units 40 arranged along the first direction M.

[0054] The driving component 10 includes a plurality of first output units 11 and a plurality of second output units 12; in one embodiment, the plurality of first output units 11 and the plurality of second output units 12 can be arranged on the side of the driving component 10 close to the display area 101.

[0055] The multiplexing circuit 20 includes a plurality of first circuit units 21 and a plurality of second circuit units 22, and the connection lines include a plurality of first connection lines 31 and a plurality of second connection lines 32. Among them, the first output unit 11 is connected to the first circuit unit 21 through the first connection line 31, and the second output unit 12 is connected to the second circuit unit 22 through the second connection line 32.

[0056] Among them, the first connection line 31 includes a first line segment 311 connected to the first output unit 11 and extending from the bonding area 1022 into the circuit area 1021, a second line segment 312 extending into the circuit area 1021 and connected to the first circuit unit 21, and a winding line segment 313 connected between the first line segment 311 and the second line segment 312 and located in the display area 101; one end of the second connection line 32 is connected to the second output unit 12, and the opposite end is connected to the second circuit unit 22.

[0057] In the embodiment of the present invention, a pixel unit group is arranged opposite to a first circuit unit 21 or a second circuit unit 22 along the first direction M, and the display panel further includes a plurality of data line groups arranged in the display area 101 along the first direction M. A data line group is connected to a first circuit unit 21 or a second circuit unit 22 along the first direction M, a data line group is connected to a pixel unit group, each data line group includes at least two data lines 50, and at least two data lines 50 are connected to the pixel units 40 in the corresponding pixel unit group.

[0058] In one embodiment, the number of data lines 50 in the data line group is four.

[0059] It can be understood that a first circuit unit 21 is connected through a first connection line 31, and then the signal is transmitted to at least two data lines 50 through the first circuit unit 21, or a second circuit unit 22 is connected through a second connection line 32, and then the signal is transmitted to at least two data lines 50 through the second circuit unit 22, so as to realize the multiplexing function of the multiplexing circuit 20.

[0060] The length of the binding area 1022 along the second direction N is shorter than the length of the circuit area 1021 along the second direction N, and thus part of the driving component 10 and part of the multiplexing circuit 20 cannot be aligned; in one embodiment, the circuit area 1021 includes a second sub-area 1032 arranged to be aligned with the binding area 1022 and a first sub-area 1031 connected to the second sub-area 1032 along the second direction N.

[0061] In an embodiment of the present invention, the first circuit unit 21 is disposed in the first sub-region 1031, and the second circuit unit 22 is disposed in the second sub-region 1032, so that the first circuit unit 21 and the second circuit unit 22 can be aligned with the corresponding pixel unit group along the first direction M, thereby avoiding the need to additionally set fan-out lines for each data line in the display area 101 for winding, thereby saving wiring space and reducing signal interference.

[0062] It should be noted that, in an embodiment of the present invention, the display panel may include a substrate, a thin film transistor layer arranged on the substrate, a conductive layer arranged on the side of the thin film transistor layer away from the substrate, and a light-emitting device layer arranged on the side of the conductive layer away from the thin film transistor layer. Further, the light-emitting device layer includes an anode layer arranged on the side of the conductive layer away from the thin film transistor layer, a light-emitting layer arranged on the side of the anode layer away from the conductive layer, and a cathode layer arranged on the side of the light-emitting layer away from the anode layer. The winding segment 313 of the first connecting line 31 may be located in the conductive layer, and the winding segment 313 may overlap with each pixel unit 40 without affecting the normal light emission of the pixel unit 40. In addition, the thin film transistor layer includes a display thin film transistor arranged in each pixel unit 40, and the display thin film transistor includes a source and drain electrode. The conductive layer may further include a transition portion connected between the source and drain electrodes and the anode layer, and the winding segment 313 is spaced apart from the transition portion.

[0063] In one embodiment, the first output unit 11 and the first circuit unit 21 are staggered along the first direction M, the second output unit 12 and the second circuit unit 22 are aligned along the first direction M, a first connecting line 31 connects a first circuit unit 21, and a second connecting line 32 connects a second circuit unit 22.

[0064] Please combine Figure 1 、 Figure 3 as well asFigure 4 The first circuit unit 21 includes a first multiplexed thin-film transistor T1 located in the thin-film transistor layer, and the first multiplexed thin-film transistor T1 includes an active layer, a gate, a source, and a drain. The second circuit unit 22 includes a second multiplexed thin-film transistor T2 located in the thin-film transistor layer, and the second multiplexed thin-film transistor T2 includes an active layer, a gate, a source, and a drain.

[0065] In the multiplexing circuit 20, for the first circuit unit 21, a first connection line 31 is connected to the sources of multiple first multiplexed thin-film transistors T1, a data line 50 is connected to the drain of one first multiplexed thin-film transistor T1, and a first control line 61 is connected to the gate of one first multiplexed thin-film transistor T1. Further, in the first circuit unit 21, multiple first control lines 61 can be used to selectively turn on or off multiple first multiplexed thin-film transistors T1, so that a first connection line 31 and multiple first thin-film transistors T1 transmit signals to multiple data lines 50, and Figure 3 Taking the example that one first circuit unit 21 is connected to four data lines 50. Similarly, for the second circuit unit 22, a second connection line 32 is connected to the sources of multiple second multiplexed thin-film transistors T2, a data line 50 is connected to the drain of one second multiplexed thin-film transistor T2, and a second control line 62 is connected to the gate of one second multiplexed thin-film transistor T2. Further, in the second circuit unit 22, multiple second control lines 62 can be used to selectively turn on or off multiple second multiplexed thin-film transistors T2, so that a second connection line 32 and multiple second thin-film transistors T2 transmit signals to multiple data lines 50, and Figure 4 Taking the example that one second circuit unit 22 is connected to four data lines 50. It can be understood that, please combine Figure 1 and Figure 3 Since the first connection line 31 is connected to the first circuit unit 21 via a first line segment 311, a winding line segment 313, and a second line segment 312 in sequence, and the second line segment 312 is arranged offset from the corresponding first circuit unit 21 in the first direction M, the winding line segment 313 is bent within the display area 101 and then wound back to be connected to the second line segment 312, so that the second line segment 312 can be aligned with the corresponding first circuit unit 21 in the first direction M. Further, the second line segment 312 extends from the boundary of the display area 101 into the first circuit unit 21 and is connected to the source of the first multiplexed thin-film transistor T1, and extends into the first circuit unit 21 in the same direction as the data line 50, as Figure 3 shown.

[0066] It can be understood that, Figure 3 and Figure 4It is only a schematic diagram of the distribution of the first circuit unit 21 and the second circuit unit 22 provided in the embodiments of the present invention, as well as the circuit lines, which can be specifically adjusted according to actual requirements and are not limited herein.

[0067] Further, the first output unit 11 and the second circuit unit 22 can be arranged in alignment along the first direction M; it should be noted that both the first line segment 311 and the second line segment 312 are located in the conductive layer. When the first line segment 311 extends from the bonding area 1022 into the circuit area 1021, it can pass through the second circuit unit 22, that is, the second line segment 312 can partially overlap with the second circuit unit 22 and can also partially overlap with the second multiplexing thin film transistor T2.

[0068] It should be noted that in the embodiments of the present invention, the first circuit unit 21 and the second circuit unit 22 are arranged in the area aligned with the corresponding pixel unit group, and then the connection between the first circuit unit 21 and the first output unit 11 and the connection between the second circuit unit 22 and the second output unit 12 are realized through the first connection line 31 and the second connection line 32. Since the first output unit 11 and the first circuit unit 21 are arranged staggeredly along the first direction M, there will be a line segment intersecting the first direction M in the first connection line 31, such as the winding line segment 313.

[0069] Continuing from the above, both the first line segment 311 and the second line segment 312 extend along the first direction M. The first line segment 311 and the second line segment 312 are arranged offset from each other along the first direction M and are distributed in a bent shape around the line segment 313 within the display area 101. That is, in the embodiment of the present invention, the first line segment 311 and the second line segment 312 of the first connection line 31 located outside the display area 101 are set as straight line segments, while the winding line segment 313 in the form of a curve or a broken line is arranged within the display area 101. Thus, the wiring space outside the display area 101 can be effectively reduced to narrow the border width. In addition, in the embodiment of the present invention, by arranging a winding in the first connection line 31 between the first output unit 11 and the first circuit unit 21, while realizing signal transmission, the first circuit unit 21 can be arranged in alignment with the corresponding pixel unit group along the first direction M. Then, the data lines 50 within the data line group corresponding to the pixel unit group can be connected to the corresponding first circuit unit 21 along the first direction M. Since there are at least two data lines 50 in each data line group, for example, there can be four. Compared with the related art, in the related art, multiple fanout traces corresponding one by one to the multiple data lines 50 need to be arranged for winding. However, in the embodiment of the present invention, the winding of the fanout traces is replaced by the winding line segment 313 in the first connection line 31 between the first circuit unit 21 and the first output unit 11, and the number of the first connection lines 31 is less than the number of the data lines 50, that is, less than the number of the fanout traces in the related art. This avoids the winding of a large number of fanout traces within the display area 101 and instead arranges the winding for a smaller number of first connection lines 31. Thus, the winding space within the display area 101 is reduced, the wiring difficulty is simplified, and the signal interference is reduced.

[0070] In addition, since the second output unit 12 and the second circuit unit 22 are arranged in alignment with each other along the first direction M, the second connection line 32 is connected between the second output unit 12 and the second circuit unit 22 along the first direction M.

[0071] Furthermore, the multiple winding line segments 313 in the multiple first connection lines 31 do not intersect, so as to reduce the wiring difficulty.

[0072] In one embodiment, the plurality of connection lines includes at least one winding group. A winding group includes a plurality of winding segments 313, and within one winding group, the plurality of winding segments 313 are nested one by one. The plurality of winding segments 313 in the plurality of first connection lines 31 are nested one by one, that is, the plurality of winding segments 313 are arranged in loops; the winding segments 313 in the first connection line 31 connected to the first circuit unit 21 on the side closer to the second sub-region 1032 are located inside the loop, and the winding segments 313 in the first connection line 31 connected to the first circuit unit 21 on the side farther from the second sub-region 1032 are located outside the loop. Further, the length of the winding segments 313 of the first connection line 31 connected to the first circuit unit 21 on the side farther from the second sub-region 1032 is greater than the length of the winding segments 313 of the first connection line 31 connected to the first circuit unit 21 on the side closer to the second sub-region 1032.

[0073] In one embodiment, please refer to Figure 1 , within the driving assembly 10, there is at least one second output unit 12 spaced between two first output units 11. For example, there is one second output unit 12 spaced between two first output units 11. In addition, the plurality of second output units 12 includes an edge second output unit 121 located at the end of the driving assembly 10, and the first output unit 11 connected to the first circuit unit 21 on the side farther from the second sub-region 1032 is located on the side of the first output unit 11 connected to the first circuit unit 21 on the side closer to the second sub-region 1032 and farther from the edge second output unit 121; further, among the plurality of second output units 12 close to the edge second output unit 121, there is one first output unit 11 spaced between two adjacent second output units 12, and among the plurality of second output units 12 far from the edge second output unit 121, the plurality of second output units 12 are arranged adjacent to each other.

[0074] Continuing from the above, in one embodiment of the present invention, please combine Figure 2 and Figure 5, where P1 to P610 are multiple circuit units in the multiplexing circuit 20, and S1 to S610 are multiple output units in the driving component 10; among them, P1 to P200 are the first circuit unit 21, P201 to P610 are the second circuit unit 22, S1 to S200 are the first output unit 11, and S201 to S610 are the second output unit 12. In the embodiment of the present invention, multiple circuit units of P1 to P610 can be aligned according to their respective corresponding data line groups or pixel unit groups, so that multiple circuit units of P1 to P610 are arranged in sequence; further, the edge second output unit 121 at the end of the driving component 10 is S201, and the ones arranged in sequence to the right starting from S201 are S201, S202, S199... S399, S2, S400, S1, S401, S402... S609, S610. Among them, multiple second output units 12 include S201 to S610, and multiple second output units 12 are arranged in sequence; multiple first output units 11 include S1 to S200 and multiple first output units 11 are arranged in reverse order.

[0075] Since P1 connected to S1 is located at the position in the first sub-region 1031 that is farthest from the second sub-region 1032, therefore, the length of the winding segment 313 corresponding to S1 is the largest, so that S1 is located at the position in S1 to S200 that is farthest from S201. P200 connected to S200 is located at the position in the first sub-region 1031 that is closest to the second sub-region 1032. Therefore, the length of the winding segment 313 corresponding to S2 is the smallest, so that S200 is adjacent to S201. Similarly, the remaining first output units 11 are arranged according to the positions of the first circuit units 21 they are connected to, so that S1 to S200 are arranged in reverse order from left to right, and the end of the driving component 10 is the edge second output unit 121 (S210). Among them, there is S200 between S201 and S202, there is S199 between S202 and S203 (not shown in the figure), there is S2 between S399 and S400, and there is S1 between S400 and S401. Continuing from the above, in the embodiment of the present invention, by arranging the first output units 11 in reverse order and the second output units 12 in sequence in the driving component 10, and arranging the first output units 11 and the second output units 12 in a disordered and alternating manner, and cooperating with the multiple winding segments 313 nested in the first connection line 31, multiple circuit units P1 to P610 can be arranged in sequence, that is, the circuit units can be aligned with the corresponding data line groups or pixel unit groups.

[0076] Further, please refer to Figure 6 , where Figure 6The first connection lines 31, the second connection lines 32, the driving component 10, and the multiplexing circuit 20 on the left and right sides in the [description] are arranged symmetrically. It can be understood that Figure 6 Multiple winding segments 313 on the left side in the [description] form a winding group, and Figure 6 Multiple winding segments 313 on the right side in the [description] form a winding group; similarly, the connections between the multiplexing circuit 20, the pixel unit group, and the data line group are the same, which will not be elaborated here.

[0077] In summary, in the embodiment of the present invention, the first line segment 311 and the second line segment 312 of the first connection line 31 located outside the display area 101 are set as straight line segments, while the winding segments 313 in the form of curves or broken lines are arranged in the display area 101, thereby effectively reducing the wiring space outside the display area 101 to reduce the frame width; in addition, in the embodiment of the present invention, by setting windings in the first connection line 31 between the first output unit 11 and the first circuit unit 21, while realizing signal transmission, the first circuit unit 21 can be arranged in alignment with the corresponding pixel unit group along the first direction M, and then the data lines 50 in the data line group corresponding to the pixel unit group can be connected to the corresponding first circuit unit 21 along the first direction M. Since there are at least two data lines 50 in each data line group, for example, there can be four, and the embodiment of the present invention avoids winding a large number of data lines 50 in the display area 101, but makes a small number of first connection lines 31 wind, thereby reducing the winding layout space in the display area 101, simplifying the wiring difficulty, and reducing signal interference.

[0078] In addition, the embodiment of the present invention further provides a display device, and the display device includes the display panel described in the above embodiment.

[0079] Since the display device is provided with the display panel provided in the above embodiment of the present invention, the display device has the same beneficial effects as the above display panel.

[0080] In one embodiment, the display device may include a television, a computer, a mobile phone, a tablet, and other display devices.

[0081] In the above embodiments, the descriptions of each embodiment have their own emphases. For the parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0082] The above has introduced in detail a display panel and a display device provided by an embodiment of the present invention. Specific examples are used herein to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only for helping to understand the technical solution and its core idea of the present invention; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, The display panel includes a display area, a bonding area, and a circuit area located between the display area and the bonding area; The display panel further includes: A driving component, disposed in the bonding area and including a first output unit; A multiplexing circuit, disposed in the circuit area and including a first circuit unit; A connection line, connecting between the driving component and the multiplexing circuit, and including a first connection line connecting between the first circuit unit and the first output unit; A plurality of pixel units, disposed in the display area and connected to the multiplexing circuit; the plurality of pixel units include a plurality of pixel unit groups arranged along a second direction, and each pixel unit group includes a plurality of the pixel units arranged along a first direction; the first direction and the second direction intersect; one pixel unit group is arranged opposite to the first circuit unit along the first direction; A plurality of data line groups, disposed in the display area, and one data line group is connected to one pixel unit group; each data line group includes at least two data lines extending along the first direction, the data lines are connected to the pixel units in the corresponding pixel unit group, and one data line group is connected to a corresponding first circuit unit along the first direction; Wherein, the first connection line includes a winding segment distributed in the display area, and the first connection line further includes a first segment extending from the bonding area to the circuit area and connected to the first output unit, and a second segment extending from the boundary of the display area to the circuit area and connected to the first circuit unit, and the winding segment is connected between the first segment and the second segment; Both the first segment and the second segment extend along the first direction, and the first direction is the direction from the bonding area to the display area, the first segment and the second segment are offset from each other along the first direction, and the winding segment is distributed in a bent shape in the display area.

2. The display panel according to claim 1, wherein The first output unit and the first circuit unit are offset from each other along the first direction.

3. The display panel according to claim 1, wherein The multiplexing circuit includes a plurality of second circuit units, the plurality of first circuit units and the plurality of second circuit units are arranged along the second direction, the driving component includes a plurality of second output units, the plurality of first output units and the plurality of second output units are arranged along the second direction, and the connection line further includes a plurality of second connection lines; Wherein, the second connection line extends along the first direction and is connected between the second circuit unit and the second output unit.

4. The display panel according to claim 3, wherein, The connection line includes a plurality of the first connection lines, and the winding segments of the plurality of first connection lines do not intersect.

5. The display panel according to claim 4, wherein The connection line includes at least one winding group, and one winding group includes a plurality of the winding segments, and in one winding group, the plurality of winding segments are nested one by one.

6. The display panel according to claim 3, wherein The length of the bonding region along the second direction is less than the length of the circuit region along the second direction, and the circuit region includes a first sub-region and a second sub-region. The second sub-region is arranged in alignment with the bonding region along the first direction, and the first sub-region is connected to the second sub-region along the second direction. Among them, a plurality of the first circuit units are distributed in the first sub-region, and a plurality of the second circuit units are distributed in the second sub-region.

7. The display panel according to claim 6, characterized in that, A plurality of the second output units include edge second output units located at the end of the driving component. The first output unit connected to the first circuit unit on the side far from the second sub-region is located on the side away from the edge second output unit with respect to the first output unit connected to the first circuit unit on the side close to the second sub-region.

8. The display panel according to claim 7, wherein Inside the driving component, among the plurality of second output units close to the edge second output unit, there is one first output unit spaced between adjacent two of the second output units. Among the plurality of second output units far from the edge second output unit, the plurality of second output units are arranged adjacent to each other.

9. The display panel according to claim 6, wherein The length of the winding segment of the first connection line connected to the first circuit unit on the side far from the second sub-region is greater than the length of the winding segment of the first connection line connected to the first circuit unit on the side close to the second sub-region.

10. The display panel according to claim 3, wherein, The second circuit unit and the second output unit are arranged in alignment with each other along the first direction.

11. The display panel according to claim 3, wherein One pixel unit group is arranged in alignment with one second circuit unit along the first direction.

12. The display panel according to claim 11, wherein One data line group is connected to a corresponding one of the second circuit units along the first direction.

13. The display panel according to claim 12, wherein The display panel includes a substrate and a thin film transistor layer provided on the substrate. The first circuit unit includes a plurality of first multiplexed thin film transistors located in the thin film transistor layer, and the second circuit unit includes a plurality of second multiplexed thin film transistors located in the thin film transistor layer. Among them, one first connection line is connected to the sources of a plurality of the first multiplexed thin film transistors, one data line is connected to the drain of one first multiplexed thin film transistor, one second connection line is connected to the sources of a plurality of the second multiplexed thin film transistors, and one data line is connected to the drain of one second multiplexed thin film transistor.

14. The display panel according to claim 13, wherein The display panel further includes a conductive layer provided on the side of the thin film transistor layer away from the substrate, and a light emitting device layer provided on the side of the conductive layer away from the thin film transistor layer. Among them, the conductive layer includes the first line segment, the second line segment, and the winding segment.

15. The display panel according to claim 13, wherein The first line segment partially overlaps with the second circuit unit, and the second line segment extends from the boundary of the display region to the first circuit unit and is connected to the source of the first multiplexed thin film transistor.

16. A display device, characterized in that, The display device includes the display panel according to any one of claims 1 to 15.

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