Gate driving unit and display device

Abstract

The application provides a gate driving unit and a display device, wherein a pull-up control module of a gate driving circuit receives a gate control signal output by a higher-level gate driving circuit, so that a level transmission module is omitted in the gate driving circuit, the level transmission control of a multi-level gate driving circuit is realized, the number of transistors used in the gate driving circuit is reduced, and the layout space occupied by the gate driving circuit is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a gate driving unit and a display device. BACKGROUND

[0002] The existing gate driving unit usually needs 15 thin film transistors to realize the function of outputting square wave pulse signals row by row, occupies a large layout space of the display panel, and is not conducive to realizing the narrow frame design of the display panel. Moreover, compared with applying the gate driving circuit to a large-size display device, applying the gate driving circuit with the same topological structure to a small-size display device, the degree of layout space occupation of the gate driving circuit to the sub-pixel in the small-size display device is greater than that in the large-size display device, which affects the display effect of the small-size display device. SUMMARY

[0003] The embodiments of the present application provide a gate driving unit and a display device, which can improve the problem that the gate driving circuit occupies a large layout space, is not conducive to realizing the narrow frame design of the display panel, and the layout space of the gate driving circuit to the sub-pixel is seriously occupied when the gate driving circuit is applied to a small-size display device.

[0004] The embodiments of the present application provide a gate driving unit, which comprises a plurality of cascaded gate driving circuits, and at least one of the gate driving circuits comprises an up pull control module, an up pull module, a down pull maintenance module and a down pull module. The up pull control module is electrically connected with a first node, and the up pull control module is configured to receive a gate control signal output by a higher-level gate driving circuit and transmit a first power supply signal to the first node. The up pull module is electrically connected with the first node, and the up pull module is configured to transmit a first clock signal to a signal output end of the gate driving circuit of the present level according to the potential of the first node. The down pull maintenance module is electrically connected with the first node, and the down pull maintenance module is configured to transmit a second power supply signal to the first node according to a second clock signal and a third clock signal. The down pull module is electrically connected with the first node, and the down pull module is configured to transmit the second power supply signal to the first node according to a gate control signal output by a lower-level gate driving circuit.

[0005] Optionally, in some embodiments of the present application, the up pull control module comprises an up pull control transistor, a control end of the up pull control transistor is configured to receive the gate control signal output by the higher-level gate driving circuit, an input end of the up pull control transistor is configured to receive the first power supply signal, and an output end of the up pull control transistor is electrically connected with the first node.

[0006] Optionally, in some embodiments of the present application, the pull-up module comprises a pull-up transistor and a storage capacitor, a control end of the pull-up transistor is electrically connected with the first node, an input end of the pull-up transistor is configured to receive the first clock signal, and an output end of the pull-up transistor is electrically connected with the signal output end of the gate drive circuit of the current stage; the storage capacitor is connected in series between the control end of the pull-up transistor and the output end of the pull-up transistor.

[0007] Optionally, in some embodiments of the present application, the pull-down maintaining module comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor. A control end of the first transistor is configured to receive the third clock signal, and an input end of the first transistor is configured to receive the third power supply signal. A control end of the second transistor is electrically connected with the first node, an output end of the second transistor is electrically connected with an output end of the first transistor, and an input end of the second transistor is configured to receive the second power supply signal. A control end of the third transistor is electrically connected with the output end of the first transistor, and an input end of the third transistor is configured to receive the third power supply signal. A control end of the fourth transistor is electrically connected with the first node, an input end of the fourth transistor is configured to receive the second power supply signal, and an output end of the fourth transistor is electrically connected with an output end of the third transistor. A control end of the fifth transistor is electrically connected with the output end of the third transistor, an input end of the fifth transistor is configured to receive the second power supply signal, and an output end of the fifth transistor is electrically connected with the first node. A control end of the sixth transistor is configured to receive the second clock signal, an input end of the sixth transistor is configured to receive the second power supply signal, and an output end of the sixth transistor is electrically connected with the control end of the fifth transistor.

[0008] Optionally, in some embodiments of the present application, the pull-down maintaining module further comprises a seventh transistor, a control end of the seventh transistor is configured to receive the second clock signal, an input end of the seventh transistor is configured to receive the second power supply signal, and an output end of the seventh transistor is electrically connected with the control end of the third transistor.

[0009] Optionally, in some embodiments of the present application, the pull-down maintaining module further comprises an eighth transistor, a control end of the eighth transistor is electrically connected with the control end of the fifth transistor, an input end of the eighth transistor is configured to receive the second power supply signal, and an output end of the eighth transistor is electrically connected with the signal output end of the gate drive circuit of the current stage.

[0010] Optionally, in some embodiments of the present application, the gate drive unit further comprises a reset module, the reset module comprising a reset transistor, a control end of the reset transistor being configured to receive a reset control signal, an input end of the reset transistor being configured to receive the third power signal, and an output end of the reset transistor being electrically connected with the control end of the fifth transistor.

[0011] Optionally, in some embodiments of the present application, the pull-down module comprises a pull-down transistor, a control end of the pull-down transistor being configured to receive the gate control signal output by a lower-level gate drive circuit, an input end of the pull-down transistor being configured to receive the second power signal, and an output end of the pull-down transistor being electrically connected with the signal output end of the gate drive circuit of the present level.

[0012] Optionally, in some embodiments of the present application, the pull-up control module of the gate drive circuit of the Nth level receives the gate control signal output by the gate drive circuit of the N-Xth level before the gate drive circuit of the Nth level, and the pull-down module of the gate drive circuit of the Nth level receives the gate control signal output by the gate drive circuit of the N+Yth level after the gate drive circuit of the Nth level; wherein Y>X, N>1, and X>0.

[0013] The present application further provides a display device comprising any of the above-mentioned gate drive units and a plurality of sub-pixels, wherein the plurality of sub-pixels are electrically connected with the plurality of gate drive circuits.

[0014] The embodiments of the present application provide a gate drive unit and a display device, by making the pull-up control module of the gate drive circuit receive the gate control signal output by the upper-level gate drive circuit, so that the level transmission module is omitted in the gate drive circuit, the level transmission control of the multi-level gate drive circuit is realized, the number of transistors used in the gate drive circuit is reduced, and the layout space occupied by the gate drive circuit is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0016] Figure 1 is a structural schematic diagram of the gate drive unit provided by the embodiments of the present application;

[0017] Figures 2A-2B is a structural schematic diagram of the gate drive circuit provided by the embodiments of the present application;

[0018] Figure 3 is a timing diagram corresponding to the gate drive circuit provided by the embodiment of the present application;

[0019] Figures 4A-4B is a simulation diagram corresponding to the gate drive circuit provided by the embodiment of the present application;

[0020] Figure 5 is a structural schematic diagram of the display device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application. In addition, it should be understood that the specific embodiments described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, the positional words such as "upper" and "lower" generally refer to the upper and lower in the actual use or working state of the device, and specifically refer to the direction of the drawing in the drawings; and "inner" and "outer" refer to the outline of the device.

[0022] Specifically, Figure 1 is a structural schematic diagram of the gate drive unit provided by the embodiment of the present application. The embodiment of the present application provides a gate drive unit, which includes a plurality of cascaded gate drive circuits 10. The plurality of cascaded gate drive circuits 10 are configured to generate a plurality of gate control signals Scan.

[0023] Figures 2A-2B is a structural schematic diagram of the gate drive circuit provided by the embodiment of the present application. At least one of the gate drive circuits 10 includes a pull-up control module 101, a pull-up module 102, a pull-down maintenance module 103, and a pull-down module 104.

[0024] The pull-up control module 101 is electrically connected with a first node Q. The pull-up control module 101 is configured to receive a gate control signal output by a superior gate drive circuit, and transmit a first power signal VGH to the first node Q to raise the potential of the first node Q.

[0025] Optionally, the pull-up control module 101 comprises a pull-up control transistor Tuc, a control terminal of the pull-up control transistor Tuc is configured to receive the gate control signal output by the upper-stage gate drive circuit, an input terminal of the pull-up control transistor Tuc is configured to receive the first power signal VGH, and an output terminal of the pull-up control transistor Tuc is electrically connected with the first node Q, and the pull-up control transistor Tuc is configured to transmit the first power signal VGH to the first node Q according to the gate control signal output by the upper-stage gate drive circuit, so as to raise the potential of the first node Q in the Nth-stage gate drive circuit.

[0026] Optionally, the pull-up control module 101 of the Nth-stage gate drive circuit receives a gate control signal Scan(N-X) output by an N-Xth-stage gate drive circuit in front of the Nth-stage gate drive circuit, so as to transmit the first power signal VGH to the first node Q of the Nth-stage gate drive circuit according to the gate control signal Scan(N-X) output by the N-Xth-stage gate drive circuit, and raise the potential of the first node Q in the Nth-stage gate drive circuit. Wherein, X>0.

[0027] Optionally, the pull-up control module 101 in the first gate drive circuit in the multi-stage gate drive circuit can receive a start signal, so as to transmit the first power signal VGH to the first node Q according to the start signal, and raise the potential of the first node Q in the first gate drive circuit.

[0028] Please continue to refer to Figures 2A-2B , the pull-up module 102 is electrically connected with the first node Q, and the pull-up module 102 is configured to transmit the first clock signal CK1 to a signal output terminal of the gate drive circuit 10 in the current stage according to the potential of the first node Q, and the signal output terminal is configured to output the gate control signal Scan.

[0029] Optionally, the pull-up module 102 comprises a pull-up transistor To and a storage capacitor Cst.

[0030] A control terminal of the pull-up transistor To is electrically connected with the first node Q, an input terminal of the pull-up transistor To is configured to receive the first clock signal CK1, an output terminal of the pull-up transistor To is electrically connected with the signal output terminal of the gate drive circuit 10 in the current stage, and the pull-up transistor To is configured to be turned on or turned off according to the potential of the first node Q, so as to transmit the first clock signal CK1 to the signal output terminal of the gate drive circuit 10 in the current stage when the pull-up transistor To is turned on, and make the gate control signal Scan output by the signal output terminal of the gate drive circuit 10 in the current stage have an effective pulse.

[0031] The storage capacitor Cst is connected in series between the control end of the pull-up transistor To and the output end of the pull-up transistor To, and the storage capacitor Cst is used to maintain the potential of the first node Q.

[0032] Please continue to refer to Figures 2A-2B The pull-down maintaining module 103 is electrically connected with the first node Q, and the pull-down maintaining module 103 is configured to transmit a second power supply signal VSSQ to the first node Q according to a second clock signal CK2 and a third clock signal CK3.

[0033] Optionally, the pull-down maintaining module 103 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6.

[0034] The control end of the first transistor T1 is configured to receive the third clock signal CK3, and the input end of the first transistor T1 is configured to receive a third power supply signal VDD.

[0035] The control end of the second transistor T2 is electrically connected with the first node Q, the output end of the second transistor T2 is electrically connected with the output end of the first transistor T1, and the input end of the second transistor T2 is configured to receive the second power supply signal VSSQ.

[0036] The control end of the third transistor T3 is electrically connected with the output end of the first transistor T1, and the input end of the third transistor T3 is configured to receive the third power supply signal VDD.

[0037] The control end of the fourth transistor T4 is electrically connected with the first node Q, the input end of the fourth transistor T4 is configured to receive the second power supply signal VSSQ, and the output end of the fourth transistor T4 is electrically connected with the output end of the third transistor T3.

[0038] The control end of the fifth transistor T5 is electrically connected with the output end of the third transistor T3, the input end of the fifth transistor T5 is configured to receive the second power supply signal VSSQ, and the output end of the fifth transistor T5 is electrically connected with the first node Q.

[0039] The control end of the sixth transistor T6 is configured to receive the second clock signal CK2, the input end of the sixth transistor T6 is configured to receive the second power supply signal VSSQ, and the output end of the sixth transistor T6 is electrically connected with the control end of the fifth transistor T5.

[0040] Optionally, the pull-down maintaining module 103 further comprises a seventh transistor T7, a control terminal of the seventh transistor T7 is configured to receive the second clock signal CK2, an input terminal of the seventh transistor T7 is configured to receive the second power supply signal VSSQ, and an output terminal of the seventh transistor T7 is electrically connected with the control terminal of the third transistor T3, and the seventh transistor T7 is configured to turn on or turn off according to the second clock signal CK2, so as to control the third transistor T3 to turn off through the second power supply signal VSSQ when the seventh transistor T7 turns on.

[0041] Optionally, the pull-down maintaining module 103 further comprises an eighth transistor T8, a control terminal of the eighth transistor T8 is electrically connected with the control terminal of the fifth transistor T5, an input terminal of the eighth transistor T8 is configured to receive the second power supply signal VSSQ, and an output terminal of the eighth transistor T8 is electrically connected with the signal output terminal of the gate drive circuit at the current stage. The eighth transistor T8 is configured to turn on synchronously with the fifth transistor T5, so as to pull down the potential of the signal output terminal of the gate drive circuit 10 through the second power supply signal VSSQ.

[0042] Please continue to refer to Figures 2A-2B The pull-down module 104 is electrically connected with the first node Q, and the pull-down module 104 is configured to transmit the second power supply signal VSSQ to the first node Q according to the gate control signal output by the gate drive circuit at the next stage.

[0043] Optionally, the pull-down module 104 comprises a pull-down transistor Td, a control terminal of the pull-down transistor Td is configured to receive the gate control signal output by the gate drive circuit at the next stage, an input terminal of the pull-down transistor Td is configured to receive the second power supply signal VSSQ, and an output terminal of the pull-down transistor Td is electrically connected with the signal output terminal of the gate drive circuit at the current stage. The pull-down transistor Td is configured to turn on or turn off according to the gate control signal output by the gate drive circuit at the next stage, so as to transmit the second power supply signal VSSQ to the first node Q to pull down the potential of the first node Q when the pull-down transistor Td turns on.

[0044] Optionally, the pull-down module of the Nth-stage gate drive circuit receives the gate control signal Scan(N+Y) output by the N+Yth-stage gate drive circuit located after the Nth-stage gate drive circuit, so that the pull-down module of the Nth-stage gate drive circuit pulls down the potential of the first node Q of the Nth-stage gate drive circuit according to the gate control signal Scan(N+Y) output by the N+Yth-stage gate drive circuit; wherein Y>0.

[0045] Optionally, the pull-up control module of the Nth-stage gate drive circuit receives a gate control signal Scan(N-X) output by an N-Xth-stage gate drive circuit in front of the Nth-stage gate drive circuit, and the pull-down module of the Nth-stage gate drive circuit receives a gate control signal Scan(N+Y) output by an N+Yth-stage gate drive circuit behind the Nth-stage gate drive circuit. Y>X, so that the pull-up and pull-down of the potential of the first node Q of the Nth-stage gate drive circuit is in an asymmetric form, and the time length corresponding to the pull-down of the potential of the first node Q is less than the time length corresponding to the pull-up of the potential of the first node Q, which is beneficial to maintaining the stability of the potential of the first node Q.

[0046] Optionally, the pull-up control module of the Nth-stage gate drive circuit receives a gate control signal Scan(N-X) output by an N-Xth-stage gate drive circuit in front of the Nth-stage gate drive circuit, and the pull-down module of the Nth-stage gate drive circuit receives a gate control signal Scan(N+Y) output by an N+Yth-stage gate drive circuit behind the Nth-stage gate drive circuit. Y>X, so that the pull-up and pull-down of the potential of the first node Q of the Nth-stage gate drive circuit is in an asymmetric form, and the time length corresponding to the pull-down of the potential of the first node Q is less than the time length corresponding to the pull-up of the potential of the first node Q, which is beneficial to maintaining the stability of the potential of the first node Q.

[0047] Optionally, in order to save layout space and power consumption, the gate drive unit includes a plurality of gate drive circuits 10, and the plurality of gate drive circuits 10 share M clock signals. Optionally, X=M / 2.

[0048] Optionally, the gate drive unit further includes a reset module 105 configured to reset the potential of the first node Q according to a reset control signal Reset and a third power signal VDD. Optionally, the reset module 105 is configured to reset the potential of the signal output end according to the reset control signal Reset and the third power signal VDD.

[0049] Optionally, the reset module 105 includes a reset transistor Ti, a control end of the reset transistor Ti is configured to receive a reset control signal Reset, an input end of the reset transistor Ti is configured to receive the third power signal VDD, and an output end of the reset transistor Ti is electrically connected with a control end of the fifth transistor T5. The reset transistor Ti is configured to be turned on or turned off according to the reset control signal Reset, so that when the reset transistor Ti is turned on, the fifth transistor T5 and the eighth transistor T8 are turned on through the third power signal VDD, and the potential of the first node Q and the potential of the signal output end are reset through the second power signal VSSQ, and residual charges at the first node Q and the signal output end are cleared.

[0050] Optionally, when the gate driving unit is applied in a display panel, a reset control signal Reset can be provided with an effective pulse at the time of starting to reset the potential of the first node and the signal output end of the multi-stage gate driving circuit; and / or, the reset control signal Reset can be provided with an effective pulse in the blanking interval between frames to reset the potential of the first node and the signal output end of the multi-stage gate driving circuit. The effective pulse of the start signal received by the first gate driving circuit in the multi-stage gate driving circuit can be located after the effective pulse of the reset control signal Reset, so that each stage of the gate driving circuit can output a corresponding gate control signal Scan based on the same first node Q potential and signal output end potential, thereby improving the uniformity of the gate control signals Scan output by the plurality of gate driving circuits.

[0051] Optionally, the voltage value corresponding to the first power signal VGH is greater than the voltage value corresponding to the second power signal VSSQ.

[0052] Optionally, to prevent the potential of the second node P (i.e., the control end of the fifth transistor) from changing from low to high when the potential of the first node Q in the gate driving circuit 10 changes from high to low, the start time of the effective pulse of the second clock signal CK2 lags behind the start time of the effective pulse of the first clock signal CK1, the start time of the effective pulse of the third clock signal CK3 lags behind the start time of the effective pulse of the second clock signal CK2, and the effective pulse of the third clock signal CK3 does not overlap with the first clock signal CK1.

[0053] Optionally, to reduce the layout space and power consumption, the multi-stage gate driving circuit 10 can share a plurality of clock signals. Thus, the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 corresponding to each stage of the gate driving circuit 10 can be determined from the plurality of clock signals according to the number of stages in which the gate driving circuit 10 is located.

[0054] Optionally, the multi-stage gate driving circuit 10 shares M clock signals, the first clock signal CK1 received by the Nth stage of the gate driving circuit 10 is CK(m), the second clock signal CK2 received by the Nth stage of the gate driving circuit 10 is CK(m+A), and the third clock signal CK3 received by the Nth stage of the gate driving circuit 10 is CK(m+B). Wherein, 0 < m ≤ M, m < m+A ≤ M, m+A < m+B ≤ M, A > 0, and B > 0; when N ≤ M, m = N; when N > M, m = N-aM, m > 0, a > 0, and a is an integer.

[0055] Optionally, B=M / 2, so that the active pulse of the third clock signal CK3 and the active pulse of the first clock signal CK1 do not coincide (i.e. the third clock signal CK3 and the first clock signal CK1 form a mutual coupling), so that the potential of the first node Q is pulled down only after the gate control signal Scan output by the gate drive circuit 10 outputs an active pulse through the signal output terminal, avoiding affecting the output of the gate control signal Scan when the potential of the first node Q is pulled down.

[0056] Optionally, the difference between B and A can be 1-3, so that when the potential of the first node Q in the gate drive circuit 10 jumps from high level to low level, there is a larger voltage coincidence point with the jump of the potential of the second node P from low level to high level.

[0057] Optionally, A is 2, 3 or 4, and B is 4, 5, 6, 7, etc. Optionally, A is 2 and B is 6, so as to improve the risk of current and charging of the first node Q due to the larger voltage coincidence point between the jump of the potential of the first node Q in the gate drive circuit 10 from high level to low level and the jump of the potential of the second node P (i.e. the control end of the fifth transistor) from low level to high level.

[0058] Optionally, A and B can be determined according to the received upper gate control signal and lower gate control signal, so as to reduce the complexity of signal selection. For example, the upper pull-up control module of the Nth gate drive circuit receives the gate control signal Scan(N-X), and the pull-down module of the Nth gate drive circuit receives the upper gate control signal Scan(N+Y), so that B=X and A=Y-X.

[0059] Optionally, at least one of the pull-up control transistor Tuc, the pull-up transistor To, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the pull-down transistor Td and the reset transistor Ti included in the gate drive circuit 10 can be a silicon transistor or an oxide transistor.

[0060] For example, the gate drive circuit 10 can include a pull-up control transistor Tuc, a pull-up transistor To, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a pull-down transistor Td and a reset transistor Ti. Figure 3is a timing diagram corresponding to the gate drive circuit provided by the embodiment of the present application, 12 clock signals are shared by the multi-stage gate drive circuit 10, the first clock signal CK1 received by the Nth stage gate drive circuit is CK(m), the second clock signal CK2 received by the Nth stage gate drive circuit is CK(m+A), the third clock signal CK3 received by the Nth stage gate drive circuit is CK(m+B), the upper gate control signal received by the Nth stage gate drive circuit is Scan(N-X), the lower gate control signal received by the Nth stage gate drive circuit is Scan(N+Y), and the transistors included in the Nth stage gate drive circuit are taken as N-type transistors, and the working principle of the Nth stage gate drive circuit is described as follows.

[0061] In the reset stage before the multi-stage gate drive circuit 10 outputs a plurality of gate control signals Scan, the reset control signal Reset is high, the reset transistor Ti in the multi-stage gate drive circuit 10 is turned on, and then the eighth transistor T8 and the fifth transistor T5 are both turned on, so that the first node Q of the multi-stage gate drive circuit 10 is at a low potential and the second node P is at a high potential.

[0062] The first stage t1: the upper gate control signal Scan(N-X) is high, and the first clock signal CK(m), the second clock signal CK(m+A), the third clock signal CK(m+B) and the lower gate control signal Scan(N+Y) are low.

[0063] The pull-up control transistor Tuc is turned on, the first power signal VGH is transmitted to the first node Q through the pull-up control transistor Tuc to raise the potential of the first node Q, the second transistor T2, the fourth transistor T4 and the pull-up transistor To are turned on, so that the second node P potential is pulled down, and the third transistor T3, the fifth transistor T5 and the eighth transistor T8 are turned off according to the second power signal VSSQ; the first clock signal CK1 is transmitted to the signal output end, so that the gate control signal Scan(N) output by the signal output end has a low level.

[0064] The second stage t2: the upper gate control signal Scan(N-X) and the first clock signal CK(m) are high, and the second clock signal CK(m+A), the third clock signal CK(m+B) and the lower gate control signal Scan(N+Y) are low.

[0065] The first node Q potential is further raised by the coupling of the first clock signal CK(m) changing from low level to high level, so that the second transistor T2, the fourth transistor T4 and the pull-up transistor To remain conductive, the third transistor T3, the fifth transistor T5 and the eighth transistor T8 remain cut-off; the first clock signal CK1 is transmitted to the signal output end, so that the gate control signal Scan(N) output by the signal output end has high level.

[0066] The third stage t3: the first clock signal CK(m) is high level, the upper gate control signal Scan(N-X), the second clock signal CK(m+A), the third clock signal CK(m+B) and the lower gate control signal Scan(N+Y) are low level.

[0067] The storage capacitor Cst maintains the potential of the first node Q, so that the second transistor T2, the fourth transistor T4 and the pull-up transistor To remain conductive, the third transistor T3, the fifth transistor T5 and the eighth transistor T8 remain cut-off; the first clock signal CK1 is transmitted to the signal output end, so that the gate control signal Scan(N) output by the signal output end still has high level.

[0068] The fourth stage t4: the first clock signal CK(m) and the second clock signal CK(m+A) are high level, the upper gate control signal Scan(N-X), the third clock signal CK(m+B) and the lower gate control signal Scan(N+Y) are low level.

[0069] The sixth transistor T6, the seventh transistor T7 are conductive according to the second clock signal CK(m+A), the storage capacitor Cst maintains the potential of the first node Q, so that the third transistor T3, the fifth transistor T5 and the eighth transistor T8 continue to remain cut-off according to the second power supply signal VSSQ, the second transistor T2, the fourth transistor T4 and the pull-up transistor To remain conductive, the first clock signal CK1 is transmitted to the signal output end, so that the gate control signal Scan(N) output by the signal output end remains to have high level.

[0070] The fifth stage t5: the second clock signal CK(m+A) is high level, the upper gate control signal Scan(N-X), the first clock signal CK(m), the third clock signal CK(m+B) and the lower gate control signal Scan(N+Y) are low level.

[0071] The sixth transistor T6 and the seventh transistor T7 remain turned on, so that the third transistor T3, the fifth transistor T5 and the eighth transistor T8 continue to remain turned off according to the second power signal VSSQ. The first node Q is pulled low by the coupling of the first clock signal CK(m) from high level to low level, and the gate control signal Scan(N) output by the signal output terminal has low level because the first clock signal CK1 has low level.

[0072] The sixth stage t6: the second clock signal CK(m+A), the third clock signal CK(m+B) are high level and the lower gate control signal Scan(N+Y), the upper gate control signal Scan(N-X) and the first clock signal CK(m) are low level.

[0073] The pull-down transistor Td is turned on according to the lower gate control signal Scan(N+Y), so that the potential of the first node Q is further pulled low, so that the second transistor T2, the fourth transistor T4 and the pull-up transistor To are turned off. The sixth transistor T6 and the seventh transistor T7 remain turned on, the first transistor T1 is turned on according to the third clock signal CK(m+B), and the control end of the third transistor T3 is affected by the third power signal VDD and the second power signal VSSQ. In some embodiments, if the difference between the third power signal VDD and the second power signal VSSQ is less than the threshold voltage of the third transistor T3, the third transistor T3 remains turned off, so that the potential of the second node P remains low potential affected by the second power signal VSSQ transmitted by the sixth transistor T6, and the fifth transistor T5 and the eighth transistor T8 remain turned off, so as to reserve sufficient time for the first node Q potential to drop to low level, so as to improve the problem that the voltage corresponding to the first node Q and the voltage corresponding to the second node P have a larger coincidence voltage value when the first node Q potential is delayed to drop due to the influence of the coupling capacitor and the second node P potential is in the rising stage.

[0074] The seventh stage t7: the third clock signal CK(m+B) is high level and the lower gate control signal Scan(N+Y), the upper gate control signal Scan(N-X), the second clock signal CK(m+A) and the first clock signal CK(m) are low level.

[0075] The pull-down transistor Td remains on, keeping the potential of the first node Q low. The second transistor T2, the fourth transistor T4, and the pull-up transistor To are off. The first transistor T1 remains on, turning on the third transistor T3, the fifth transistor T5, and the eighth transistor T8. The second power supply signal VSSQ is output to the signal output terminal, ensuring that the gate control signal Scan(N) output from the signal output terminal remains low.

[0076] Subsequently, the first clock signal CK(m), the second clock signal CK(m+A), and the third clock signal CK(m+B) transition between low and high levels. However, because the upper-level gate control signal Scan(NX) remains low, the potential of the first node Q may be affected by the first clock signal CK(m) in practical applications, resulting in coupled transitions at the transition points of the first clock signal CK(m). The potential of the second node P will be low when affected by the second clock signal CK(m+A) and high when affected by the third clock signal CK(m+B).

[0077] Figures 4A-4B This is a simulation diagram of the gate driving circuit provided in the embodiment of the present invention. The inventors of this application performed a reliability simulation on the gate driving unit of this application in a high temperature and high humidity environment. The simulation waveforms obtained show that: the potential of the second node P of the single-stage gate driving circuit 10 changes from high to low, which is in line with the design expectation; the potential change of the first node Q is in line with the design expectation; the gate control signal Scan output from the signal output terminal is normal, which can maintain the stability of the output of the gate driving circuit 10. Figure 4A As shown. The multi-stage gate drive circuit 10 can realize normal stage transmission function, and the multi-stage gate drive circuit 10 can realize row-by-row output of gate control signal Scan with square pulses, such as... Figure 4B As shown. Therefore, the gate driving circuit 10 provided in this application can achieve output and reliability functions similar to those of a conventional gate driving circuit 10 using a smaller number of transistors. As an application implementation of this application, the gate driving circuit 10 of this application has been applied to a 27-inch full HD resolution model for verification, and the verification results are as follows. Figures 4A-4B The simulation results are shown.

[0078] The gate drive circuit 10 provided by the present application can reduce the number of transistors used in the single-stage gate drive circuit 10 by omitting the level transmission module, so that the pull-up control unit of the gate drive circuit 10 is no longer affected by the level transmission signal. As a result, the single-stage gate drive circuit 10 only needs at most 12 transistors, which can maintain the stability and reliability of the conventional gate drive circuit 10, and is conducive to meeting the design requirements of the extremely narrow frame product. When the gate drive unit is applied to a small-size display panel, the gate drive circuit 10 can reduce the occupation of the sub-pixel layout space.

[0079] In addition, the prior art also uses a gate drive circuit with multi-stage output function (i.e., the single-stage gate drive circuit 10 simultaneously outputs two or more stages of gate control signals Scan), so as to reduce the number of gate drive circuits included in the gate drive unit, and reduce the number of transistors included in each gate drive circuit on average. However, the simultaneous output of multiple stages of gate control signals Scan by the single-stage gate drive circuit will result in a large overall load of the gate drive circuit and the gate drive unit, and the size of each transistor also needs to be increased to support the required performance requirements. Therefore, the gate drive circuit which simultaneously outputs multiple stages of gate control signals Scan has a large power consumption, and the gate drive circuit needs to further increase the layout space to meet the stability and reliability requirements. Furthermore, the gate drive circuit which simultaneously outputs multiple stages of gate control signals Scan also has stability problems. In order to improve the stability problem, two power supply signals lower than the first power supply signal VGH need to be further introduced to pull down the potential of the first node and the signal output terminal. However, the present application only needs to apply one power supply signal (i.e., the second power supply signal VSSQ) lower than the first power supply signal VGH to maintain the stability and reliability of the gate drive circuit 10.

[0080] Therefore, compared with the gate drive circuit which simultaneously outputs multiple stages of gate control signals Scan, the gate drive circuit 10 provided by the present application has lower power consumption, reduces the layout space occupied by the gate drive circuit 10, and meets the stability and reliability requirements without adjusting the size of the transistor. In addition, the number of signals applied is also smaller, which is conducive to reducing the control difficulty.

[0081] Figure 5 The present application also provides a display device, which comprises any of the above-mentioned gate drive units and a plurality of sub-pixels Pi. The plurality of sub-pixels are electrically connected to the plurality of gate drive circuits 10.

[0082] Optionally, the display device comprises a passive light-emitting display device (such as a liquid crystal display device), a self-luminous display device (such as a display device comprising an organic light-emitting diode, a sub-millimeter light-emitting diode, a micro light-emitting diode, etc.

[0083] Optionally, the sub-pixel Pi comprises a pixel driving circuit, the pixel driving circuit comprising at least one transistor, a control terminal of the transistor receiving a corresponding gate control signal Scan.

[0084] Optionally, the pixel driving circuit can adopt a topology structure in the form of 2T1C (i.e. 2 transistors, 1 capacitor), 5T2C (i.e. 5 transistors, 2 capacitors), 7T1C (i.e. 7 transistors, 1 capacitor), 8T2C (i.e. 8 transistors, 2 capacitors) and the like.

[0085] The principles and implementation manners of the present application are described herein by applying specific examples, and the above description of the examples is only for helping to understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manners and application ranges, and in view of the above, the content of the present description should not be understood as limiting the present application.

Claims

1. A gate drive unit characterized by, The gate drive circuit includes a plurality of cascaded gate drive circuits, at least one of the gate drive circuits includes: The pull-up control module is electrically connected with the first node and is configured to receive a gate control signal output by a higher-level gate drive circuit and transmit a first power signal to the first node; The pull-up module is electrically connected with the first node and is configured to transmit a first clock signal to a signal output end of the gate drive circuit according to a potential of the first node; The pull-down maintaining module is electrically connected with the first node and a second node and is configured to transmit a second power signal to the first node according to a second clock signal and a third clock signal; and The pull-down module is electrically connected with the first node and is configured to transmit the second power signal to the first node according to a gate control signal output by a lower-level gate drive circuit; In a first time period, the pull-down maintaining module is configured to transmit the second power signal to the second node according to the second clock signal and is configured to disconnect a current path between the second power end and the first node according to a signal of the second node; the first time period does not overlap with a second time period in which the pull-up control module transmits the first power signal to the first node according to the gate control signal output by the higher-level gate drive circuit, and the first time period partially overlaps with a third time period in which the pull-up module transmits the first clock signal to the signal output end of the gate drive circuit according to the potential of the first node; an ending moment of the first time period lags behind a starting moment of an effective pulse of the gate control signal output by the lower-level gate drive circuit and lags behind a starting moment of an effective pulse of the third clock signal.

2. The gate drive unit of claim 1, wherein, The pull-up control module includes: The pull-up control transistor has a control end configured to receive the gate control signal output by the higher-level gate drive circuit, an input end configured to receive the first power signal, and an output end electrically connected with the first node.

3. The gate drive unit of claim 1, wherein, The pull-up module includes: The pull-up transistor has a control end electrically connected with the first node, an input end configured to receive the first clock signal, and an output end electrically connected with the signal output end of the gate drive circuit; and The storage capacitor is connected in series between the control end of the pull-up transistor and the output end of the pull-up transistor.

4. The gate drive unit of claim 1, wherein, The pull-down maintaining module includes: The first transistor has a control end configured to receive the third clock signal and an input end configured to receive a third power signal; The second transistor has a control end electrically connected with the first node, an output end electrically connected with an output end of the first transistor, and an input end configured to receive the second power signal; and The third transistor has a control end electrically connected with the second node, an output end electrically connected with the output end of the first transistor, and an input end configured to receive the second power signal. a third transistor, a control terminal of the third transistor being electrically connected with an output terminal of the first transistor, an input terminal of the third transistor being configured to receive the third power supply signal; a fourth transistor, a control terminal of the fourth transistor being electrically connected with the first node, an input terminal of the fourth transistor being configured to receive the second power supply signal, an output terminal of the fourth transistor being electrically connected with an output terminal of the third transistor; a fifth transistor, a control terminal of the fifth transistor being electrically connected with the output terminal of the third transistor and the second node, an input terminal of the fifth transistor being configured to receive the second power supply signal, an output terminal of the fifth transistor being electrically connected with the first node; and a sixth transistor, a control terminal of the sixth transistor being configured to receive the second clock signal, an input terminal of the sixth transistor being configured to receive the second power supply signal, an output terminal of the sixth transistor being electrically connected with the control terminal of the fifth transistor and the second node.

5. The gate drive unit of claim 4, wherein, The pull-down maintaining module further comprises: a seventh transistor, a control terminal of the seventh transistor being configured to receive the second clock signal, an input terminal of the seventh transistor being configured to receive the second power supply signal, an output terminal of the seventh transistor being electrically connected with the control terminal of the third transistor.

6. The gate drive unit of claim 4, wherein, The pull-down maintaining module further comprises: an eighth transistor, a control terminal of the eighth transistor being electrically connected with the control terminal of the fifth transistor, an input terminal of the eighth transistor being configured to receive the second power supply signal, an output terminal of the eighth transistor being electrically connected with the signal output terminal of the gate drive circuit of the present stage.

7. The gate drive unit of claim 4, wherein, Further comprising a reset module, the reset module comprising: a reset transistor, a control terminal of the reset transistor being configured to receive a reset control signal, an input terminal of the reset transistor being configured to receive the third power supply signal, an output terminal of the reset transistor being electrically connected with the control terminal of the fifth transistor.

8. The gate drive unit of claim 1, wherein, The pull-down module comprises: a pull-down transistor, a control terminal of the pull-down transistor being configured to receive the gate control signal output by the gate drive circuit of the next stage, an input terminal of the pull-down transistor being configured to receive the second power supply signal, an output terminal of the pull-down transistor being electrically connected with the signal output terminal of the gate drive circuit of the present stage.

9. The gate drive unit of claim 1, wherein, The pull-up control module of the gate drive circuit of the Nth stage receives the gate control signal output by the gate drive circuit of the N-Xth stage before the gate drive circuit of the Nth stage, the pull-down module of the gate drive circuit of the Nth stage receives the gate control signal output by the gate drive circuit of the N+Yth stage after the gate drive circuit of the Nth stage; wherein Y>X, N>1, X>0.

10. A display device, characterized by comprising: The gate drive unit comprises the gate drive unit and a plurality of sub-pixels. The plurality of sub-pixels are electrically connected with the plurality of gate drive circuits.

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