Memory block programming using defect rate information

Abstract

The present disclosure relates to memory block programming using defect rate information. Methods, systems, and apparatuses include retrieving a defect rate footprint for a portion of memory, the portion of memory consisting of a plurality of blocks. A tier programming order for a current block of the plurality of blocks is determined based on the defect rate footprint. The current block consists of a plurality of tiers. The tier programming order is an order in which the plurality of tiers are programmed. The plurality of tiers are programmed according to the determined tier programming order.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to memory block programming, and more specifically to memory block programming using defect rate information. BACKGROUND

[0002] A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory sub-system to store and retrieve data at the memory devices. SUMMARY

[0003] In one aspect, the present disclosure relates to a method comprising: retrieving a defect rate footprint of a portion of memory, the portion of memory consisting of a plurality of blocks; determining a tier programming order for a current block of the plurality of blocks based on the defect rate footprint, wherein the current block consists of a plurality of tiers and wherein the tier programming order comprises an order in which the plurality of tiers are programmed; and programming the plurality of tiers according to the determined tier programming order.

[0004] In another aspect, the present disclosure relates to a non-transitory computer- readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: retrieve a defect rate footprint of a portion of memory, the portion of memory consisting of a plurality of blocks; determine a tier programming order for a current block of the plurality of blocks based on the defect rate footprint, wherein the current block consists of a plurality of tiers and wherein the tier programming order comprises an order in which the plurality of tiers are programmed; and program the plurality of tiers according to the determined tier programming order.

[0005] In yet another aspect, the present disclosure relates to a system comprising: a plurality of memory devices; and a processing device operatively coupled with the plurality of memory devices to: retrieve a defect rate footprint of a portion of memory, the portion of memory consisting of a plurality of blocks; determine a tier programming order for a current block of the plurality of blocks based on the defect rate footprint, wherein the current block consists of a plurality of tiers, wherein each of the plurality of tiers comprises a top side and a bottom side, and wherein the tier programming order comprises an order in which the plurality of tiers are programmed and a direction in which each of the plurality of tiers is programmed, the direction indicating whether each of the plurality of tiers is programmed from the top side to the bottom side or from the bottom side to the top side; and program the plurality of tiers according to the determined tier programming order. BRIEF DESCRIPTION OF DRAWINGS

[0006] The disclosure will be more fully understood from the following detailed description, taken in connection with the accompanying drawings, of various embodiments of the disclosure. However, the drawings should not be understood to limit the disclosure to particular embodiments, but rather, the intention is to convey the concepts of the disclosure to those skilled in the art.

[0007] Figure 1 An example computing system including a memory sub-system according to some embodiments of the disclosure is described.

[0008] Figure 2 Memory block programming using defect rate information according to some embodiments of the disclosure is described.

[0009] Figure 3 Memory block programming using defect rate information according to some embodiments of the disclosure is described.

[0010] Figure 4 Memory block programming using defect rate information according to some embodiments of the disclosure is described.

[0011] Figure 5 is a flow diagram of an example method to program a memory block using defect rate information according to some embodiments of the disclosure.

[0012] Figure 6 is a flow diagram of an example method to program a memory block using defect rate information according to some embodiments of the disclosure.

[0013] Figure 7 is a block diagram of an example computer system in which embodiments of the disclosure can operate. DETAILED DESCRIPTION

[0014] Aspects of the disclosure relate to memory block programming using defect rate information in a memory sub-system. The memory sub-system can be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices and memory modules are described below in connection with Figure 1 An example computing system including a memory sub-system according to some embodiments of the disclosure is described.

[0015] A memory device can be a non-volatile memory device. A non-volatile memory device is a package of one or more dies. One example of a non-volatile memory device is a "not- and" (NAND) memory device. Examples of storage devices and memory modules are described below in connection with Figure 1Other examples of non-volatile memory devices are described. Dies in a package can be assigned to one or more channels for communication with a memory subsystem controller. Each die can be composed of one or more planes. Planes can be grouped into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND memory devices), each plane is composed of a group of physical blocks, which are groups of memory cells for storing data. A cell is an electronic circuit that stores information.

[0016] Depending on the type of cell, a cell can store one or more binary bits of information, and have various logical states related to the number of bits stored. The logical states can be represented by binary values such as "0" and "1" or combinations of such values. There are various types of cells, such as single-level cells (SLCs), multi-level cells (MLCs), triple-level cells (TLCs), and quad-level cells (QLCs). For example, an SLC can store one bit of information and have two logical states.

[0017] In conventional memory systems, defects are introduced during manufacturing and during operation that can prevent a memory block from being programmed correctly. When attempting to program a memory block containing a defect, user data written to the memory block can be lost upon a programming failure. To preserve the data, user data programmed into the memory block is held in a buffer upon programming. For example, a buffer of four SLC blocks can be used to ensure that data loss does not occur due to defects when programming a QLC block. If the memory block to be programmed is not completely covered, defects in the memory block can cause a programming failure and an increase in uncorrectable bit error rate (UBER). However, for a QLC block that does not contain defects, a buffer of four SLC blocks is excessive. Thus, there is a tradeoff between UBER and over-provisioning to provide complete buffer coverage of a memory block.

[0018] Aspects of the present disclosure address the above and other deficiencies by first programming regions of memory having defects using known defect rate information of a memory system. If a programming failure occurs in these regions, the user data affected can be recovered using less buffer space because, for example, less data of the memory block was subjected to a programming operation upon failure. Thus, there is no increase in UBER that would normally accompany a smaller buffer size. In other words, this memory block programming scheme minimizes buffer space and the corresponding over-provisioning penalty while still providing adequate defect rate coverage.

[0019] Figure 1An example computing system 100 including a memory sub-system 110 is described in accordance with some embodiments of the present disclosure. The memory sub-system 110 can include media, such as one or more volatile memory devices (e.g., memory devices 140), one or more non-volatile memory devices (e.g., memory devices 130), or a combination of such.

[0020] The memory sub-system 110 can be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded Multi-Media Controllers (eMMC) drives, Universal Flash Storage (UFS) drives, Secure Digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0021] The computing system 100 can be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a car, or other transportation vehicle), an Internet of Things (IoT) capable device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such computing device including memory and a processing device.

[0022] The computing system 100 can include a host system 120 coupled to one or more memory sub-systems 110. In some embodiments, the host system 120 is coupled to different types of memory sub-systems 110. Figure 1 An example of a host system 120 coupled to one memory sub-system 110 is described. As used herein, “coupled to” or “coupled with” generally refers to a connection between components that can be an indirect communicative connection or a direct communicative connection (e.g., without intermediary components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0023] The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, memory controllers (e.g., NVDIMM controllers), and storage protocol controllers (e.g., PCIe controllers, SATA controllers). The host system 120 uses the memory sub-system 110 (e.g.,) to write data to the memory sub-system 110 and read data from the memory sub-system 110.

[0024] The host system 120 can be coupled to the memory sub-system 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a small computer system interface (SCSI), a double data rate (DDR) memory bus, a dual in-line memory module (DIMM) interface (e.g., a DIMM socket interface that supports double data rate (DDR)), an open NAND flash interface (ONFI), double data rate (DDR), low power double data rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between the host system 120 and the memory sub-system 110. When the memory sub-system 110 is coupled with the host system 120 by a PCIe interface, the host system 120 can further utilize an NVM express (NVMe) interface to access components (e.g., the memory devices 130). The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system 110 and the host system 120. Figure 1 The memory sub-system 110 is illustrated as an example. In general, the host system 120 can access multiple memory sub-systems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0025] The memory devices 130, 140 can include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (such as the memory devices 140) can be, but are not limited to, random access memories (RAMs), such as dynamic random access memories (DRAMs) and synchronous dynamic random access memories (SDRAMs).

[0026] Some examples of non-volatile memory devices (such as the memory devices 130) include “not-and” (NAND) type flash memory and in-situ write memory, such as a three-dimensional cross-point (“3D cross-point”) memory device, which is a cross-point array of non-volatile memory cells. A cross-point array of non-volatile memory can perform bit storage based on bulk resistance changes along with a stacked cross-grid format data access array. Additionally, in contrast to many flash-based memories, cross-point non-volatile memory can perform in-situ write operations, where a non-volatile memory cell can be programmed without previously erasing the non-volatile memory cell. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0027] Although non-volatile memory devices of NAND type memory (e.g., 2D NAND, 3D NAND) and 3D cross-point arrays of non-volatile memory cells are described, memory devices 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), “NOR” (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0028] Memory sub-system controller 115 (or, for simplicity, controller 115) can communicate with memory devices 130 to perform operations such as reading data, writing data, or erasing data at memory devices 130 and other such operations (e.g., in response to commands scheduled on a command bus by controller 115). Memory sub-system controller 115 can include hardware such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic for performing the operations described herein. Memory sub-system controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

[0029] Memory sub-system controller 115 can include a processing device 117 (processor) configured to execute instructions stored in local memory 119. In the illustrated example, local memory 119 of memory sub-system controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control operations of memory sub-system 110, including handling communications between memory sub-system 110 and host system 120.

[0030] In some embodiments, local memory 119 can include memory registers that store memory pointers, fetched data, etc. Local memory 119 can also include read-only memory (ROM) for storing microcode. Although microcode has been described as being stored in ROM, it can be stored in any suitable type of memory, such as RAM. Figure 1The example memory sub-system 110 in FIG. 1 is illustrated as including a memory sub-system controller 115, but in another embodiment of the present disclosure, the memory sub-system 110 does not include a memory sub-system controller 115 and can instead rely on external control (e.g., provided by an external host, or by a processor or controller separate from the memory sub-system 110).

[0031] In general, the memory sub-system controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130 and / or 140. The memory sub-system controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between logical block addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory devices 130. The memory sub-system controller 115 can further include host interface circuitry to communicate with the host system 120 via the physical host interface. The host interface circuitry can convert commands received from the host system into command instructions to access the memory devices 130 and / or 140, and convert responses associated with the memory devices 130 and / or 140 into information for the host system 120.

[0032] The memory sub-system 110 can also include additional circuitry or components not illustrated. In some embodiments, the memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row and column decoders) that can receive addresses from the memory sub-system controller 115 and decode the addresses to access the memory devices 130.

[0033] In some embodiments, the memory devices 130 include a local media controller 135 that operates in conjunction with the memory sub-system controller 115 to perform operations on one or more memory cells of the memory devices 130. An external controller (e.g., the memory sub-system controller 115) can externally manage the memory devices 130 (e.g., perform media management operations on the memory devices 130). In some embodiments, the memory devices 130 are managed memory devices, which are raw memory devices combined with a local controller (e.g., the local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0034] The memory subsystem 110 includes a memory block programming sequence component 113 that programs memory blocks using defect rate information. In some embodiments, the controller 115 includes at least a portion of the memory block programming sequence component 113. For example, the controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the memory block programming sequence component 113 is part of the host system 120, an application program, or an operating system.

[0035] The memory block programming sequence component 113 can use defect rate information to program sub-components of the memory block in an efficient order to reduce bit error problems while using minimal buffer space. Further details regarding the operation of the memory block programming sequence component 113 are described below.

[0036] Figure 2 This describes memory block programming using defect rate information according to some embodiments of this disclosure. The described memory block programming can be performed by processing logic, which may include hardware (e.g., processing device, circuit system, special-purpose logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device) or a combination thereof. Figure 2 As shown, the illustrated memory block programming is performed by the memory block programming sequence component 113. Although not explicitly stated, in some embodiments, the illustrated memory block programming is performed by... Figure 1 The processor 117 executes the program. In other embodiments, some portions of the illustrated memory block programming are executed by the memory block programming sequence component 113, while others are executed by the processor 117. The illustrated embodiments should be understood as examples only, and the illustrated memory block programming can be executed in different orders, and / or some memory block programming can be executed in parallel. Additionally, one or more steps may be omitted in various embodiments. Therefore, not all steps are required in every embodiment. Other processes are possible.

[0037] like Figure 2 As shown in the diagram, the memory subsystem (e.g.) Figure 1 The memory subsystem 110 is programming a memory block with an early defect set 215. This memory block contains a memory block top layer 205 and a memory block bottom layer 210. In some embodiments, the memory block consists of a QLC, and each of the memory block top layer 205 and the memory block bottom layer 210 is half of the entire memory block. In such embodiments, each of the memory block top layer 205 and the memory block bottom layer 210 holds an amount of data equal to half the amount in the QLC block (e.g., the amount of data held in the MLC block).

[0038] In other embodiments, the memory block is composed of another cell type (e.g., MLC or TLC), and each of the top layer 205 and the bottom layer 210 of the memory block is half or other subdivision of the entire memory block. In these embodiments, each layer thus holds an amount of data equal to the corresponding portion of the entire MLC or TLC block. For example, the memory block is composed of TLC, and each layer is one-third of the entire memory block. Each layer thus holds an amount of data equal to one-third of the TLC block (e.g., the amount of data held in an SLC block). In an alternative instance, the memory block is composed of MLC, and each layer is half of the entire memory block. Each layer thus holds an amount of data equal to half of the MLC block (e.g., the amount of data held in an SLC block).

[0039] In some embodiments, although only two layers are described, namely the top layer 205 and the bottom layer 210 of the memory block, the memory block may be divided into more than two layers. For the purposes of this disclosure, the term layer refers to a subdivision of the memory block that can be independently programmed or erased. Therefore, the higher the number of layers in the memory block, the greater the flexibility in determining the region with the highest probability of programming failure. A layer may not be the smallest subdivision of the memory block, and a layer may contain subdivisions within itself.

[0040] like Figure 2 As shown, the first portion of the bottom layer 210 of the memory block holds half the amount of data (e.g., the amount of data held in the SLC block). The defect rate protection buffer 1 220 is a memory block composed of SLCs such that the user data held in the defect rate protection buffer 1 220 is also stored in the first portion of the bottom layer 210 of the memory block in a one-to-one correspondence.

[0041] In some embodiments, defect rate protection buffer 1 220 and defect rate protection buffer 2 230 are blocks composed of SLCs. In other embodiments, defect rate protection buffer 1 220 and defect rate protection buffer 2 230 are another cell type having a smaller bit density than the cell types at the top layer 205 and bottom layer 210 of the memory block. Defect rate protection buffer 1 220 and defect rate protection buffer 2 230 are cell / memory types with high reliability and low error probability.

[0042] In some embodiments, defect rate protection buffer 1 220 and defect rate protection buffer 2 230 are local memories of the memory subsystem (e.g., Figure 1 This is part of the local memory 119. In other embodiments, defect rate protection buffer 1 220 and defect rate protection buffer 2 230 are part of the memory block programming sequence component 113.

[0043] The memory sub-system receives one or more commands from a host system (e.g. Figure 1 the host system 120) to program user data to the memory. In some embodiments, in response to receiving the commands, the memory sub-system controller (e.g. Figure 1 the memory sub-system controller 115) sends commands to program data to the memory block top tier 205 and the memory block bottom tier 210. Because the memory block top tier 205 and the memory block bottom tier 210 are independent tiers, each of the memory block top tier 205 and the memory block bottom tier 210 can be programmed individually and in a direction from top to bottom or bottom to top.

[0044] In some embodiments, the memory block programming order component 113 determines an order in which to program the memory block top tier 205 and the memory block bottom tier 210. Then, the memory block programming order component 113 programs the memory block top tier 205 and the memory block bottom tier 210 in the determined order. For example, the memory block programming order component 113 can determine, based on the early defect set 215, that the memory block bottom tier 210 is to be programmed first. The memory block programming order component 113 therefore programs the memory block bottom tier 210 and then programs the memory block top tier 205.

[0045] As shown in Figure 2 , the memory block bottom tier 210 includes an early defect set 215. As used throughout this disclosure, the terms defect and defectivity refer to a deviation from standard operation of a device. More specifically, a defect, in the context of a memory device (e.g. Figure 1 the memory device 130 or 140) or in the context of a memory block (e.g. a memory block composed of the memory block top tier 205 and the memory block bottom tier 210) can refer to a memory region in which manufacturing material was not deposited correctly. A defect can also include a memory region that has an insulating breakdown between various components, causing a failure during operation. A defect can also include an unintended open circuit in a memory region. These defects can occur at the time of manufacturing (e.g. incorrect deposition), or can manifest during operation, such as an electric field breaking down the insulation between components.

[0046] In the programming phase 200, the memory block programming order component 113 retrieves a defectivity footprint of the memory device, which includes defectivity information related to the memory block top tier 205 and the memory block bottom tier 210. The defectivity footprint is of the memory device (e.g. Figure 1The defect rate footprint includes information about the location of defects that occurred during manufacturing (e.g., each defect set can include early defects, late defects, or a combination of both) and the severity of the defects. As used throughout the specification, early defects refer to defects near the top of the memory block level, while late defects refer to defects near the bottom of the memory block level. In some embodiments, the severity of a defect corresponds to a measure of the likelihood that the defect will cause a failure during programming.

[0047] The memory block programming order component 113 uses the defect rate information from the defect rate footprint to determine that the early defect set 215 is at the top of the memory block bottom level 210. For example, the memory block programming order component 113 uses a lookup table or similar method to find the defect rate information in the defect rate footprint that is related to the memory block top level 205 and the memory block bottom level 210. For purposes of illustration, the top side of the memory block bottom level 210 refers to the side of the memory block bottom level 210 that is between the memory block top level 205 and the memory block bottom level 210. Similarly, the bottom side of the memory block bottom level 210 refers to the side of the memory block bottom level 210 that is opposite the memory block top level 205.

[0048] This defect rate information indicates that the early defect set 215 is located on the top side of the memory block bottom level 210. In some embodiments, the defect rate information is information that indicates the likelihood of a failure during programming of each word line corresponding to the memory device (e.g., memory device 130 or 140) that is being programmed. In other embodiments, the defect rate information includes different levels of granularity. The level of granularity of the defect rate information varies depending on available storage, operating conditions, and other parameters. In one embodiment, the level of granularity of the defect rate information is related to the size of the level. For example, for a level size of half of a QLC block, the level of granularity of the defect rate information can be half of the level size. At this level of granularity, the memory block programming order component 113 can use the level order and the programming direction of each level to ensure that the early defect set 215 is programmed first. Figure 1

[0049] ​In response to the memory block programming order component 113 determining that the early defect set 215 is at the top of the memory block bottom level 210, the memory block programming order component 113 programs the memory block bottom level 210 first. In one embodiment, the memory block programming order component 113 programs the first portion of the memory block bottom level 210 containing the early defect set 215, which is denoted by the dashed line, first. The memory block programming order component 113 loads the user data to be programmed to the first portion of the memory block bottom level 210 into the defect rate protection buffer 1 220. In some embodiments, the memory block programming order component 113 also loads user data (e.g., user data to be programmed to the second portion of the memory block bottom level 210) into the defect rate protection buffer 2 230. While the memory block programming order component 113 loads user data into the defect rate protection buffer 1 220, the memory block programming order component 113 also programs the user data into the first portion of the memory block bottom level 210.

[0050] In some embodiments, the memory block programming order component 113 determines the programming order for the entire memory block containing the memory block top level 205 and the memory block bottom level 210 before programming the first portion of the memory block bottom level 210. In other embodiments, the memory block programming order component 113 determines that the first portion of the memory block bottom level 210 is programmed first only.

[0051] As shown in the programming phases 200 and 225, Figure 2 As shown in the programming phases 200 and 225, the memory block programming order component 113 selects a programming direction for the memory block bottom level 210 using the location of the early defect set 215. In some embodiments, although the entire each portion is illustrated as being programmed simultaneously, each portion of the memory block top level 205 and the memory block bottom level 210 is programmed word line by word line according to the programming direction. The memory block programming order component 113 selects a programming direction corresponding to the earliest possible programming of the early defect set 215. For example, the memory block programming order component 113 uses a top-to-bottom programming direction for the memory block bottom level 210 because the early defect set 215 is located on the top side of the memory block bottom level 210. In the event of a failure during programming of the first portion of the memory block bottom level 210, the defect rate protection buffer 1 220 contains user data, so the UBER of the memory sub-system does not improve.

[0052] In programming phase 225, memory block programming order component 113 programs memory block bottom tier 210 with user data stored in defect rate protection buffer 2 230. In some embodiments, memory block programming order component 113 uses defect rate information from the defect rate footprint retrieved in programming phase 200 to determine that the second portion of memory block bottom tier 210 has the second highest likelihood of programming failure. In other embodiments, the programming order is determined in programming phase 200. As Figure 2 In programming phase 225, memory block programming order component 113 programs memory block bottom tier 210 with user data stored in defect rate protection buffer 2 230. In some embodiments, memory block programming order component 113 uses defect rate information from the defect rate footprint retrieved in programming phase 200 to determine that the second portion of memory block bottom tier 210 has the second highest likelihood of programming failure. In other embodiments, the programming order is determined in programming phase 200. As

[0053] In one embodiment, in response to memory block programming order component 113 determining that the second portion of memory block bottom tier 210 has the second highest likelihood of programming failure, memory block programming order component 113 then programs the second portion of memory block bottom tier 210. In some embodiments, once the early defect set 215 has been programmed, memory block programming order component 113 programs the remaining portion of the memory block in a default order rather than based on likelihood of programming failure.

[0054] If memory block programming order component 113 has not loaded user data into defect rate protection buffer 2 230 in programming phase 200, memory block programming order component 113 loads user data into defect rate protection buffer 2 230. As memory block programming order component 113 loads user data into defect rate protection buffer 2 230, memory block programming order component 113 also programs the user data into the second portion of memory block bottom tier 210.

[0055] In some embodiments, the second portion of memory block bottom tier 210 holds an amount of data equal to half of memory block bottom tier 210 and equivalent to the amount of data held by the SLC block. Defect rate protection buffer 2 230 is a memory block composed of SLC such that user data held in defect rate protection buffer 2 230 is stored in the second portion of memory block bottom tier 210 on a one-to-one basis.

[0056] In programming phase 225, memory block programming order component 113 programs memory block bottom tier 210 with user data stored in defect rate protection buffer 2 230. In some embodiments, memory block programming order component 113 uses defect rate information from the defect rate footprint retrieved in programming phase 200 to determine that the second portion of memory block bottom tier 210 has the second highest likelihood of programming failure. In other embodiments, the programming order is determined in programming phase 200. As Figure 2As shown in programming phase 225, memory block program order component 113 uses the same program direction for memory block bottom tier 210 as for programming phase 200. Memory block program order component 113 attempts to program the second portion of memory block bottom tier 210 starting from the word line directly below the last word line covered by defect rate protection buffer 1 220. In the event of a failure during programming of the second portion of memory block bottom tier 210, defect rate protection buffer 1 220 contains user data for the first portion of memory block bottom tier 210 and defect rate protection buffer 2 230 contains user data for the second portion of memory block bottom tier 210, such that the UBER of the memory sub-system does not change due to the program failure.

[0057] In programming phase 250, memory block program order component 113 clears defect rate protection buffer 1 220, removing the data stored since the beginning of programming of the first portion of memory block bottom tier 210 in programming phase 200. In some embodiments, memory block program order component 113 also clears defect rate protection buffer 2 230, removing the data stored since the beginning of programming of the second portion of memory block bottom tier 210 in programming phase 225. In some embodiments, memory block program order component 113 clears both defect rate protection buffer 1 220 and defect rate protection buffer 2 230 in response to programming of the second portion of memory block bottom tier 210. Memory block program order component 113 loads the next set of user data into defect rate protection buffer 1 220. In some embodiments, memory block program order component 113 also loads user data into defect rate protection buffer 2 230. In response to loading user data into defect rate protection buffer 1 220, memory block program order component 113 programs the user data into the first portion of memory block top tier 205.

[0058] In some embodiments, in response to a program failure during programming phase 200 or 225, memory block program order component 113 stops programming user data into the memory block. Memory block program order component 113 can also send an indication to the memory sub-system controller (e.g., memory sub-system controller 115 of Figure 1 the host system (e.g., host system 120 of Figure 1 ). This indication conveys that the programming has failed and can further convey the tier or even the word line at which the program failure occurred.

[0059] In programming phase 250, in some embodiments, the memory block programming order component 113 uses the defect rate information from the defect rate footprint retrieved in programming phase 200 to determine that the first portion of the memory block top level 205 has the second highest likelihood of programming failure. In other embodiments, the programming order is determined in programming phase 200. As Figure 2 In programming phase 250, in some embodiments, the memory block programming order component 113 uses the defect rate information from the defect rate footprint retrieved in programming phase 200 to determine that the first portion of the memory block top level 205 has the second highest likelihood of programming failure. In other embodiments, the programming order is determined in programming phase 200. As

[0060] In response to the memory block programming order component 113 determining that the first portion of the memory block top level 205 has the second highest likelihood of programming failure, the memory block programming order component 113 programs the first portion of the memory block top level 205. In some embodiments, once the early defect set 215 has been programmed, the remaining portion of the memory block is programmed in a default order rather than based on the likelihood of programming failure.

[0061] In programming phase 275, the memory block programming order component 113 programs the memory block top level 205 with the user data stored in the defect rate protection buffer 2 230. For example, the memory block programming order component 113 programs the second portion of the memory block top level 205. As Figure 2 In programming phase 275, the memory block programming order component 113 programs the memory block top level 205 with the user data stored in the defect rate protection buffer 2 230. For example, the memory block programming order component 113 programs the second portion of the memory block top level 205. As

[0062] In response to the memory block programming order component 113 determining that the second portion of the memory block top level 205 is the last unprogrammed portion of the remaining memory block, the memory block programming order component 113 then programs the second portion of the memory block top level 205. In some embodiments, once the early defect set 215 has been programmed, the memory block programming order component 113 programs the remaining portion of the memory block in a default order rather than based on the likelihood of programming failure.

[0063] In some embodiments, in response to successfully programming the memory block bottom tier 210, the memory block programming sequence component 113 flushes the defect rate protection buffer 2 230, removing the data stored since the beginning of programming the second portion of the memory block bottom tier 210 in programming phase 225. In some embodiments, the memory block programming sequence component 113 loads user data into the defect rate protection buffer 2 230 in programming phase 275. In other embodiments, the memory block programming sequence component 113 loads user data into the defect rate protection buffer 2 230 in programming phase 250. While the memory block programming sequence component 113 loads user data into the defect rate protection buffer 2 230, the memory block programming sequence component 113 also programs the user data into the second portion of the memory block top tier 205.

[0064] As shown in programming phase 275, the memory block programming sequence component 113 uses the same programming direction for the memory block top tier 205 as 250. The memory block programming sequence component 113 attempts to program the second portion of the memory block top tier 205 starting from the word line directly above the last word line covered by the defect rate protection buffer 1 220. Because the portion of the memory block with the highest likelihood of failure (i.e., the early defect set 215) has already been successfully programmed, it is less likely that a programming failure will occur during programming of the second portion of the memory block top tier 205. Next, the memory block programming sequence component 113 prepares to program the next memory block. For example, the memory block programming sequence component 113 flushes the defect rate protection buffer 1 220 and the defect rate protection buffer 2 230.

[0065] Figure 3 Memory block programming using defect rate information according to some embodiments of the present disclosure is illustrated. The illustrated memory block programming can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. As Figure 3 As shown in programming phase 275, the memory block programming sequence component 113 uses the same programming direction for the memory block top tier 205 as 250. The memory block programming sequence component 113 attempts to program the second portion of the memory block top tier 205 starting from the word line directly above the last word line covered by the defect rate protection buffer 1 220. Because the portion of the memory block with the highest likelihood of failure (i.e., the early defect set 215) has already been successfully programmed, it is less likely that a programming failure will occur during programming of the second portion of the memory block top tier 205. Next, the memory block programming sequence component 113 prepares to program the next memory block. For example, the memory block programming sequence component 113 flushes the defect rate protection buffer 1 220 and the defect rate protection buffer 2 230. Figure 1The processor 117 executes the program. In other embodiments, some portions of the illustrated memory block programming are executed by the memory block programming sequence component 113, while others are executed by the processor 117. The illustrated embodiments should be understood as examples only, and the illustrated memory block programming can be executed in different orders, and / or some memory block programming can be executed in parallel. Additionally, one or more steps may be omitted in various embodiments. Therefore, not all steps are required in every embodiment. Other processes are possible.

[0066] like Figure 3 As shown, the memory block top layer 205 contains late defect sets 305. During the programming phase 300, the memory block programming sequence component 113 retrieves the defect rate footprint of the memory device, which contains defect rate information related to the memory block top layer 205 and the memory block bottom layer 210. The defect rate footprint is displayed in memory devices containing the memory block top layer 205 and the memory block bottom layer 210 (e.g., memory devices containing the memory block top layer 205 and the memory block bottom layer 210). Figure 1 The defect rate footprint is generated during the manufacturing of the memory device 130 or 140. It contains information about the location of defects occurring during manufacturing (e.g., each defect set may include early defects, late defects, or a combination of both) and the severity of the defects. In some embodiments, the severity of a defect corresponds to a measure of the likelihood that the defect will cause a failure during programming.

[0067] The memory block programming sequence component 113 uses defect rate information from the defect rate footprint to determine where the late defect set 305 is located at the bottom of the memory block top layer 205. For example, the memory block programming sequence component 113 uses a lookup table or similar method to find defect rate information in the defect rate footprint that is related to the memory block top layer 205 and the memory block bottom layer 210.

[0068] This defect rate information indicates that late defect concentration 305 is located on the bottom side of the top layer 205 of the memory block. In some embodiments, the defect rate information indicates the location of late defects corresponding to the memory device (e.g., ...). Figure 1 The defect rate information contains information about the probability of failure occurring during programming each word line of the memory device 130 or 140. In other embodiments, the defect rate information includes different levels of granularity. The granularity level of the defect rate information varies depending on available storage, operating conditions, and other parameters. In one embodiment, the granularity level of the defect rate information is related to the layer size. For example, for a layer size that is half the size of a QLC block, the granularity level of the defect rate information could be half the layer size. At this granularity level, the memory block programming sequence component 113 can use the layer order and the programming direction of each layer to ensure that the late defect set 305 is programmed first.

[0069] In response to the memory block programming order component 113 determining that the late defect set 305 is at the bottom of the memory block top level 205, the memory block programming order component 113 programs the memory block top level 205 first. In one embodiment, the memory block programming order component 113 programs the first portion of the memory block top level 205 containing the late defect set 305, which is denoted by the dashed line, first. The memory block programming order component 113 loads the user data to be programmed to the first portion of the memory block top level 205 into the defect rate protection buffer 1 220. In some embodiments, the memory block programming order component 113 also loads user data (e.g., user data to be programmed to the second portion of the memory block top level 205) into the defect rate protection buffer 2 230. While the memory block programming order component 113 loads user data into the defect rate protection buffer 1 220, the memory block programming order component 113 also programs the user data into the first portion of the memory block top level 205.

[0070] In some embodiments, the memory block programming order component 113 determines the programming order for the entire memory block containing the memory block top level 205 and the memory block bottom level 210 before programming the first portion of the memory block top level 205. In other embodiments, the memory block programming order component 113 determines that only the first portion of the memory block top level 205 is programmed first.

[0071] As shown in the programming phases 300 and 325, Figure 3 As shown in the programming phases 300 and 325, the memory block programming order component 113 selects a programming direction for the memory block top level 205 using the location of the late defect set 305. In some embodiments, although the entire each portion is illustrated as being programmed simultaneously, each portion of the memory block top level 205 and the memory block bottom level 210 is programmed word line by word line according to the programming direction. The memory block programming order component 113 selects a programming direction corresponding to the earliest possible programming of the late defect set 305. For example, the memory block programming order component 113 uses a bottom to top programming direction for the memory block top level 205 because the late defect set 305 is located on the bottom side of the memory block top level 205. In the event of a failure during programming of the first portion of the memory block top level 205, the defect rate protection buffer 1 220 contains user data, so the UBER of the memory sub-system is not increased.

[0072] In programming phase 325, memory block program order component 113 programs memory block top tier 205 with user data stored in defect rate protection buffer 2 230. In some embodiments, memory block program order component 113 uses defect rate information from the defect rate footprint retrieved in programming phase 300 to determine that the second portion of memory block top tier 205 has the second highest likelihood of programming failure. In other embodiments, the program order is determined in programming phase 300. As Figure 3 In programming phase 325, memory block program order component 113 programs memory block top tier 205 with user data stored in defect rate protection buffer 2 230. In some embodiments, memory block program order component 113 uses defect rate information from the defect rate footprint retrieved in programming phase 300 to determine that the second portion of memory block top tier 205 has the second highest likelihood of programming failure. In other embodiments, the program order is determined in programming phase 300. As

[0073] In one embodiment, in response to memory block program order component 113 determining that the second portion of memory block top tier 205 has the second highest likelihood of programming failure, memory block program order component 113 then programs the second portion of memory block top tier 205. In some embodiments, once the late defect set 305 has been programmed, memory block program order component 113 programs the remaining portion of the memory block in a default order rather than based on likelihood of programming failure.

[0074] If memory block program order component 113 has not loaded user data into defect rate protection buffer 2 230 in programming phase 300, memory block program order component 113 loads user data into defect rate protection buffer 2 230. As memory block program order component 113 loads user data into defect rate protection buffer 2 230, memory block program order component 113 also programs the user data into the second portion of memory block top tier 205.

[0075] In some embodiments, the second portion of memory block top tier 205 retains an amount of data equal to half of memory block top tier 205 and equivalent to the amount of data held by the SLC block. Defect rate protection buffer 2 230 is a memory block composed of SLC such that user data held in defect rate protection buffer 2 230 is stored in the second portion of memory block top tier 205 on a one-to-one basis.

[0076] In programming phase 325, memory block program order component 113 programs memory block top tier 205 with user data stored in defect rate protection buffer 2 230. In some embodiments, memory block program order component 113 uses defect rate information from the defect rate footprint retrieved in programming phase 300 to determine that the second portion of memory block top tier 205 has the second highest likelihood of programming failure. In other embodiments, the program order is determined in programming phase 300. As Figure 3As shown in programming phase 325, the memory block program order component 113 uses the same program direction for the memory block top tier 205 as in programming phase 300. The memory block program order component 113 attempts to program the second portion of the memory block top tier 205 starting from the word line directly above the last word line covered by the defect rate protection buffer 1 220. In the event that a failure occurs during programming of the second portion of the memory block top tier 205, the defect rate protection buffer 1 220 contains user data for the first portion of the memory block top tier 205 and the defect rate protection buffer 2 230 contains user data for the second portion of the memory block top tier 205, such that the UBER of the memory sub-system does not change due to the program failure.

[0077] In programming phase 350, the memory block program order component 113 clears the defect rate protection buffer 1 220, removing the data stored since the beginning of programming of the first portion of the memory block top tier 205 in 300. In some embodiments, the memory block program order component 113 also clears the defect rate protection buffer 2 230, removing the data stored since the beginning of programming of the second portion of the memory block top tier 205 in programming phase 325. In some embodiments, the memory block program order component 113 clears the defect rate protection buffer 1 220 and the defect rate protection buffer 2 230 in response to programming the second portion of the memory block top tier 205. The memory block program order component 113 loads the next set of user data into the defect rate protection buffer 1 220. In some embodiments, the memory block program order component 113 also loads user data into the defect rate protection buffer 2 230. In response to loading user data into the defect rate protection buffer 1220, the memory block program order component 113 programs the user data into the first portion of the memory block bottom tier 210.

[0078] In some embodiments, in response to a program failure during programming phase 300 or 325, the memory block program order component 113 stops programming user data into the memory block. The memory block program order component 113 can also send an indication to the memory sub-system controller (e.g., memory sub-system controller 115 of Figure 1 the host system (e.g., host system 120 of Figure 1 ). This indication conveys that the programming has failed and can further convey the tier or even the word line at which the program failure occurred.

[0079] In programming phase 350, in some embodiments, the memory block programming order component 113 uses the defect rate information from the defect rate footprint retrieved in programming phase 300 to determine that the first portion of the memory block bottom tier 210 has the second highest likelihood of programming failure. In other embodiments, the programming order is determined in programming phase 300. As shown in Figure 3 In programming phase 350, in some embodiments, the memory block programming order component 113 uses the defect rate information from the defect rate footprint retrieved in programming phase 300 to determine that the first portion of the memory block bottom tier 210 has the second highest likelihood of programming failure. In other embodiments, the programming order is determined in programming phase 300. As shown in

[0080] In response to the memory block programming order component 113 determining that the first portion of the memory block bottom tier 210 has the second highest likelihood of programming failure, the memory block programming order component 113 programs the first portion of the memory block bottom tier 210. In some embodiments, once the late defect set 305 has been programmed, the remaining portions of the memory block are programmed in a default order rather than based on the likelihood of programming failure.

[0081] In programming phase 375, the memory block programming order component 113 programs the memory block bottom tier 210 with the user data stored in the defect rate protection buffer 2 230. For example, the memory block programming order component 113 programs the second portion of the memory block bottom tier 210. As shown in Figure 3 In programming phase 375, the memory block programming order component 113 programs the memory block bottom tier 210 with the user data stored in the defect rate protection buffer 2 230. For example, the memory block programming order component 113 programs the second portion of the memory block bottom tier 210. As shown in

[0082] In response to the memory block programming order component 113 determining that the second portion of the memory block bottom tier 210 is the last unprogrammed portion of the remaining memory block, the memory block programming order component 113 then programs the second portion of the memory block bottom tier 210. In some embodiments, once the late defect set 305 has been programmed, the memory block programming order component 113 programs the remaining portions of the memory block in a default order rather than based on the likelihood of programming failure.

[0083] In some embodiments, in response to successfully programming the top tier 205 of the memory block, the memory block programming sequence component 113 flushes the defect rate protection buffer 2 230, removing the data stored since the beginning of programming the second portion of the top tier 205 of the memory block in the programming phase 325. In some embodiments, the memory block programming sequence component 113 loads user data into the defect rate protection buffer 2 230 in the programming phase 375. In other embodiments, the memory block programming sequence component 113 loads user data into the defect rate protection buffer 2 230 in the programming phase 350. As the memory block programming sequence component 113 loads user data into the defect rate protection buffer 2 230, the memory block programming sequence component 113 also programs the user data into the second portion of the bottom tier 210 of the memory block.

[0084] As shown in the programming phase 375, the memory block programming sequence component 113 uses the same programming direction for the bottom tier 210 of the memory block as in 350. The memory block programming sequence component 113 attempts to program the second portion of the bottom tier 210 of the memory block starting from the word line directly above the last word line covered by the defect rate protection buffer 1 220. Because the portion of the memory block with the highest likelihood of failure (i.e., the late defect set 305) has already been successfully programmed, it is less likely that a programming failure will occur during the programming of the second portion of the bottom tier 210 of the memory block. Next, the memory block programming sequence component 113 prepares to program the next memory block. For example, the memory block programming sequence component 113 flushes the defect rate protection buffer 1 220 and the defect rate protection buffer 2 230.

[0085] Figure 4 Memory block programming using defect rate information according to some embodiments of the present disclosure is illustrated. The illustrated memory block programming can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. As Figure 4 The illustrated memory block programming is performed by the memory block programming sequence component 113, as shown in the programming phase 375. Although not illustrated, in some embodiments, the illustrated memory block programming is performed by the processor 117 of the memory device 100. In other embodiments, some portions of the illustrated memory block programming are performed by the memory block programming sequence component 113, while other portions are performed by the processor 117. The illustrated embodiments should be understood as being examples only, and the illustrated memory block programming can be performed in a different order, and / or some memory block programming can be performed in parallel. Additionally, in various embodiments, one or more steps can be omitted. Thus, not all steps are required in every embodiment. Other flows are possible. Figure 1 The illustrated memory block programming is performed by the memory block programming sequence component 113, as shown in the programming phase 375. Although not illustrated, in some embodiments, the illustrated memory block programming is performed by the processor 117 of the memory device 100. In other embodiments, some portions of the illustrated memory block programming are performed by the memory block programming sequence component 113, while other portions are performed by the processor 117. The illustrated embodiments should be understood as being examples only, and the illustrated memory block programming can be performed in a different order, and / or some memory block programming can be performed in parallel. Additionally, in various embodiments, one or more steps can be omitted. Thus, not all steps are required in every embodiment. Other flows are possible.

[0086] As Figure 4 shown in the middle, the top tier 205 of the memory block includes a first defective set 405 and a second defective set 410. In the programming phase 400, the memory block programming order component 113 retrieves a defectivity footprint of the memory device, which includes defectivity information related to the top tier 205 of the memory block and the bottom tier 210 of the memory block. The defectivity footprint is generated during manufacturing of the memory device (e.g., memory device 130 or 140) that includes the top tier 205 of the memory block and the bottom tier 210 of the memory block. The defectivity footprint includes information about the location of defects that occurred during manufacturing (e.g., each defective set can include early defects, late defects, or a combination of both) and the severity of the defects. In some embodiments, the severity of the defects corresponds to a measure of the likelihood that the defects will cause a failure during programming. Figure 1

[0087] The memory block programming order component 113 uses the defectivity information from the defectivity footprint to determine that the first defective set 405 is at the bottom of the top tier 205 of the memory block and the second defective set 410 is at the top of the bottom tier 210 of the memory block. For example, the memory block programming order component 113 uses a lookup table or similar method to find the defectivity information related to the top tier 205 of the memory block and the bottom tier 210 of the memory block in the defectivity footprint. This defectivity information indicates that there is a first defective set 405 located on the bottom side of the top tier 205 of the memory block and a second defective set 410 located on the top side of the bottom tier 210 of the memory block. The defectivity information also indicates that the first defective set 405 is of higher priority. In some embodiments, determining the priority of the first defective set 405 and the second defective set 410 is based on the size of the first defective set 405 and the second defective set 410. In other embodiments, determining the priority of the first defective set 405 and the second defective set 410 is based on another measure, such as a programming failure likelihood or a combination of the size and likelihood of a programming failure.

[0088] In some embodiments, the defectivity information indicates that the first defective set 405 and the second defective set 410 are located at the bottom of the top tier 205 of the memory block and the top of the bottom tier 210 of the memory block, respectively, based on the defectivity footprint of the memory device (e.g., memory device 130 or 140) that includes the top tier 205 of the memory block and the bottom tier 210 of the memory block. Figure 1 ​information includes different levels of granularity. The level of granularity of the defect rate information varies depending on available storage, operating conditions, and other parameters. In one embodiment, the level of granularity of the defect rate information is related to the size of the tier. For example, for a tier size of half of a QLC block, the level of granularity of the defect rate information can be half of the tier size. At this level of granularity, the memory block programming order component 113 can use the tier order and the programming direction of each tier to ensure that the first defect set 405 is programmed first and the second defect set 410 is programmed next.

[0089] In response to the memory block programming order component 113 determining that the first defect set 405 is located on the bottom side of the top tier 205 of the memory block, the second defect set 410 is located on the top side of the bottom tier 210 of the memory block, and the first defect set 405 has a higher priority than the second defect set 410, the memory block programming order component 113 first programs the top tier 205 of the memory block. In one embodiment, the memory block programming order component 113 programs a first portion of the top tier 205 of the memory block that includes the first defect set 405, which is denoted by the dashed line. The memory block programming order component 113 loads user data to be programmed to the first portion of the top tier 205 of the memory block into the defect rate protection buffer 1 220. In some embodiments, the memory block programming order component 113 also loads user data (e.g., user data to be programmed to a first portion of the bottom tier 210 of the memory block) into the defect rate protection buffer 2 230. While the memory block programming order component 113 loads user data into the defect rate protection buffer 1 220, the memory block programming order component 113 also programs the user data into the first portion of the top tier 205 of the memory block.

[0090] In some embodiments, the memory block programming order component 113 determines the programming order of the entire memory block that includes the top tier 205 of the memory block and the bottom tier 210 of the memory block before programming the first portion of the top tier 205 of the memory block. In other embodiments, the memory block programming order component 113 only determines that the first portion of the top tier 205 of the memory block is programmed first.

[0091] As Figure 4As shown in programming phases 400 and 450, the memory block programming order component 113 selects a programming direction for the memory block top tier 205 using the locations of the first defect set 405. In some embodiments, although the entire each portion is illustrated as being programmed simultaneously, each portion of the memory block top tier 205 and the memory block bottom tier 210 is programmed word line by word line according to the programming direction. The memory block programming order component 113 selects a programming direction corresponding to the earliest possible programming of the first defect set 405. For example, the memory block programming order component 113 uses a bottom-to-top programming direction for the memory block top tier 205 because the first defect set 405 is located on the bottom side of the memory block top tier 205. In the event of a failure during programming of the first portion of the memory block top tier 205, the defect rate protection buffer 1220 contains user data, so the UBER of the memory sub-system is not improved.

[0092] In programming phase 425, the memory block programming order component 113 programs the memory block bottom tier 210 with user data stored in the defect rate protection buffer 2 230. In some embodiments, the memory block programming order component 113 uses defect rate information from the defect rate footprint retrieved in programming phase 400 to determine that a first portion of the memory block bottom tier 210 has a second highest likelihood of programming failure due to the second defect set 410. In other embodiments, the programming order is determined in programming phase 400. As shown in FIG. 4B, the first portion of the memory block bottom tier 210 represented by the dashed line receives user data from the memory block programming order component 113 in programming phase 425. Figure 4 In programming phase 425, the memory block programming order component 113 programs the memory block bottom tier 210 with user data stored in the defect rate protection buffer 2 230. In some embodiments, the memory block programming order component 113 uses defect rate information from the defect rate footprint retrieved in programming phase 400 to determine that a first portion of the memory block bottom tier 210 has a second highest likelihood of programming failure due to the second defect set 410. In other embodiments, the programming order is determined in programming phase 400. As shown in FIG. 4B, the first portion of the memory block bottom tier 210 represented by the dashed line receives user data from the memory block programming order component 113 in programming phase 425.

[0093] In one embodiment, in response to the memory block programming order component 113 determining that the first portion of the memory block bottom tier 210 has a second highest likelihood of programming failure, the memory block programming order component 113 then programs the first portion of the memory block bottom tier 210.

[0094] If the memory block programming order component 113 has not loaded user data into the defect rate protection buffer 2 230 in programming phase 400, the memory block programming order component 113 loads user data into the defect rate protection buffer 2 230. As the memory block programming order component 113 loads user data into the defect rate protection buffer 2 230, the memory block programming order component 113 also programs the user data into the first portion of the memory block bottom tier 210.

[0095] In some embodiments, the first portion of the bottom layer 210 of the memory block holds a data amount equal to half the size of the bottom layer 210 of the memory block and equivalent to the amount of data held by the SLC block. The defect rate protection buffer 2 230 is a memory block composed of SLCs such that the user data held in the defect rate protection buffer 2 230 is stored in the first portion of the bottom layer 210 of the memory block in a one-to-one correspondence.

[0096] like Figure 4 As shown in programming phase 425, the memory block programming sequence component 113 selects a programming direction for the bottom layer 210 of the memory block using the location of the second defect set 410. In some embodiments, although each portion is illustrated as being programmed simultaneously, each portion of the top layer 205 and the bottom layer 210 of the memory block is programmed word-for-word according to the programming direction. The memory block programming sequence component 113 selects a programming direction for the bottom layer 210 corresponding to the earliest possible programming of the second defect set 410. For example, the memory block programming sequence component 113 uses a top-to-bottom programming direction for the bottom layer 210 of the memory block because the second defect set 410 is located on the top side of the bottom layer 210 of the memory block. In the event of a failure during programming of the first portion of the bottom layer 210 of the memory block, the defect rate protection buffer 1 220 contains user data from the first portion of the top layer 205 of the memory block and the defect rate protection buffer 2 230 contains user data from the first portion of the bottom layer 210 of the memory block, so the UBER of the memory subsystem does not increase.

[0097] In programming phase 450, memory block programming sequence component 113 clears defect rate protection buffer 1 220, thereby removing data stored since programming of the first portion of the top layer 205 of the memory block in 400. In some embodiments, memory block programming sequence component 113 also clears defect rate protection buffer 2 230, thereby removing data stored since programming of the first portion of the bottom layer 210 of the memory block in programming phase 425. In some embodiments, memory block programming sequence component 113 clears defect rate protection buffer 1 220 and defect rate protection buffer 2 230 in response to programming the first portion of the bottom layer 210 of the memory block. Memory block programming sequence component 113 loads the next set of user data into defect rate protection buffer 1 220. In some embodiments, memory block programming sequence component 113 also loads user data into defect rate protection buffer 2 230. In response to loading user data into defect rate protection buffer 1 220, memory block programming sequence component 113 programs user data into a second portion of the top layer 210 of the memory block.

[0098] In some embodiments, in response to a programming failure during the programming phase 400 or 425, the memory block programming order component 113 stops programming user data into the memory block. The memory block programming order component 113 can also send an indication to the memory sub-system controller (e.g., memory sub-system controller 115 of Figure 1 ) or to the host system (e.g., host system 120 of Figure 1 ) that conveys that the programming has failed and can further convey the level or even word line of the programming failure.

[0099] In the programming phase 450, in some embodiments, the memory block programming order component 113 uses the defect rate information from the defect rate footprint retrieved in the programming phase 400 to determine that a second portion of the memory block top level 205 has a second highest likelihood of programming failure. In other embodiments, the programming order is determined in the programming phase 400. As shown in Figure 4 , the second portion of the memory block top level 205, represented by the dashed line, receives user data from the memory block programming order component 113 in the programming phase 450.

[0100] In response to the memory block programming order component 113 determining that the second portion of the memory block top level 205 has a second highest likelihood of programming failure, the memory block programming order component 113 programs the second portion of the memory block top level 205. In some embodiments, once the first defect set 405 and the second defect set 410 have been programmed, the remaining portion of the memory block is programmed in a default order rather than based on the likelihood of programming failure.

[0101] As shown in the programming phase 450 of Figure 4 , the memory block programming order component 113 uses the same programming direction for the memory block top level 205 as in the programming phase 400. The memory block programming order component 113 attempts to program the second portion of the memory block top level 205 starting from the word line directly above the last word line covered by the defect rate protection buffer 1 220. Because the portions of the memory block with the highest likelihood of failure (i.e., the first defect set 405 and the second defect set 410) have already been successfully programmed, it is less likely that a programming failure will occur during the programming of the second portion of the memory block top level 205.

[0102] In the programming phase 475, the memory block programming order component 113 programs the memory block bottom level 210 with user data stored in the defect rate protection buffer 2 230. For example, the memory block programming order component 113 programs a second portion of the memory block bottom level 210. As shown in Figure 4As shown in programming phase 475, a second portion of the memory block bottom level 210, represented by the dashed line, receives user data from the memory block programming order component 113 in programming phase 475.

[0103] In response to the memory block programming order component 113 determining that the second portion of the memory block bottom level 210 is the last unprogrammed portion of the remaining memory block, the memory block programming order component 113 proceeds to program the second portion of the memory block bottom level 210. In some embodiments, once the first defect cluster 405 and the second defect cluster 410 have been programmed, the memory block programming order component 113 programs the remaining portion of the memory block in a default order rather than based on the likelihood of programming failure.

[0104] In some embodiments, in response to successfully programming the first portion of the memory block bottom level 210, the memory block programming order component 113 clears the defect rate protection buffer 2 230, removing the data stored since the beginning of programming the first portion of the memory block bottom level 210 in programming phase 425. In some embodiments, the memory block programming order component 113 loads user data into the defect rate protection buffer 2 230 in programming phase 475. In other embodiments, the memory block programming order component 113 loads user data into the defect rate protection buffer 2 230 in programming phase 450. As the memory block programming order component 113 loads user data into the defect rate protection buffer 2 230, the memory block programming order component 113 also programs the user data into the second portion of the memory block bottom level 210.

[0105] As shown in programming phase 475, the memory block programming order component 113 uses the same programming direction for the memory block bottom level 210 as 425. The memory block programming order component 113 attempts to program the second portion of the memory block bottom level 210 starting from the word line directly below the last word line covered by the defect rate protection buffer 2 230. Because the portions of the memory block with the highest likelihood of failure (i.e., the first defect cluster 405 and the second defect cluster 410) have already been successfully programmed, it is less likely that a programming failure will occur during programming of the second portion of the memory block bottom level 210. Next, the memory block programming order component 113 prepares to program the next memory block. For example, the memory block programming order component 113 clears the defect rate protection buffer 1 220 and the defect rate protection buffer 2 230.

[0106] Figure 5This is a flowchart of an example method 500 for programming a memory block using defect rate information according to some embodiments of the present disclosure. Method 500 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 500 is performed by… Figure 1 The memory block programming sequence component 113 is executed. Although shown in a specific order or sequence, the order of the processes is modifiable unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are used in every embodiment. Other process flows are possible.

[0107] At operation 505, the processing device retrieves the defect rate footprint. For example, the processing device may retrieve data stored in memory (e.g., ...). Figure 1 The defect rate footprint is stored in local memory 119, memory device 140, or memory device 130. The defect rate footprint is based on known defects detected during and / or after manufacturing. In some embodiments, these manufacturing defects are detected via programming state failures, programming instant scan failures, and other associated failures. In some embodiments, the defect rate footprint is based on continuous updates to the firmware log. The firmware log is associated with programming state failures, programming instant scan failures, and other associated failures. In some embodiments, the programming log indicates whether a defect occurred and where the defect occurred (word line information).

[0108] At operation 510, the processing device determines whether the top layer has a higher defect severity. For example, based on the defect rate footprint retrieved in operation 505, the processing device can determine whether the top layer or the bottom layer of the memory block has a higher defect severity. If the processing device determines that the top layer has a higher defect severity, then the processing device proceeds to operation 515. However, if the processing device determines that the top layer does not have a higher defect severity, then the processing device proceeds to operation 535.

[0109] In some embodiments, defect severity is based on the number of word lines in the defective layer. In other embodiments, defect severity is based on the severity of the defect. In some embodiments, the memory block consists of a QLC, and each of the top and bottom layers is half of the entire memory block. In such embodiments, each of the top and bottom layers holds an amount of data equal to half the amount of data in the QLC block (e.g., the amount of data held in the MLC block).

[0110] In other embodiments, the memory block is composed of another cell type (e.g., MLC or TLC), and each of the top and bottom tiers is a half or other subdivision of the entire memory block. In these embodiments, each of the tiers thus holds an amount of data equal to the corresponding portion of the entire MLC or TLC block. For example, the memory block is composed of TLC, and each tier is one-third of the entire memory block. Each of the tiers thus holds an amount of data equal to one-third of the TLC block (e.g., the amount of data held in an SLC block). In an alternative example, the memory block is composed of MLC, and each tier is one-half of the entire memory block. Each of the tiers thus holds an amount of data equal to one-half of the MLC block (e.g., the amount of data held in an SLC block).

[0111] In some embodiments, although operation 510 can imply that there are only two tiers, top and bottom, the memory block can be divided into more than two tiers. For the purposes of this disclosure, the term tier refers to a subdivision of a memory block that can be programmed or erased independently. Thus, the higher the number of tiers in a memory block, the greater the flexibility in determining the location of the area with the highest probability of program failure. Tiers can not be the smallest subdivision of a memory block, and tiers themselves can also contain subdivisions.

[0112] At operation 515, the processing device determines whether the concentration of defects is located on the top of the top tier. For example, in response to determining that the top tier has a higher concentration of defects, the processing device can also determine the location on the top tier where the concentration of defects is highest. In some embodiments, this determination is based on the number of words containing defects and the location on the top tier where the defective word lines are located. In some embodiments, this determination is also based on the severity of the defects. If the processing device determines that the concentration of defects is on the top of the top tier, the processing device continues to operation 520. However, if the processing device determines that the concentration of defects is not on the top of the top tier, the processing device continues to operation 525.

[0113] At operation 520, the processing device programs the top tier from top to bottom. For example, in response to determining that the concentration of defects is on the top of the top tier, the processing device programs the top tier (starting from the top-most word line and programming in a downward direction).

[0114] At operation 525, the processing device programs the top tier from bottom to top. For example, in response to determining that the concentration of defects is not on the top of the top tier, the processing device programs the top tier (starting from the bottom-most word line and programming in an upward direction).

[0115] At operation 530, the processing device determines whether the current block has been completely programmed. For example, the processing device determines whether all levels of the current memory block have been programmed. If all levels have been programmed, the processing device continues to operation 555.

[0116] At operation 535, the processing device determines whether the defectivity is centered on top of the bottom level. For example, in response to determining that the top level does not have a higher defect severity, the processing device can also determine where the highest defect severity is located on the bottom level. In some embodiments, this determination is based on the number of defective word numbers and where the defective word lines are located on the top level. In some embodiments, this determination is also based on the severity of the defects. If the processing device determines that the defectivity is centered on top of the bottom level, the processing device continues to operation 540. However, if the processing device determines that the defectivity is not centered on top of the bottom level, the processing device continues to operation 545.

[0117] At operation 540, the processing device programs the bottom level from top to bottom. For example, in response to determining that the defectivity is centered on top of the bottom level, the processing device programs the bottom level (starting from the topmost word line and programming in a downward direction).

[0118] At operation 545, the processing device programs the bottom level from bottom to top. For example, in response to determining that the defectivity is not centered on top of the bottom level, the processing device programs the bottom level (starting from the bottommost word line and programming in an upward direction).

[0119] At operation 550, the processing device determines whether the current block has been completely programmed. For example, the processing device determines whether all levels of the current memory block have been programmed. If all levels have been programmed, the processing device continues to operation 555.

[0120] At operation 555, the processing device moves to program the next memory block. For example, the processing device can clear the buffers used to program the current block in preparation for the next block.

[0121] Figure 6 A flow diagram of an example method 600 to program a memory block using defectivity information according to some embodiments of the present disclosure. The method 600 can be performed by processing logic that can comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 600 is performed by a processing device, such as the processing device 110 of FIG. 1. Figure 1The memory block programming order component 113 executes. Although shown in a particular order or sequence, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0122] At operation 605, the processing device retrieves a defect rate footprint. For example, the processing device can retrieve a defect rate footprint stored in memory (e.g., local memory 119, memory device 140, or memory device 130) of the memory system 100. The defect rate footprint is based on known defects detected during and / or after manufacturing. In some embodiments, these manufacturing defects are detected by program status failures, program immediate scan failures, and other associated failures. In some embodiments, the defect rate footprint is continuously updated based on a firmware log. The firmware log is associated with program status failures, program immediate scan failures, and other associated failures. In some embodiments, the program log indicates whether a defect occurred and word line information where the defect occurred. Figure 1

[0123] At operation 610, the processing device determines a layer programming order. For example, the processing device determines a number of layers contained within the current block. In some embodiments, the current block is composed of a top layer and a bottom layer. In other embodiments, the current block has more than two distinct layers. After determining the number of layers contained, the processing device determines which layers should be programmed first based on the defect rate footprint retrieved in operation 605.

[0124] The defect rate footprint retrieved in 605 contains defect rate information related to the layers within the current block. The processing device can use this defect rate information to determine which layers should be programmed first. For example, layers with a higher concentration of defects or more defects should be programmed first. In some embodiments, the layer programming order is in the form of a page map indicating the order in which pages in the current block are programmed.

[0125] In some embodiments, the layer programming order also includes a layer programming direction. For example, each layer has a first word line and a last word line defined as top and bottom for the present disclosure. The processing device thus determines whether each layer is programmed from top to bottom or bottom to top.

[0126] At operation 615, the processing device programs the block according to the layer programming order. For example, the processing device loads user data into a buffer, such as buffer 120, and programs the data into the memory block according to the layer programming order. Figure 2 3 ​​and 4. The defect rate protection buffers 1 and 2 220 and 230 are then programmed with the user data for the current block according to the tier programming order determined in 610. In some embodiments, the processing device clears the buffers after each tier is programmed. For example, after the tier with the highest defect severity is programmed, the processing device clears the user data just written into the tier with the highest defect severity from the buffers. The processing device then stores the user data for the next tier to be programmed using the buffers.

[0127] Figure 7 An example machine of a computer system 700, within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, can be executed, is described. In some embodiments, the computer system 700 can correspond to a host system (e.g., the host system 120 of FIG. 1) that includes, is coupled to, or utilizes a memory sub-system (e.g., the memory sub-system 110 of FIG. 1) or can be used to perform operations of a controller (e.g., execute an operating system to perform operations of the memory block programming order component 113 of FIG. 1 corresponding to the Figure 1 Figure 1 Figure 1 In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine can operate in the capacity of a server or a client machine in client-server network environments, as a peer machine in peer-to-peer (or distributed) network environments, or as a server or a client machine in cloud computing infrastructure or environments.

[0128] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0129] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

[0130] ​​The processing device 702 represents one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like. More particularly, the processing device can be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or processors implementing a combination of instruction sets. The processing device 702 can also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. The computer system 700 can further include a network interface device 708 to communicate over the network 720.

[0131] The data storage system 718 can include a machine-readable storage medium 724 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 726 or software embodying any one or more of the methodologies or functions described herein. The instructions 726 can also reside, completely or at least partially, within the main memory 704 and / or within the processing device 702 during execution thereof by the computer system 700, the main memory 704 and the processing device 702 also constituting machine-readable storage media. The machine-readable storage medium 724, data storage system 718, and / or main memory 704 can correspond to memory subsystem 110 of FIG. 1. Figure 1

[0132] In one embodiment, the instructions 726 include instructions to implement functionality corresponding to a memory block programming order component (e.g., memory block programming order component 113 of FIG. 1). Figure 1 Although the machine-readable storage medium 724 is shown in an example embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

[0133] ​Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0134] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

[0135] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. For example, a computer system or other data processing system (e.g., controller 115) can perform the computer-implemented methods 500 and 600 in response to its processor executing a computer program (e.g., a sequence of instructions) contained in a memory or other non-transitory machine-readable storage medium. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0136] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as follows in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure described herein.

[0137] The disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions, which can be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium (e.g., read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory components, etc.).

[0138] In the foregoing specification, embodiments of the disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications can be made to a particular example embodiment without departing from the broader spirit and scope of embodiments of the disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Claims

1. A method comprising: retrieving a defect rate footprint of a portion of memory, the portion of memory consisting of a plurality of blocks; determining a tier programming order for a current block of the plurality of blocks based on the defect rate footprint, wherein the current block consists of a plurality of tiers and wherein the tier programming order comprises an order in which the plurality of tiers are programmed; and programming the plurality of tiers according to the determined tier programming order.

2. The method of claim 1, wherein each of the plurality of tiers comprises a top side and a bottom side, and wherein the tier programming order further comprises a direction in which each of the plurality of tiers is programmed, the direction indicating whether each of the plurality of tiers is programmed from the top side to the bottom side or from the bottom side to the top side.

3. The method of claim 1, further comprising: determining a defect severity for each of the plurality of tiers based on the defect rate footprint, wherein the tier programming order is an order from a highest defect severity to a lowest defect severity.

4. The method of claim 3, wherein the defect rate footprint comprises a location of one or more defects and the defect severity for each of the one or more defects.

5. The method of claim 1, wherein the plurality of tiers includes two tiers, each tier comprising one half of the current block.

6. The method of claim 1, further comprising: updating the defect rate footprint based on a program log indicating areas of the portion of memory that were determined to be defective during operation of the portion of memory.

7. The method of claim 6, wherein the program log comprises a log of locations of uncorrectable errors in the portion of memory.

8. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: retrieve a defect rate footprint of a portion of memory, the portion of memory consisting of a plurality of blocks; determine a tier programming order for a current block of the plurality of blocks based on the defect rate footprint, wherein the current block consists of a plurality of tiers and wherein the tier programming order comprises an order in which the plurality of tiers are programmed; and program the plurality of tiers according to the determined tier programming order.

9. The non-transitory computer-readable storage medium of claim 8, wherein each of the plurality of tiers comprises a top side and a bottom side, and wherein the tier programming order further comprises a direction in which each of the plurality of tiers is programmed, the direction indicating whether each of the plurality of tiers is programmed from the top side to the bottom side or from the bottom side to the top side.

10. The non-transitory computer-readable storage medium of claim 8, wherein the processing device is further to: determine a defect severity for each of the plurality of tiers based on the defect rate footprint, wherein the tier programming order is an order from a highest defect severity to a lowest defect severity.

11. The non-transitory computer-readable storage medium of claim 10, wherein the defect rate footprint comprises locations of one or more defects and the defect severity of each of the one or more defects.

12. The non-transitory computer-readable storage medium of claim 8, wherein the plurality of tiers includes two tiers, each tier comprising one half of the current block.

13. The non-transitory computer-readable storage medium of claim 8, wherein the processing device is further to: update the defect rate footprint based on a program log indicative of areas of the portion of memory determined to be defective during operation of the portion of memory.

14. The non-transitory computer-readable storage medium of claim 13, wherein the program log comprises a log of locations of uncorrectable errors in the portion of memory.

15. A system comprising: a plurality of memory devices; and a processing device operatively coupled with the plurality of memory devices to: retrieve a defect rate footprint for a portion of memory, the portion of memory comprised of a plurality of blocks; determine a tier programming order for a current block of the plurality of blocks based on the defect rate footprint, wherein the current block is comprised of a plurality of tiers, wherein each of the plurality of tiers comprises a top side and a bottom side, and wherein the tier programming order comprises an order in which the plurality of tiers are programmed and a direction in which each of the plurality of tiers is programmed, the direction indicating whether each of the plurality of tiers is programmed from the top side to the bottom side or from the bottom side to the top side; and program the plurality of tiers according to the determined tier programming order.

16. The system of claim 15, wherein the processing device is further to: determine a defect severity for each of the plurality of tiers based on the defect rate footprint, wherein the tier programming order is an order from a highest defect severity to a lowest defect severity.

17. The system of claim 16, wherein the defect rate footprint comprises locations of one or more defects and the defect severity of each of the one or more defects.

18. The system of claim 15, wherein the plurality of tiers includes two tiers, each tier comprising one half of the current block.

19. The system of claim 15, wherein the processing device is further to: update the defect rate footprint based on a program log indicative of areas of the portion of memory determined to be defective during operation of the portion of memory.

20. The system of claim 19, wherein the program log comprises a log of locations of uncorrectable errors in the portion of memory.

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