Electrode structure and polarization method for ultrathin back-gate ferroelectric dielectric layer

Abstract

The application discloses an electrode structure and a polarization method for an ultrathin back gate ferroelectric dielectric layer, which comprises a source electrode, a drain electrode and a gate electrode; a channel is arranged on the upper surface of the ferroelectric dielectric layer, the source electrode and the drain electrode are arranged at two ends of the channel respectively, and the gate electrode is arranged on the lower surface of the ferroelectric dielectric layer; a first polarization pulse input port is arranged between the source electrode and the gate electrode, and a second polarization pulse input port is arranged between the drain electrode and the gate electrode. The application solves the problems that the low breakdown strength is introduced due to the ultrathin thickness of the ferroelectric film, and the polarization electric field cannot be applied to the vertical channel due to the back gate structure, so that the polarization is insufficient, realizes the regulation and control of the polarization performance of the hafnium-based ultrathin ferroelectric film serving as a back gate dielectric layer in a field effect transistor, further improves the reliability and stability of the residual polarization field, and has important significance for constructing a floating gate structure of a field effect device and inhibiting device leakage and power consumption.

Description

Technical Field

[0001] This invention relates to the field of post-processing technology for ultrathin ferroelectric back-gate dielectric layers, specifically to an electrode structure and polarization method for ultrathin back-gate ferroelectric dielectric layers. Background Technology

[0002] As the miniaturization and integration of micro and nano devices continue to improve, Moore's Law is approaching its limits, placing higher demands on improving gate controllability and reducing device power consumption. Traditional field-effect transistors (FETs) use SiO2, Al2O3, HfO2, etc., as the gate dielectric layer, requiring a thickness of hundreds of nanometers to suppress the short-channel effect caused by quantum tunneling and the heat generated by gate-source leakage; moreover, a gate voltage needs to be continuously applied to control the channel characteristics, which not only introduces high power consumption but also shortens the device's lifespan.

[0003] Ferroelectric materials, such as polyvinylidene fluoride-trifluoroethylene copolymer (P(VDF-TrFE)) and lead zirconate titanate (PZT), offer a new approach to solving this problem. Their spontaneous polarization can be controlled by an external electric field. After the external voltage is removed, the remaining polarization field can stably act on the channel, serving as a gate dielectric layer and acting as a floating gate using the electrostatic field effect. During device operation, the channel carrier concentration can be effectively controlled without the need for an external gate voltage input, significantly suppressing device power consumption.

[0004] Traditional ferroelectric materials, such as P(VDF-TrFE), PZT, and (Ba,Sr)TiO3(BTO), only exhibit ferroelectric properties at thicknesses of 100 nanometers, and require polarization excitation voltages as high as 10–20 V, which does not meet the needs of practical applications. A novel high-performance hafnium oxide-based nano-ferroelectric thin film, however, maintains high remanent polarization at a thickness of only 10 nm, and the electric field acting on the channel reaches 10... 8 V / m can fully deplete the intrinsic carriers of the channel and improve the switching performance of the device. However, the ultrathin thickness of hafnium oxide-based ferroelectric materials, represented by aluminum-doped hafnium oxide (Al:HfO2) thin films, also leads to a low breakdown field strength. Especially when used as a back gate dielectric layer in devices, conventional gate-source voltage application methods are difficult to control the orientation of ferroelectric domains directly below the channel, resulting in insufficient polarization and inability to maintain long-term stability.

[0005] Therefore, for devices using hafnium oxide-based ferroelectric thin films as the back gate dielectric layer, the low breakdown strength of the ferroelectric thin films and the difficulty in introducing a vertically acting polarized electric field into the back gate structure have become urgent problems to be solved. Summary of the Invention

[0006] The purpose of this invention is to provide an electrode structure and polarization method for ultrathin back-gate ferroelectric dielectric layers to overcome the defects of existing technologies. This invention solves the problems of low breakdown strength caused by the thickness of ultrathin ferroelectric films and insufficient polarization caused by the inability of the back-gate structure to apply a polarization electric field acting vertically to the channel. It realizes the control of the polarization performance of hafnium oxide-based ultrathin ferroelectric films used as back-gate dielectric layers in field-effect transistors, further improving the reliability and stability of the residual polarization field. This is of great significance for constructing floating gate structures for field-effect devices and suppressing device leakage and power consumption.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] An electrode structure for an ultrathin back-gate ferroelectric layer includes a source, a drain, and a gate.

[0009] A channel is provided on the upper surface of the ferroelectric dielectric layer, the source and drain are respectively disposed at both ends of the channel, and the gate is disposed on the lower surface of the ferroelectric dielectric layer;

[0010] A first polarization pulse input port is provided between the source and the gate, and a second polarization pulse input port is provided between the drain and the gate.

[0011] Furthermore, the source and drain electrodes are prepared by ultraviolet lithography and electron beam evaporation processes.

[0012] Furthermore, the source and drain electrodes are Ti-Au composite electrodes.

[0013] Furthermore, the source and drain are square electrodes.

[0014] Furthermore, the ferroelectric dielectric layer is a hafnium oxide-based ultrathin ferroelectric thin film prepared by atomic layer deposition.

[0015] Furthermore, the thickness of the ferroelectric dielectric layer is 10 nm.

[0016] Furthermore, the gate is made of heavily p-doped silicon, with a gate thickness ranging from 500±15 μm, a gate resistivity ranging from 0.002 to 0.004 Ω·cm, and a gate crystal orientation of [missing information]. <100> ±0.5°.

[0017] A polarization method for an ultrathin back-gate ferroelectric layer includes:

[0018] Bipolar pulses are simultaneously and periodically applied between the gate and the source, and between the gate and the drain, through the first polarization pulse input port and the second polarization pulse input port, respectively. The waveform of the applied bipolar pulses includes two stages: step-by-step voltage boost and cyclic holding, until the ferroelectric dielectric layer is fully polarized.

[0019] Furthermore, the polarization excitation pulse source of the bipolar pulse is a dual-channel signal generator.

[0020] Furthermore, the coercive voltage of the ferroelectric dielectric layer is obtained through the hysteresis loop.

[0021] Compared with the prior art, the present invention has the following beneficial technical effects:

[0022] This invention designs an electrode structure and polarization method for ultrathin back-gate ferroelectric dielectric layers. To overcome the problems of low breakdown strength and insufficient control of ferroelectric domain orientation under the back-gate structure in current novel ultrathin nano-ferroelectric thin films, this invention proposes a polarization method that sets polarization pulse input ports between the gate-source and gate-drain electrodes, connects the source and drain to the two output channels of a signal generator, and grounds the gate. This allows for the simultaneous and periodic application of bipolar pulses between the gate-source and gate-drain electrodes. The pulse application is divided into two stages: step-by-step voltage boosting prevents rapid breakdown of the ferroelectric thin film, and cyclic holding promotes the alignment of ferroelectric domains along the direction of the applied electric field. The floating gate structure introduced by the residual polarization field controls the device to operate in a gateless mode, realizing ultrathin, low-power, high-performance micro / nano devices. Compared to the gate-source voltage polarization method commonly used in traditional organic ferroelectric thin films such as P(VDF-TrFE) and PZT, the back gate structure does not have a top gate electrode, and the external electric field cannot be applied perpendicularly to the ferroelectric thin film directly below the channel. The remaining polarization field is difficult to effectively control the channel characteristics. The method of applying polarization pulses to both the gate-source and gate-drain ports proposed in this invention increases the uniformity and control range of the polarization electric field, and enhances the stability and reliability of the floating gate.

[0023] Furthermore, the source and drain electrodes are square electrodes. The use of square electrodes in this invention increases the contact area between the semiconductor channel and the metal electrode, thereby improving the uniformity of the polarization electric field.

[0024] Furthermore, the source and drain electrodes are Ti-Au composite electrodes. Ti, as an interface improvement layer, will match the work function between the metal electrode and the semiconductor channel, effectively reducing the contact resistance and making it an ohmic contact.

[0025] Furthermore, when testing the hysteresis loop of the ferroelectric thin film, a Pt electrode can be directly fabricated on the surface of the ferroelectric dielectric layer to form a metal-ferroelectric-insulator-semiconductor (MFIS) structure. The hysteresis loop can be tested by applying a triangular pulse to obtain information such as the coercive voltage, breakdown electric field, residual polarization intensity, and maximum polarization intensity of the ferroelectric dielectric layer. Attached Figure Description

[0026] The accompanying drawings are provided to further understand the invention and constitute a part of this invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0027] Figure 1 This is a schematic diagram of the electrode structure circuit connection for the ultrathin back-gate ferroelectric layer described in this invention;

[0028] Figure 2 This is a schematic diagram of the pulse waveform applied using the polarization method described in this embodiment of the invention;

[0029] Figure 3 In this embodiment of the invention, the Al:HfO2 ferroelectric thin film is tuned to an unpolarized Fresh state and an upwardly polarized P state. up State and downward polarized P down The output characteristic curve of the device under the specified conditions.

[0030] In the figure, 1 is a silicon substrate, 2 is an Al:HfO2 ferroelectric back gate dielectric layer, 3 is a source-drain composite electrode, 4 is a two-dimensional MoS2 channel, and 5 is a signal generator. Detailed Implementation

[0031] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0032] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0033] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0034] Example 1

[0035] This invention provides an electrode structure for an ultrathin back-gate ferroelectric layer, comprising a source, a drain, and a gate;

[0036] A channel is provided on the upper surface of the ferroelectric dielectric layer, the source and drain are respectively disposed at both ends of the channel, and the gate is disposed on the lower surface of the ferroelectric dielectric layer;

[0037] A first polarization pulse input port is provided between the source and the gate, and a second polarization pulse input port is provided between the drain and the gate.

[0038] This invention designs an electrode structure and polarization method for ultrathin back-gate ferroelectric dielectric layers. To overcome the problems of low breakdown strength and insufficient control of ferroelectric domain orientation under the back-gate structure in current novel ultrathin nano-ferroelectric thin films, this invention proposes a polarization method that sets polarization pulse input ports between the gate-source and gate-drain electrodes, connects the source and drain to the two output channels of a signal generator 5 respectively, and grounds the gate. This allows for the simultaneous and periodic application of bipolar pulses between the gate-source and gate-drain electrodes. The pulse application is divided into two stages: step-by-step voltage boosting prevents rapid breakdown of the ferroelectric thin film, and cyclic maintenance promotes the alignment of ferroelectric domains along the direction of the applied electric field. The floating gate structure introduced by the residual polarization field controls the device to operate in a gateless mode, realizing ultrathin, low-power, high-performance micro / nano devices. Compared to the gate-source voltage polarization method commonly used in traditional organic ferroelectric thin films such as P(VDF-TrFE) and PZT, the back gate structure does not have a top gate electrode, and the external electric field cannot be applied perpendicularly to the ferroelectric thin film directly below the channel. The remaining polarization field is difficult to effectively control the channel characteristics. The method of applying polarization pulses to both the gate-source and gate-drain ports proposed in this invention increases the uniformity and control range of the polarization electric field, and enhances the stability and reliability of the floating gate.

[0039] Furthermore, the source and drain electrodes are square electrodes prepared by standard ultraviolet lithography and electron beam evaporation processes. The preparation process includes spin coating, baking, ultraviolet exposure, development, evaporation, and resist removal. Square electrodes can increase the contact area between the semiconductor channel and the metal electrode and improve the uniformity of the polarization electric field.

[0040] Preferably, the source and drain are square electrodes with dimensions of 100μm×100μm, and the distance between the source and drain is 5μm.

[0041] Furthermore, the source and drain electrodes are Ti-Au composite electrodes made of metal Ti and metal Au. Ti, as an interface improvement layer, will match the work function between the metal electrode and the semiconductor channel, effectively reducing the contact resistance and making it an ohmic contact.

[0042] Preferably, a Ti-Au composite electrode is prepared using 5 nm thick metallic Ti and 50 nm thick metallic Au.

[0043] Furthermore, the gate (back gate electrode) is made of heavily p-doped silicon with a thickness of 500±15μm, a resistivity of 0.002~0.004Ω·cm, and a crystal orientation of [missing information]. <100> ±0.5°.

[0044] Furthermore, the ferroelectric dielectric layer is a hafnium oxide-based ultrathin ferroelectric thin film prepared by standard atomic layer deposition. The specific preparation process includes steps such as etching the silicon substrate oxide layer, atomic layer deposition, and rapid annealing, and its thickness is about 10 nm.

[0045] Another aspect of the present invention relates to a polarization method for an ultrathin back-gate ferroelectric dielectric layer using the electrode structure of the present invention, comprising the following steps: applying periodic bipolar pulses simultaneously through a first polarization pulse input port and a second polarization pulse input port between the gate-source and gate-drain electrodes, respectively. The pulse waveform is divided into two stages: progressive voltage boost and cyclic holding. The magnitude of the coercive voltage is obtained through the hysteresis loop to achieve effective control of the polarization direction of the ferroelectric thin film.

[0046] Furthermore, the polarization excitation pulse source of the bipolar pulse is a dual-channel signal generator 5.

[0047] Furthermore, when testing the hysteresis loop of the ferroelectric thin film, a Pt electrode with a thickness of 30 nm and a diameter of 600 μm can be prepared on the surface of the ferroelectric dielectric layer obtained by atomic layer deposition using an ion sputtering coating instrument to form a metal-ferroelectric-insulator-semiconductor (MFIS) structure. A 1 kHz triangular pulse is applied to test the hysteresis loop in the aixACCT TF Analyzer 2000E ferroelectric testing system to obtain information such as the coercive voltage, breakdown electric field, remanent polarization intensity, and maximum polarization intensity of the ferroelectric thin film.

[0048] This invention proposes an effective polarization method for ultrathin ferroelectric thin films in back-gate structures. Traditional organic and perovskite ferroelectric materials have large thicknesses, high breakdown fields, and high operating voltages. Hafnium oxide-based thin films, as gate dielectric materials, are thin and prone to breakdown, making it difficult to fully polarize them as back-gate dielectric layers. By designing square electrodes to improve the uniformity of the applied polarization electric field, and by utilizing bipolar pulses through two stages of progressive voltage boosting and cyclic holding, the probability of film breakdown is reduced and the residual polarization retention effect is improved. This allows the ferroelectric floating gate to act stably in the channel for a long time, providing a new approach to reduce device power consumption, improve device integration, and meet the needs of flexible wearable applications.

[0049] Specifically, the polarization method for an ultrathin back-gate ferroelectric dielectric layer provided by this invention consists of two stages: step-by-step voltage increase and cyclic holding. Since the film thickness is only about 10 nm, the breakdown voltage is only around 10 V. The step-by-step voltage increase is to avoid breakdown caused by directly applying a high-amplitude pulse to the ultrathin ferroelectric film. Specifically, a bipolar pulse with a frequency of 1 kHz is set, with a rise time of 250 μs and a fall time of 250 μs. Its amplitude is gradually increased from 1 V to near the coercive voltage of the ferroelectric film. During this process, the hysteresis window of the film gradually opens, showing ferroelectric polarization performance.

[0050] During the cyclic holding phase, a bipolar pulse with a frequency of 1kHz is used, with a rise time of 250μs and a fall time of 250μs. The amplitude is kept constant as the coercive voltage and the pulse is cyclically repeated for 20 cycles to fully rotate the ferroelectric domains and arrange them along the direction of the applied electric field, thereby enhancing the polarization holding effect.

[0051] Since the effect of polarization pulses on the orientation of ferroelectric domains is closely related to the quality of the ferroelectric thin film crystal, the uniformity of the ferroelectric thin film, the quality of electrode deposition, the quality of the channel material, and the contact between the channel and the electrode, the amplitude of the pulse voltage applied during the cycle holding phase sometimes needs to be slightly greater than the coercive voltage value, and the number of cycles sometimes needs to be increased. Adjustments should be made according to the actual polarization situation, but care should be taken to prevent the thin film from being broken down.

[0052] During polarization reversal, due to the imperfect uniformity of the ferroelectric gate dielectric layer deposition and the asymmetry of the device structure, the peak voltages required for forward polarization and reverse polarization are not equal. To achieve polarization reversal, the bipolar pulses need to be reversed, and the peak value of reverse polarization is slightly greater than that of forward polarization.

[0053] Based on the application requirements of micro and nano devices, the ultrathin ferroelectric back gate dielectric layer is modulated into a polarization-oriented P-type. up Or polarized downward P down The gate voltage is then removed, and the remaining polarization field acts as a long-term stable floating gate on the channel, further modulating the channel carrier transport characteristics, avoiding continuous external gate voltage application, effectively suppressing gate-source leakage and reducing device power consumption.

[0054] Furthermore, the polarization electrode structure and polarization method of the present invention have high versatility and are applicable to the polarization control of hafnium oxide-based ultrathin ferroelectric thin films doped with elements such as Al, Zr, Si, Y, Sr, and La in the back gate structure.

[0055] Example 2

[0056] This embodiment provides an ultrathin phototransistor with a CVD-grown monolayer MoS2 channel and a 10nm thick Al:HfO2 ferroelectric thin film as the back gate dielectric layer. The device structure diagram and polarization circuit connection diagram are shown below. Figure 1 As shown.

[0057] The ultrathin phototransistor, from bottom to top, consists of: a heavily p-doped silicon substrate 1 with a thickness of 500±15 μm; an Al:HfO2 ferroelectric back gate dielectric layer 2 with an aluminum doping concentration of 7 mol% and a film thickness of 10 nm, obtained through standard atomic layer deposition and rapid annealing; a source-drain composite electrode 3, with a Ti metal thickness of 5 nm and an Au metal thickness of 50 nm, the patterned source-drain electrode obtained through standard ultraviolet lithography and electron beam evaporation; and a two-dimensional MoS2 channel 4, grown by chemical vapor deposition (CVD) with a thickness of 0.65 nm (single layer), the source and drain of which are connected to the two output channels of a signal generator 5, and the gate is grounded. Figure 1 The two polarization pulse input ports are V1 and V2.

[0058] In this embodiment, as Figure 2 As shown, polarization excitation pulses V1 and V2 are simultaneously applied at the first polarization pulse input port between the gate and source and the second polarization pulse input port between the gate and drain. The bipolar pulse frequency in the step-by-step boosting stage is 1kHz, with both the rising and falling edges being 250μs. The amplitude increases from 1V to 7V (as can be seen from the hysteresis loop test results, the coercivity voltage of this ferroelectric thin film is about 7V), gradually opening the hysteresis window of the ferroelectric thin film and displaying its polarization characteristics.

[0059] During the cyclic holding phase, bipolar pulses with a frequency of 1 kHz and an amplitude of 7 V are simultaneously applied to V1 and V2 for 20 cycles, promoting the ferroelectric domains to align along the direction of the applied electric field. After the polarization pulse voltage is removed, the residual polarization field of the ferroelectric thin film is in the upward polarized P state. up In this state, a scanning voltage of -1V to 1V is applied between the source and drain electrodes to obtain P. up The output characteristic curve at that time.

[0060] Subsequently, a reverse bipolar pulse with a frequency of 1kHz and an amplitude of 8V is simultaneously applied to V1 and V2 for 20 cycles, causing the ferroelectric domains to flip. Due to the asymmetry of the device structure, P... down The required polarization pulse peak value is slightly higher than P. up The pulse was then removed, and the residual polarization field of the downward-polarized ferroelectric thin film, i.e., P, was measured. down The output characteristic curve of the device.

[0061] like Figure 3 As shown, P up In the current channel, the carriers are in a state of aggregation due to the floating gate modulation guided by the residual polarization field of the Al:HfO2 ferroelectric thin film, and the source-drain current increases by two orders of magnitude compared to the Fresh state; P downIn the fresh state, the carriers in the channel are fully depleted by the ferroelectric floating gate, the source and drain currents are reduced by two orders of magnitude compared to the fresh state, and the device's on / off ratio is at least 10. 4 The polarization method proposed in this invention effectively controls the polarization state of ultrathin hafnium oxide-based ferroelectric thin films in back-gate structures. It requires no gate voltage input during operation, and the residual polarization field provides long-term stability, thereby regulating channel characteristics, suppressing leakage caused by tunneling, and significantly reducing device power consumption.

[0062] As can be seen from the above results, the polarization method for ultrathin back-gate ferroelectric dielectric layers disclosed in this invention solves the problems of low breakdown strength caused by the ultrathin thickness of hafnium oxide-based ferroelectric thin films and insufficient and unstable polarization caused by the inability of the polarization electric field to act perpendicularly due to the back-gate structure. The method is simple and highly reliable, and shows broad prospects in the fabrication and control of large-scale, highly integrated, low-power micro-nano device arrays.

[0063] The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solution based on the technical concept proposed in this invention shall fall within the scope of protection of the claims of this invention.

Claims

1. A polarization method for an ultrathin back-gate ferroelectric layer, based on an electrode structure for the ultrathin back-gate ferroelectric layer, wherein the electrode structure for the ultrathin back-gate ferroelectric layer includes a source, a drain, and a gate; A channel is provided on the upper surface of the ferroelectric dielectric layer, the source and drain are respectively disposed at both ends of the channel, and the gate is disposed on the lower surface of the ferroelectric dielectric layer; A first polarization pulse input port is provided between the source and the gate, and a second polarization pulse input port is provided between the drain and the gate; The thickness of the ferroelectric dielectric layer is 10 nm; Its features include: Bipolar pulses are simultaneously and periodically applied between the gate and the source, and between the gate and the drain, through the first polarization pulse input port and the second polarization pulse input port, respectively. The waveform of the applied bipolar pulse includes two stages: step-by-step voltage boost and cyclic holding, until the ferroelectric dielectric layer is fully polarized. The two stages of gradual voltage increase and cyclic holding are as follows: in the gradual voltage increase stage, the voltage amplitude gradually increases to near the coercive voltage of the ferroelectric thin film, and in the cyclic holding stage, the amplitude remains constant at the coercive voltage.

2. The polarization method for an ultrathin back-gate ferroelectric layer according to claim 1, characterized in that, The polarization excitation pulse source of the bipolar pulse is a dual-channel signal generator (5).

3. The polarization method for an ultrathin back-gate ferroelectric layer according to claim 1, characterized in that, The coercive voltage of the ferroelectric dielectric layer is obtained through the hysteresis loop.

4. The polarization method for an ultrathin back-gate ferroelectric layer according to claim 1, characterized in that, The source and drain electrodes are prepared by ultraviolet lithography and electron beam evaporation processes.

5. The polarization method for an ultrathin back-gate ferroelectric layer according to claim 1, characterized in that, The source and drain electrodes are Ti-Au composite electrodes.

6. The polarization method for an ultrathin back-gate ferroelectric layer according to claim 1, characterized in that, The source and drain are square electrodes.

7. The polarization method for an ultrathin back-gate ferroelectric layer according to claim 1, characterized in that, The ferroelectric dielectric layer is a hafnium oxide-based ultrathin ferroelectric thin film prepared by atomic layer deposition.

8. The polarization method for an ultrathin back-gate ferroelectric layer according to claim 1, characterized in that, The gate is made of heavily p-doped silicon, with a thickness ranging from 500±15 μm and a resistivity ranging from 0.002 to 0.004 Ω·cm. The crystal orientation of the gate is... <100> ±0.5°.

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