A no-off-chip capacitor LDO with improved PSR performance and fast transient response

Abstract

The application discloses a slice-out capacitor-free LDO with improved PSR performance and fast transient response, and relates to the technical field of integrated circuits, in particular to a slice-out capacitor-free LDO with improved PSR performance and fast transient response. The application discloses a slice-out capacitor-free LDO with improved PSR performance and fast transient response, and relates to the technical field of integrated circuits, in particular to a slice-out capacitor-free LDO with improved PSR performance and fast transient response. The application discloses a slice-out capacitor-free LDO with improved PSR performance and fast transient response, and relates to the technical field of integrated circuits, in particular to a slice-out capacitor-free LDO with improved PSR performance and fast transient response. The application discloses a slice-out capacitor-free LDO with improved PSR performance and fast transient response, and relates to the technical field of integrated circuits, in particular to a slice-out capacitor-free LDO with improved PSR performance and fast transient response. The application discloses a slice-out capacitor-free LDO with improved PSR performance and fast transient response, and relates to the technical field of integrated circuits, in particular to a slice-out capacitor-free LDO with improved PSR performance and fast transient response. The application discloses a slice-out capacitor-free LDO with improved PSR performance and fast transient response, and relates to the technical field of integrated circuits, in particular to a slice-out capacitor-free LDO with improved PSR performance and fast transient response. The application discloses a slice-out capacitor-free LDO with improved PSR performance and fast transient response, and relates to the technical field of integrated circuits, in particular to a slice-out capacitor-free LDO with improved PSR performance and fast transient response. The application discloses a slice-out capacitor-free LDO with improved PSR performance and fast transient response, and relates to the technical field of integrated circuits, in particular to a slice-out capacitor-free LDO with improved PSR performance and fast transient response. The application discloses a slice-out capacitor-free LDO with improved PSR performance and fast transient response, and relates to the technical field of integrated circuits, in particular to a slice-out capacitor-free LDO with improved PSR performance and fast transient response. The application discloses a slice-out capacitor-free LDO with improved PSR performance and fast transient response, and relates to the technical field

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of LDO circuit, and particularly relates to a Capless LDO with improved PSR performance and fast transient response. BACKGROUND

[0002] As a linear output voltage regulator, LDO (low dropout linear regulator) is widely used due to its small size, low noise, low output ripple, no electromagnetic interference, simple design, and few peripheral components. In a laser radar receiver, AFE (analog front-end circuit), ADC (analog-to-digital converter), TDC (time-to-digital converter) and other modules in the laser radar receiver need to use a power supply, and these modules are very sensitive to power supply noise. Therefore, LDO is needed to suppress power supply noise to ensure signal integrity.

[0003] Compared with the LDO with large off-chip load capacitor, the Capless LDO has higher integration, which can reduce the number of chip pins and the use of large off-chip load capacitor, thereby reducing the cost and the PCB area. However, the existing Capless LDO has the shortcomings that the PSR performance needs to be improved, especially the PSR performance at medium and high frequencies. Another difficulty is to ensure good PSR performance under large load capability, and the load capability of the existing Capless LDO with high PSR is generally within 20 mA (milliampere), which is difficult to use in a multi-channel laser radar receiver, and the application is limited. In addition, the existing Capless LDO lacks a large off-chip load capacitor at the output end, and when the load current changes in steps, the voltage drop and overshoot are difficult to quickly suppress, therefore, the transient response performance needs to be improved to suppress the voltage drop and overshoot. SUMMARY

[0004] In view of the deficiencies of the prior art, the present application aims to provide a Capless LDO with improved PSR performance and fast transient response, which can solve the problems described in the background.

[0005] The technical scheme for achieving the object of the present application is as follows: a no-off-chip capacitor LDO with improved PSR performance and fast transient response, comprising resistors R1, R2, R3, R4, capacitors C1, C2, C3, MOS transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, M15, M16, M17, an operational amplifier OP2, an error amplifier EA and a ripple amplification circuit RAC, the gate and the drain of the MOS transistor M1 are connected, and then connected to a 10 mu A constant current source and a voltage VDD, one end of a first series circuit is also connected to the voltage VDD, the other end of the first series circuit is connected to the source of the MOS transistor M1 and is grounded, the first series circuit comprises the resistors R1, R2 and R3 connected in series, one end of the resistor R1 is connected to the voltage VDD, one end of the resistor R3 is connected to the source of the MOS transistor M1, the sources of the MOS transistors M2, M5, M6, M8, M15 and M15 are connected to the voltage VDD, one end of the resistor R4, one end of the capacitor C1, the sources of the MOS transistors M10, M11, M12, one end of a first parallel circuit and one end of the capacitor C3 are connected to the ground end to which the source of the MOS transistor M1 is connected, the first parallel circuit comprises the capacitor C LOAD and the resistor R LOAD , the other end of the first parallel circuit, one end of the capacitor C2 and the sources of the MOS transistors M11 and M13 are connected to the drain of the MOS transistor M15, and form an output end VOUT_LDO of the no-off-chip capacitor LDO,

[0006] the VP access end of the operational amplifier OP2 is connected to the connection node between the resistors R2 and R3, the VN access end of the operational amplifier OP2 is connected to the sources of the MOS transistors M4 and the other end of the resistor R4, respectively, the VBIAS access end of the operational amplifier OP2 is connected to the VBIAS access end of the ripple amplification circuit RAC, the VBIAS access end of the error amplifier EA, the gate of the MOS transistor M12 and the gate of the MOS transistor M1, respectively, the output end of the operational amplifier OP2 is connected to the gate of the MOS transistor M4, the drain of the MOS transistor M4 is connected to the other end of the capacitor C1, the drain of the MOS transistor M3, the gate of the MOS transistor M2 and the gate of the MOS transistor M8, respectively, the drain of the MOS transistor M2 is connected to the source of the MOS transistor M3, the gate of the MOS transistor M3 is connected to the gate of the MOS transistor M7 and is connected to a bias voltage VB_CAS,

[0007] The gate of the MOS transistor M5, the gate of the MOS transistor M6, the drain of the MOS transistor M10, and the gate of the MOS transistor M9 are commonly connected together, the drain of the MOS transistor M6, the drain of the MOS transistor M9, the drain of the MOS transistor M7, the gate of the MOS transistor Mp, and the gate of the MOS transistor M15 are commonly connected together, the source of the MOS transistor M9, the gate of the MOS transistor M10, the gate of the MOS transistor M11, the drain of the MOS transistor M12, and the drain of the MOS transistor M13 are commonly connected together, the gate of the MOS transistor M13 is connected with the other end of the capacitor C3 and the output end of the error amplifier EA,

[0008] The input end VP of the error amplifier EA is connected with the voltage input end VREF of the ripple amplification circuit RAC, and then the two are commonly connected with a 1.8V reference voltage, the input end ADA_VBIAS of the error amplifier EA, the gate of the MOS transistor M17, the drain of the MOS transistor M17, the input end ADA_VBIAS of the ripple amplification circuit RAC, and the source of the MOS transistor M16 are commonly connected, and the input end VN of the error amplifier EA is connected with the output end VOUT_LDO,

[0009] The other end of the capacitor C2 is connected with the connecting node between the resistor R1 and the resistor R2 and the input end of the inverter U1, respectively, the output end of the inverter U1 is connected with the gate of the MOS transistor M14, the source of the MOS transistor M14 is grounded, and the drain of the MOS transistor M14, the gate of the MOS transistor Mp, the gate of the MOS transistor M15, the drain of the MOS transistor M7, the drain of the MOS transistor M6, and the drain of the MOS transistor M9 are commonly connected,

[0010] The output end VBODY of the ripple amplification circuit RAC is further connected with the substrate of the MOS transistor Mp.

[0011] Further, the MOS tube MP, the MOS tube M13, the MOS tube M10, the MOS tube M5 and the MOS tube M6 constitute a first loop, which is used for: when the voltage output by the output terminal VOUT_LDO decreases, the drain voltage of the MOS tube M13 decreases, the gate voltage of the MOS tube M10 decreases, the drain voltage of the MOS tube M10 increases, the gate voltage of the MOS tube M6 increases, the current of the MOS tube M6 decreases, thereby the gate voltage of the MOS tube Mp decreases, so that the MOS tube Mp can provide greater current, thereby the output voltage of the output terminal VOUT_LDO increases; when the voltage output by the output terminal VOUT_LDO increases, the drain voltage of the MOS tube M13 increases, the gate voltage of the MOS tube M10 increases, the drain voltage of the MOS tube M10 decreases, the gate voltage of the MOS tube M6 decreases, the current of the MOS tube M6 increases, thereby the gate voltage of the MOS tube Mp increases, so that the current provided by the MOS tube Mp decreases, thereby the output voltage of the output terminal VOUT_LDO decreases,

[0012] The MOS tube Mp, the MOS tube M13 and the MOS tube M9 constitute a second loop, which is a FVF structure, and is used for: when the voltage output by the output terminal VOUT_LDO decreases, the drain voltage of the MOS tube M13 decreases, the gate voltage of the MOS tube M10 decreases and the source voltage of the MOS tube M9 decreases, so that the drain voltage of the MOS tube M10 increases and the gate voltage of the MOS tube M9 increases, the current passing through the MOS tube M9 increases, thereby the gate voltage of the MOS tube Mp decreases, so that the MOS tube Mp can provide greater current, thereby the output voltage of the output terminal VOUT_LDO increases; when the voltage output by the output terminal VOUT_LDO increases, the drain voltage of the MOS tube M13 increases, the gate voltage of the MOS tube M10 increases and the source voltage of the MOS tube M9 increases, so that the drain voltage of the MOS tube M10 decreases and the gate voltage of the MOS tube M9 decreases, the current passing through the MOS tube M9 decreases, thereby the gate voltage of the MOS tube Mp increases, so that the current provided by the MOS tube Mp decreases, thereby the output voltage of the output terminal VOUT_LDO decreases,

[0013] The MOS tube Mp, the MOS tube M13 and the MOS tube M11 constitute a third loop, which is a pull-down loop, and is used for: when the output voltage of the output terminal VOUT_LDO rapidly increases, the drain voltage of the MOS tube M13 rapidly increases, the MOS tube M11 rapidly opens, thereby the output voltage of the output terminal VOUT_LDO is rapidly pulled down,

[0014] The MOS transistor Mp, the capacitor C2, the inverter U1 and the MOS transistor M14 constitute a fourth loop, and the fourth loop comprises a TEC circuit for suppressing the drop of the output voltage of the output terminal VOUT_LDO, wherein the common mode level of the input terminal of the inverter U1 is set to When the output voltage of the output terminal VOUT_LDO rapidly drops, the inverter U1 outputs a high level, rapidly opens the MOS transistor M14, thereby rapidly lowers the gate voltage of the MOS transistor Mp, and rapidly raises the output voltage of the output terminal VOUT_LDO,

[0015] The MOS transistor Mp, the error amplifier EA and the MOS transistor M13 constitute a fifth loop, and the fifth loop is a slow loop circuit for further improving the loop gain of the main loop, thereby improving the load regulation rate and the linear regulation rate of the output terminal VOUT_LDO, and further improving the PSR performance at the middle and low frequencies.

[0016] Further, the error amplifier EA is an amplifier with the accelerating transistors M21 and M22 for realizing gain improvement, compares the output voltage of the output terminal VOUT_LDO with the reference voltage VREF, and feeds back the amplified difference signal of the output voltage and the reference voltage to the gate of the MOS transistor M13, thereby ensuring that the output voltage of the output terminal VOUT_LDO is equal to the reference voltage VREF, and realizing a high loop gain.

[0017] Further, the error amplifier EA includes MOS transistor M18, MOS transistor M19, MOS transistor M20, MOS transistor M21, MOS transistor M22, MOS transistor M23, MOS transistor M24, MOS transistor M25, MOS transistor M26, MOS transistor M27, MOS transistor M28, MOS transistor M29, the source of MOS transistor M18, the source of MOS transistor M20, the source of MOS transistor M21, the source of MOS transistor M22, the source of MOS transistor M23, the source of MOS transistor M24 are connected together and are connected to voltage VDD, the drain of MOS transistor M18, the drain of MOS transistor M19, the gate of MOS transistor M19, the gate of MOS transistor M29 are connected together, the source of MOS transistor M19, the source of MOS transistor M27, the source of MOS transistor M28, the source of MOS transistor M29 are connected to ground, the gate of MOS transistor M18, the gate of MOS transistor M20, the drain of MOS transistor M20, the drain of MOS transistor M21, the gate of MOS transistor M22, the drain of MOS transistor M25 are connected together, the gate of MOS transistor M21, the drain of MOS transistor M22, the drain of MOS transistor M23, the gate of MOS transistor M23, the gate of MOS transistor M24, the drain of MOS transistor M26 are connected together, the source of MOS transistor M25, the source of MOS transistor M26, the drain of MOS transistor M27, the drain of MOS transistor M28 are connected together, the gate of MOS transistor M25 is the input terminal VN of the error amplifier EA, the gate of MOS transistor M26 is the input terminal VP of the error amplifier EA, the gate of MOS transistor M27 is the input terminal VBIAS of the error amplifier EA, the gate of MOS transistor M28 is the input terminal ADA_VBIAS of the error amplifier EA, the drain of MOS transistor M24 and the drain of MOS transistor M29 are connected together and are the output terminal VOUT_EA of the error amplifier EA.

[0018] Further, the ripple amplification circuit RAC comprises a resistor R5, a resistor R6, a resistor R7, a resistor R8, a capacitor C4, a capacitor C5, a MOS transistor M30 and an operational amplifier OP1, one end of the resistor R5 and the resistor R6 are connected together and serve as an input terminal VREF of the ripple amplification circuit RAC, the other end of the resistor R5 is connected to an input terminal VN of the operational amplifier OP1 and one end of the resistor R7 respectively, the other end of the resistor R6 is connected to one end of the capacitor C4 and an input terminal VP of the operational amplifier OP1 respectively, the other end of the capacitor C4 is connected to a voltage VDD, the other end of the resistor R7 is connected to a drain of the MOS transistor M30, a gate of the MOS transistor M30 is connected to the voltage VDD, a source of the MOS transistor M30 is connected to an output terminal VOUT_OP1 of the operational amplifier OP1 and one end of the capacitor C5 respectively, the other end of the capacitor C5 is connected to one end of the resistor R8 and serves as an output terminal VBOD Y of the ripple amplification circuit RAC, the other end of the resistor R8 is connected to the voltage VDD, an input terminal VBIAS of the operational amplifier OP1 serves as an input terminal VBIAS of the ripple amplification circuit RAC, and an input terminal ADA_VBIAS of the operational amplifier OP1 serves as an input terminal ADA_VBIAS of the ripple amplification circuit RAC.

[0019] Further, the operational amplifier OP1 comprises MOS transistor M31, MOS transistor M32, MOS transistor M33, MOS transistor M34, MOS transistor M35, MOS transistor M36, MOS transistor M37, MOS transistor M38, MOS transistor M39, MOS transistor M40, MOS transistor M41, MOS transistor M42, MOS transistor M43, MOS transistor M44, MOS transistor M45, MOS transistor M46, MOS transistor M47, the source of MOS transistor M31, the source of MOS transistor M32, the source of MOS transistor M33, the source of MOS transistor M34, the source of MOS transistor M41, the source of MOS transistor M42 are connected together and connected to voltage VDD, the drain of MOS transistor M31, the drain of MOS transistor M39, the gate of MOS transistor M39, the gate of MOS transistor M40 are connected together, the source of MOS transistor M39, the source of MOS transistor M37, the source of MOS transistor M38, the source of MOS transistor M40, the source of MOS transistor M44, the source of MOS transistor M45, the source of MOS transistor M46, the source of MOS transistor M47 are connected together and connected to ground, the gate of MOS transistor M31, the gate of MOS transistor M32, the drain of MOS transistor M32, the drain of MOS transistor M35 are connected together, the gate of MOS transistor M34, the gate of MOS transistor M33, the drain of MOS transistor M33, the drain of MOS transistor M36 are connected together, the source of MOS transistor M35, the source of MOS transistor M36, the drain of MOS transistor M37, the drain of MOS transistor M38 are connected together, the gate of MOS transistor M35 is the input terminal VN of the operational amplifier OP1, the gate of MOS transistor M36 is the input terminal VP of the operational amplifier OP1, the gate of MOS transistor M37 is the input terminal VBIAS of the operational amplifier OP1, the gate of MOS transistor M38 is the input terminal ADA_VBIAS of the operational amplifier OP1, the drain of MOS transistor M40, the drain of MOS transistor M34, the gate of MOS transistor M43 are connected together, the drain of MOS transistor M41, the source of MOS transistor M43, the drain of MOS transistor M45 are connected together, the gate of MOS transistor M41, the gate of MOS transistor M42, the drain of MOS transistor M42, the drain of MOS transistor M46, the drain of MOS transistor M47 are connected together, the drain of MOS transistor M43, the gate of MOS transistor M45, the drain of MOS transistor M44 are connected together, the gate of MOS transistor M44 is connected to a bias voltage VB1, the gate of MOS transistor M46 is the input terminal VBIAS of the operational amplifier OP1, the gate of MOS transistor M47 is the input terminal ADA_VBIAS of the operational amplifier OP1,

[0020] The connection node, in which the drain of the MOS transistor M41, the source of the MOS transistor M43 and the drain of the MOS transistor M45 are connected together, is the output terminal VOUT_OP1 of the operational amplifier OP1, and the output terminal VOUT_OP1 is connected to the connection node between the capacitor C5 and the source of the MOS transistor M30.

[0021] The beneficial effects of the present application are: the present application adopts the TEC structure, the fast loop formed by the fourth loop, the output voltage drop when the load current jumps is suppressed, and the transient response is improved. By adopting the error amplifier EA, the difference between the output voltage of the LDO and the reference voltage VREF is amplified and fed back to the gate of the control tube of the FVF structure, thereby introducing the fifth loop as a slow loop, increasing the gain of the loop, improving the load regulation rate and the linear regulation rate, and further improving the PSR performance of the medium and low frequency. Since the RFFC structure is adopted, the power supply ripple of the medium frequency is amplified and injected into the gate of the power tube, and the medium frequency PSR performance of the LDO is improved. Since the RAC structure is adopted, the power supply ripple of the high frequency is amplified and injected into the substrate of the power tube through the RC high-pass network, and the high frequency PSR performance of the LDO is improved. In addition, the advantages of the RC high-pass network are: on the one hand, the load capacitance driven by the RAC is reduced, ensuring that the RAC still has a certain amplification capacity at high frequency, and on the other hand, a VDD bias voltage is provided for the substrate of the power tube, preventing the risk of forward conduction of the parasitic diode of the source-substrate of the power tube. And even in the case of large load current, the LDO still has good PSR performance in the frequency range of 1Hz-10GHz. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 It is a circuit schematic diagram of the present application;

[0023] Figure 2 It is Figure 1 a circuit schematic diagram of the middle A part;

[0024] Figure 3 It is Figure 1 a circuit schematic diagram of the middle B part;

[0025] Figure 4 It is Figure 1 a circuit schematic diagram of the middle C part;

[0026] Figure 5 It is Figure 1 an internal circuit schematic diagram of the error amplifier EA in the middle;

[0027] Figure 6 It is Figure 1 an internal circuit schematic diagram of the ripple amplification circuit RAC in the middle;

[0028] Figure 7 It isFigure 6 Internal circuit schematic diagram of the operational amplifier OP1;

[0029] Figure 8 Load transient response result schematic diagram of the LDO without off-chip capacitor of the present application;

[0030] Figure 9 PSR result comparison diagram of the LDO with and without RAC and RFFC structure when the load current is 100 mA;

[0031] Figure 10 PSR result comparison diagram of the TIA with and without LDO power supply;

[0032] Figure 11 Load regulation result diagram of the LDO under different power supply voltages;

[0033] Figure 12 Linear regulation result diagram of the LDO under different load currents. DETAILED DESCRIPTION

[0034] The present application will be further described below in conjunction with the drawings and specific embodiments:

[0035] As Figures 1-12As shown, a piece of external capacitor LDO with improved PSR performance and fast transient response includes resistance R1, resistance R2, resistance R3, resistance R4, capacitor C1, capacitor C2, capacitor C3, MOS tube M1, MOS tube M2, MOS tube M3, MOS tube M4, MOS tube M5, MOS tube M6, MOS tube M7, MOS tube M8, MOS tube M9, MOS tube M10, MOS tube M11, MOS tube M12, MOS tube M13, MOS tube M14, MOS tube M15, MOS tube M16, MOS tube M17, operational amplifier OP2, error amplifier EA and ripple amplification circuit RAC, the gate and drain of MOS tube M1 are connected, then connected to 10uA constant current source, then connected to voltage VDD, one end of the first series circuit is also connected to voltage VDD, the other end of the first series circuit is connected to the source of MOS tube M1 and is commonly grounded, the first series circuit includes resistance R1, resistance R2 and resistance R3 connected in series, one end of resistance R1 is connected to voltage VDD, one end of resistance R3 is connected to the source of MOS tube M1, the sources of MOS tube M2, MOS tube M5, MOS tube M6, MOS tube M8, MOS tube M15 and MOS tube M15 are commonly connected and then connected to voltage VDD, one end of resistance R4, one end of capacitor C1, the sources of MOS tube M10, MOS tube M11, MOS tube M12, one end of the first parallel circuit, one end of capacitor C3, one end of the source of MOS tube M17 are commonly connected and then connected to the ground end connected to the source of MOS tube M1, the first parallel circuit includes capacitor C LOAD and resistance R LOAD , the other end of the first parallel circuit, one end of capacitor C2, the drain of MOS tube M11 and the source of MOS tube M13 are commonly connected to the drain of MOS tube M15, and form the output end VOUT_LDO of the piece of external capacitor LDO.

[0036] The VP access end of operational amplifier OP2 is connected to the connection node between resistance R2 and resistance R3, the VN access end of operational amplifier OP2 is respectively connected to the source of MOS tube M4 and the other end of resistance R4, the VBIAS access end of operational amplifier OP2 is respectively connected to the VBIAS access end of ripple amplification circuit RAC, the VBIAS access end of error amplifier EA, the gate of MOS tube M12 and the gate of M1, the output end of operational amplifier OP2 is connected to the gate of MOS tube M4, the drain of MOS tube M4 is respectively connected to the other end of capacitor C1, the drain of MOS tube M3, the gate of MOS tube M2, the gate of MOS tube M8, the drain of MOS tube M2 is connected to the source of MOS tube M3, the gate of MOS tube M3 is connected to the gate of MOS tube M7 and is connected to bias voltage VB_CAS.

[0037] The gate of the MOS transistor M5, the gate of the MOS transistor M6, the drain of the MOS transistor M10, and the gate of the MOS transistor M9 are connected together, the drain of the MOS transistor M6, the drain of the MOS transistor M9, the drain of the MOS transistor M7, the gate of the MOS transistor Mp, and the gate of the MOS transistor M15 are connected together, the source of the MOS transistor M9, the gate of the MOS transistor M10, the gate of the MOS transistor M11, the drain of the MOS transistor M12, and the drain of the MOS transistor M13 are connected together, and the gate of the MOS transistor M13 is connected to the other end of the capacitor C3 and the output end of the error amplifier EA.

[0038] The input end VP of the error amplifier EA and the voltage input end VREF of the ripple amplification circuit RAC are connected to a 1.8V reference voltage, the input end ADA_VBIAS of the error amplifier EA, the gate of the MOS transistor M17, the drain of the MOS transistor M17, the input end ADA_VBIAS of the ripple amplification circuit RAC, and the source of the MOS transistor M16 are connected together, and the input end VN of the error amplifier EA is connected to the output end VOUT_LDO.

[0039] The other end of the capacitor C2 is connected to a connection node between the resistor R1 and the resistor R2 and the input end of the inverter U1, the output end of the inverter U1 is connected to the gate of the MOS transistor M14, the source of the MOS transistor M14 is grounded, and the drain of the MOS transistor M14, the gate of the MOS transistor Mp, the gate of the MOS transistor M15, the drain of the MOS transistor M7, the drain of the MOS transistor M6, and the drain of the MOS transistor M9 are connected together.

[0040] The output end VBODY of the ripple amplification circuit RAC is further connected to the substrate of the MOS transistor Mp, so as to inject the amplified power supply ripple into the substrate of the MOS transistor Mp, so that the ripple current is 0 at high frequency, and the PSR performance at high frequency is improved.

[0041] The MOS transistor MP, the MOS transistor M13, the MOS transistor M10, the MOS transistor M5 and the MOS transistor M6 constitute a first loop (i.e. LOOP1 in the figure). When the voltage output by the output terminal VOUT_LDO decreases, the drain voltage of the MOS transistor M13 decreases, the gate voltage of the MOS transistor M10 decreases, the drain voltage of the MOS transistor M10 increases, the gate voltage of the MOS transistor M6 increases, the current of the MOS transistor M6 decreases, the gate voltage of the MOS transistor Mp decreases, the MOS transistor Mp can provide more current, and the output voltage of the output terminal VOUT_LDO increases; when the voltage output by the output terminal VOUT_LDO increases, the drain voltage of the MOS transistor M13 increases, the gate voltage of the MOS transistor M10 increases, the drain voltage of the MOS transistor M10 decreases, the gate voltage of the MOS transistor M6 decreases, the current of the MOS transistor M6 increases, the gate voltage of the MOS transistor Mp increases, the current provided by the MOS transistor Mp decreases, and the output voltage of the output terminal VOUT_LDO decreases.

[0042] The MOS transistor Mp, the MOS transistor M13 and the MOS transistor M9 constitute a second loop (i.e. LOOP2 in the figure), and the second loop is a FVF structure (Flipped-Voltage-Follower). When the voltage output by the output terminal VOUT_LDO decreases, the drain voltage of the MOS transistor M13 decreases, the gate voltage of the MOS transistor M10 decreases, the source voltage of the MOS transistor M9 decreases, the drain voltage of the MOS transistor M10 increases, the gate voltage of the MOS transistor M9 increases, the current passing through the MOS transistor M9 increases, the gate voltage of the MOS transistor Mp decreases, the MOS transistor Mp can provide more current, and the output voltage of the output terminal VOUT_LDO increases; when the voltage output by the output terminal VOUT_LDO increases, the drain voltage of the MOS transistor M13 increases, the gate voltage of the MOS transistor M10 increases, the source voltage of the MOS transistor M9 increases, the drain voltage of the MOS transistor M10 decreases, the gate voltage of the MOS transistor M9 decreases, the current passing through the MOS transistor M9 decreases, the gate voltage of the MOS transistor Mp increases, the current provided by the MOS transistor Mp decreases, and the output voltage of the output terminal VOUT_LDO decreases.

[0043] The MOS transistor Mp, the MOS transistor M13 and the MOS transistor M11 constitute a third loop (i.e. LOOP3 in the figure), and the third loop is a pull-down loop. When the output voltage of the output terminal VOUT_LDO rapidly increases, the drain voltage of the MOS transistor M13 rapidly increases, the MOS transistor M11 rapidly opens, and the output voltage of the output terminal VOUT_LDO is rapidly pulled down.

[0044] MOS transistor Mp, capacitor C2, inverter U1 and MOS transistor M14 constitute a fourth loop (i.e. LOOP4 in the figure), which comprises a TEC (Transient-Enhanced Circuit) circuit for suppressing the drop of the output voltage of the output terminal VOUT_LDO, wherein the common mode level of the input terminal of the inverter U1 is set at When the output voltage of the output terminal VOUT_LDO drops rapidly, the inverter U1 outputs a high level, rapidly opens the MOS transistor M14, thereby rapidly lowers the gate voltage of the MOS transistor Mp, and rapidly raises the output voltage of the output terminal VOUT_LDO.

[0045] MOS transistor Mp, error amplifier EA and MOS transistor M13 constitute a fifth loop (i.e. LOOP5 in the figure), which is a slow loop circuit for further improving the loop gain of the main loop, thereby improving the load regulation and linear regulation of the output terminal VOUT_LDO, and further improving the PSR performance at low and medium frequencies.

[0046] The error amplifier EA is an OTA (i.e. Operational Transconductance Amplifier) with positive feedback type accelerating transistors M21 and M22 for gain improvement, which compares the output voltage of the output terminal VOUT_LDO with the reference voltage VREF, and amplifies the difference signal of the output voltage and the reference voltage and feeds it back to the gate of the MOS transistor M13, thereby ensuring that the output voltage of the output terminal VOUT_LDO is equal to the reference voltage VREF, and achieving a very high loop gain.

[0047] The error amplifier EA includes MOS transistor M18, MOS transistor M19, MOS transistor M20, MOS transistor M21, MOS transistor M22, MOS transistor M23, MOS transistor M24, MOS transistor M25, MOS transistor M26, MOS transistor M27, MOS transistor M28, MOS transistor M29, the source of MOS transistor M18, the source of MOS transistor M20, the source of MOS transistor M21, the source of MOS transistor M22, the source of MOS transistor M23, the source of MOS transistor M24 are connected together and are connected to voltage VDD, the drain of MOS transistor M18, the drain of MOS transistor M19, the gate of MOS transistor M19, the gate of MOS transistor M29 are connected together, the source of MOS transistor M19, the source of MOS transistor M27, the source of MOS transistor M28, the source of MOS transistor M29 are connected to ground, the gate of MOS transistor M18, the gate of MOS transistor M20, the drain of MOS transistor M20, the drain of MOS transistor M21, the gate of MOS transistor M22, the drain of MOS transistor M25 are connected together, the gate of MOS transistor M21, the drain of MOS transistor M22, the drain of MOS transistor M23, the gate of MOS transistor M23, the gate of MOS transistor M24, the drain of MOS transistor M26 are connected together, the source of MOS transistor M25, the source of MOS transistor M26, the drain of MOS transistor M27, the drain of MOS transistor M28 are connected together, the gate of MOS transistor M25 is the input terminal VN of the error amplifier EA, the gate of MOS transistor M26 is the input terminal VP of the error amplifier EA, the gate of MOS transistor M27 is the input terminal VBIAS of the error amplifier EA, the gate of MOS transistor M28 is the input terminal ADA_VBIAS of the error amplifier EA, the drain of MOS transistor M24 and the drain of MOS transistor M29 are connected together and are the output terminal VOUT_EA of the error amplifier EA.

[0048] The entire circuit includes three poles (ω p1 ,ω p2 ,ω p3 ) and one zero point (ω z1 ), the gate of MOS transistor Mp as a power transistor as the first pole ω p1 , that is, the main pole. The output terminal of the error amplifier EA as the second pole ω p2 , and there is also a zero point (ω z1 ) here as the first zero point, and the output terminal VOUT_LDO as the third pole ω p3MOS transistor M15 is used as a sampling transistor to sample the load current, so that the bias current of error amplifier EA can be adaptively controlled, thereby adjusting the positions of the second pole and the first zero point at the output of error amplifier EA, so as to ensure the stability of the entire LDO under different load currents. When the load current increases, it is equivalent to the decrease of the load resistance, so that the frequency of the third pole at the output of the entire LDO increases, and the frequencies of the second pole and the first zero point at the output of error amplifier EA increase due to the increase of the bias current of error amplifier EA; when the load current decreases, it is equivalent to the increase of the load resistance, so that the frequency of the third pole at the output of the output VOUT_LDO decreases, and the frequencies of the second pole and the first zero point at the output of error amplifier EA decrease due to the decrease of the bias current of error amplifier EA, so that the second pole and the third pole always maintain a certain distance in the frequency domain, thereby ensuring the stability of the loop.

[0049] The ripple amplification circuit RAC (Ripple-Amplification-Circuit) comprises a resistor R5, a resistor R6, a resistor R7, a resistor R8, a capacitor C4, a capacitor C5, a MOS transistor M30 and an operational amplifier OP1. One end of the resistor R5 and the resistor R6 are connected together and serve as an input terminal VREF of the ripple amplification circuit RAC. The other end of the resistor R5 is connected to an input terminal VN of the operational amplifier OP1 and one end of the resistor R7, respectively. The other end of the resistor R6 is connected to one end of the capacitor C4 and an input terminal VP of the operational amplifier OP1, respectively. The other end of the capacitor C4 is connected to a voltage VDD. The other end of the resistor R7 is connected to a drain of the MOS transistor M30. A gate of the MOS transistor M30 is connected to the voltage VDD. A source of the MOS transistor M30 is connected to an output terminal VOUT_OP1 of the operational amplifier OP1 and one end of the capacitor C5, respectively. The other end of the capacitor C5 is connected to one end of the resistor R8 and serves as an output terminal VBOD Y of the ripple amplification circuit RAC. The other end of the resistor R8 is connected to the voltage VDD. An input terminal VBIAS of the operational amplifier OP1 serves as an input terminal VBIAS of the ripple amplification circuit RAC. An input terminal ADA_VBIAS of the operational amplifier OP1 serves as an input terminal ADA_VBIAS of the ripple amplification circuit RAC.

[0050] The operational amplifier OP1 includes MOS tube M31, MOS tube M32, MOS tube M33, MOS tube M34, MOS tube M35, MOS tube M36, MOS tube M37, MOS tube M38, MOS tube M39, MOS tube M40, MOS tube M41, MOS tube M42, MOS tube M43, MOS tube M44, MOS tube M45, MOS tube M46, MOS tube M47, the source of MOS tube M31, the source of MOS tube M32, the source of MOS tube M33, the source of MOS tube M34, the source of MOS tube M41, the source of MOS tube M42 are commonly connected and connected to voltage VDD, the drain of MOS tube M31, the drain of MOS tube M39, the gate of MOS tube M39, the gate of MOS tube M40 are commonly connected together, the source of MOS tube M39, the source of MOS tube M37, the source of MOS tube M38, the source of MOS tube M40, the source of MOS tube M44, the source of MOS tube M45, the source of MOS tube M46, the source of MOS tube M47 are commonly connected together and grounded, the gate of MOS tube M31, the gate of MOS tube M32, the drain of MOS tube M32, the drain of MOS tube M35 are connected together, the gate of MOS tube M34, the gate of MOS tube M33, the drain of MOS tube M33, the drain of MOS tube M36 are connected together, the source of MOS tube M35, the source of MOS tube M36, the drain of MOS tube M37, the drain of MOS tube M38 are connected together, the gate of MOS tube M35 is the input terminal VN of the operational amplifier OP1, the gate of MOS tube M36 is the input terminal VP of the operational amplifier OP1, the gate of MOS tube M37 is the input terminal VBIAS of the operational amplifier OP1, the gate of MOS tube M38 is the input terminal ADA_VBIAS of the operational amplifier OP1, the drain of MOS tube M40, the drain of MOS tube M34, the gate of MOS tube M43 are connected together, the drain of MOS tube M41, the source of MOS tube M43, the drain of MOS tube M45 are connected together, the gate of MOS tube M41, the gate of MOS tube M42, the drain of MOS tube M42, the drain of MOS tube M46, the drain of MOS tube M47 are connected together, the drain of MOS tube M43, the gate of MOS tube M45, the drain of MOS tube M44 are connected together, the gate of MOS tube M44 is connected to a bias voltage VB1, the gate of MOS tube M46 is the input terminal VBIAS of the operational amplifier OP1, the gate of MOS tube M47 is the input terminal ADA_VBIAS of the operational amplifier OP1.

[0051] The connection node, in which the drain of the MOS transistor M41, the source of the MOS transistor M43, and the drain of the MOS transistor M45 are connected together, is the output terminal VOUT_OP1 of the operational amplifier OP1, and the output terminal VOUT_OP1 is connected to the connection node between the capacitor C5 and the source of the MOS transistor M30.

[0052] The operational amplifier OP2 is an OTA, and its structure is basically the same as that of the error amplifier EA, but without the positive feedback accelerating transistors M21 and M22. The operational amplifier OP2, the MOS transistor M4, and the resistor R4 are used together to generate a bias current that will follow the linear change of the power supply voltage, and the bias current is mirrored to the branch in which the MOS transistor M8 is located in the form of a common-source and common-gate current mirror. The reason for using the common-source and common-gate current mirror bias is to make the current mirroring more accurate and prevent the current in the branch in which the MOS transistor M8 is located (i.e., the current injected into the gate of the power transistor Mp) from being too large to affect the stability of the entire loop. The MOS transistor M7 and the MOS transistor M8 constitute an RFFC structure (Ripple-FeedForward-Circuit). The gate of the MOS transistor M8 is connected to a 5pF capacitor for filtering, so as to ensure that the amount of the power supply ripple signal on the gate of the MOS transistor M8 is about 0, and the power supply ripple signal is input from the source of the MOS transistor M8, so that the MOS transistor M8 can amplify the power supply ripple.

[0053] The ripple amplification circuit RAC can amplify the power supply ripple appropriately, and inject the amplified power supply ripple into the substrate of the MOS transistor Mp as the power transistor, so that the power supply ripple current at high frequency is 0, thereby improving the PSR performance at high frequency. The ripple amplification circuit RAC is essentially a non-inverting amplifier, which couples the power supply ripple to the non-inverting input terminal of the operational amplifier OP1 through a capacitor, and amplifies the power supply ripple by a factor of where RM30 is the on-resistance of the MOS transistor M30, and then the amplified power supply ripple signal is injected into the substrate of the power transistor Mp through the high-pass network composed of R8-C5, thereby improving the PSR at high frequency. The advantage of using the high-pass network composed of R8-C5 is that, on the one hand, compared with directly driving the power transistor substrate capacitor from the output terminal of the operational amplifier OP1, after using the high-pass network composed of R8-C5, the equivalent load capacitor of the operational amplifier OP1 is the series connection of the capacitor C5 and the power transistor Mp substrate capacitor, that is, the capacitor driven by the output terminal of the operational amplifier OP1 is greatly reduced, which makes the closed-loop bandwidth of the ripple amplification circuit RAC increase, thereby ensuring that the ripple amplification circuit RAC still has a certain amplification effect at high frequency. On the other hand, the potential of the power transistor Mp substrate is still VDD, which can prevent the risk of forward conduction of the parasitic diode between the source and the substrate of the power transistor Mp.

[0054] The operational amplifier OP1 adopts a two-stage structure to increase the open loop gain bandwidth product, the first stage is an OTA composed of MOS tubes M31-M40, used to increase the open loop gain; the second stage is an SSF (Super-Source-Follower) composed of MOS tubes M41-M47, wherein MOS tube M43 and MOS tube M45 are the key structure of the SSF, used to increase the output pole frequency of the operational amplifier OP1 to ensure the loop stability of the ripple amplification circuit RAC.

[0055] The application adopts a TEC structure, a fast loop formed by the fourth loop, suppresses the output voltage drop when the load current jumps, and improves the transient response. By adopting the error amplifier EA, the difference between the output voltage of the LDO and the reference voltage VREF is amplified and fed back to the gate of the control tube of the FVF structure, thereby introducing the fifth loop as a slow loop, increasing the gain of the loop, improving the load regulation rate and the linear regulation rate, and further improving the PSR performance at middle and low frequencies. Since the RFFC structure is adopted, the power supply ripple at middle frequencies is amplified and injected into the gate of the power tube, improving the PSR performance of the LDO at middle frequencies. Since the RAC structure is adopted, the power supply ripple at high frequencies is amplified in an appropriate amount and injected into the substrate of the power tube through the RC high-pass network, improving the PSR performance of the LDO at high frequencies. In addition, the RC high-pass network has the advantages of: on the one hand, reducing the load capacitance driven by the RAC, ensuring that the RAC still has a certain amplification capability at high frequencies, and on the other hand, providing a VDD bias voltage for the substrate of the power tube, preventing the risk of forward conduction of the parasitic diode of the source-substrate of the power tube. And even under the condition of large load current, the LDO still has good PSR performance in the frequency range of 1Hz-10GHz.

[0056] The embodiments disclosed in the specification are only an example of the one-sided features of the application, and the protection scope of the application is not limited to this embodiment, and any other functionally equivalent embodiments fall within the protection scope of the application. For those skilled in the art, other various corresponding changes and modifications can be made according to the above-described technical solutions and concepts, and all these changes and modifications should belong to the protection scope of the claims of the application.

Claims

1. A no-capacitor-outside-chip LDO with improved PSR performance and fast transient response, characterized in that, The error amplifier EA, the ripple amplification circuit RAC, the MOS transistor M1, the resistor R1, the resistor R2, the resistor R3, the resistor R4, the capacitor C1, the capacitor C2, the capacitor C3, the MOS transistor M2, the MOS transistor M5, the MOS transistor M6, the MOS transistor M8, the MOS transistor M10, the MOS transistor M11, the MOS transistor M12, the MOS transistor M13, the MOS transistor M14, the MOS transistor M15, the MOS transistor M16, the MOS transistor M17, and the operational amplifier OP2 are connected in series, and the gate and the drain of the MOS transistor M1 are connected to a 10 μA constant current source and a voltage VDD, and one end of a first series circuit is also connected to the voltage VDD, and the other end of the first series circuit is connected to the source of the MOS transistor M1 and grounded, and the first series circuit comprises the resistor R1, the resistor R2, and the resistor R3 connected in series, one end of the resistor R1 is connected to the voltage VDD, one end of the resistor R3 is connected to the source of the MOS transistor M1, the source of the MOS transistor M2, the source of the MOS transistor M5, the source of the MOS transistor M6, the source of the MOS transistor M8, the source of the MOS transistor M10, and the source of the MOS transistor M11 are connected to the voltage VDD, one end of the resistor R4, one end of the capacitor C1, the source of the MOS transistor M10, the source of the MOS transistor M11, the source of the MOS transistor M12, one end of a first parallel circuit, one end of the capacitor C3, and one end of the source of the MOS transistor M17 are connected to the ground end to which the source of the MOS transistor M1 is connected, the first parallel circuit comprises the capacitor C2 and the resistor R4 connected in parallel, the other end of the first parallel circuit, one end of the capacitor C2, the drain of the MOS transistor M11, and the source of the MOS transistor M13 are connected to the drain of the MOS transistor M10, and form an output end VOUT_LDO of the LDO without an external capacitor. LOAD LOAD ​​ The VP access end of the operational amplifier OP2 is connected with the connection node between the resistor R2 and the resistor R3, the VN access end of the operational amplifier OP2 is respectively connected with the source of the MOS tube M4 and the other end of the resistor R4, the VBIAS access end of the operational amplifier OP2 is respectively connected with the VBIAS access end of the ripple amplification circuit RAC, the VBIAS access end of the error amplifier EA, the gate of the MOS tube M12 and the gate of M1, the output end of the operational amplifier OP2 is connected with the gate of the MOS tube M4, the drain of the MOS tube M4 is respectively connected with the other end of the capacitor C1, the drain of the MOS tube M3, the gate of the MOS tube M2, the gate of the MOS tube M8, the drain of the MOS tube M2 is connected with the source of the MOS tube M3, the gate of the MOS tube M3 is connected with the gate of the MOS tube M7 and is connected to the bias voltage VB_CAS, The gate of the MOS tube M5, the gate of the MOS tube M6, the drain of the MOS tube M10, the gate of the MOS tube M9 are commonly connected together, the drain of the MOS tube M6, the drain of the MOS tube M9, the drain of the MOS tube M7, the gate of the MOS tube Mp, the gate of the MOS tube M15 are commonly connected together, the source of the MOS tube M9, the gate of the MOS tube M10, the gate of the MOS tube M11, the drain of the MOS tube M12, the drain of the MOS tube M13 are commonly connected together, the gate of the MOS tube M13 is connected with the other end of the capacitor C3 and the output end of the error amplifier EA, The input end VP of the error amplifier EA is connected with the voltage input end VREF of the ripple amplification circuit RAC and is commonly connected with a 1.8V reference voltage, the input end ADA_VBIAS of the error amplifier EA, the gate of the MOS tube M17, the drain of the MOS tube M17, the input end ADA_VBIAS of the ripple amplification circuit RAC, the source of the MOS tube M16 are commonly connected, the input end VN of the error amplifier EA is connected with the output end VOUT_LDO, The other end of the capacitor C2 is respectively connected with the connection node between the resistor R1 and the resistor R2 and the input end of the inverter U1, the output end of the inverter U1 is connected with the gate of the MOS tube M14, the source of the MOS tube M14 is grounded, the drain of the MOS tube M14, the gate of the MOS tube Mp, the gate of the MOS tube M15, the drain of the MOS tube M7, the drain of the MOS tube M6, the drain of the MOS tube M9 are commonly connected, The output end VBODY of the ripple amplification circuit RAC is also connected with the substrate of the MOS tube Mp.

2. The PSR performance improved and fast transient response off-chip capacitor free LDO of claim 1, wherein, The MOS transistor MP, the MOS transistor M13, the MOS transistor M10, the MOS transistor M5 and the MOS transistor M6 constitute a first loop, and are used for: when the voltage output by the output end VOUT_LDO decreases, the drain voltage of the MOS transistor M13 decreases, the gate voltage of the MOS transistor M10 decreases, the drain voltage of the MOS transistor M10 increases, the gate voltage of the MOS transistor M6 increases, the current of the MOS transistor M6 decreases, the gate voltage of the MOS transistor Mp decreases, the MOS transistor Mp can provide greater current, and the output voltage of the output end VOUT_LDO increases; when the voltage output by the output end VOUT_LDO increases, the drain voltage of the MOS transistor M13 increases, the gate voltage of the MOS transistor M10 increases, the drain voltage of the MOS transistor M10 decreases, the gate voltage of the MOS transistor M6 decreases, the current of the MOS transistor M6 increases, the gate voltage of the MOS transistor Mp increases, the current provided by the MOS transistor Mp decreases, and the output voltage of the output end VOUT_LDO decreases, The MOS transistor Mp, the MOS transistor M13 and the MOS transistor M9 constitute a second loop, and the second loop is an FVF structure, and is used for: when the voltage output by the output end VOUT_LDO decreases, the drain voltage of the MOS transistor M13 decreases, the gate voltage of the MOS transistor M10 decreases, the source voltage of the MOS transistor M9 decreases, the drain voltage of the MOS transistor M10 increases, the gate voltage of the MOS transistor M9 increases, the current passing through the MOS transistor M9 increases, the gate voltage of the MOS transistor Mp decreases, the MOS transistor Mp can provide greater current, and the output voltage of the output end VOUT_LDO increases; when the voltage output by the output end VOUT_LDO increases, the drain voltage of the MOS transistor M13 increases, the gate voltage of the MOS transistor M10 increases, the source voltage of the MOS transistor M9 increases, the drain voltage of the MOS transistor M10 decreases, the gate voltage of the MOS transistor M9 decreases, the current passing through the MOS transistor M9 decreases, the gate voltage of the MOS transistor Mp increases, the current provided by the MOS transistor Mp decreases, and the output voltage of the output end VOUT_LDO decreases, The MOS transistor Mp, the MOS transistor M13 and the MOS transistor M11 constitute a third loop, and the third loop is a pull-down loop, and is used for: when the output voltage of the output end VOUT_LDO rapidly increases, the drain voltage of the MOS transistor M13 rapidly increases, the MOS transistor M11 rapidly opens, and the output voltage of the output end VOUT_LDO is rapidly pulled down, The MOS transistor Mp, the capacitor C2, the inverter U1 and the MOS transistor M14 constitute a fourth loop, and the fourth loop comprises a TEC circuit for suppressing the drop of the output voltage of the output terminal VOUT_LDO, wherein the common mode level of the input terminal of the inverter U1 is set to When the output voltage of the output terminal VOUT_LDO rapidly drops, the inverter U1 outputs a high level, rapidly opens the MOS transistor M14, thereby rapidly lowers the gate voltage of the MOS transistor Mp, so that the output voltage of the output terminal VOUT_LDO is rapidly raised, The MOS transistor Mp, the error amplifier EA and the MOS transistor M13 constitute a fifth loop, and the fifth loop is a slow loop circuit, and is used for further improving the loop gain of the main loop, thereby improving the load regulation rate and the linear regulation rate of the output end VOUT_LDO, and also improving the PSR performance at a low frequency.

3. The no off-chip capacitor LDO with improved PSR performance and fast transient response of claim 2, wherein, The error amplifier EA is a positive feedback type accelerating tube M21 and M22 to realize gain enhancement amplifier, error amplifier EA will output voltage and reference voltage VREF comparison, and output voltage and reference voltage difference signal is amplified after feedback to the gate of MOS tube M13, thereby ensuring that the output voltage of the output terminal VOUT_LDO is equal to the reference voltage VREF, and a high loop gain can be achieved.

4. The no off-chip capacitor LDO with improved PSR performance and fast transient response of claim 2, wherein, The error amplifier EA includes MOS tube M18, MOS tube M19, MOS tube M20, MOS tube M21, MOS tube M22, MOS tube M23, MOS tube M24, MOS tube M25, MOS tube M26, MOS tube M27, MOS tube M28, MOS tube M29, the source of MOS tube M18, the source of MOS tube M20, the source of MOS tube M21, the source of MOS tube M22, the source of MOS tube M23, the source of MOS tube M24 are connected together, and are connected to the voltage VDD, the drain of MOS tube M18, the drain of MOS tube M19, the gate of MOS tube M19, the gate of MOS tube M29 are connected together, the source of MOS tube M19, the source of MOS tube M27, the source of MOS tube M28, the source of MOS tube M29 are connected to ground, the gate of MOS tube M18, the gate of MOS tube M20, the drain of MOS tube M20, the drain of MOS tube M21, the gate of MOS tube M22, the drain of MOS tube M25 are connected together, the gate of MOS tube M21, the drain of MOS tube M22, the drain of MOS tube M23, the gate of MOS tube M23, the gate of MOS tube M24, the drain of MOS tube M26 are connected together, the source of MOS tube M25, the source of MOS tube M26, the drain of MOS tube M27, the drain of MOS tube M28 are connected together, the gate of MOS tube M25 is the input terminal VN of the error amplifier EA, the gate of MOS tube M26 is the input terminal VP of the error amplifier EA, the gate of MOS tube M27 is the input terminal VBIAS of the error amplifier EA, the gate of MOS tube M28 is the input terminal ADA_VBIAS of the error amplifier EA, the drain of MOS tube M24 and the drain of MOS tube M29 are connected together, and are the output terminal VOUT_EA of the error amplifier EA.

5. The no off-chip capacitor LDO with improved PSR performance and fast transient response of claim 4, wherein, The ripple amplification circuit RAC comprises a resistor R5, a resistor R6, a resistor R7, a resistor R8, a capacitor C4, a capacitor C5, a MOS transistor M30 and an operational amplifier OP1, one end of the resistor R5 and the resistor R6 are connected together and serve as an input terminal VREF of the ripple amplification circuit RAC, the other end of the resistor R5 is connected with an input terminal VN of the operational amplifier OP1 and one end of the resistor R7 respectively, the other end of the resistor R6 is connected with one end of the capacitor C4 and an input terminal VP of the operational amplifier OP1 respectively, the other end of the capacitor C4 is connected with a voltage VDD, the other end of the resistor R7 is connected with a drain of the MOS transistor M30, a gate of the MOS transistor M30 is connected with the voltage VDD, a source of the MOS transistor M30 is connected with an output terminal VOUT_OP1 of the operational amplifier OP1 and one end of the capacitor C5 respectively, the other end of the capacitor C5 is connected with one end of the resistor R8 and serves as an output terminal VBOD of the ripple amplification circuit RAC, the other end of the resistor R8 is connected with the voltage VDD, an input terminal VBIAS of the operational amplifier OP1 serves as an input terminal VBIAS of the ripple amplification circuit RAC, and an input terminal ADA_VBIAS of the operational amplifier OP1 serves as an input terminal ADA_VBIAS of the ripple amplification circuit RAC.

6. The no off-chip capacitor LDO with improved PSR performance and fast transient response of claim 5, wherein, The operational amplifier OP1 includes MOSFETs M31, M32, M33, M34, M35, M36, M37, M38, M39, M40, M41, M42, M43, M44, M45, M46, and M47. The sources of MOSFETs M31, M32, M33, M34, M41, and M42 are all connected to and connected to voltage VDD. The drains of MOSFETs M31, M39, and M39, and the gate of MOSFET M40 are connected together. The sources of MOSFETs M39, M37, M38, M40, M44, M45, M46, and M47 are connected together and grounded. The gates of MOSFETs M31, M32, M32, and M35 are connected together. The gates of MOSFETs M34 and M33, and the gate of MOSFET M40 are connected together. The drains of M33 and M36 are connected together. The sources of M35, M36, M37, and M38 are connected together. The gate of M35 serves as the input terminal VN of operational amplifier OP1. The gate of M36 serves as the input terminal VP of operational amplifier OP1. The gate of M37 serves as the input terminal VBIAS of operational amplifier OP1. The gate of M38 serves as the input terminal ADA_VBIAS of operational amplifier OP1. The drains of M40, M34, and M43 are connected together. Together, the drains of MOSFET M41, M43, and M45 are connected together; the gates of MOSFET M41, M42, M42, M46, and M47 are connected together; and the drains of MOSFET M43, M45, and M44 are connected together. The gate of MOSFET M44 is connected to a bias voltage VB1. The gate of MOSFET M46 serves as the input terminal VBIAS of operational amplifier OP1, and the gate of MOSFET M47 serves as the input terminal ADA_VBIAS of operational amplifier OP1. The connection node in which the drain of the MOS transistor M41, the source of the MOS transistor M43, and the drain of the MOS transistor M45 are connected together serves as an output terminal VOUT_OP1 of the operational amplifier OP1, and the output terminal VOUT_OP1 is connected to the connection node between the capacitor C5 and the source of the MOS transistor M30.

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