Gate driving circuit and display panel

Abstract

The application provides a gate drive circuit and a display panel. The gate drive circuit comprises a pull-up control module, a pull-down module and an anti-leakage module. The pull-down module outputs a first voltage provided by a first power supply end to a first node according to a pull-down control signal. The pull-down module comprises a first pull-down transistor connected in series between the first node and a common node and a second pull-down transistor connected in series between the common node and the first power supply end. The anti-leakage module comprises a first anti-leakage unit. The first anti-leakage unit outputs a preset voltage to the common node according to the pull-up control signal, so that the first pull-down transistor and the second pull-down transistor are in an off state during the process in which the pull-up control module lifts the potential of the first node according to the pull-up control signal, thereby blocking the path of the leakage of the first node to the first power supply end, and the problem of the leakage of the first node caused by the negative bias of the threshold voltage of the transistor during the operation of the gate drive circuit is improved. The display panel comprises the gate drive circuit.

Description

Technical Field

[0001] This invention relates to the field of display technology, specifically to a gate driving circuit and a display panel. Background Technology

[0002] On-line gate drive (ILD) technology allows for the integration of shift register functions onto the panel, facilitating narrow bezel designs. However, the gate drive circuit demands high transistor stability. Leakage due to threshold voltage shifts during transistor operation can affect the gate drive circuit's performance, consequently impacting the display panel's capabilities. For instance, if the threshold voltage of the transistors in the pull-down module becomes negatively biased during the rise of the first node's potential (which is electrically connected to the pull-up output module), the first node's potential will be affected by this negative threshold voltage, causing a potential drop during the rise. This negative bias impacts the gate drive circuit's operation and, consequently, the display panel's performance. Summary of the Invention

[0003] This invention provides a gate driving circuit and a display panel, which can improve the problem of leakage current in the first node caused by the negative bias of the threshold voltage of the transistor included in the pull-down module when the gate driving circuit is working.

[0004] This invention provides a gate driving circuit, including a pull-up control module, a pull-down module, and a leakage protection module. The pull-up control module is electrically connected to a first node and configured to raise the potential of the first node according to a pull-up control signal. The pull-down module includes a first pull-down transistor and a second pull-down transistor. The first pull-down transistor is connected in series between the first node and a common node, and the second pull-down transistor is connected in series between the common node and a first power supply terminal. The first and second pull-down transistors are configured to output a first voltage provided by the first power supply terminal to the first node according to the pull-down control signal. The leakage protection module is electrically connected to the common node and includes a first leakage protection unit. The first leakage protection unit is configured to output a preset voltage to the common node according to the pull-up control signal, so that the first and second pull-down transistors are in a cutoff state during the process of the pull-up control module raising the potential of the first node according to the pull-up control signal.

[0005] Optionally, in some embodiments of the present invention, the first leakage protection unit includes a first leakage protection transistor and a second leakage protection transistor. The gate of the first leakage protection transistor is configured to receive the pull-up control signal, and one of the source and drain of the first leakage protection transistor is configured to receive the preset voltage; the gate of the second leakage protection transistor is configured to receive the pull-up control signal, and one of the source and drain of the second leakage protection transistor is configured to be electrically connected to the other of the source and drain of the first leakage protection transistor, and the other of the source and drain of the second leakage protection transistor is configured to be electrically connected to the common node.

[0006] Optionally, in some embodiments of the present invention, the leakage protection module further includes a second leakage protection unit, which includes a third leakage protection transistor and a fourth leakage protection transistor. The gate of the third leakage protection transistor is configured to be electrically connected to the first node, and one of the source and drain of the third leakage protection transistor is configured to receive the preset voltage. The gate of the fourth leakage protection transistor is configured to be electrically connected to the first node, and one of the source and drain of the fourth leakage protection transistor is configured to be electrically connected to the other of the source and drain of the third leakage protection transistor. The other of the source and drain of the fourth leakage protection transistor is configured to be electrically connected to the common node. The third and fourth leakage protection transistors are configured to output the preset voltage to the common node according to the potential of the first node when the potential of the first node is raised to a level greater than or equal to the preset potential.

[0007] Optionally, in some embodiments of the present invention, the pull-down module includes a first pull-down unit, the first pull-down unit including a first sub-transistor and a second sub-transistor, the first sub-transistor and the second sub-transistor being configured to output the first voltage to the first node according to a first pull-down control signal before the potential of the first node is raised. Wherein, the first pull-down transistor includes the first sub-transistor, the second pull-down transistor includes the second sub-transistor, and the pull-down control signal includes the first pull-down control signal.

[0008] Optionally, in some embodiments of the present invention, the gate driving circuit further includes a pull-up output module electrically connected to the first node and the clock signal line. The pull-up output module is configured to output the clock signal transmitted by the clock signal line to the output terminal of the gate driving circuit according to the potential of the first node. The pull-down module includes a second pull-down unit, which includes a third sub-transistor and a fourth sub-transistor. The third sub-transistor and the fourth sub-transistor are configured to output the first voltage provided by the first power supply terminal to the first node according to a second pull-down control signal after the clock signal is transmitted to the output terminal of the gate driving circuit. Wherein, the first pull-down transistor includes the third sub-transistor, the second pull-down transistor includes the fourth sub-transistor, and the pull-down control signal includes the second pull-down control signal.

[0009] Optionally, in some embodiments of the present invention, the pull-up output module includes a first pull-up output unit, a second pull-up output unit, and a third pull-up output unit. The first pull-up output unit includes a first pull-up transistor and a first capacitor. The gate of the first pull-up transistor is configured to be electrically connected to the first node. One of the source and drain of the first pull-up transistor is configured to be electrically connected to a first clock signal line. The other of the source and drain of the first pull-up transistor is configured to be electrically connected to the stage signal output terminal of the gate driving circuit. The first capacitor is connected in series between the first node and the stage signal output terminal. The second pull-up output unit includes a second pull-up transistor and a second capacitor. The gate of the second pull-up transistor is configured to be electrically connected to the first node. One of the source and drain of the second pull-up transistor is configured to be electrically connected to a second clock signal line. The other of the source and drain of the second pull-up transistor is configured to be electrically connected to the write signal output terminal of the gate driving circuit. The second capacitor is connected in series between the first node and the write signal output terminal. The third pull-up output unit includes a third pull-up transistor and a third capacitor. The gate of the third pull-up transistor is configured to be electrically connected to the first node. One of the source and drain of the third pull-up transistor is configured to be electrically connected to a third clock signal line. The other of the source and drain of the third pull-up transistor is configured to be electrically connected to the read signal output terminal of the gate drive circuit. The third capacitor is connected in series between the first node and the read signal output terminal. The clock signal lines include the first clock signal line, the second clock signal line, and the third clock signal line. The output terminals include the cascade signal output terminal, the write signal output terminal, and the read signal output terminal.

[0010] Optionally, in some embodiments of the present invention, the gate driving circuit further includes a first pull-down sustaining module, which includes a first pull-down sustaining transistor, a second pull-down sustaining transistor, and a third pull-down sustaining transistor. The gate of the first pull-down sustaining transistor is configured to receive the first pull-down control signal. One of the source and drain of the first pull-down sustaining transistor is configured to be electrically connected to the stage signal output terminal, and the other of the source and drain of the first pull-down sustaining transistor is configured to be electrically connected to the first power supply terminal. The gate of the second pull-down sustaining transistor is configured to receive the first pull-down control signal. One of the source and drain of the second pull-down sustaining transistor is configured to be electrically connected to the write signal output terminal, and the other of the source and drain of the second pull-down sustaining transistor is configured to be electrically connected to the third power supply terminal. The gate of the third pull-down sustaining transistor is configured to receive the first pull-down control signal, one of the source and drain of the third pull-down sustaining transistor is configured to be electrically connected to the read signal output terminal, and the other of the source and drain of the third pull-down sustaining transistor is configured to be electrically connected to the third power supply terminal.

[0011] Optionally, in some embodiments of the present invention, the gate driving circuit further includes an inverting module electrically connected to the first node, the second node, the first power supply terminal, and the second power supply terminal. The inverting module is configured to control the potential change of the second node according to a low-frequency clock signal, the pull-up control signal, the potential of the first node, the first voltage, and the second voltage transmitted from the second power supply terminal, to obtain a third pull-down control signal corresponding to the potential change of the second node. The pull-down module includes a third pull-down unit, which includes a fifth sub-transistor and a sixth sub-transistor. The fifth and sixth sub-transistors are configured to output the first voltage provided by the first power supply terminal to the first node according to the third pull-down control signal. The first pull-down transistor includes the fifth sub-transistor, the second pull-down transistor includes the sixth sub-transistor, and the pull-down control signal includes the third pull-down control signal.

[0012] Optionally, in some embodiments of the present invention, the gate driving circuit further includes a second pull-down sustaining module, which includes a fourth pull-down sustaining transistor, a fifth pull-down sustaining transistor, and a sixth pull-down sustaining transistor. The gate of the fourth pull-down sustaining transistor is configured to be electrically connected to the second node, one of the source and drain of the fourth pull-down sustaining transistor is configured to be electrically connected to a pass signal output terminal, and the other of the source and drain of the fourth pull-down sustaining transistor is configured to be electrically connected to the first power supply terminal. The gate of the fifth pull-down sustaining transistor is configured to be electrically connected to the second node, one of the source and drain of the fifth pull-down sustaining transistor is configured to be electrically connected to a write signal output terminal, and the other of the source and drain of the fifth pull-down sustaining transistor is configured to be electrically connected to a third power supply terminal. The gate of the sixth pull-down sustaining transistor is configured to be electrically connected to the second node, one of the source and drain of the sixth pull-down sustaining transistor is configured to be electrically connected to the read signal output terminal, and the other of the source and drain of the sixth pull-down sustaining transistor is configured to be electrically connected to the third power supply terminal. The inverting module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor.

[0013] The gate of the first transistor is configured to receive the low-frequency clock signal, and one of the source and drain of the first transistor is configured to receive the low-frequency clock signal. The gate of the second transistor is configured to receive the low-frequency clock signal, and one of the source and drain of the second transistor is configured to be electrically connected to the other of the source and drain of the first transistor. The gate of the third transistor is configured to be electrically connected to the other of the source and drain of the second transistor, and one of the source and drain of the third transistor is configured to receive the low-frequency clock signal, while the other of the source and drain of the third transistor is configured to be electrically connected to the second node. The gate of the fourth transistor is configured to be electrically connected to the first node, and one of the source and drain of the fourth transistor is configured to be electrically connected to the second node, while the other of the source and drain of the fourth transistor is configured to be electrically connected to the first power supply terminal. The gate of the fifth transistor is configured to receive a node potential signal. One of the source and drain of the fifth transistor is configured to be electrically connected to the gate of the third transistor, and the other of the source and drain of the fifth transistor is configured to be electrically connected to the second power supply terminal. The gate of the sixth transistor is configured to be electrically connected to the first node. One of the source and drain of the sixth transistor is configured to be electrically connected to the gate of the third transistor, and the other of the source and drain of the sixth transistor is configured to be electrically connected to the second power supply terminal. The gate of the seventh transistor is configured to receive the pull-up control signal. One of the source and drain of the seventh transistor is configured to be electrically connected to the second node, and the other of the source and drain of the seventh transistor is configured to be electrically connected to the first power supply terminal.

[0014] The present invention also provides a display panel including any of the above-described gate driving circuits.

[0015] This invention provides a gate driving circuit and a display panel. The gate driving circuit includes a pull-up control module, a pull-down module, and a leakage protection module. The pull-up control module is configured to raise the potential of a first node according to a pull-up control signal. The pull-down module is configured to output a first voltage provided by a first power supply terminal to the first node according to a pull-down control signal. The pull-down module includes a first pull-down transistor and a second pull-down transistor. The first pull-down transistor is connected in series between the first node and a common node, and the second pull-down transistor is connected in series between the common node and the first power supply terminal. The leakage protection module includes a first leakage protection unit, which is configured to output a preset voltage to the common node according to the pull-up control signal. This prevents the first and second pull-down transistors from being turned off during the process of the pull-up control module raising the potential of the first node according to the pull-up control signal, thereby blocking the leakage path from the first node to the first power supply terminal. This improves the problem of leakage at the first node caused by the negative bias of the threshold voltage of the transistors included in the pull-down module during the operation of the gate driving circuit. The display panel includes the gate driving circuit. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the pixel driving circuit provided in an embodiment of the present invention;

[0018] Figure 2 This is a schematic diagram of the gate driving circuit provided in an embodiment of the present invention;

[0019] Figure 3 This is a timing diagram of the potential change of the first node provided in an embodiment of the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of the present invention and are not intended to limit the present invention. In the present invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0021] Specifically, Figure 1 This is a schematic diagram of the pixel driving circuit provided in an embodiment of the present invention. The pixel driving circuit includes a light-emitting device D, a driving transistor DT, a data transistor DaT, a sensing transistor ST, and a storage capacitor Cst.

[0022] The light-emitting device D includes sub-millimeter light-emitting diodes, micro light-emitting diodes, and organic light-emitting diodes, etc.

[0023] The gate of the driving transistor DT is electrically connected to one of the source and drain of the data transistor DaT. One of the source and drain of the driving transistor DT is electrically connected to a first voltage terminal VDD. The other of the source and drain of the driving transistor DT is electrically connected to the light-emitting device D. The driving transistor DT is configured to generate a driving current to drive the light-emitting device D to emit light.

[0024] The gate of the data transistor DaT is electrically connected to the write signal output terminal WR(n), and the other of the source and drain of the data transistor DaT is electrically connected to the data signal terminal Data. The data transistor DaT is configured to transmit the data signal transmitted at the data signal terminal Data to the gate of the driving transistor DT according to the write signal output from the write signal output terminal WR(n).

[0025] Optionally, the data signal includes a detection data signal for being output to the gate of the driving transistor DT during the blanking interval phase, and a display data signal for being output to the gate of the driving transistor DT during the display phase.

[0026] The gate of the sensing transistor ST is electrically connected to the read signal output terminal RD(n), one of the source and drain of the sensing transistor ST is electrically connected to the other of the source and drain of the driving transistor DT, and the other of the source and drain of the sensing transistor ST is electrically connected to the sensing signal terminal Sense. The sensing transistor ST is configured to detect the threshold voltage of the driving transistor DT in response to the read signal output terminal RD(n).

[0027] Optionally, the sensing signal terminal Sense is configured to provide a reset signal to the anode of the light-emitting device D during the display phase to reset the anode potential of the light-emitting device D; or it is configured to provide a sensing control signal during the blanking interval phase to obtain the threshold voltage of the driving transistor DT.

[0028] The storage capacitor Cst is connected in series between the gate of the driving transistor DT and the other of the source and drain of the driving transistor DT.

[0029] In the pixel driving circuit, the gate of the data transistor DaT is electrically connected to the write signal output terminal WR(n), and the gate of the sensing transistor ST is electrically connected to the read signal output terminal RD(n). Therefore, the operating state of the data transistor DaT is determined by the write signal output from the write signal output terminal WR(n), and the operating state of the sensing transistor ST is determined by the read signal output from the read signal output terminal RD(n). Both the write signal and the read signal can be generated by the gate driving circuit.

[0030] Understandably, the pixel driving circuit can be in the form of 2T1C, 5T2C, 7T1C, etc. Here, T represents a transistor, and C represents a capacitor. Correspondingly, the pixel driving circuit is electrically connected to the corresponding scan signal via a scan line, so that the pixel driving circuit drives the light-emitting device D to emit light. The scan signal can be generated by the gate driving circuit accordingly.

[0031] To reduce the impact of transistor threshold voltage offset on the read signal, write signal, or scan signal output from the gate drive circuit to the pixel drive circuit, this application provides a gate drive circuit, such as... Figure 2 The diagram shown is a schematic representation of the gate driving circuit provided in an embodiment of the present invention. The gate driving circuit includes a pull-up control module 100, a pull-down module, and a leakage protection module 200.

[0032] The pull-up control module 100 is electrically connected to the first node Q(n), and the pull-up control module 100 is configured to raise the potential of the first node Q(n) according to the pull-up control signal Cout-PU.

[0033] Optionally, the pull-up control module 100 includes a first pull-up control transistor T11 and a second pull-up control transistor T12. The gates of the first pull-up control transistor T11 and the second pull-up control transistor T12 are both electrically connected to the pull-up control signal Cout-PU. One of the source and drain of the first pull-up control transistor T11 is electrically connected to the pull-up control signal Cout-PU. The other of the source and drain of the first pull-up control transistor T11 is electrically connected to one of the source and drain of the second pull-up control transistor T12. The other of the source and drain of the second pull-up control transistor T12 is electrically connected to the first node Q(n).

[0034] The pull-down module includes a first pull-down transistor and a second pull-down transistor. The first pull-down transistor is connected in series between the first node Q(n) and the common node N(n), and the second pull-down transistor is connected in series between the common node N(n) and the first power supply terminal VGL1. The first pull-down transistor and the second pull-down transistor are configured to output a first voltage provided by the first power supply terminal VGL1 to the first node Q(n) according to a pull-down control signal.

[0035] The leakage protection module 200 is electrically connected to the common node N(n). The leakage protection module 200 includes a first leakage protection unit, which is configured to output a preset voltage VGH to the common node N(n) according to the pull-up control signal Cout-PU. During the process of the pull-up control module 100 raising the potential of the first node Q(n) according to the pull-up control signal Cout-PU, the first pull-down transistor and the second pull-down transistor are in the off state, thereby blocking the leakage path from the first node Q(n) to the first power supply terminal VGL1. This improves the problem that when the gate drive circuit is working, the potential of the first node Q(n) decreases during the rise of the transistor threshold voltage included in the pull-down module due to the negative bias, which affects the working state of the gate drive circuit and thus affects the performance of the display panel. This can improve circuit stability and ensure the normal output of the gate drive circuit.

[0036] Optionally, the first leakage protection unit includes a first leakage protection transistor T81 and a second leakage protection transistor T82. The gate of both the first leakage protection transistor T81 and the gate of the second leakage protection transistor T82 are configured to receive the pull-up control signal Cout-PU. One of the source and drain of the first leakage protection transistor T81 is configured to receive the preset voltage VGH. One of the source and drain of the second leakage protection transistor T82 is configured to be electrically connected to the other of the source and drain of the first leakage protection transistor T81, and the other of the source and drain of the second leakage protection transistor T82 is configured to be electrically connected to the common node N(n).

[0037] Optionally, the leakage protection module 200 further includes a second leakage protection unit, which includes a third leakage protection transistor T71 and a fourth leakage protection transistor T72. The gates of both the third and fourth leakage protection transistors T71 and T72 are configured to be electrically connected to the first node Q(n). One of the source and drain of the third leakage protection transistor T71 is configured to receive the preset voltage VGH. One of the source and drain of the fourth leakage protection transistor T72 is configured to be electrically connected to the other of the source and drain of the third leakage protection transistor T71. The other of the source and drain of the fourth leakage protection transistor T72 is configured to be electrically connected to the common node N(n).

[0038] The third anti-leakage transistor T71 and the fourth anti-leakage transistor T72 are configured to output the preset voltage VGH to the common node N(n) according to the potential of the first node Q(n) when the potential of the first node Q(n) is raised to a level greater than or equal to a preset potential.

[0039] Before the potential of the first node Q(n) rises to the preset potential, both the third anti-leakage transistor T71 and the fourth anti-leakage transistor T72 are in the off state. Therefore, the preset voltage VGH cannot be transmitted to the common node N(n) through the third anti-leakage transistor T71 and the fourth anti-leakage transistor T72, thereby blocking the path of leakage from the first node Q(n) to the first power supply terminal VGL1. However, by setting the first anti-leakage transistor T81 and the second anti-leakage transistor T82, the preset voltage VGH can be transmitted to the common node N(n) through the first anti-leakage transistor T81 and the second anti-leakage transistor T82 during the process of the potential of the first node Q(n) rising to the preset potential, thereby completely turning off the first pull-down transistor and the second pull-down transistor, thus preventing the potential of the first node Q(n) from decreasing. After the first node Q(n) is charged to the preset potential, the third anti-leakage transistor T71 and the fourth anti-leakage transistor T72 can prevent the potential of the first node Q(n) from decreasing.

[0040] Optionally, the first leakage protection transistor T81 and the second leakage protection transistor T82 may be in the form of dual-gate transistors, and the third leakage protection transistor T71 and the fourth leakage protection transistor T72 may be in the form of dual-gate transistors. Optionally, one of the source and drain of the first leakage protection transistor T81 can be shared with one of the source and drain of the third leakage protection transistor T71, and the other of the source and drain of the second leakage protection transistor T82 can be shared with the other of the source and drain of the fourth leakage protection transistor T72 (e.g., the source of the first leakage protection transistor T81 and the source of the third leakage protection transistor T71 receive a preset voltage VGH, and the source of the first leakage protection transistor T81 and the source of the third leakage protection transistor T71 are shared; the drain of the second leakage protection transistor T82 and the drain of the fourth leakage protection transistor T72 are both electrically connected to the common node N(n), and the drain of the second leakage protection transistor T82 and the drain of the fourth leakage protection transistor T72 are shared), in order to save layout space and reduce process difficulty.

[0041] Optionally, the pull-down module includes a first pull-down unit 301, which includes a first sub-transistor T43B and a second sub-transistor T44B. The first sub-transistor T43B and the second sub-transistor T44B are configured to output the first voltage to the first node Q(n) according to a first pull-down control signal QB(n+1) before or after the potential of the first node Q(n) is raised. The first pull-down transistor includes the first sub-transistor T43B, the second pull-down transistor includes the second sub-transistor T44B, and the pull-down control signal includes the first pull-down control signal QB(n+1).

[0042] Optionally, the gate drive circuit further includes a pull-up output module 400, which is electrically connected to the first node Q(n) and the clock signal line. The pull-up output module 400 is configured to output the clock signal transmitted by the clock signal line to the output terminal of the gate drive circuit according to the potential of the first node Q(n).

[0043] Optionally, the pull-up output module 400 includes a first pull-up output unit, a second pull-up output unit, and a third pull-up output unit.

[0044] The first pull-up output unit includes a first pull-up transistor T21 and a first capacitor C1. The gate of the first pull-up transistor T21 is configured to be electrically connected to the first node Q(n). One of the source and drain of the first pull-up transistor T21 is configured to be electrically connected to the first clock signal line Cka. The other of the source and drain of the first pull-up transistor T21 is configured to be electrically connected to the stage transmission signal output terminal Cout(n) of the gate drive circuit. The first capacitor C1 is connected in series between the first node Q(n) and the stage transmission signal output terminal Cout(n).

[0045] The second pull-up output unit includes a second pull-up transistor T22 and a second capacitor C2. The gate of the second pull-up transistor T22 is configured to be electrically connected to the first node Q(n). One of the source and drain of the second pull-up transistor T22 is configured to be electrically connected to the second clock signal line Ckb. The other of the source and drain of the second pull-up transistor T22 is configured to be electrically connected to the write signal output terminal WR(n) of the gate drive circuit. The second capacitor C2 is connected in series between the first node Q(n) and the write signal output terminal WR(n).

[0046] The third pull-up output unit includes a third pull-up transistor T23 and a third capacitor C3. The gate of the third pull-up transistor T23 is configured to be electrically connected to the first node Q(n). One of the source and drain of the third pull-up transistor T23 is configured to be electrically connected to the third clock signal line Ckc. The other of the source and drain of the third pull-up transistor T23 is configured to be electrically connected to the read signal output terminal RD(n) of the gate drive circuit. The third capacitor C3 is connected in series between the first node Q(n) and the read signal output terminal RD(n).

[0047] The clock signal lines include the first clock signal line Cka, the second clock signal line Ckb, and the third clock signal line Ckc; the output terminals include the cascade signal output terminal Cout(n), the write signal output terminal WR(n), and the read signal output terminal RD(n).

[0048] Optionally, the pull-down module includes a second pull-down unit 302, which includes a third sub-transistor T41 and a fourth sub-transistor T42. The third sub-transistor T41 and the fourth sub-transistor T42 are configured to output the first voltage provided by the first power supply terminal VGL1 to the first node Q(n) according to a second pull-down control signal Cout-PD before or after the clock signal is transmitted to the output terminal of the gate drive circuit. The first pull-down transistor includes the third sub-transistor T41, the second pull-down transistor includes the fourth sub-transistor T42, and the pull-down control signal includes the second pull-down control signal Cout-PD.

[0049] Optionally, the gate drive circuit further includes an inverting module 500, which is electrically connected to the first node Q(n), the second node QB(n), the first power supply terminal VGL1, and the second power supply terminal VGL2. The inverting module 500 is configured to control the potential change of the second node QB(n) according to the low-frequency clock signal LC1, the pull-up control signal Cout-PU, the potential of the first node Q(n), the first voltage, and the second voltage transmitted by the second power supply terminal VGL2, so as to obtain a third pull-down control signal QB(n) corresponding to the potential change of the second node QB(n).

[0050] Optionally, the gate drive circuit may include two inverting modules 500, which operate in a time-sharing manner.

[0051] Optionally, the inverting module 500 includes a first transistor T51, a second transistor T52, a third transistor T53, a fourth transistor T54, a fifth transistor T55, a sixth transistor T56, and a seventh transistor T57.

[0052] The gate of the first transistor T51 is configured to receive the low-frequency clock signal LC1, and one of the source and drain of the first transistor T51 is configured to receive the low-frequency clock signal LC1; the gate of the second transistor T52 is configured to receive the low-frequency clock signal LC1, and one of the source and drain of the second transistor T52 is configured to be electrically connected to the other of the source and drain of the first transistor T51. Optionally, the first transistor T51 and the second transistor T52 may employ a dual-gate transistor structure to save layout space.

[0053] The gate of the third transistor T53 is configured to be electrically connected to the other of the source and drain of the second transistor T52, one of the source and drain of the third transistor T53 is configured to receive the low-frequency clock signal LC1, and the other of the source and drain of the third transistor T53 is configured to be electrically connected to the second node QB(n).

[0054] The gate of the fourth transistor T54 is configured to be electrically connected to the first node Q(n), one of the source and drain of the fourth transistor T54 is configured to be electrically connected to the second node QB(n), and the other of the source and drain of the fourth transistor T54 is configured to be electrically connected to the first power supply terminal VGL1.

[0055] The gate of the fifth transistor T55 is configured to receive the node potential signal Q(n+1), one of the source and drain of the fifth transistor T55 is configured to be electrically connected to the gate of the third transistor T53, and the other of the source and drain of the fifth transistor T55 is configured to be electrically connected to the second power supply terminal VGL2.

[0056] The gate of the sixth transistor T56 is configured to be electrically connected to the first node Q(n), one of the source and drain of the sixth transistor T56 is configured to be electrically connected to the gate of the third transistor T53, and the other of the source and drain of the sixth transistor T56 is configured to be electrically connected to the second power supply terminal VGL2.

[0057] The gate of the seventh transistor T57 is configured to receive the pull-up control signal Cout-PU, one of the source and drain of the seventh transistor T57 is configured to be electrically connected to the second node QB(n), and the other of the source and drain of the seventh transistor T57 is configured to be electrically connected to the first power supply terminal VGL1.

[0058] Optionally, the pull-down module includes a third pull-down unit 303, which includes a fifth sub-transistor T43A and a sixth sub-transistor T44A. The fifth sub-transistor T43A and the sixth sub-transistor T44A are configured to output the first voltage provided by the first power supply terminal VGL1 to the first node Q(n) according to the third pull-down control signal QB(n). The first pull-down transistor includes the fifth sub-transistor T43A, the second pull-down transistor includes the sixth sub-transistor T44A, and the pull-down control signal includes the third pull-down control signal QB(n).

[0059] Optionally, the gate drive circuit further includes a pull-down sustaining module configured to maintain the potential of the first node Q(n).

[0060] Optionally, the pull-down sustaining module includes a first pull-down sustaining module 601, which includes a first pull-down sustaining transistor T31B, a second pull-down sustaining transistor T32B, and a third pull-down sustaining transistor T33B.

[0061] The gate of the first pull-down sustaining transistor T31B is configured to receive the first pull-down control signal QB(n+1), one of the source and drain of the first pull-down sustaining transistor T31B is configured to be electrically connected to the stage signal output terminal Cout(n), and the other of the source and drain of the first pull-down sustaining transistor T31B is configured to be electrically connected to the first power supply terminal VGL1.

[0062] The gate of the second pull-down sustaining transistor T32B is configured to receive the first pull-down control signal QB(n+1), one of the source and drain of the second pull-down sustaining transistor T32B is configured to be electrically connected to the write signal output terminal WR(n), and the other of the source and drain of the second pull-down sustaining transistor T32B is configured to be electrically connected to the third power supply terminal VGL3.

[0063] The gate of the third pull-down sustaining transistor T33B is configured to receive the first pull-down control signal QB(n+1), one of the source and drain of the third pull-down sustaining transistor T33B is configured to be electrically connected to the read signal output terminal RD(n), and the other of the source and drain of the third pull-down sustaining transistor T33B is configured to be electrically connected to the third power supply terminal VGL3.

[0064] Optionally, the pull-down sustaining module further includes a second pull-down sustaining module 602, which includes a fourth pull-down sustaining transistor T31A, a fifth pull-down sustaining transistor T32A, and a sixth pull-down sustaining transistor T33A.

[0065] The gate of the fourth pull-down sustaining transistor T31A is configured to be electrically connected to the second node QB(n), one of the source and drain of the fourth pull-down sustaining transistor T31A is configured to be electrically connected to the cascade signal output terminal Cout(n), and the other of the source and drain of the fourth pull-down sustaining transistor T31A is configured to be electrically connected to the first power supply terminal VGL1.

[0066] The gate of the fifth pull-down sustaining transistor T32A is configured to be electrically connected to the second node QB(n), one of the source and drain of the fifth pull-down sustaining transistor T32A is configured to be electrically connected to the write signal output terminal WR(n), and the other of the source and drain of the fifth pull-down sustaining transistor T32A is configured to be electrically connected to the third power supply terminal VGL3.

[0067] The gate of the sixth pull-down sustaining transistor T33A is configured to be electrically connected to the second node QB(n), one of the source and drain of the sixth pull-down sustaining transistor T33A is configured to be electrically connected to the read signal output terminal RD(n), and the other of the source and drain of the sixth pull-down sustaining transistor T33A is configured to be electrically connected to the third power supply terminal VGL3.

[0068] like Figure 3 This is a timing diagram of the potential change of the first node Q(n) provided in an embodiment of the present invention. Wherein, Qd(n) represents the timing diagram of the potential change of the first node Q(n) under ideal conditions, and Ql(n) represents the timing diagram of the potential change of the first node Q(n) under leakage conditions.

[0069] In the first stage t1, the pull-up control signal Cout-PU controls the first pull-up control transistor T11, the second pull-up control transistor T12, the first leakage protection transistor T81, and the second leakage protection transistor T82 to be turned on. The preset voltage VGH is transmitted to the common node N(n) through the first leakage protection transistor T81 and the second leakage protection transistor T82, thereby completely turning off the first pull-down transistor and the second pull-down transistor (i.e., the first sub-transistor T43B, the second sub-transistor T44B, the third sub-transistor T41, the fourth sub-transistor T42, the fifth sub-transistor T43A, and the sixth sub-transistor T44A). This prevents the third leakage protection transistor T71 and the fourth leakage protection transistor T72 from being turned on before the potential of the first node Q(n) is charged to the preset potential, causing the potential of the first node Q(n) to leak through the pull-down module and resulting in the failure of the leakage protection function.

[0070] In the second stage t2, the potential of the first node Q(n) remains high, and the pull-up output module 400 outputs the clock signal transmitted by the clock signal line to the output terminal of the gate drive circuit according to the potential of the first node Q(n).

[0071] This application also provides a display panel including any of the gate driving circuits described above. Optionally, multiple gate driving circuits may be cascaded, and the multiple gate driving circuits may be located in the non-display area or display area of ​​the display panel.

[0072] Optionally, the plurality of gate driving circuits are electrically connected to the plurality of pixel driving circuits to drive the plurality of light-emitting devices of the display panel to display.

[0073] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A gate driving circuit, characterized in that, include: The pull-up control module is electrically connected to the first node and is configured to raise the potential of the first node according to the pull-up control signal; A pull-down module includes a first pull-down transistor and a second pull-down transistor. The first pull-down transistor is connected in series between the first node and a common node, and the second pull-down transistor is connected in series between the common node and a first power supply terminal. The first pull-down transistor and the second pull-down transistor are configured to output a first voltage provided by the first power supply terminal to the first node according to a pull-down control signal. The leakage protection module is electrically connected to the common node and includes a first leakage protection unit. The first leakage protection unit is configured to output a preset voltage to the common node according to the pull-up control signal, so that the first pull-down transistor and the second pull-down transistor are in the off state during the process of the pull-up control module raising the potential of the first node according to the pull-up control signal.

2. The gate driving circuit according to claim 1, characterized in that, The first leakage protection unit includes: A first leakage-proof transistor, wherein the gate of the first leakage-proof transistor is configured to receive the pull-up control signal, and one of the source and drain of the first leakage-proof transistor is configured to receive the preset voltage; and The second leakage protection transistor has a gate configured to receive the pull-up control signal, one of the source and drain of the second leakage protection transistor is configured to be electrically connected to the other of the source and drain of the first leakage protection transistor, and the other of the source and drain of the second leakage protection transistor is configured to be electrically connected to the common node.

3. The gate driving circuit according to claim 1, characterized in that, The leakage protection module further includes a second leakage protection unit, which includes: A third leakage-proof transistor, wherein the gate of the third leakage-proof transistor is configured to be electrically connected to the first node, and one of the source and drain of the third leakage-proof transistor is configured to receive the preset voltage; and A fourth leakage protection transistor, wherein the gate of the fourth leakage protection transistor is configured to be electrically connected to the first node, one of the source and drain of the fourth leakage protection transistor is configured to be electrically connected to the other of the source and drain of the third leakage protection transistor, and the other of the source and drain of the fourth leakage protection transistor is configured to be electrically connected to the common node. The third and fourth anti-leakage transistors are configured to output the preset voltage to the common node according to the potential of the first node when the potential of the first node is raised to a level greater than or equal to a preset potential.

4. The gate driving circuit according to claim 1, characterized in that, The drop-down module includes: The first pull-down unit includes a first sub-transistor and a second sub-transistor, the first sub-transistor and the second sub-transistor being configured to output the first voltage to the first node according to a first pull-down control signal before the potential of the first node is raised; Wherein, the first pull-down transistor includes the first sub-transistor, the second pull-down transistor includes the second sub-transistor, and the pull-down control signal includes the first pull-down control signal.

5. The gate driving circuit according to claim 4, characterized in that, The gate drive circuit further includes a pull-up output module, which is electrically connected to the first node and the clock signal line. The pull-up output module is configured to output the clock signal transmitted by the clock signal line to the output terminal of the gate drive circuit according to the potential of the first node. The pull-down module includes a second pull-down unit, which includes a third sub-transistor and a fourth sub-transistor. The third sub-transistor and the fourth sub-transistor are configured to output the first voltage provided by the first power supply to the first node according to the second pull-down control signal after the clock signal is transmitted to the output terminal of the gate drive circuit. Wherein, the first pull-down transistor includes the third sub-transistor, the second pull-down transistor includes the fourth sub-transistor, and the pull-down control signal includes the second pull-down control signal.

6. The gate driving circuit according to claim 5, characterized in that, The pull-up output module includes: The first pull-up output unit includes a first pull-up transistor and a first capacitor. The gate of the first pull-up transistor is configured to be electrically connected to the first node. One of the source and drain of the first pull-up transistor is configured to be electrically connected to a first clock signal line. The other of the source and drain of the first pull-up transistor is configured to be electrically connected to the stage transmission signal output terminal of the gate drive circuit. The first capacitor is connected in series between the first node and the stage transmission signal output terminal. The second pull-up output unit includes a second pull-up transistor and a second capacitor. The gate of the second pull-up transistor is configured to be electrically connected to the first node. One of the source and drain of the second pull-up transistor is configured to be electrically connected to a second clock signal line. The other of the source and drain of the second pull-up transistor is configured to be electrically connected to the write signal output terminal of the gate drive circuit. The second capacitor is connected in series between the first node and the write signal output terminal. The third pull-up output unit includes a third pull-up transistor and a third capacitor. The gate of the third pull-up transistor is configured to be electrically connected to the first node. One of the source and drain of the third pull-up transistor is configured to be electrically connected to the third clock signal line. The other of the source and drain of the third pull-up transistor is configured to be electrically connected to the read signal output terminal of the gate drive circuit. The third capacitor is connected in series between the first node and the read signal output terminal. The clock signal lines include the first clock signal line, the second clock signal line, and the third clock signal line; the output terminals include the transmission signal output terminal, the write signal output terminal, and the read signal output terminal.

7. The gate driving circuit according to claim 6, characterized in that, It also includes a first dropdown sustaining module, which includes: A first pull-down sustaining transistor, wherein the gate of the first pull-down sustaining transistor is configured to receive the first pull-down control signal, one of the source and drain of the first pull-down sustaining transistor is configured to be electrically connected to the stage signal output terminal, and the other of the source and drain of the first pull-down sustaining transistor is configured to be electrically connected to the first power supply terminal. A second pull-down sustaining transistor, wherein the gate of the second pull-down sustaining transistor is configured to receive the first pull-down control signal, one of the source and drain of the second pull-down sustaining transistor is configured to be electrically connected to the write signal output terminal, and the other of the source and drain of the second pull-down sustaining transistor is configured to be electrically connected to a third power supply terminal; and A third pull-down sustaining transistor, wherein the gate of the third pull-down sustaining transistor is configured to receive the first pull-down control signal, one of the source and drain of the third pull-down sustaining transistor is configured to be electrically connected to the read signal output terminal, and the other of the source and drain of the third pull-down sustaining transistor is configured to be electrically connected to the third power supply terminal.

8. The gate driving circuit according to claim 1, characterized in that, The gate drive circuit further includes an inverting module, which is electrically connected to the first node, the second node, the first power supply terminal, and the second power supply terminal. The inverting module is configured to control the potential change of the second node according to a low-frequency clock signal, the pull-up control signal, the potential of the first node, the first voltage, and the second voltage transmitted from the second power supply terminal, so as to obtain a third pull-down control signal corresponding to the potential change of the second node. The pull-down module includes a third pull-down unit, which includes a fifth sub-transistor and a sixth sub-transistor. The fifth sub-transistor and the sixth sub-transistor are configured to output the first voltage provided by the first power supply terminal to the first node according to the third pull-down control signal. Wherein, the first pull-down transistor includes the fifth sub-transistor, the second pull-down transistor includes the sixth sub-transistor, and the pull-down control signal includes the third pull-down control signal.

9. The gate driving circuit according to claim 8, characterized in that, The gate driving circuit further includes a second pull-down sustaining module, the second pull-down sustaining module comprising: A fourth pull-down sustaining transistor, wherein the gate of the fourth pull-down sustaining transistor is configured to be electrically connected to the second node, one of the source and drain of the fourth pull-down sustaining transistor is configured to be electrically connected to the cascade signal output terminal, and the other of the source and drain of the fourth pull-down sustaining transistor is configured to be electrically connected to the first power supply terminal. A fifth pull-down sustaining transistor, wherein the gate of the fifth pull-down sustaining transistor is configured to be electrically connected to the second node, one of the source and drain of the fifth pull-down sustaining transistor is configured to be electrically connected to the write signal output terminal, and the other of the source and drain of the fifth pull-down sustaining transistor is configured to be electrically connected to the third power supply terminal; and A sixth pull-down sustaining transistor, wherein the gate of the sixth pull-down sustaining transistor is configured to be electrically connected to the second node, one of the source and drain of the sixth pull-down sustaining transistor is configured to be electrically connected to the read signal output terminal, and the other of the source and drain of the sixth pull-down sustaining transistor is configured to be electrically connected to the third power supply terminal. The inverting module includes: A first transistor, wherein the gate of the first transistor is configured to receive the low-frequency clock signal, and one of the source and drain of the first transistor is configured to receive the low-frequency clock signal; The second transistor has its gate configured to receive the low-frequency clock signal, and one of its source and drain is configured to be electrically connected to the other of the source and drain of the first transistor. A third transistor, wherein the gate of the third transistor is configured to be electrically connected to the other of the source and drain of the second transistor, one of the source and drain of the third transistor is configured to receive the low-frequency clock signal, and the other of the source and drain of the third transistor is configured to be electrically connected to the second node. A fourth transistor, wherein the gate of the fourth transistor is configured to be electrically connected to the first node, one of the source and drain of the fourth transistor is configured to be electrically connected to the second node, and the other of the source and drain of the fourth transistor is configured to be electrically connected to the first power supply terminal. A fifth transistor, wherein the gate of the fifth transistor is configured to receive a node potential signal, one of the source and drain of the fifth transistor is configured to be electrically connected to the gate of the third transistor, and the other of the source and drain of the fifth transistor is configured to be electrically connected to the second power supply terminal. A sixth transistor, wherein the gate of the sixth transistor is configured to be electrically connected to the first node, one of the source and drain of the sixth transistor is configured to be electrically connected to the gate of the third transistor, and the other of the source and drain of the sixth transistor is configured to be electrically connected to the second power supply terminal; and A seventh transistor, wherein the gate of the seventh transistor is configured to receive the pull-up control signal, one of the source and drain of the seventh transistor is configured to be electrically connected to the second node, and the other of the source and drain of the seventh transistor is configured to be electrically connected to the first power supply terminal.

10. A display panel, characterized in that, Includes the gate drive circuit as described in any one of claims 1 to 9.

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