Gate driving circuit and display panel

Abstract

The application discloses a gate driving circuit and a display panel, which comprise a pull-down maintaining module connected to a common point; wherein the pull-down maintaining module comprises a first inverting unit, a second inverting unit and a pull-down unit; the first inverting unit is connected with the second inverting unit through the pull-down unit; the first inverting unit comprises a first transistor and a fifth transistor. In the driving circuit provided by the application, the first inverting unit and the second inverting unit are driven by a first clock signal, so that the driving circuit has better stability; and the first clock signal and a level signal cannot be turned on, so that the driving circuit has no risk of damage when driving a liquid crystal display to work.

Description

Technical Field

[0001] This application relates to the field of liquid crystal display technology, and in particular to a gate driving circuit and a display panel. Background Technology

[0002] GOA (Gate Driver on Array) circuits (shift register units) have been widely used in the display technology field. GOA circuits include pull-down sustaining units. These pull-down sustaining units typically contain inverters, usually two sets, which alternately operate by switching between them using an LC signal. However, due to the long switching period of the LC signal, the threshold voltage of the transistors in the inverters is prone to drift, leading to electrical instability. Furthermore, there is a risk of conduction between the clock signal and the level signal in the circuit; if conduction occurs, it can easily damage the LCD display. Summary of the Invention

[0003] This application provides a gate driving circuit and a display panel to solve the technical problems in the prior art.

[0004] To address the aforementioned technical problems, this application discloses the following technical solution:

[0005] In a first aspect, a gate driving circuit is provided, including a pull-down sustaining module connected to a common point;

[0006] The pull-down sustaining module includes a first inverting unit, a second inverting unit, and a pull-down unit; the first inverting unit is connected to the second inverting unit through the pull-down unit.

[0007] The first inverting unit includes a first transistor and a fifth transistor. The first control terminal of the first transistor is connected to a first clock signal, the first output terminal of the first transistor is connected to a high-level signal, the fifth control terminal of the fifth transistor is connected to a second clock signal, the fifth output terminal of the fifth transistor is connected to a first output point, and the fifth input terminal of the fifth transistor is connected to a low-level signal.

[0008] The second inverting unit includes a sixth transistor and a tenth transistor. The sixth control terminal of the sixth transistor is connected to a first clock signal, the sixth output terminal of the sixth transistor is connected to a high-level signal, the tenth control terminal of the tenth transistor is connected to the second clock signal, the tenth output terminal of the tenth transistor is connected to a second output point, and the tenth input terminal of the tenth transistor is connected to a low-level signal.

[0009] In conjunction with the first aspect, the first inverting unit further includes a second transistor, a third transistor, and a fourth transistor. The second control terminal of the second transistor is connected to the common point, the second output terminal of the second transistor is connected to the first input terminal of the first transistor, and the second input terminal of the second transistor is connected to the low-level signal. The third control terminal of the third transistor is connected to the first input terminal, the third output terminal of the third transistor is connected to the high-level signal, and the third input terminal of the third transistor is connected to the first output point. The fourth control terminal of the fourth transistor is connected to the common point, the third output terminal of the fourth transistor is connected to the first output point, and the fourth input terminal of the fourth transistor is connected to the low-level signal.

[0010] In conjunction with the first aspect, the second inverting unit further includes a seventh transistor, an eighth transistor, and a ninth transistor. The seventh control terminal of the seventh transistor is connected to the common point, the seventh output terminal of the seventh transistor is connected to the sixth input terminal of the sixth transistor, and the seventh input terminal of the seventh transistor is connected to the low-level signal. The eighth control terminal of the eighth transistor is connected to the seventh input terminal, the eighth output terminal of the eighth transistor is connected to the high-level signal, and the eighth input terminal of the eighth transistor is connected to the second output point. The ninth control terminal of the ninth transistor is connected to the common point, the eighth output terminal of the ninth transistor is connected to the second output point, and the ninth input terminal of the ninth transistor is connected to the low-level signal.

[0011] In conjunction with the first aspect, the gate drive circuit further includes a pull-up control module, which includes an eleventh transistor. The eleventh control terminal of the eleventh transistor is connected to a first control signal, the eleventh output terminal of the eleventh transistor is connected to a first scan signal, and the eleventh input terminal of the eleventh transistor is connected to a common point.

[0012] In conjunction with the first aspect, the gate drive circuit further includes a pull-up module, which includes a twelfth transistor, a thirteenth transistor, and a capacitor. The twelfth control terminal of the twelfth transistor and the thirteenth control terminal of the thirteenth transistor are both connected to a common point. The twelfth output terminal of the twelfth transistor and the thirteenth output terminal of the thirteenth transistor are both connected to a first clock signal. The twelfth input terminal of the twelfth transistor is connected to a second control signal, and the thirteenth input terminal of the thirteenth transistor is connected to a second scan signal. One end of the capacitor is connected to the twelfth control terminal, and the other end is connected to the second scan signal.

[0013] In conjunction with the first aspect, the gate drive circuit further includes a reset module, the reset module including a fourteenth transistor, the fourteenth control terminal of the fourteenth transistor being connected to a third control signal, the fourteenth output terminal of the fourteenth transistor being connected to a common point, and the fourteenth input terminal of the fourteenth transistor being connected to a low-level signal.

[0014] In conjunction with the first aspect, the gate drive circuit further includes a pull-down module, the pull-down module including a fifteenth transistor, the fifteenth control terminal of the fifteenth transistor being connected to a third scan signal, the fifteenth output terminal of the fifteenth transistor being connected to a common point, and the fifteenth input terminal of the fifteenth transistor being connected to the low-level signal.

[0015] In conjunction with the first aspect, the pull-down unit includes a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, and a nineteenth transistor. The sixteenth output terminal of the sixteenth transistor is connected to the eighteenth output terminal of the eighteenth transistor. The sixteenth control terminal of the sixteenth transistor and the seventeenth control terminal of the seventeenth transistor are connected to a first input terminal. The seventeenth control terminal of the seventeenth transistor and the nineteenth control terminal of the nineteenth transistor are connected to a second input terminal. The seventeenth output terminal of the seventeenth transistor and the nineteenth output terminal of the nineteenth transistor are connected to a common point. The sixteenth input terminal of the sixteenth transistor, the seventeenth input terminal of the seventeenth transistor, the eighteenth input terminal of the eighteenth transistor, and the nineteenth input terminal of the nineteenth transistor are all connected to the low-level signal.

[0016] In conjunction with the first aspect, the first clock signal and the second clock signal are inverted signals.

[0017] Secondly, a display panel is provided, including:

[0018] Drive substrate and display unit;

[0019] The driving substrate is provided with a gate driving circuit as described in any one of the first aspects, the display unit is connected to the gate driving circuit, and the gate driving circuit controls the operation of the display unit.

[0020] One of the above technical solutions has the following advantages or beneficial effects:

[0021] Compared with the prior art, the gate driving circuit of this application includes a pull-down sustaining module connected to a common point. The pull-down sustaining module includes a first inverting unit, a second inverting unit, and a pull-down unit. The first inverting unit is connected to the second inverting unit via the pull-down unit. The first inverting unit includes a first transistor and a fifth transistor. The first control terminal of the first transistor is connected to a first clock signal, and the first output terminal of the first transistor is connected to a high-level signal. The fifth control terminal of the fifth transistor is connected to a second clock signal, the fifth output terminal of the fifth transistor is connected to a first output point, and the fifth input terminal of the fifth transistor is connected to a low-level signal. The second inverting unit includes a sixth transistor and a tenth transistor. The sixth control terminal of the sixth transistor is connected to the first clock signal, and the sixth output terminal of the sixth transistor is connected to a high-level signal. The tenth control terminal of the tenth transistor is connected to the second clock signal, the tenth output terminal of the tenth transistor is connected to a second output point, and the tenth input terminal of the tenth transistor is connected to a low-level signal. The first and second inverting units in the driving circuit provided by this application are driven by the first clock signal, thereby giving the driving circuit better stability. Furthermore, the first clock signal and the level signal do not conduct, so there is no risk of damage to the driving circuit when driving the liquid crystal display. Attached Figure Description

[0022] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0023] Figure 1 This is a schematic diagram of the gate drive circuit structure provided in an embodiment of this application;

[0024] Figure 2 A schematic diagram of the circuit structure of the pull-down sustaining module provided in an embodiment of this application;

[0025] Figure 3 This is a schematic diagram of the signal waveforms of the common point Q, the first output point K, and the second output point P provided in the embodiments of this application.

[0026] The attached figures are labeled as follows:

[0027] 100 - Pull-up control module, 200 - Pull-down sustaining module, 210 - First inverting unit, 220 - Second inverting unit, 230 - Pull-down unit, 300 - Reset module, 400 - Pull-up module, 500 - Pull-down module. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0029] The applicant notes that current GOA inverters are generally configured in two ways. The first is the LC type, which typically consists of two sets of inverters that work alternately by switching the LC signal potential. However, due to the long switching cycle of the LC signal, the TFT (Thin Film Transistor) of the inverter is prone to TFT threshold voltage (Vth) drift caused by long-term bias, resulting in electrical instability. The second is the CK type, where the driving signal is the CK signal, so the voltage on the inverter's TFT constantly switches, making TFT Vth drift less noticeable and electrically more stable. However, in the CK type inverter, the CK signal and VSS signal are in the same circuit path, posing a risk of conduction between them. If conduction occurs, it will negatively impact the entire GOA stage. Based on the current state of these two types of inverters, this application proposes a gate driving circuit that maintains the electrical stability of the CK inverter TFT and eliminates the risk of conduction between the CK and VSS signals.

[0030] It should be noted that the control terminal of the transistor mentioned in this application is the gate of the transistor, the input terminal is the source of the transistor, and the output terminal is the drain of the transistor.

[0031] The specific implementation methods of this application are illustrated below through examples:

[0032] like Figure 1As shown, this application embodiment provides a gate driving circuit, including: a pull-down sustaining module 200, a pull-up control module 100, a pull-up module 400, a reset module 300, and a pull-down module 500; the pull-down sustaining module 200, the pull-up control module 100, the pull-up module 400, the reset module 300, and the pull-down module 500 are connected to a common point Q; wherein, the pull-down sustaining module 200 includes a first inverting unit 210, a second inverting unit 220, and a pull-down unit 230; the first inverting unit 210 is connected to the second inverting unit 220 through the pull-down unit 230; the first inverting unit 210 includes a first transistor T51 and a fifth transistor T55, the first control terminal of the first transistor T51 is connected to a first clock signal CK, and the first crystal... The first output terminal of transistor T51 is connected to a high-level signal VGH; the fifth control terminal of the fifth transistor T55 is connected to a second clock signal XCK; the fifth output terminal of the fifth transistor T55 is connected to the first output point K; and the fifth input terminal of the fifth transistor T55 is connected to a low-level signal VSS. The second inverter unit 220 includes a sixth transistor T61 and a tenth transistor T65. The sixth control terminal of the sixth transistor T61 is connected to the first clock signal CK; the sixth output terminal of the sixth transistor T61 is connected to a high-level signal VGH; the tenth control terminal of the tenth transistor T65 is connected to the second clock signal XCK; the tenth output terminal of the tenth transistor T65 is connected to the second output point P; and the tenth input terminal of the tenth transistor T65 is connected to a low-level signal VSS. Specifically, as follows... Figure 2 As shown, the first inverting unit 210 and the second inverting unit 220 in this application are symmetrically designed. The first transistor T51 in the first inverting unit 210 is equivalent to the sixth transistor T61 in the second inverting unit. The drains of both the first transistor T51 and the sixth transistor T61 are connected to the high-level signal VGH, and the gates of both the first transistor T51 and the sixth transistor T61 are connected to the first clock signal CK. The fifth transistor T55 in the first inverting unit 210 is equivalent to the tenth transistor T65 in the second inverting unit 220. The gates of both the fifth transistor T55 and the tenth transistor T65 are connected to the second clock signal XCK. The first clock signal CK and the second clock signal XCK are opposite signals, that is, when the first clock signal CK is high, the second clock signal XCK is low; when the first clock signal CK is low, the second clock signal XCK is high. Figure 3As shown, the first inverting unit 210 and the second inverting unit 220 of this application control the potential of the common point Q to be opposite to the potential of the first output point K or the second output point P. Furthermore, when the common point Q is at a low potential, the potential changes of the first output point K or the second output point P will not affect the normal operation of the pull-down sustaining module 200. When the common point Q is at a low potential, the potential changes of the first output point K or the second output point P prevent the transistors in the pull-down sustaining module 200 from being in a fixed bias state for a long time. Therefore, the risk of threshold voltage Vth drift in the transistors of the pull-down sustaining module 200 can be reduced, thereby ensuring a more stable gate drive circuit.

[0033] like Figure 1 As shown in the embodiment of this application, the first inverting unit 210 further includes a second transistor T52, a third transistor T53, and a fourth transistor T54. The second control terminal of the second transistor T52 is connected to the common point Q, the second output terminal of the second transistor T52 is connected to the first input terminal of the first transistor T51, and the second input terminal of the second transistor T52 is connected to a low-level signal VSS. The third control terminal of the third transistor T53 is connected to the first input terminal, the third output terminal of the third transistor T53 is connected to a high-level signal VGH, and the third input terminal of the third transistor T53 is connected to the first output point K. The fourth control terminal of the fourth transistor T54 is connected to the common point Q, the third output terminal of the fourth transistor T54 is connected to the first output point K, and the fourth input terminal of the fourth transistor T54 is connected to the low-level signal VSS. Specifically, the first transistor T51 is driven by the first clock signal CK, and the fifth transistor T55 is driven by the second clock signal XCK. At the same time, the drains of the first transistor T51 and the third transistor T53 are connected to the high-level signal VGH, while the sources of the second transistor T52, the fourth transistor T54, and the fifth transistor T55 are connected to the low-level signal VSS. Through the cooperation of the first transistor T51, the second transistor T52, the third transistor T53, the fourth transistor T54, and the fifth transistor T55, the first output point K can output a signal opposite to that of the common point Q.

[0034] like Figure 1As shown in the embodiment of this application, the second inverting unit 220 further includes a seventh transistor T62, an eighth transistor T63, and a ninth transistor T64. The seventh control terminal of the seventh transistor T62 is connected to the common point Q, the seventh output terminal of the seventh transistor T62 is connected to the sixth input terminal of the sixth transistor T61, and the seventh input terminal of the seventh transistor T62 is connected to a low-level signal VSS. The eighth control terminal of the eighth transistor T63 is connected to the seventh input terminal, the eighth output terminal of the eighth transistor T63 is connected to a high-level signal VGH, and the eighth input terminal of the eighth transistor T63 is connected to the second output point P. The ninth control terminal of the ninth transistor T64 is connected to the common point Q, the eighth output terminal of the ninth transistor T64 is connected to the second output point P, and the ninth input terminal of the ninth transistor T64 is connected to the low-level signal VSS. Specifically, the sixth transistor T61 is driven by the first clock signal CK, and the seventh transistor T62 is driven by the second clock signal XCK. At the same time, the drains of the sixth transistor T61 and the eighth transistor T63 are connected to the high-level signal VGH, while the sources of the seventh transistor T62, the ninth transistor T64, and the tenth transistor T65 are connected to the low-level signal VSS. Through the cooperation of the sixth transistor T61, the seventh transistor T62, the eighth transistor T63, the ninth transistor T64, and the tenth transistor T65, the second output point P can output a signal opposite to that of the common point Q.

[0035] In the embodiments of this application, it should be noted that the first transistor T51, the second transistor T52, the third transistor T53, the fourth transistor T54 and the fifth transistor T55 in the first inverter unit 210, and the sixth transistor T61, the seventh transistor T62, the eighth transistor T63, the ninth transistor T64 and the tenth transistor T65 in the second inverter unit 220 are all TFT thin film transistors. The active layer material of all TFT thin film transistors can be not only amorphous silicon material, but also oxide material.

[0036] like Figure 1As shown in this embodiment, the pull-down unit 230 includes a sixteenth transistor T32, a seventeenth transistor T42, an eighteenth transistor T33, and a nineteenth transistor T43. The sixteenth output terminal of the sixteenth transistor T32 is connected to the eighteenth output terminal of the eighteenth transistor T33. The sixteenth control terminal of the sixteenth transistor T32 and the seventeenth control terminal of the seventeenth transistor T42 are connected to the first input terminal. The seventeenth control terminal of the seventeenth transistor T42 and the nineteenth control terminal of the nineteenth transistor T43 are connected to the second input terminal. The seventeenth output terminal of the seventeenth transistor T42 and the nineteenth output terminal of the nineteenth transistor T43 are connected to a common point Q. The sixteenth input terminal of the sixteenth transistor T32, the seventeenth input terminal of the seventeenth transistor T42, the eighteenth input terminal of the eighteenth transistor T33, and the nineteenth input terminal of the nineteenth transistor T43 are all connected to a low-level signal VSS. Specifically, after the pull-down unit 230 is connected to the first inverting unit 210 and the second inverting unit 220, it outputs corresponding signals in conjunction with the first inverting unit 210 and the second inverting unit 220.

[0037] like Figure 1 As shown in the embodiment of this application, the pull-up control module 100 includes an eleventh transistor T11. The eleventh control terminal of the eleventh transistor T11 is connected to a first control signal ST(NX), the eleventh output terminal of the eleventh transistor T11 is connected to a first scan signal G(NX), and the eleventh input terminal of the eleventh transistor T11 is connected to a common point Q. Specifically, the main function of the pull-up control module 100 is to control the pull-up state of the common point Q. The pull-up control module 100 consists of an eleventh transistor T11, used to control the connection and disconnection of the common point Q. When the eleventh transistor T11 receives a signal to turn on, the common point Q is connected to the pull-up power supply, and the common point Q is pulled high. When the eleventh transistor T11 receives a signal to turn off, the common point Q is disconnected from the pull-up power supply, and the common point Q is pulled low.

[0038] like Figure 1As shown in this embodiment, the pull-up module 400 includes a twelfth transistor T21, a thirteenth transistor T22, and a capacitor. The twelfth control terminal of the twelfth transistor T21 and the thirteenth control terminal of the thirteenth transistor T22 are both connected to a common point Q. The twelfth output terminal of the twelfth transistor T21 and the thirteenth output terminal of the thirteenth transistor T22 are both connected to a first clock signal CK. The twelfth input terminal of the twelfth transistor T21 is connected to a second control signal ST(N), and the thirteenth input terminal of the thirteenth transistor T22 is connected to a second scan signal G(N). One end of the capacitor is connected to the twelfth control terminal, and the other end is connected to the second scan signal G(N). Specifically, the main function of the pull-up module 400 is to pull the potential of the common point Q to a high level. In this gate drive circuit, when there is no external input signal, the pull-up module 400 can ensure that the potential of the common point Q remains at a high level to avoid uncertain logic states.

[0039] like Figure 1 As shown in this embodiment, the reset module 300 includes a fourteenth transistor TrQ. The fourteenth control terminal of the fourteenth transistor TrQ is connected to a third control signal STV, the fourteenth output terminal of the fourteenth transistor TrQ is connected to a common point Q, and the fourteenth input terminal of the fourteenth transistor TrQ is connected to a low-level signal VSS. Specifically, the reset module 300 is used to implement the reset function of the gate drive circuit. When the gate drive circuit starts up or when a specific event occurs, it is necessary to restore the circuit or system to a known state. The reset module 300 restores the circuit to its initial state by transmitting a reset signal, ensuring controllable operation and avoiding uncertain logic states.

[0040] like Figure 1 As shown in this embodiment, the pull-down module 500 includes a fifteenth transistor T41. The fifteenth control terminal of the fifteenth transistor T41 is connected to the third scan signal, the fifteenth output terminal of the fifteenth transistor T41 is connected to the common point Q, and the fifteenth input terminal of the fifteenth transistor T41 is connected to the low-level signal VSS. Specifically, the pull-down module 500 is typically used in conjunction with the pull-up module 400. When the input signal is low, the pull-down module 500 pulls the common point Q low to a low level, while the pull-up module 400 pulls the common point Q high to a high level.

[0041] This application also provides a display panel, including: a driving substrate and a display unit; the driving substrate is provided with a gate driving circuit as provided in any of the above embodiments, the display unit is connected to the gate driving circuit, and the gate driving circuit controls the operation of the display unit.

[0042] The above provides a detailed description of a gate driving circuit and display panel provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A gate drive circuit characterized by comprising: The pull-down maintaining module (200) connected to the common point, the pull-down maintaining module (200) comprising a first inverting unit (210), a second inverting unit (220) and a pull-down unit (230); the first inverting unit (210) is connected with the second inverting unit (220) through the pull-down unit (230); The first inverting unit (210) comprises a first transistor and a fifth transistor, the first control end of the first transistor is connected with a first clock signal, the first output end of the first transistor is connected with a high level signal, the fifth control end of the fifth transistor is connected with a second clock signal, the fifth output end of the fifth transistor is connected with a first output point, and the fifth input end of the fifth transistor is connected with a low level signal; The second inverting unit (220) comprises a sixth transistor and a tenth transistor, the sixth control end of the sixth transistor is connected with the first clock signal, the sixth output end of the sixth transistor is connected with the high level signal, the tenth control end of the tenth transistor is connected with the second clock signal, the tenth output end of the tenth transistor is connected with a second output point, and the tenth input end of the tenth transistor is connected with the low level signal; The first clock signal and the second clock signal are inverse signals of each other.

2. The gate drive circuit of claim 1, wherein, The first inverting unit (210) further comprises a second transistor, a third transistor and a fourth transistor, the second control end of the second transistor is connected with the common point, the second output end of the second transistor is connected with the first input end of the first transistor, the second input end of the second transistor is connected with the low level signal, the third control end of the third transistor is connected with the first input end, the third output end of the third transistor is connected with the high level signal, the third input end of the third transistor is connected with the first output point, the fourth control end of the fourth transistor is connected with the common point, the third output end of the fourth transistor is connected with the first output point, and the fourth input end of the fourth transistor is connected with the low level signal.

3. The gate drive circuit according to claim 1 or 2, characterized in that, The second inverting unit (220) further comprises a seventh transistor, an eighth transistor and a ninth transistor, the seventh control end of the seventh transistor is connected with the common point, the seventh output end of the seventh transistor is connected with the sixth input end of the sixth transistor, the seventh input end of the seventh transistor is connected with the low level signal, the eighth control end of the eighth transistor is connected with the seventh input end, the eighth output end of the eighth transistor is connected with the high level signal, the eighth input end of the eighth transistor is connected with the second output point, the ninth control end of the ninth transistor is connected with the common point, the eighth output end of the ninth transistor is connected with the second output point, and the ninth input end of the ninth transistor is connected with the low level signal.

4. The gate drive circuit of claim 1, wherein, The gate drive circuit further comprises a pull-up control module (100), the pull-up control module (100) comprising an eleventh transistor, an eleventh control end of the eleventh transistor being connected with a first control signal, an eleventh output end of the eleventh transistor being connected with a first scanning signal, and an eleventh input end of the eleventh transistor being connected with a common point.

5. The gate drive circuit of claim 1, wherein, The gate drive circuit further comprises a pull-up module (400), the pull-up module (400) comprising a twelfth transistor, a thirteenth transistor and a capacitor, a twelfth control end of the twelfth transistor and a thirteenth control end of the thirteenth transistor being connected with the common point, a twelfth output end of the twelfth transistor and a thirteenth output end of the thirteenth transistor being connected with a first clock signal, a twelfth input end of the twelfth transistor being connected with a second control signal, a thirteenth input end of the thirteenth transistor being connected with a second scanning signal, and one end of the capacitor being connected with the twelfth control end and the other end being connected with the second scanning signal.

6. The gate drive circuit of claim 1, wherein, The gate drive circuit further comprises a reset module (300), the reset module (300) comprising a fourteenth transistor, a fourteenth control end of the fourteenth transistor being connected with a third control signal, a fourteenth output end of the fourteenth transistor being connected with the common point, and a fourteenth input end of the fourteenth transistor being connected with a low-level signal.

7. The gate drive circuit of claim 1, wherein, The gate drive circuit further comprises a pull-down module (500), the pull-down module (500) comprising a fifteenth transistor, a fifteenth control end of the fifteenth transistor being connected with a third scanning signal, a fifteenth output end of the fifteenth transistor being connected with the common point, and a fifteenth input end of the fifteenth transistor being connected with the low-level signal.

8. The gate drive circuit of claim 2, wherein, The pull-down unit (230) comprises a sixteenth transistor, a seventeenth transistor, an eighteenth transistor and a nineteenth transistor, a sixteenth output end of the sixteenth transistor being connected with an eighteenth output end of the eighteenth transistor, a sixteenth control end of the sixteenth transistor and a seventeenth control end of the seventeenth transistor being connected with a first input end, a seventeenth control end of the seventeenth transistor and a nineteenth control end of the nineteenth transistor being connected with a second input end, a seventeenth output end of the seventeenth transistor and a nineteenth output end of the nineteenth transistor being connected with the common point, and a sixteenth input end of the sixteenth transistor, a seventeenth input end of the seventeenth transistor, an eighteenth input end of the eighteenth transistor and a nineteenth input end of the nineteenth transistor being connected with the low-level signal.

9. A display panel, characterized by, Comprise: a driving substrate and a display unit; the driving substrate is provided with the gate drive circuit as claimed in any one of claims 1-8, the display unit is connected with the gate drive circuit, and the gate drive circuit controls the display unit to operate.

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