A TOPCon battery and a method for preparing a TOPCon battery

Abstract

The present application discloses a TOPCon battery and a preparation method thereof, belonging to the field of solar cells. The battery includes: a substrate; a stacked passivation film and an electrode are disposed on one surface of the substrate; the stacked passivation film includes a tunneling layer, a first doped polysilicon layer, a diffusion barrier layer, and a second doped polysilicon layer which are sequentially disposed in a direction away from the substrate; one surface of the substrate facing the electrode has a metallized region and a non-metallized region, and the diffusion barrier layer corresponds to the non-metallized region, and is used to block the diffusion of doping elements in the second doped polysilicon layer into the first doped polysilicon layer, so that the doping concentration of the first doped polysilicon layer in the non-metallized region is lower than the doping concentration of the first doped polysilicon layer in the metallized region. By adopting a double-layer doped polysilicon layer and arranging a diffusion barrier layer in the non-metallized region, the doping concentration of the inner doped polysilicon layer is reduced, ensuring that the Auger recombination rate is reduced while the passivation effect is improved.

Description

Technical Field

[0001] The present application relates to the field of solar cells, and in particular to a TOPCon cell and a method for preparing the TOPCon cell. Background Art

[0002] In the current industrial production of crystalline silicon TOPCon (Tunnel Oxide Passivated Contact) cell technology, a stacked passivation structure of a tunnel oxide layer and doped polysilicon is usually prepared on the front, back or both sides of the TOPCon cell. Among them, doped polysilicon is to deposit intrinsic amorphous silicon or in-situ doped amorphous silicon on the surface of the tunnel oxide layer of the crystalline silicon cell by chemical vapor deposition, and the intrinsic amorphous silicon or in-situ doped amorphous silicon is converted into a microcrystalline or polycrystalline silicon thin film layer through high temperature treatment.

[0003] In order to match the current more mature metallization paste printing technology, screen printing paste technology is usually used to form an ohmic contact with a passivation effect between the polysilicon film layer and the electrode. First, in order to ensure good ohmic contact between the electrode and the polysilicon film layer, the polysilicon film layer usually adopts a high doping concentration. In order to reduce the Auger recombination rate caused by the high doping concentration in the polysilicon film layer as much as possible, it is usually necessary to reduce the thickness of the polysilicon film layer as much as possible; and reducing the thickness of the polysilicon film layer will reduce the passivation effect of the polysilicon film layer; secondly, it is limited by the corrosive characteristics of the current metallization paste, especially the strong corrosiveness of the glass phase in the aluminum paste, which will penetrate the polysilicon film layer during the subsequent high-temperature sintering process. The current polysilicon film layer thickness is usually controlled within a range of greater than 120nm. It is necessary to seek the thickness of the doped polysilicon film layer that best balances between reducing the Auger recombination rate of the doped polysilicon film layer and improving the passivation effect. Therefore, how to improve the passivation effect while reducing the Auger recombination rate is a technical problem that technicians in this field currently need to solve. Summary of the invention

[0004] The purpose of the present application is to provide a TOPCon battery and a method for preparing a TOPCon battery, which can both reduce the Auger recombination rate and improve the passivation effect, thereby improving the conversion efficiency of the battery.

[0005] To achieve the above-mentioned object, the present application provides a TOPCon battery, comprising: a substrate; a laminated passivation film and an electrode are provided on one side surface of the substrate;

[0006] The stacked passivation film comprises a tunneling layer, a first doped polysilicon layer, a diffusion barrier layer, and a second doped polysilicon layer which are sequentially arranged in a direction away from the substrate;

[0007] One side surface of the substrate facing the electrode has a metallized region and a non-metallized region. The diffusion barrier layer corresponds to the non-metallized region and is used to block the diffusion of doping elements in the second doped polysilicon layer into the first doped polysilicon layer, so that the doping concentration of the first doped polysilicon layer in the non-metallized region is lower than that in the metallized region of the first doped polysilicon layer.

[0008] Optionally, the diffusion barrier layer is a silicon oxide layer.

[0009] Optionally, the stacked passivation film is disposed on the back surface of the substrate. The first doped polysilicon layer, the second doped polysilicon layer and the substrate adopt the same type of doping elements. The overall doping concentration of the first doped polysilicon layer is greater than the overall doping concentration of the substrate, and the overall doping concentration of the second doped polysilicon layer is higher than the overall doping concentration of the first doped polysilicon layer.

[0010] Optionally, a back passivation layer is disposed on one side surface of the stacked passivation film facing away from the substrate. The electrode passes through the back passivation layer and contacts the stacked passivation film; the back passivation layer includes SiN x film, SiO x N y film, Al2O3 / SiN x stacked film, SiO x N y / SiN x at least one of the stacked films.

[0011] Optionally, the thickness of the first doped polysilicon layer is 20 nm - 40 nm, including both end values;

[0012] The thickness from the surface of the second doped polysilicon layer facing away from the substrate to the surface of the diffusion barrier layer facing away from the substrate is 20 nm - 200 nm, including both end values.

[0013] Optionally, the overall doping concentration of the first doped polysilicon layer is 1E19 cm -3 -3E20 cm -3 , including both end values;

[0014] The overall doping concentration of the second doped polysilicon layer is 5E20 cm -3 -1E21 cm -3 , including both end values.

[0015] To achieve the above object, the present application also provides a method for manufacturing a TOPCon cell, including:

[0016] A stacked passivation film layer is prepared on one side surface of a substrate; the stacked passivation film includes a tunneling layer, a first doped polysilicon layer, a diffusion barrier layer, and a second doped polysilicon layer that are sequentially arranged in a direction away from the substrate; one side surface of the substrate corresponding to the stacked passivation film layer has a metallized region and a non-metallized region, and the diffusion barrier layer corresponds to the non-metallized region, and is used to block the diffusion of doping elements in the second doped polysilicon layer into the first doped polysilicon layer, so that the doping concentration of the first doped polysilicon layer in the non-metallized region is lower than the doping concentration of the first doped polysilicon layer in the metallized region.

[0017] Optionally, preparing the stacked passivation film layer on the surface of the substrate includes:

[0018] Depositing the tunneling layer on the surface of the substrate;

[0019] Depositing a first intrinsic amorphous silicon layer on the surface of the tunneling layer;

[0020] Preparing the diffusion barrier layer on the surface of the first intrinsic amorphous silicon layer corresponding to the non-metallized region;

[0021] Depositing a second intrinsic amorphous silicon layer on the surface of the first intrinsic amorphous silicon layer corresponding to the metallized region and on the surface of the diffusion barrier layer;

[0022] Performing doping element diffusion, so that in the metallized region, the doping elements sequentially diffuse into the second intrinsic amorphous silicon layer and the first intrinsic amorphous silicon layer, and in the non-metallized region, the doping elements sequentially diffuse into the second intrinsic amorphous silicon layer, the diffusion barrier layer, and the first intrinsic amorphous silicon layer, so that the second intrinsic amorphous silicon layer becomes the second doped polysilicon layer, and the first intrinsic amorphous silicon layer becomes the first doped polysilicon layer.

[0023] Optionally, after depositing the first intrinsic amorphous silicon layer on the surface of the tunneling layer, it further includes:

[0024] Performing light doping on the first intrinsic amorphous silicon layer.

[0025] Optionally, preparing the stacked passivation film layer on the surface of the substrate includes:

[0026] Depositing the tunneling layer on the surface of the substrate;

[0027] Depositing the first doped polysilicon layer on the surface of the tunneling layer by in-situ doping;

[0028] Preparing the diffusion barrier layer on the surface of the first doped polysilicon layer corresponding to the non-metallized region;

[0029] Deposit the second doped polysilicon layer on the surface of the first doped polysilicon layer corresponding to the metallization region and the surface of the diffusion barrier layer;

[0030] Anneal the first doped polysilicon layer and the second doped polysilicon layer.

[0031] Obviously, a TOPCon battery provided by the present application adopts a double-layer doped polysilicon layer. While ensuring that the thickness of the inner doped polysilicon layer can achieve a good passivation effect, by adding a diffusion barrier layer between the two doped polysilicon layers, the diffusion barrier layer corresponds to the non-metallization region, and plays a blocking role on the doping elements of the outer doped polysilicon layer, so that the doping concentration of the inner doped polysilicon layer is high in the metallization region and low in the non-metallization region, thereby reducing the overall doping concentration of the inner doped polysilicon layer, and further reducing the Auger recombination rate; the concentration of the outer doped polysilicon layer is higher than that of the inner doped polysilicon layer, and the doping concentration of the inner doped polysilicon layer is high in the metallization region, which can ensure good ohmic contact. The present application also provides a preparation method of a TOPCon battery, and the TOPCon battery prepared by this preparation method has the above beneficial effects. Description of the Drawings

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to the provided drawings.

[0033] Figure 1 It is a structural diagram of a TOPCon battery provided by an embodiment of the present application;

[0034] Figure 2 It is a structural diagram of the stacked passivation film in the metallization region provided by an embodiment of the present application;

[0035] Figure 3 It is a structural diagram of the stacked passivation film in the non-metallization region provided by an embodiment of the present application;

[0036] Figure 4 It is a flowchart of a preparation method of a TOPCon battery provided by an embodiment of the present application;

[0037] Figure 5 It is a structural diagram of the TOPCon battery after texturing provided by an embodiment of the present application;

[0038] Figure 6 It is a structural diagram of the TOPCon battery after boron diffusion provided by an embodiment of the present application;

[0039] Figure 7 It is a partial enlarged view of the TOPCon cell after boron diffusion provided by the embodiment of the present application;

[0040] Figure 8 It is a structural diagram of the TOPCon cell after removing BSG provided by the embodiment of the present application;

[0041] Figure 9 It is a structural diagram of the TOPCon cell after polishing provided by the embodiment of the present application;

[0042] Figure 10 It is a structural diagram of the TOPCon cell after patterning provided by the embodiment of the present application;

[0043] Figure 11 It is a structural diagram of the TOPCon cell after forming a stacked passivation film provided by the embodiment of the present application;

[0044] Figure 12 It is a structural diagram of the TOPCon cell after phosphorus diffusion provided by the embodiment of the present application;

[0045] Figure 13 It is a curve graph showing the variation of doping concentration with thickness provided by the embodiment of the present application;

[0046] Figure 14 It is a structural diagram of the TOPCon cell after forming a front passivation film and a back passivation film provided by the embodiment of the present application.

[0047] The description of the reference numerals is as follows:

[0048] 1 - Substrate / crystalline silicon substrate; 1a - First surface; 1b - Second surface; 11a - Doped layer / P - type doped layer; 11a′ - BSG layer; 13 - Stacked passivation film; 131 - Tunneling silicon oxide layer; 132 - First doped polysilicon layer / first intrinsic amorphous silicon layer; 1321 - First high - passivation silicon - containing layer; 1322 - First low - passivation silicon - containing layer; 133 - Diffusion barrier layer; 134 - Second doped polysilicon layer / second intrinsic amorphous silicon layer; 14 - PSG layer; 151 - Back passivation layer; 152 - Front passivation layer; 161 - Back electrode; 162 - Front electrode. Detailed implementation manners

[0049] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some, but not all, of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0050] An embodiment of the present application provides a TOPCon battery, which may include: a substrate; a stacked passivation film and an electrode are disposed on one side surface of the substrate;

[0051] The stacked passivation film includes a tunneling layer, a first doped polysilicon layer, a diffusion barrier layer, and a second doped polysilicon layer sequentially disposed in a direction away from the substrate;

[0052] One side surface of the substrate facing the electrode has a metallized region and a non - metallized region. The diffusion barrier layer corresponds to the non - metallized region and is used to block the diffusion of doping elements in the second doped polysilicon layer into the first doped polysilicon layer, so that the doping concentration of the first doped polysilicon layer in the non - metallized region is lower than the doping concentration of the first doped polysilicon layer in the metallized region.

[0053] This embodiment does not limit the specific type of the substrate. The specific type of the substrate can be determined according to the actual situation. For example, the substrate can be a crystalline silicon substrate. This embodiment does not limit the specific type of the substrate. For example, the substrate can be an N - type substrate; it can also be a P - type substrate. In this embodiment, the first doped polysilicon layer, the second doped polysilicon layer, and the substrate adopt the same type of doping elements. This embodiment does not limit the specific type of the doping elements. For example, the doping elements can be B (boron), P (phosphorus), or Ga (gallium). It should be noted that the corresponding doping elements need to be selected according to the specific type of the substrate.

[0054] It should be noted that in this embodiment, the stacked passivation film can be disposed on the front and / or back surface of the substrate, that is, the stacked passivation film and the front electrode can be sequentially disposed on the front surface of the substrate, and / or the stacked passivation film and the back electrode can be sequentially disposed on the back surface of the substrate. When the stacked passivation film and the front electrode are sequentially disposed on the front surface of the substrate, this embodiment does not limit the specific structure of the back surface of the substrate. When the stacked passivation film and the back electrode are sequentially disposed on the back surface of the substrate, this embodiment does not limit the specific structure of the front surface of the substrate. For example, a doped layer and a front electrode can be sequentially disposed on the front surface of the substrate. This embodiment does not limit the specific type of the doped layer. The specific type of the doped layer can be determined according to the specific type of the substrate. For example, when the substrate is an N - type substrate, the doped layer can be a P - type doped layer.

[0055] This embodiment does not limit the specific type of the tunneling layer, as long as it can provide chemical passivation on the surface of the substrate. For example, the tunneling layer can be a tunneling silicon oxide layer. It should be noted that the tunneling silicon oxide layer can be prepared by high - temperature thermal oxidation of silicon atoms on the surface of the crystalline silicon substrate. Its function is to provide overall chemical passivation for the crystalline silicon substrate, and at the same time provide a tunneling and / or perforation channel for the photo - generated carriers generated in the crystalline silicon substrate to be transported to the electrode, and its thickness does not exceed 2nm.

[0056] It should be noted that the amorphous silicon in the first doped polysilicon layer can further enhance the chemical passivation effect of the tunneling silicon oxide layer. Moreover, the bandgap width of the amorphous silicon material itself is much larger than that of the crystalline silicon substrate (1.12 eV). After doping with group 3 and group 5 elements (group 3 and group 5 doping elements include: B, P, Ga, etc.), it provides partial field passivation effect for the transport of photo-generated carriers in crystalline silicon. In addition, after the first doped polysilicon layer is doped with group 3 and group 5 elements, its resistivity is reduced, so it can also provide a conduction path for the transport of photo-generated carriers generated by the crystalline silicon substrate.

[0057] This embodiment does not limit the specific thickness of the first doped polysilicon layer. For example, the thickness of the first doped polysilicon layer 132 can be 20 nm - 40 nm, including both ends.

[0058] It should be noted that since a single thin tunneling layer is not sufficient to provide the best passivation effect for the crystalline silicon cell, adding the first doped polysilicon layer here can further enhance the passivation effect of the crystalline silicon cell. However, if the thickness of the first doped polysilicon layer is too large, it will inevitably introduce too many foreign doping atoms into the in-situ deposited intrinsic amorphous silicon due to element doping, and then introduce too many recombination centers, which is not conducive to reducing the Auger recombination rate of the first doped polysilicon layer; if the thickness of the first doped polysilicon layer is too small, the passivation effect of the in-situ deposited intrinsic amorphous silicon cannot be fully exerted.

[0059] This embodiment does not limit the specific overall doping concentration of the first doped polysilicon layer. For example, the overall doping concentration of the first doped polysilicon layer can be greater than the overall doping concentration of the substrate; it can be less than the overall doping concentration of the substrate 1; it can also be equal to the overall doping concentration of the substrate. It should be noted that when the overall doping concentration of the first doped polysilicon layer is greater than the overall doping concentration of the substrate, a surface field passivation effect can be established between the substrate and the first doped polysilicon layer, thereby accelerating the selective absorption of electrons or holes in the photo-generated carriers.

[0060] In this embodiment, the diffusion barrier layer is adjacent to the first doped polysilicon layer corresponding to the metallization region, and is used to block the diffusion of doping elements in the second doped polysilicon layer into the first doped polysilicon layer. This embodiment does not limit the specific type of the diffusion barrier layer, as long as it can ensure that the doping elements are blocked from diffusing into the first doped polysilicon layer. For example, the diffusion barrier layer can be a silicon oxide layer. The silicon oxide layer can be composed of silicon dioxide deposited by CVD (Chemical Vapor Deposition). Specifically, it can be prepared by introducing oxygen or a carrier gas containing oxygen into the CVD deposition chamber and using the oxidation reaction of oxygen with the intrinsic amorphous silicon in the first doped polysilicon layer.

[0061] It should be noted that during the preparation of the TOPCon cell in this embodiment, when the intrinsic amorphous silicon is atomically doped to prepare the doped polysilicon layer subsequently, the relatively dense crystal structure in the silicon dioxide is utilized to provide a good interface barrier layer for the atomic doping of the intrinsic amorphous silicon, and slow down the diffusion movement of the doped atoms in the silicon dioxide layer serving as the diffusion barrier layer.

[0062] It should be noted that the second doped polysilicon layer is located on the surface of the diffusion barrier layer away from the substrate; it is obtained by doping the intrinsic amorphous silicon deposited by CVD with doped atoms and performing high-temperature crystallization treatment, providing overall surface passivation and field passivation for the crystalline silicon substrate. Moreover, after the second doped polysilicon layer is highly doped with group 3 and 5 elements, its conductivity is greatly improved, thereby providing a conduction path for the transport of photo-generated carriers generated by the crystalline silicon substrate.

[0063] It should be noted that since the doped elements need to diffuse through the diffusion barrier layer to the first doped polysilicon layer in the non-metallized region, the overall doping concentration of the second doped polysilicon layer is higher than that of the first doped polysilicon layer. This embodiment does not limit the specific values of the overall doping concentrations of the first doped polysilicon layer or the second doped polysilicon layer. For example, the overall doping concentration of the first doped polysilicon layer can be 1E19 cm -3 -3E20 cm -3 , including the values at both ends; the overall doping concentration of the second doped polysilicon layer can be 5E20 cm -3 -1E21 cm -3 , including the values at both ends.

[0064] This embodiment does not limit the specific thickness of the second doped polysilicon layer. For example, the thickness from the surface of the second doped polysilicon layer facing away from the substrate to the surface of the diffusion barrier layer facing away from the substrate can be 20 nm - 200 nm, including the values at both ends.

[0065] It should be noted that in this embodiment, by setting the second doped polysilicon layer, a sufficient corrosion penetration thickness can be provided for the corrosive glass phase in the metallization paste, ensuring that the metal electrode material obtained after sintering the metallization paste during printing the electrodes will not burn through the tunneling layer, that is, the contact interface formed under the corrosion of the glass phase in the metallization paste by the sintered metal electrode material can be located at: the second doped polysilicon layer, the diffusion barrier layer, or the first doped polysilicon layer. As Figure 1As shown, when the electrode forms an ohmic contact with the first doped polysilicon layer, the different doping concentrations of the doping elements in the first doped polysilicon layer can enable the electrode to form a good ohmic contact with the first doped polysilicon layer with a higher doping concentration of the doping elements. And the corresponding non-metallized region in the first doped polysilicon layer has a better passivation effect due to the lower doping concentration of phosphorus atoms. Therefore, the conversion efficiency of the battery can be improved. When the electrode forms an ohmic contact with the second doped polysilicon layer, since electrons tend to be transmitted along the path of the low-doping-concentration region of the first doped polysilicon layer with better conductivity, the transmission resistance loss of electrons can be reduced. In addition, the different doping concentrations of the doping elements in the first doped polysilicon layer are conducive to reducing the doping concentration of the doping elements therein while ensuring the passivation effect of the first polysilicon layer, and then increasing the Auger recombination rate caused by atomic doping. Therefore, the conversion efficiency of the battery can be improved.

[0066] When the stacked passivation film is disposed on the back surface of the substrate, further, in order to enhance the passivation effect, a back passivation layer may be provided on the surface of the stacked passivation film facing away from the substrate in this embodiment, and the electrode passes through the back passivation layer and contacts the stacked passivation film. The specific type of the back passivation layer is not limited in this embodiment. For example, the back passivation layer may include SiN x film, SiO x N y film, Al2O3 / SiN x stacked film, SiO x N y / SiN x stacked film, or at least one of them.

[0067] Based on the above embodiments, the present application adopts a double-layer doped polysilicon layer, which can avoid penetration of the doped polysilicon layer during the printing electrode sintering process; while ensuring that the thickness of the inner doped polysilicon layer can achieve a good passivation effect, by adding a diffusion barrier layer between the two doped polysilicon layers, the diffusion barrier layer corresponds to the non-metallized region, and plays a blocking role on the doping elements of the outer doped polysilicon layer, so that the doping concentration of the inner doped polysilicon layer is high in the metallized region and low in the non-metallized region, thereby reducing the Auger recombination rate; the concentration of the outer doped polysilicon layer is higher than that of the inner doped polysilicon layer, and the doping concentration of the inner doped polysilicon layer is high in the metallized region, which can ensure good ohmic contact.

[0068] Please refer to Figure 1 , Figure 1A structural diagram of a TOPCon battery provided by an embodiment of the present application. The TOPCon battery may include: a substrate 1; a doped layer 11a, a front passivation layer 152, and a front electrode 162 are sequentially disposed on the front surface of the substrate 1; a stacked passivation film 13, a back passivation layer 151, and a back electrode 161 are sequentially disposed on the back surface of the substrate 1;

[0069] The stacked passivation film 13 includes a tunneling silicon oxide layer 131, a first doped polysilicon layer 132, a diffusion barrier layer 133, and a second doped polysilicon layer 134 sequentially disposed in a direction away from the substrate 1;

[0070] One side surface of the substrate 1 facing the back electrode 161 has a metallized region and a non-metallized region. The diffusion barrier layer 133 corresponds to the non-metallized region and is used to block the diffusion of doping elements in the second doped polysilicon layer 134 into the first doped polysilicon layer 132, so that the doping concentration of the first doped polysilicon layer 132 in the non-metallized region is lower than the doping concentration of the first doped polysilicon layer 132 in the metallized region;

[0071] The surface of the back electrode 161 close to the substrate 1 is located in the first doped polysilicon layer 132, so that the back electrode 161 forms an ohmic contact with the first doped polysilicon layer 132.

[0072] It should be noted that in the longitudinal direction of the substrate 1, as Figure 2 shown, the metallized region from the inside to the outside sequentially includes: a tunneling silicon oxide layer 131, a first doped polysilicon layer 132, and a second doped polysilicon layer 134; as Figure 3 shown, the non-metallized region from the inside to the outside sequentially includes: a tunneling silicon oxide layer 131, a first doped polysilicon layer 132, a diffusion barrier layer 133, and a second doped polysilicon layer 134. The diffusion barrier layer 133 corresponds to the non-metallized region. When doping the stacked passivation film 13, since the diffusion barrier layer 133 blocks the doping elements, a first doped polysilicon layer 132 with a lower doping concentration is formed in the non-metallized region, while the first doped polysilicon layer 132 corresponding to the metallized region has a relatively high doping concentration due to the lack of any diffusion barrier layer 133 to block the diffusion of doping elements, thereby forming a differential doping concentration in the first doped polysilicon layer 132.

[0073] Based on the above embodiments, the present application adopts a double-layer doped polysilicon layer. While ensuring that the thickness of the inner doped polysilicon layer can achieve a good passivation effect, a diffusion barrier layer 133 is added between the two doped polysilicon layers. The diffusion barrier layer 133 corresponds to the non-metallized region and plays a role in blocking the doping elements of the outer doped polysilicon layer, making the doping concentration of the inner doped polysilicon layer high in the metallized region and low in the non-metallized region, thereby reducing the overall doping concentration of the inner doped polysilicon layer and further reducing the Auger recombination rate; through the front passivation layer 152 and the back passivation layer 151, the effect of the stacked passivation film 13 is superimposed to further enhance the passivation effect.

[0074] An embodiment of the present application also provides a method for manufacturing a TOPCon battery, which may include:

[0075] A stacked passivation film layer is prepared on one side surface of the substrate; the stacked passivation film includes a tunneling layer, a first doped polysilicon layer, a diffusion barrier layer, and a second doped polysilicon layer sequentially arranged in a direction away from the substrate; one side surface of the substrate corresponding to the stacked passivation film layer has a metallized region and a non-metallized region, and the diffusion barrier layer corresponds to the non-metallized region and is used to block the doping elements in the second doped polysilicon layer from diffusing into the first doped polysilicon layer, so that the doping concentration of the first doped polysilicon layer in the non-metallized region is lower than the doping concentration of the first doped polysilicon layer in the metallized region.

[0076] This embodiment does not limit the specific method for preparing the stacked passivation film, as long as it can ensure the formation of the stacked passivation film on the surface of the substrate. For example, the following two methods can be adopted:

[0077] (1) Deposit a tunneling layer on the surface of the substrate; deposit a first intrinsic amorphous silicon layer on the surface of the tunneling layer; prepare a diffusion barrier layer on the surface of the first intrinsic amorphous silicon layer corresponding to the non-metallized region; deposit a second intrinsic amorphous silicon layer on the surface of the first intrinsic amorphous silicon layer corresponding to the metallized region and on the surface of the diffusion barrier layer; perform doping element diffusion, so that the doping elements diffuse into the second intrinsic amorphous silicon layer and the first intrinsic amorphous silicon layer in sequence in the metallized region, and the doping elements diffuse into the second intrinsic amorphous silicon layer, the diffusion barrier layer, and the first intrinsic amorphous silicon layer in sequence in the non-metallized region, so that the second intrinsic amorphous silicon layer becomes the second doped polysilicon layer and the first intrinsic amorphous silicon layer becomes the first doped polysilicon layer.

[0078] Further, in order to avoid too low doping concentration of the first doped polysilicon layer, after depositing the first intrinsic amorphous silicon layer on the surface of the tunneling layer in this embodiment, the first intrinsic amorphous silicon layer can also be lightly doped to adjust the carrier transport performance of the first doped polysilicon layer.

[0079] (2) Deposit a tunneling layer on the surface of the substrate; deposit a first doped polysilicon layer on the surface of the tunneling layer by in-situ doping; prepare a diffusion barrier layer on the surface of the first doped polysilicon layer corresponding to the non-metallized region; deposit a second doped polysilicon layer on the surface of the first doped polysilicon layer corresponding to the metallized region and on the surface of the diffusion barrier layer; anneal the first doped polysilicon layer and the second doped polysilicon layer.

[0080] It should be noted that in method (1), the first doped polysilicon layer and the second doped polysilicon layer are prepared by impurity diffusion; in method (2), the first doped polysilicon layer and the second doped polysilicon layer are prepared by in-situ doping followed by annealing.

[0081] It should be noted that in this embodiment, the stacked passivation film can be disposed on the front and / or back of the substrate, that is, the stacked passivation film and the front electrode can be sequentially disposed on the front of the substrate, and / or the stacked passivation film and the back electrode can be sequentially disposed on the back of the substrate. When the stacked passivation film and the front electrode are sequentially disposed on the front of the substrate, the specific structure of the back of the substrate is not limited in this embodiment. When the stacked passivation film and the back electrode are sequentially disposed on the back of the substrate, the specific structure of the front of the substrate is not limited in this embodiment. For example, a doped layer and a front electrode can be sequentially disposed on the front of the substrate.

[0082] When the stacked passivation film and the back electrode are sequentially disposed on the back of the substrate; when a doped layer and a front electrode are sequentially disposed on the front of the substrate, the manufacturing method of this embodiment may include:

[0083] Prepare a doped layer on the front of the substrate;

[0084] After the doped layer is prepared, prepare a stacked passivation film layer on the back of the substrate; the stacked passivation film includes a tunneling layer, a first doped polysilicon layer, a diffusion barrier layer, and a second doped polysilicon layer sequentially disposed in a direction away from the substrate; one side surface of the substrate corresponding to the stacked passivation film layer has a metallized region and a non-metallized region, and the diffusion barrier layer corresponds to the non-metallized region, and is used to block the doping elements in the second doped polysilicon layer from diffusing into the first doped polysilicon layer, so that the doping concentration of the first doped polysilicon layer in the non-metallized region is lower than the doping concentration of the first doped polysilicon layer in the metallized region;

[0085] Print a back electrode on the surface of the stacked passivation film away from the substrate, and print a front electrode on the surface of the doped layer away from the substrate to obtain a TOPCon battery.

[0086] Based on the above embodiments, the TOPCon cell prepared in this application adopts a double-layer doped polysilicon layer. While ensuring that the thickness of the inner doped polysilicon layer can achieve a good passivation effect, a diffusion barrier layer is added between the two doped polysilicon layers. The diffusion barrier layer corresponds to the non-metallized area and plays a role in blocking the doping elements of the outer doped polysilicon layer, making the doping concentration of the inner doped polysilicon layer higher in the metallized area and lower in the non-metallized area. Thus, the overall doping concentration of the inner doped polysilicon layer is reduced, and the Auger recombination rate is further reduced. The concentration of the outer doped polysilicon layer is higher than that of the inner doped polysilicon layer, and the doping concentration of the inner doped polysilicon layer in the metallized area is high, which can ensure good ohmic contact.

[0087] Please refer to Figure 4 , Figure 4 which is a flowchart of a method for preparing a TOPCon cell provided by an embodiment of this application. The method may include:

[0088] S101: Prepare a doped layer on the front surface of the substrate.

[0089] This embodiment does not limit the specific method for preparing the doped layer. The specific method for preparing the doped layer can be determined according to the specific type of the doped layer. For example, when the doped layer is a P-type doped layer, boron diffusion can be performed on the substrate to prepare the doped layer on the front surface of the substrate. It should be noted that a BSG (BoroSilicate Glass) layer may be formed on both sides of the substrate during the diffusion process. Further, in this embodiment, the BSG layer on the back surface of the substrate can be removed after step S101. This embodiment does not limit the specific method for removing the BSG layer, as long as it can ensure the removal of the BSG layer. For example, the BSG layer on the front and back surfaces of the substrate can be removed by a chain cleaning method.

[0090] Further, in order to improve the light trapping effect of the substrate, the substrate can be subjected to double-sided alkaline texturing before step S101 to obtain a substrate with a pyramid texture structure. It should be noted that after double-sided alkaline texturing of the substrate, the back surface of the substrate needs to be polished after the doped layer on the front surface of the substrate is prepared to obtain a relatively flat back surface.

[0091] S102: After the doped layer is prepared, deposit a tunneling layer on the back surface of the substrate.

[0092] This embodiment does not limit the specific method of depositing the tunneling layer, and the specific method of depositing the tunneling layer can be determined according to the specific type of the tunneling layer. For example, when the tunneling layer is a tunneling silicon oxide layer, oxygen or a carrier gas containing oxygen (including but not limited to inert gases such as nitrogen, argon, or helium) can be introduced into the CVD deposition chamber, and the tunneling silicon oxide layer can be obtained by the thermal oxidation reaction of oxygen with silicon atoms on the back surface of the crystalline silicon.

[0093] S103: Deposit a first intrinsic amorphous silicon layer on the surface of the tunneling layer.

[0094] This embodiment does not limit the specific method of depositing the first intrinsic amorphous silicon layer. For example, a mixed gas of a silicon source gas and / or a carrier gas carrying the silicon source gas can be introduced into the CVD deposition chamber, and the first intrinsic amorphous silicon layer can be in-situ deposited on the surface of the tunneling layer under high-temperature conditions through the silicon source gas.

[0095] S104: Prepare a diffusion barrier layer on the surface of the first intrinsic amorphous silicon layer corresponding to the non-metallized region.

[0096] This embodiment does not limit the specific method of preparing the diffusion barrier layer. For example, oxygen or a carrier gas containing oxygen can be introduced into the CVD deposition chamber, and the diffusion barrier layer can be obtained by the oxidation reaction of oxygen with the first intrinsic amorphous silicon.

[0097] It should be noted that oxygen directly contacts the silicon atoms in the first intrinsic amorphous silicon layer for oxidation reaction to prepare silicon oxide Si x O y , so compared with the tunneling silicon oxide layer prepared by thermal oxidation of the crystalline silicon substrate, the Si-O crystal structure in the silicon oxide Si x O y prepared based on the oxidation of the first intrinsic amorphous silicon layer is also relatively loose, which can provide an appropriate barrier effect for the diffusion of subsequent doping elements.

[0098] The metallized region and the non-metallized region have different requirements for the concentration of doping elements. If patterning distribution starts when forming the diffusion barrier layer, the non-metallized region is blocked by the diffusion barrier layer, and the non-metallized region is not blocked by the diffusion barrier layer, that is, it can be determined that the non-metallized region and the metallized region have different doping concentrations. After the diffusion barrier layer is deposited by CVD, additional patterning treatment of the diffusion barrier layer is performed to prepare the diffusion barrier layer on the surface of the first intrinsic amorphous silicon layer corresponding to the non-metallized region. The patterning treatment steps are as follows:

[0099] A diffusion barrier layer is formed on the back surface of the substrate; after forming the diffusion barrier layer, a patterned mask corresponding to the non-metallized region is formed on the back surface of the substrate; after forming the patterned mask, the substrate is placed in an acid solution or an alkali solution, and the diffusion barrier layer in the region not covered by the patterned mask is removed by etching; after removing the diffusion barrier layer, the patterned mask is removed by cleaning. This embodiment does not limit the specific manner of forming the patterned mask. For example, a patterned mask corresponding to the non-metallized region can be formed on the back surface of the substrate by screen printing, laser transfer printing or photolithography. When the screen printing method is adopted, in this embodiment, a slurry resistant to HF (hydrofluoric acid) corrosion or an acid and alkali resistant wax can be printed on the back surface of the substrate to form a patterned mask corresponding to the non-metallized region.

[0100] S105: Deposit a second intrinsic amorphous silicon layer on the surface of the first intrinsic amorphous silicon layer corresponding to the metallized region and on the surface of the diffusion barrier layer.

[0101] This embodiment does not limit the specific manner of depositing the second intrinsic amorphous silicon layer. For example, a mixed gas of a silicon source gas and / or a carrier gas carrying a silicon source gas can be introduced into a CVD deposition chamber, and the second intrinsic amorphous silicon layer can be in-situ deposited on the surface of the first intrinsic amorphous silicon layer corresponding to the metallized region and on the surface of the diffusion barrier layer by the silicon source gas under high-temperature conditions.

[0102] S106: Perform doping element diffusion. In the metallized region, the doping element diffuses into the second intrinsic amorphous silicon layer and the first intrinsic amorphous silicon layer in sequence. In the non-metallized region, the doping element diffuses into the second intrinsic amorphous silicon layer, the diffusion barrier layer and the first intrinsic amorphous silicon layer in sequence, so that the second intrinsic amorphous silicon layer becomes a second doped polysilicon layer and the first intrinsic amorphous silicon layer becomes a first doped polysilicon layer.

[0103] This embodiment does not limit the specific manner of performing doping element diffusion, as long as it can ensure that the doping element diffuses towards the substrate direction and diffuses into the second intrinsic amorphous silicon layer, the diffusion barrier layer and the first intrinsic amorphous silicon layer in sequence. For example, a doping element gas source and oxygen can be introduced into a CVD deposition chamber.

[0104] It should be noted that a deposited PSG (PhosphoSilicate Glass) layer may be formed on the front edge of the substrate 1 during the diffusion process. Further, in this embodiment, the deposited PSG layer on the front surface of the substrate can also be removed after step S106.

[0105] Further, in order to enhance the passivation effect, a front passivation layer can also be deposited on the front surface of the substrate 1 after step S106 in this embodiment; a back passivation layer is printed on the back surface of the substrate 1.

[0106] S107: Print the back electrode on the surface of the stacked passivation film facing away from the substrate, and print the front electrode on the surface of the doped layer facing away from the substrate to fabricate a TOPCon cell.

[0107] It should be noted that the front electrode or the back electrode is usually formed by printing metallization paste.

[0108] Based on the above embodiments, the TOPCon cell prepared in this application adopts a double-layer doped polysilicon layer. While ensuring that the thickness of the inner doped polysilicon layer can achieve a good passivation effect, a diffusion barrier layer is added between the two doped polysilicon layers. The diffusion barrier layer corresponds to the non-metallized area and plays a role in blocking the doping elements of the outer doped polysilicon layer, making the doping concentration of the inner doped polysilicon layer high in the metallized area and low in the non-metallized area, thereby reducing the overall doping concentration of the inner doped polysilicon layer and further reducing the Auger recombination rate; the concentration of the outer doped polysilicon layer is higher than that of the inner doped polysilicon layer, and the doping concentration of the inner doped polysilicon layer is high in the metallized area, which can ensure good ohmic contact.

[0109] The following combines specific examples to illustrate the preparation process of the above TOPCon cell. Please refer to Figures 5 to 14 , in this embodiment, the substrate 1 is an N-type crystalline silicon substrate 1, and the process is as follows:

[0110] Step 1: Prepare a single-sided crystalline silicon substrate 1 with a polished surface;

[0111] 1. Please refer to Figure 5 , perform double-sided alkaline texturing on the crystalline silicon substrate 1 to obtain a crystalline silicon substrate 1 with a pyramid texture structure. Among them, the light-facing surface of the crystalline silicon substrate 1 corresponds to the first surface 1a, and the second surface 1b where the backlight surface is located corresponds to the first surface 1a;

[0112] 2. Please refer to Figure 6 and Figure 7 , perform boron diffusion on the crystalline silicon substrate 1 with a pyramid texture structure to prepare a PN junction, and form a P-type doped layer 11a (for forming the PN junction) and a BSG layer 11a' on the first surface 1a of the crystalline silicon substrate 1; similarly, a P-type doped layer and a BSG layer are also formed on the second surface 1b of the crystalline silicon substrate 1;

[0113] 3. Please refer to Figure 8 , use a chain cleaning method to remove the BSG layer on the second surface 1b of the crystalline silicon substrate 1;

[0114] 4. Please refer to Figure 9 , use a chain cleaning method to polish the second surface 1b of the crystalline silicon substrate 1 to obtain a relatively flat second surface 1b;

[0115] Step 2: Prepare a stacked passivation film 13 on the second surface 1b of the crystalline silicon substrate 1;

[0116] Place the silicon wafer into a CVD deposition chamber to deposit and prepare the stacked passivation film 13;

[0117] In the first stage, introduce oxygen or a carrier gas containing oxygen (including but not limited to inert gases such as nitrogen, argon, or helium) into the CVD deposition chamber. A thermal oxidation reaction occurs between the oxygen and the silicon atoms on the back surface of the crystalline silicon substrate 1 to obtain a tunneling oxide layer 131;

[0118] In the second stage, introduce a mixture of a silicon source gas and / or a carrier gas carrying the silicon source gas into the CVD deposition chamber. The silicon source gas is in-situ deposited on the surface of the tunneling oxide layer 131 under high-temperature conditions to obtain a first intrinsic amorphous silicon layer 132; among them, the first intrinsic amorphous silicon layer 132 has a first thickness W1 of 20 nm - 40 nm (including the values at both ends). Stacking a doped polysilicon layer with a minimum thickness of 20 nm and about 1.5 nm of the tunneling oxide layer 131 can meet the better passivation level for the surface of the N-type crystalline silicon substrate 1;

[0119] In the third stage, introduce oxygen or a carrier gas containing oxygen into the CVD deposition chamber. The oxygen directly contacts the silicon atoms in the first intrinsic amorphous silicon layer 132 and undergoes an oxidation reaction with them to prepare a diffusion barrier layer 133 composed of an oxide layer; among them, the oxygen directly contacts the silicon atoms in the first intrinsic amorphous silicon layer 132 for an oxidation reaction to prepare silicon oxide Si x O y O. Therefore, compared with the tunneling oxide layer 131 prepared by thermal oxidation of the crystalline silicon substrate 1, the Si - O crystal structure in the silicon oxide Si x O y prepared based on the oxidation of the first intrinsic amorphous silicon layer 132 is also relatively loose, which can provide an appropriate blocking effect for the diffusion of subsequent doping elements;

[0120] Regarding the different requirements for the concentration of doping elements in the metallized area and the non-metallized area, if patterning distribution starts when forming the diffusion barrier layer 133, the non-metallized area is blocked by the diffusion barrier layer 133, and the non-metallized area is not blocked by the diffusion barrier layer 133, that is, it can be determined that the non-metallized area and the metallized area have different doping concentrations. After the diffusion barrier layer 133 is deposited by CVD, further patterning treatment of the diffusion barrier layer 133 is added to prepare the diffusion barrier layer 133 on the surface corresponding to the first intrinsic amorphous silicon layer 132 and the non-metallized area. The patterning treatment steps are as follows:

[0121] After forming the diffusion barrier layer 133 on the back surface of the crystalline silicon substrate 1, a patterned mask corresponding to the non-metallized region pattern is formed. The patterned mask can be prepared by screen printing, laser transfer printing, photolithography, or other methods.

[0122] Please refer to Figure 10 As shown, in one embodiment, the patterned mask can be formed by printing a slurry, paste, or ink resistant to HF corrosion, or using an acid and alkali resistant wax. The crystalline silicon wafer is placed in an HF solution. Among them, the diffusion barrier layer 133 not protected by the patterned mask will be removed by HF. Then, the patterned mask is removed by washing in sequence to prepare a selectively patterned diffusion barrier layer 133 on the back surface of the crystalline silicon substrate 1.

[0123] In the fourth stage, please refer to Figure 11 , a mixed gas of a silicon source gas and a carrier gas carrying the silicon source gas is introduced into the CVD deposition chamber. The second intrinsic amorphous silicon layer 134 is in-situ deposited on the surfaces corresponding to the metallized regions on the back surface of the first intrinsic amorphous silicon layer 132 and the substrate 1 and the surface of the diffusion barrier layer 133 by the silicon source gas under high-temperature conditions. Among them, the second silicon-containing layer 134 has a second thickness of 20 nm - 200 nm (including both ends).

[0124] Step 3: Diffuse and dope elements on the back surface of the crystalline silicon substrate 1.

[0125] Please refer to Figure 12 , a doping element gas source of POCl3 (phosphorus oxychloride) and oxygen are introduced into the CVD deposition chamber. Oxygen reacts with POCl3 to generate P2O5 (phosphorus pentoxide). The phosphorus atoms in P2O5 continuously diffuse towards the direction of the crystalline silicon substrate 1 under high-temperature conditions. The phosphorus atoms diffuse into the second intrinsic amorphous silicon layer 134, the diffusion barrier layer 133, the first intrinsic amorphous silicon layer 132, and the tunneling oxide layer 131 in sequence. And through the annealing process brought by the diffusion of phosphorus atoms, a second doped polysilicon layer 134, a diffusion barrier layer 133, a first doped polysilicon layer 132, a tunneling oxide layer 131, and a PSG layer (not shown in the figure) doped with phosphorus atoms are formed on the back surface of the crystalline silicon substrate 1, and a bypass PSG layer 14 is formed on the front edge of the crystalline silicon substrate 1.

[0126] Among them, due to the diffusion barrier effect of the diffusion barrier layer 133 on phosphorus atoms in the non-metallized region, a differential local doping concentration is formed in the first intrinsic amorphous silicon layer 132 during the diffusion of phosphorus atoms. That is, the first doped polysilicon layer 132 includes a first high-passivation silicon-containing layer 1321 with a relatively high phosphorus atom diffusion concentration and a first low-passivation silicon-containing layer 1322 with a relatively low phosphorus atom diffusion concentration. It should be noted that the diffusion of phosphorus atoms in the first intrinsic amorphous silicon is a diffuse diffusion in all directions. However, since the length of the diffusion barrier layer 133 in the horizontal direction is much greater than the length of the diffusion barrier layer 133 in the vertical direction, during the short-time diffusion process of phosphorus atoms, the diffusion of phosphorus atoms in the horizontal direction can be ignored. Therefore, the diffusion of phosphorus atoms in the first intrinsic amorphous silicon layer 132 can be physically approximated as the diffusion of phosphorus atoms only in the vertical direction.

[0127] The second doped polysilicon layer 134 has a second phosphorus atom doping concentration C1; since the diffusion barrier layer 133 is made of a silicon oxide layer that has a blocking effect on the diffusion of phosphorus atoms, it can effectively block the diffusion of phosphorus atoms, and the phosphorus atom doping concentration therein is less than the second phosphorus atom doping concentration C1.

[0128] The first doped polysilicon layer 132 has a first phosphorus atom doping concentration C2. Since phosphorus atoms need to diffuse through the diffusion barrier layer 133 to the first doped polysilicon layer 132, the first phosphorus atom doping concentration C2 is less than the phosphorus atom doping concentration in the diffusion barrier layer 133.

[0129] Please refer to Figure 13 , in the figure, the thicknesses of t1, t2, t3, and t4 are 90 nm, 95 nm, 120 nm, and 125 nm respectively. The thickness direction corresponding to the X-axis is defined as: taking the surface where the second doped polysilicon layer 134 is located as the reference plane and extending along the direction towards the silicon substrate 1. Specifically, the thickness t1 corresponds to the second thickness W2 of the second doped polysilicon layer 134, the thickness t2 corresponds to the thickness between the diffusion barrier layer 133 and the reference plane of the second doped polysilicon layer 134, the thickness t3 corresponds to the thickness between the first doped polysilicon layer 132 and the reference plane of the second doped polysilicon layer 134, and the thickness t4 corresponds to the thickness between the tunneling silicon oxide and the reference plane of the second doped polysilicon layer 134.

[0130] The Y-axis corresponds to the phosphorus atom doping concentration in each layer of the stacked passivation film 13 layers. Specifically, the second phosphorus atom doping concentration of the second doped polysilicon layer 134 is C1, the phosphorus atom doping concentration of the first doped polysilicon layer 132 is C2, and the phosphorus atom doping concentration at the interface between the crystalline silicon substrate 1 and the tunneling silicon oxide layer 131 is C3 (atoms / cm³) (where the concentrations of C1, C2, and C3 are 5E20 cm -3 、3E20 cm -3 and 6E19 cm -3));

[0131] Among them, since both the first thickness W1 and the second thickness W2 are in the nanometer scale, and the high-temperature phosphorus diffusion rate is relatively small compared to the nanometer-scale intrinsic amorphous silicon layer, it can be approximately considered that the diffusion concentration of phosphorus atoms is equal everywhere in the first thickness W1 and the second thickness W2;

[0132] However, the presence of the diffusion barrier layer 133 will reduce the diffusion concentration of phosphorus atoms from the second intrinsic amorphous silicon layer 134 to the first intrinsic amorphous silicon layer 132, especially for the silicon oxide layer prepared by using the above-mentioned first intrinsic amorphous silicon layer 132 after high-temperature annealing treatment;

[0133] The second phosphorus atom doping concentration C1 in the second doped polysilicon layer 134 is 5E20 cm -3 -1E21 cm -3 (including the values at both ends). The second doped polysilicon layer 134 with a higher doping concentration can provide an ideal ohmic contact for the contact of the back electrode 161, greatly reducing the transmission resistance loss of photo-generated carriers;

[0134] The first phosphorus atom doping concentration C2 in the first doped polysilicon layer 132 is 1E19 cm -3 -3E20 cm -3 (including the values at both ends). The first doped polysilicon layer 132 with a lower doping concentration can provide chemical passivation for the solar cell, and moreover, due to its lower doping concentration, the Auger recombination rate in the TOPCon cell can also be greatly reduced;

[0135] Step Four: Form a passivation film on the front and back surfaces of the crystalline silicon substrate 1, and prepare electrodes to obtain a solar cell structure as shown in Figure 1 the figure.

[0136] Please refer to Figure 14 , form a back passivation film on the back surface of the crystalline silicon substrate 1, and form a front passivation film on the front surface of the crystalline silicon substrate 1; then print metallization paste on the front and back surfaces of the crystalline silicon substrate 1 to prepare a TOPCon cell as shown in Figure 1 the figure.

[0137] In this article, specific examples are used to elaborate on the principles and implementation methods of this application, and there is a progressive relationship between the various embodiments. The key points of each embodiment are the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other. The descriptions of the above embodiments are only used to help understand the method and its core idea of this application. For those of ordinary skill in the art in this technical field, without departing from the principles of this application, several improvements and modifications can be made to this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

[0138] It should also be noted that in this specification, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

Claims

1. A TOPCon battery, characterized in that, Comprising: A substrate; a stacked passivation film and an electrode are disposed on one side surface of the substrate; The stacked passivation film includes a tunneling layer, a first doped polysilicon layer, a diffusion barrier layer, and a second doped polysilicon layer sequentially disposed in a direction away from the substrate; The stacked passivation film is disposed on the back surface of the substrate. The first doped polysilicon layer and the second doped polysilicon layer use the same type of doping element as the substrate. The overall doping concentration of the first doped polysilicon layer is greater than the overall doping concentration of the substrate, and the overall doping concentration of the second doped polysilicon layer is higher than the overall doping concentration of the first doped polysilicon layer; One side surface of the substrate facing the electrode has a metallized region and a non-metallized region. The diffusion barrier layer corresponds to the non-metallized region and is used to block the diffusion of doping elements in the second doped polysilicon layer into the first doped polysilicon layer, so that the doping concentration of the first doped polysilicon layer in the non-metallized region is lower than the doping concentration of the first doped polysilicon layer in the metallized region.

2. The TOPCon battery according to claim 1, characterized in that, The diffusion barrier layer is a silicon oxide layer.

3. The TOPCon cell according to claim 1, wherein a back passivation layer is provided on a surface of the stacked passivation film facing away from the substrate, and the electrode passes through the back passivation layer and contacts the stacked passivation film; the back passivation layer includes SiN x film, SiO x N y film, Al2O3 / SiN x stacked film, SiO x N y / SiN x stacked film, or at least one of them.

4. The TOPCon battery according to claim 1, wherein The thickness of the first doped polysilicon layer is 20 nm - 40 nm, and both end values are included; The thickness from the surface of the second doped polysilicon layer facing away from the substrate to the surface of the diffusion barrier layer facing away from the substrate is 20 nm - 200 nm, and both end values are included.

5. The TOPCon battery according to claim 1, wherein, The overall doping concentration of the first doped polysilicon layer is 1E19 cm -3 - 3E20 cm -3 , and includes the values at both ends; The overall doping concentration of the second doped polysilicon layer is 5E20 cm -3 -1E21 cm -3 , and includes both end values.

6. A preparation method of a TOPCon battery, characterized in that, Comprising: Preparing a stacked passivation film layer on one side surface of a substrate; the stacked passivation film includes a tunneling layer, a first doped polysilicon layer, a diffusion barrier layer, and a second doped polysilicon layer sequentially disposed in a direction away from the substrate; the stacked passivation film is disposed on the back surface of the substrate. The first doped polysilicon layer and the second doped polysilicon layer use the same type of doping element as the substrate. The overall doping concentration of the first doped polysilicon layer is greater than the overall doping concentration of the substrate, and the overall doping concentration of the second doped polysilicon layer is higher than the overall doping concentration of the first doped polysilicon layer; one side surface of the substrate corresponding to the stacked passivation film layer has a metallized region and a non-metallized region. The diffusion barrier layer corresponds to the non-metallized region and is used to block the diffusion of doping elements in the second doped polysilicon layer into the first doped polysilicon layer, so that the doping concentration of the first doped polysilicon layer in the non-metallized region is lower than the doping concentration of the first doped polysilicon layer in the metallized region.

7. The preparation method of the TOPCon battery according to claim 6, characterized in that, The preparing the stacked passivation film layer on the surface of the substrate includes: Depositing the tunneling layer on the surface of the substrate; Depositing a first intrinsic amorphous silicon layer on the surface of the tunneling layer; Preparing the diffusion barrier layer on the surface of the first intrinsic amorphous silicon layer corresponding to the non-metallized region; Depositing a second intrinsic amorphous silicon layer on the surface of the first intrinsic amorphous silicon layer corresponding to the metallized region and on the surface of the diffusion barrier layer; Perform doping element diffusion, and in the metallized region, make the doping element diffuse into the second intrinsic amorphous silicon layer and the first intrinsic amorphous silicon layer in sequence, and in the non-metallized region, make the doping element diffuse into the second intrinsic amorphous silicon layer, the diffusion barrier layer and the first intrinsic amorphous silicon layer in sequence, so that the second intrinsic amorphous silicon layer becomes the second doped polysilicon layer and the first intrinsic amorphous silicon layer becomes the first doped polysilicon layer.

8. The preparation method of the TOPCon battery according to claim 7, characterized in that, After depositing the first intrinsic amorphous silicon layer on the surface of the tunneling layer, it further includes: Lightly dope the first intrinsic amorphous silicon layer.

9. The preparation method of the TOPCon battery according to claim 6, wherein, The preparation of the stacked passivation film layer on the surface of the substrate includes: Deposit the tunneling layer on the surface of the substrate; Deposit the first doped polysilicon layer on the surface of the tunneling layer by in-situ doping; Prepare the diffusion barrier layer on the surface of the first doped polysilicon layer corresponding to the non-metallized region; Deposit the second doped polysilicon layer on the surface of the first doped polysilicon layer corresponding to the metallized region and on the surface of the diffusion barrier layer; Anneal the first doped polysilicon layer and the second doped polysilicon layer.

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